general description the max4970/max4971/max4972 family of overvolt- age protection devices features a low 40m (typ) r on internal fet and protect low-voltage systems against voltage faults up to +28v. these devices also drive an optional external pfet to protect against reverse-polari- ty input voltages. when the input voltage exceeds the overvoltage threshold, the internal fet is turned off to prevent damage to the protected components. all switches feature a 2.3a (min) current-limit protec- tion. during a short-circuit occurrence, the device oper- ates in an autoretry mode where the internal mosfet is turned on to check if the fault has been removed. the autoretry interval time is 15ms, and if the fault is removed, the mosfet remains on. the max4970/max4971/max4972 feature an enable input ( en ) that controls the operation of the internal nfet as well as the optional external pfet. the use of en allows the external pfet to block reverse voltages independent of any signal present at the output. the overvoltage thresholds (ovlo) are preset to 4.65v (max4972), 5.8v (max4970), or 6.35v (max4971). the undervoltage thresholds (uvlo) are preset to 2.45v. when the input voltage drops below the uvlo, the devices enter a low-current standby mode. all devices are offered in a small 12-bump, wlp pack- age and operate over the -40? to +85? extended temperature range. applications cell phones digital still cameras pdas and palmtop devices mp3 players features ? input voltage protection up to +28v ? integrated nfet switch ? reverse voltage protection with external pfet ? enable input ? preset overvoltage protection trip level 5.8v (max4970) 6.35v (max4971) 4.65v (max4972) ? low-current undervoltage-lockout mode ? short-circuit protection (autoretry) ? internal 15ms startup delay and retry times ? input-voltage power-good logic output ? thermal-shutdown protection ? 2mm x 1.5mm, 12-bump wlp package max4970/max4971/max4972 overvoltage-protection controllers with a low r on internal fet ________________________________________________________________ maxim integrated products 1 ordering information/selector guide 19-4139; rev 1; 8/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: all devices are specified over the -40? to +85? operating temperature range. + denotes a lead-free/rohs-compliant package. t = tape-and-reel package. typical operating circuit appears at end of data sheet. part pin-package top mark package code uvlo (v) ovlo ( v ) acok action max4970 ewc+t 12 wlp aaa w121a2+1 2.45 5.8 uvlo only max4971 ewc+t 12 wlp aab w121a2+1 2.45 6.35 uvlo only max4972 ewc+t 12 wlp aac w121a2+1 2.45 4.65 uvlo and ovlo pin configuration top view (bumps on bottom) max4970/max4971/max4972 out out out out gp in in gnd in in 1234 a b c wlp en acok
max4970/max4971/max4972 overvoltage-protection controllers with a low r on internal fet 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to gnd.) in ............................................................................-0.3v to +30v in-gp.........................................................................(30v - 5.4v) out.............................................................-0.3v to +(in + 0.3)v en , acok .................................................................-0.3v to +6v gp...........................................................................-0.3v to +30v continuous power dissipation (t a = +70?) for multilayer board: 12-bump wlp (derate 8.5mw/? above +70?).....678mw wlp package junction-to-ambient thermal resistance ( ja ) (note 1)...........................................118?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering) .........................................+300? note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . electrical characteristics (v in = +2.2v to +28v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units input voltage range v in 2.2 28 v t a = +25? 176 230 e n = 0v v i n = 12v ; gp cl am p on t a = t min to t max 250 t a = +25? 60 107 en = 0v v in = 5v (max4970), v in = 5.5v (max4971), v in = 3.8v (max4972) t a = t min to t max 150 input supply current i in en = 1.4v 50 100 ? uvlo supply current i uvlo v in < v uvlo ; v in = 2.2v 40 ? v in falling 2.20 2.45 2.65 in undervoltage lockout v uvlo v in rising 2.25 2.5 2.7 v in undervoltage lockout hysteresis 1% max4970 5.6 5.9 6.2 max4971 6.0 6.4 6.8 v in rising max4972 4.35 4.70 5.05 max4970 5.50 5.80 6.15 max4971 6.00 6.35 6.70 overvoltage trip level v ovlo v in falling max4972 4.30 4.65 5.00 v in overvoltage lockout hysteresis 1%
max4970/max4971/max4972 overvoltage-protection controllers with a low r on internal fet _______________________________________________________________________________________ 3 note 2: all specifications are 100% production tested at t a = +25?, unless otherwise noted. specifications are over -40? to +85? and are guaranteed by design. electrical characteristics (continued) (v in = +2.2v to +28v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units switch on-resistance r on v in = 5v (max4970), v in = 5.5v (max4971), v in = 3.8v (max4972); i out = 400ma 40 90 m overcurrent protection threshold i lim v in = 5v (max4970), v in = 5.5v (max4971), v in = 3.8v (max4972) 2.30 3.36 a gp clamp voltage v gpc v in - v gp , v in up to 28v 5.4 7.0 8.5 v gp pulldown resistor r gppd en = low, v gp = v in = 5v (max4970), v gp = v in = 5.5v (max4971), v gp = v in = 3.8v (max4972) 16 36 54 k en = high, v in = 5v 9 15 25 k en input-voltage high v ih 1.4 v en input-voltage low v il 0.4 v en input leakage current i en v en = 5v 1 a acok output-low voltage v ol i sink = 1ma 0.4 v acok high leakage current v acok = 5.5v, acok deasserted 1 a thermal shutdown +150 ? thermal-shutdown hysteresis 40 ? maximum output capacitance c out 1000 ? timing characteristics (figure 1) debounce time t indbc time from v uvlo < v in < v ovlo , r load = 100 , c load = 1? to charge-pump enable 15 ms switch turn-on time t on v uvlo < v in < v ovlo , r load = 100 , c load = 1? from en low to 90% of v out 13 ms v u v lo < v in to acok l ow ( m ax 4970/m ax 4971) acok assertion time t acok o n o o ac ok l ow ( m ax 4972) 15 ms v in < v uvlo to internal switch off 4 8 switch turn-off time t off v in > v ovlo to internal switch off, r load = 100 511 ? current limit turn-off time t blank overcurrent fault to internal switch off 10 ? autoretry time t retry from overcurrent fault to internal switch turn-on, figure 2 15 ms
max4970/max4971/max4972 overvoltage-protection controllers with a low r on internal fet 4 _______________________________________________________________________________________ 250 19 229 208 187 166 145 124 103 82 61 40 014 72128 supply current vs. supply voltage max4970/71/72 toc01 voltage (v) current ( a) 0 16 48 32 64 80 -40 35 60 10 -15 85 r on vs. temperature ax4970/71/72 toc02 temperature ( c) r on (m ) 0.990 0.996 0.994 0.992 0.998 1.000 1.002 1.004 1.006 1.008 1.010 -40 10 -15 35 60 85 normalized uvlo threshold vs. temperature ax4970/71/72 toc03 temperature ( c) normalized uvlo threshold 0.990 0.996 0.994 0.992 0.998 1.000 1.002 1.004 1.006 1.008 1.010 -40 10 -15 35 60 85 normalized ovlo threshold vs. temperature max4970/1/2 toc04 temperature ( c) normalized ovlo threshold -40 85 normalized debounce time vs. temperature max4970/71/72 toc07 temperature ( c) 10 -15 35 60 0.95 0.97 1.01 0.99 1.03 0.96 0.98 1.02 1.00 1.04 1.05 normalized debounce time 4.00 3.75 3.50 3.25 3.00 -40 10 -15 35 60 85 current limit vs. temperature max4970/1/2 toc05 temperature ( c) current limit (a) 0.95 0.97 1.01 0.99 1.03 0.96 0.98 1.02 1.00 1.04 1.05 -40 10 -15 35 60 85 max4970/71/72 toc06 temperature ( c) normalized acok assertion time normalized acok assertion time vs. temperature power-up response ax4970/71/72 toc08 10ms/div v in 5v/div v out 5v/div i out 1a/div v acok 5v/div overvoltage fault response max4970/71/72 toc09 20 s/div v in 5v/div 8v 3v v out 5v/div i out 500ma/div v acok 5v/div typical operating characteristics (t a = +25?, unless otherwise noted.)
max4970/max4971/max4972 overvoltage-protection controllers with a low r on internal fet _______________________________________________________________________________________ 5 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) pin description pin name function a1 acok active-low open-drain adapter-voltage indicator output. acok is driven low after the adapter voltage is stable between uvlo and ovlo for 15ms (typ) (max4972), or after the adapter voltage is stable and greater than uvlo for 15ms (typ) (max4970/max4971). connect a pullup resistor from acok to the logic i/o voltage of the host system. a2, a3, a4, b2 out output voltage. output of the internal switch. connect all the out outputs together for proper operation. b1 gnd ground b3, c2, c3, c4 in voltage input. bypass in with a 1? ceramic capacitor as close as possible to the device to obtain ?5kv human body model (hbm) esd protection. no capacitor is required for ?kv (hbm) esd protection. connect all the in inputs together for proper operation. b4 gp external pfet gate-drive output. gp pulls the external pfet gate down when the input is above uvlo and when en is active (low). c1 en enable input. drive en low to turn gp pulldown on, gp pullup off, and to turn on the charge pump. drive en high to turn off the device. undervoltage fault response max4970/71/72 toc10 4ms/div v in 5v/div 4v v out 5v/div i out 1a/div v acok 5v/div short-circuit fault response max4970/71/72 toc11 4 s/div v in 5v/div v out 5v/div i out 10a/div v acok 5v/div overcurrent duration time (during autoretry) max4970/71/72 toc12 4ms/div v out 2v/div i out 1a/div r load = 1 c load = 0.1 f
max4970/max4971/max4972 detailed description the max4970/max4971/max4972 overvoltage protec- tion devices feature a low r on internal fet and protect low-voltage systems against voltage faults up to +28v. if the input voltage exceeds the overvoltage threshold, the internal mosfet is turned off to prevent damage to the protected components. these devices also drive an optional external pfet to protect against reverse-polari- ty input voltages. the 15ms debounce time prevents false turn-on of the internal nfet during startup. device operation the max4970/max4971/max4972 have timing logic that control the turn-on of the internal nfet. the timing logic controls the turn-on of the charge pump and the state of the open-drain acok output. if v in < v uvlo or if v in > v ovlo , the timing logic disables the charge pump. if v uvlo < v in < v ovlo , the internal charge pump is enabled. the charge-pump startup, after a 15ms debounce delay, turns on the internal nfet (see the functional diagram ). acok is high impedance dur- ing startup until the acok 15ms debounce period expires. at this point, the device is in its on state. at any time, if v in drops below v uvlo or rises above v ovlo , the charge pump is disabled. internal nfet the max4970/max4971/max4972 incorporate an inter- nal nfet with a 40m (typ) r on . the nfet is internally driven by a charge pump that generates a 5v voltage above in. the internal nfet is equipped with 2.3a (min) current-limit protection that turns off the nfet within 10? (typ) during an overcurrent fault condition. autoretry the max4970/max4971/max4972 have an overcurrent autoretry function that turns on the nfet again after a 15ms (typ) retry time (see figure 2). the fast turn-off time and 15ms retry time result in a very low duty cycle to keep power consumption low. if the faulty load con- dition is not present, the nfet remains on. gp gate drive the gp gate drive is controlled by internal logic and by the en input. when en is high, the internal pullup between gp and in is active, thus disabling the exter- nal pfet, and the load is protected against negative voltages down to the voltage rating of the external pfet. when en is active (low), and the input voltage at in is above the uvlo threshold, the pulldown between gp and in is active, thus enabling the external pfet. overvoltage-protection controllers with a low r on internal fet 6 _______________________________________________________________________________________ overcurrent fault max4970 max4971 max4972 out in gnd charge pump 15ms debounce timer and retry time oscillator logic control v bg reference + - + - en temperature faults acok start gp r gppu r gppd en functional diagram
note that the uvlo threshold is measured at in, but the input voltage is applied at the drain of the external pfet. the body diode of the external pfet adds to the uvlo threshold increasing its value to v bodydiode + v uvlo . the internal clamp diode limits the gate to source voltage on the external pfet to 7.0v (typ) for protection of the pfet during an overvoltage fault. undervoltage lockout (uvlo) the max4970/max4971/max4972 have a 2.45v under- voltage-lockout threshold (uvlo). when v in is less than v uvlo , acok is high impedance. overvoltage lockout (ovlo) the max4970 has a 5.8v (typ) overvoltage thres- hold (ovlo), the max4971 has a 6.35v (typ) ovlo threshold, and the max4972 has a 4.65v (typ) ovlo threshold. when v in is greater than v ovlo , acok is high impedance for the max4972. max4970/max4971/max4972 overvoltage-protection controllers with a low r on internal fet _______________________________________________________________________________________ 7 ovlo uvlo t indbc t on in out gp t indbc t off t indbc 90% v out t off t off t acok t acok t acok t acok t acok t acok t acok *acok *acok timing for the max4972. **acok **acok timing for the max4970/max4971. 10% v out figure 1. max4970/max4971/max4972 timing diagram nfet on nfet off current through nfet i lim t off t retry nfet on figure 2. autoretry timing diagram
max4970/max4971/max4972 acok acok is an active-low, open-drain output that asserts low when v uvlo < v in < v ovlo for 15ms (typ) for the max4972. acok asserts low when v in > v uvlo for 15ms (typ) for the max4970 and max4971. connect a pullup resistor from acok to the logic i/o voltage of the host system. during a short-circuit fault, acok may deassert due to v in dropping below v uvlo from high current. thermal-shutdown protection the max4970/max4971/max4972 feature thermal- shutdown circuitry. the internal nfet turns off when the junction temperature exceeds +150? (typ). the device exits thermal shutdown after the junction temperature cools by 40? (typ). applications information reverse polarity protection the optional external p-channel mosfet can provide reverse polarity protection down to the voltage rating of the pfet. in bypass capacitor for most applications, bypass in to gnd with a 1? ceramic capacitor as close as possible to the device to enable ?5kv (hbm) esd protection on the pin. if the external pfet is used, the 1uf capacitor must be con- nected between the drain and ground. if ?5kv (hbm) esd is not required, there is no capacitor required at in. if the power source has significant inductance due to long lead length, take care to prevent overshoots due to the lc tank circuit and provide protection if nec- essary to prevent exceeding the +30v absolute maxi- mum rating on in. out output capacitor the slow turn-on time provides a soft-start function that allows the max4970/max4971/max4972 to charge an output capacitor up to 1000? without turning off due to an overcurrent condition. esd test conditions esd performance depends on a number of conditions. the max4970/max4971/max4972 are specified for ?5kv (hbm) typical esd resistance on in when in is bypassed to ground with a 1? ceramic capacitor. hbm esd protection figure 3 shows the human body model, and figure 4 shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest, which is then discharged into the device through a 1.5k resistor. overvoltage-protection controllers with a low r on internal fet 8 _______________________________________________________________________________________ charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test figure 3. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 4. human body current waveform
max4970/max4971/max4972 overvoltage-protection controllers with a low r on internal fet maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. package type package code document no. 12 wlp w121a2+1 21-0009 in gp out max4970 max4971 max4972 phone load en vbus micro- controller usb connector gnd charger optional pfet 1 f acok v i/o typical operating circuit chip information process: bicmos package information for the latest package outline information, go to www.maxim-ic.com/packages .
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