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designed to provide the power supply requirements of next generation car audio and infotainment systems, the a8590 provides all the control and protection circuitry to produce a high current regulator with 1.0% output voltage accuracy. the a8590 employs pulse frequency modulation (pfm) to draw less than 50 a from 12 v in while supplying 3.3 v/40 a. after startup, the a8590 operates down to at least 3.6 v in (v in falling). features of the a8590 include a pwm/ pfm mode control input to enable pwm (logic high) or pfm (logic low). if the pwm/ pfm input is driven by an external clock signal higher than the base frequency (f osc ) the pwm frequency synchronizes to the incoming clock frequency. the sleep input pin commands an ultra-low current shutdown mode requiring less than 5 a for internal circuitry and 10 a (max) for mosfet leakage at 16 v in , 85oc. the a8590 has external compensation to accommodate a wide range of frequencies and external components, and provides a power-on reset (npor) signal validated by the output voltage. the a8590 utilizes enhanced a8590-ds, rev. 2 ? automotive aec-q100 qualified ? w ithstands surge voltages up to 40 v ? operates as low as 3.4 v in (typ) with v in decreasing ? utilizes pulse frequency modulation (pfm) to draw only tens of microamperes from vin while maintaining keep- alive vout ? pwm/ pfm mode control input pin ? delivers up to 3.0 a of output current with integrated 110 m high voltage mosfet ? sleep input pin commands ultra-low current shutdown mode ? adjustable output voltage with 1.0% accuracy from 0cto 85c, 1.5% from C40c to 150c ? programmable switching frequency: 250 khz to 2.4 mhz ? synchronization capability: applying a clock input to thepwm/ pfm input pin will increase the pwm frequency wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output package: 16-pin tssop with exposed themal pad (suffix lp) typical application diagram a8590 v in en mode c in c p r z c z c ss r fset c vreg 1 2 5 13 9 3 8 12 4 6 vin vin gnd comp ss fset vreg sleep pwm/pfm npor fb bias sw sw boot 16 15 14 11 10 7 c boot l 0 d 1 r fb2 r fb1 c fb 3.3 v r pu 10 k vout c o a8590 continued on next page... features and benefits description not to scale applications ? automotive: instrument clusters audio systems ? home audio navigation hv ac continued on next page...
2 selection guide part number operating ambient temperature range ta, (oc) packing A8590KLPTR-T C40 to 125 4000 pieces per 13-in. reel idle/stop-start recovery technique to reduce or eliminate output overshoot when v in recovers from levels below v in minimum (i.e. v out drops out of regulation). extensive protection features of the a8590 include pulse-by-pulse current limit, hiccup mode short circuit protection, open/short asynchronous diode protection, boot open/short voltage protection, v in undervoltage lockout, v out overvoltage protection and thermal shutdown. the a8590 is supplied in a low profile 16-pin tssop package with exposed power pad (suffix lp). it is lead (pb) free, with 100% matte-tin leadframe plating. ? active low , power-on reset (npor) open-drain output ? maximized duty cycle for low dropout enhanced recovery idle-stop transients ? pre-bias startup capable, vout will not cause a reset ? external compensation for maximum flexibility ? stable with ceramic or electrolytic output capacitors ? excellent set of protection features to satisfy the most demanding applications ? overvoltage, pulse-by-pulse current limit, hiccup mode short circuit, and thermal protection ? robust fmea, with pin open/short and component faults ? thermally enhanced, surface mount package features and benefits description table of contents specifications 3 absolute maximum ratings 3 thermal characteristics 3 functional block diagram 4 pin-out diagram and terminal list table 5 electrical characteristics 6 characteristic performance 10 functional description 12 overview 12 reference v oltage 12 pwm switching frequency 12 sleep input 12 pwm/ pfm input and pwm synchronization 13 bias input functionality , ratings, and connections 13 t ransconductance error amplifier 13 slope compensation 14 current sense amplifier 14 power mosfet s 14 boot regulator 14 pulse width modulation (pwm) mode 14 maximized duty cycle control 15 low-iq pulse freqency modulation (pwm) mode 15 reduced current (low-ip) pwm mode 17 soft start (startup) and inrush current control 17 pre-biased startup 18 not power-on reset (npor) output 18 protection features 19 undervoltage lockout (uvlo) 19 pulse-by-pulse overcurrent protection (ocp) 19 ocp and hiccup mode 20 boot capacitor protection 20 asynchronous diode protection 20 output overvoltage protection (ovp) 21 pin-to-ground and pin-to-pin short protections 21 thermal shutdoawn (tsd) 21 application information 25 design and component selection 25 setting the output v oltage (v out ) 25 pwm base switching frequency (f osc , r fset ) 26 output inductor (l o ) 26 output capacitors 27 low-iq pfm output v oltage ripple calculation 28 input capacitors 28 asynchronous diode (d1) 29 bootstrap capacitor 29 soft start and hiccup mode timing (c ss ) 29 compensation components (rz, cz, and cp) 30 a generalized tuning procedure 32 power dissipation and thermal calculations 34 pcb component placement and routing 35 package outline drawing 37 wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 absolute maximum ratings* characteristic symbol notes rating unit vin, sleep, ss pin voltage C0.3 to 40 v sw pin voltage v sw continuous (minimum limit is a function of temperature) C0.3 to v in + 0.3 v t < 50 ns C1.0 to v in + 0.3 v boot pin voltage v boot continuous v sw C 0.3 to v sw + 5.5 v boot ov fault condition v sw C 0.3 to v sw + 7.0 v bias pin voltage v bias continuous C0.3 to 5.5 v bias ov fault condition C0.3 to 6 v all other pin voltages C0.3 to 5.5 v operating ambient temperature t a k temperature range C40 to 125 oc maximum junction temperature t j(max) 150 oc storage temperature t stg C55 to 150 oc *operation at levels beyond the ratings listed in this table may cause permanent damage to the device. the absolute maximum ratingsare stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reliability. thermal characteristics (may require derating at maximum conditions, see application information) characteristic symbol test conditions* value unit package thermal resistance r qja on 4-layer pcb based on jedec standard 34 oc/w *additional thermal information available on the allegro website. specifications wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 vin vreg sleep fset pwm/pfm fb ldo vreg ldo off delay 84 s 2.90 v bg 1.205 v por digital 3.6 v bias > ldo + 50 mv out uvlo 5.75 v regov 5.0 v q boot reg boot off en boot reg boot off boot fault oc 250 ma g csa 2x pwml i sense pwm 400 mv pwm bias boot 2 v, 4.1 v sw diodeok vreg boot < 4.1 v current comp pfm 750 ma q q s q r blankon minoff f f/2 f/4 f > 1.2x sleep pwm delay 2048 pfm controller idle/start recovery control fb < 0.8 v fb < 0.2 v fb < 0.4 v i fb error ampli?er 800 mv sleep pwm sleep pwm sleep pwm 400 mv sleep pwm clamp ocl fb < 700 mv fb < 700 mv fb < 740 mv fb < 880 mv fb > 880 mv ocl diodeok boot fault regov uvlo por tsd hic set hic rst pull down boot off hiccup logic hiccup 20 a 5 a 1 k? 2 k? comp ss npor delay 7.5 ms tg maxduty maxduty bg swlodet compfalling ssdischarge off swlodet fault logic (see fault table) functional block diagram wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 terminal list table name number function bias 11 bias input, supplies internal circuitry. boot 16 high-side gate drive boost input. this pin supplies the drive for the high-side n-channel mosfet. connect a 47 nf ceramic capacitor from boot to sw. comp 9 output of the error amplifier and compensation node for the current mode control loop. connect a series rc network from this pin to gnd for loop compensation. see the design and component selection section of this datasheet for further details. fb 10 feedback (negative) input to the error amplifier. connect a resistor divider from the regulator output, vout, to this pin to program the output voltage. fset 8 frequency setting pin. a resistor, r fset , from this pin to gnd sets the base pwm switching frequency (f osc ). see the design and component selection section for information on determining the value of r fset . gnd 5, 13 ground pins. npor 7 active low, power-on reset output signal. this pin is an open drain output that transitions from low to high impedance after the output has maintained regulation for t d(npor ). pad C exposed pad of the package providing enhanced thermal dissipation. this pad must be connected to the ground plane(s) of the pcb with at least 6 vias, directly in the pad land. pwm/pfm 6 sets operating output mode (f sw ). setting this pin low forces low-iq pfm mode (f sw set by load). setting this pin high forces pwm mode switching at the the base frequency (f osc ), set by r fset . applying an external clock input to this pin forces synchronization of pwm to the clock input rate (f sync ), at a rate higher than f osc . sleep low overrides this pin. sleep 4 setting this pin low forces sleep mode (very low current shutdown mode: vout = 0 v). this pin must be set high to enable the a8590. if the application does not require a sleep mode, then this pin can be tied directly to vin. do not float this pin ss 3 soft start and hiccup pin. connect a capacitor, c ss , from this pin to gnd to set soft start mode duration. the capacitor also determines the hiccup period during overcurrent. sw 14, 15 the source of the high-side n-channel mosfet. the external free-wheeling diode (d1) and output inductor (l o ) should be connected to this pin. both d1 and l o should be placed close to this pin and connected with relatively wide traces. vin 1, 2 power input for the control circuits and the drain of the high-side n-channel mosfet. connect this pin to a power supply providing from 4.0 to 35 v. a high quality ceramic capacitor should be placed and grounded very close to this pin. vreg 12 internal voltage regulator bypass capacitor pin. connect a 1 f ceramic capacitor from this pin to ground and place it very close to the a8590. 1 boot vin 2 sw vin 3 sw ss 4 gnd sleep 5 vreg gnd 6 bias npor pwm/pfm 7 8 fb comp fset 9 10 11 12 13 14 15 16 pa d package lp, 16-pin tssop pin-out diagram pin-out diagram and terminal list table wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 characteristics symbol test conditions min. typ. max. unit input voltage input voltage range 1 v in 4.0 C 35 v vin uvlo start v inuv(on) v in rising 3.6 3.8 4.0 v vin uvlo stop v inuv(off) v in falling 3.2 3.4 3.6 v vin uvlo hysteresis v inuv(hys) C 400 C mv input supply current sleep mode input supply current 2,5 i in(sleep) v sleep 0.5 v, t j = 85oc, v in = 16 v C 5 15 a v sleep 0.5 v, t j = 85oc, v in = 35 v C 7 25 a pwm mode input supply current 2 i in(pwm) v bias > 3.2 v, i out = 0 ma C 2.5 5.0 ma low-iq pfm input supply current 2.3 i lo_iq(1) v in = 12 v, v out = 3.3 v, v pwmpfm 0.8 v, i out = 40 a, t a = 25oc, components selected per table 3 C C 50 a v in = 12 v, v out = 5.0 v, v pwmpfm 0.8 v, i out = 200 a, t a = 25oc, components selected per table 3 C C 250 a v in = 12 v, v out = 6.5 v, v pwmpfm 0.8 v, i out = 1 ma, t a = 25oc, components selected per table 3 C C 750 a voltage regulation feedback voltage accuracy 4 v fb 0oc < t j < 85oc, v in 4.1 v, v fb = v comp 792 800 808 mv C40oc < t j < 150oc, v in 4.1 v, v fb = v comp 788 800 812 mv low-iq pfm mode output voltage setting range 1,3 v out(lo_iq) 3.0 v < v bias < 5.5 v and i lo_iq specifications satisfied 3.3 C 6.5 v pwm output voltage setting range 3 v out v bias = gnd, pwm only, no pfm mode 0.8 C 10 v output dropout voltage 3 v out(sat) t a = 85c, dcr lo 75 m, v in = 3.6 v, i out = 1 a, f sw = 425 khz 3.27 3.295 C v t a = 85c, dcr lo 75 m, v in = 5.3 v, i out = 1 a, f sw = 425 khz 4.95 5.0 C v t a = 85c, dcr lo 50 m, v in = 3.75 v, i out = 1 a, f sw = 2 mhz 3.25 3.3 C v t a = 85c, dcr lo 50 m, v in = 5.5 v, i out = 1 a, f sw = 2 mhz 4.89 5.0 C v low-iq pfm mode ripple voltage 3 v out(lo_iq) 8 v < v in < 12 v, components selected per table 3 C 30 65 mv pp low-iq pfm mode peak current threshold i peak(lo_iq) f sw < 750 khz C 750 C ma peak f sw < 750 khz C 850 C ma peak low-iq pfm mode dc load current 3 i out(lo_iq) maximum load to maintain v out(lo_iq) , components selected per table 3 400 550 700 ma electrical characteristics : valid at 4.0 v v in 35 v; C40oc t a = t j 150oc; unless otherwise specifed. continued on next page... 1 thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, pcb layout, and airfow . 2 negative current is defned as coming out of the node or pin, positive current is defned as going into the node or pin. 3 ensured by design and characterization, not production tested. 4 performance at the 0c and 85c ranges ensured by design and characterization, not production tested. 5 performance at 85c ensured by design and characterization, not production tested. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 characteristics symbol test conditions min. typ. max. unit error amplifier feedback input bias current 7 i fb C38 C C16 na open loop voltage gain a vol v comp = 1.2 v C 65 C db transconductance g m 400 mv < v fb 500 750 950 a/v 0 v < v fb < 400 mv 275 375 475 a/v output current i ea v comp = 1.2 v C 75 C a comp pull-down resistance r comp fault = 1 or hiccup = 1 C 1 C k pulse width modulation (pwm) pwm ramp offset pwm offs v comp level required for 0% duty cycle C 400 C mv minimum controllable pwm on-time t on(min)pwm 12 v < v in < 16 v, i out = 1 a, v boot C v sw = 4.5 v C 95 135 ns minimum switch off-time t off(min)pwm C 95 130 ns comp to sw current gain g mpower C 4.0 C a/v slope compensation 8 s e f osc = 2.44 mhz 2.31 3.30 4.30 a/s f osc = 1.00 mhz 0.66 1.00 1.32 a/s f osc = 252 khz 0.15 0.22 0.29 a/s mosfet parameters 6 high-side mosfet on-resistance 9 r ds(on)hs t j =25oc, v boot C v sw = 4.5 v, i ds = 0.4 a C 110 125 m t j =150oc, v boot C v sw = 4.5 v, i ds = 0.4 a C 190 215 m high-side mosfet leakage 7,10 i lkg(hs) t j < 85c, v sleep 0.5 v, v sw = 0 v, v in = 16 v C C 10 a t j 150c, v sleep 0.5 v, v sw = 0 v, v in = 16 v C 60 150 a sw node slew rate 8 sr sw 12 v < v in < 16 v C 0.72 C v/ns low-side mosfet on-resistance 9 r ds(on)ls t j = 25oc, v in 6 v, i ds = 0.1 a C C 10 pwm switching frequency base pwm switching frequency f osc r fset = 8.06 k, v pwm/pfm = high 2.20 2.44 2.70 mhz r fset = 23.7 k, v pwm/pfm = high 0.90 1.00 1.10 mhz r fset = 102 k, v pwm/pfm = high C 252 C khz pwm synchronization timing synchronization frequency range f sync(mult) 1.2 f osc (typ) C 1.5 f osc (typ) C synchronized pwm frequency f sync(pwm) C C 2.9 mhz synchronization input duty cycle d sync C C 80 % synchronization input pulse width t wsync 200 C C ns synchronization input rise time 8 t rsync C 10 15 ns synchronization input fall time 8 t fsync C 10 15 ns electrical characteristics (continued) : valid at 4.0 v v in 35 v; C40oc t a = t j 150oc; unless otherwise specifed. continued on next page... 6 thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, pcb layout, and airfow . 7 negative current is defned as coming out of the node or pin, positive current is defned as going into the node or pin. 8 ensured by design and characterization, not production tested. 9 performance at 25c ensured by design and characterization, not production tested. 10 performance at 85c ensured by design and characterization, not production tested. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 characteristics symbol test conditions min. typ. max. unit pwm/pfm pin input thresholds pwm/pfm high threshold v pwmpfm(h) 3.0 v < v bias < 3.6 v, v pwmpfm rising C C 2.0 v 4.5 v < v bias < 5.5 v, v pwmpfm rising C C 2.6 v pwm/pfm low threshold v pwmpfm(l) 3.0 v < v bias < 3.6 v, v pwmpfm falling 0.8 C C v 4.5 v < v bias < 5.5 v, v pwmpfm falling 1.2 C C v pwm/pfm hysteresis v pwmpfmhys 3.0 v < v bias < 3.6 v, v pwmpfm(h) C v pwmpfm(l) C 200 C mv 4.5 v < v bias < 5.5 v, v pwmpfm(h) C v pwmpfm(l) C 400 C mv pwm/pfm input resistance r pwmpfm 120 200 280 k low-iq pfm transition delay t d(lo_iq) pwm/pfm = low, v ss > hic/pfm en , npor = high C 2048 C counts pfm mode timing constant pfm off-time t off(pfm) f osc < 1.5 mhz C 435 C ns f osc > 1.5 mhz C 275 C ns maximum pfm on-time t on(pfm)max C 4.1 C s sleep pin input thresholds sleep high threshold v sleep(h) v sleep rising C 1.3 2.1 v sleep low threshold v sleep(l) v sleep falling 0.5 1.2 C v sleep delay t d(sleep) v sleep transitioning low 55 103 150 s sleep input bias current i sleepbias v sleep = 5 v C 500 C na vreg pin output vreg output voltage v vreg v bias = 0 v C 3.05 C v bias input voltage range v bias 3.2 C 5.5 v boot regulator boot voltage enable threshold v boot(en) v boot rising 1.7 2.0 2.2 v boot voltage enable hysteresis v boot(hys) C 200 C mv boot voltage low-side switch disable threshold v bootls(dis) v boot rising C 4.1 C v soft start pin fault, hiccup reset voltage v ssrst v ss falling due to rss(flt) C 200 275 mv hiccup ocp (and low iq pfm counter enable) threshold hic/pfm en v ss rising C 2.3 C v maximum charge voltage v ss(max) C v vreg C C startup (source) current i sssu hiccup = fault = 0 C30 C20 C10 a hiccup (sink) current i sshic hiccup = 1 2.4 5 10 a pull-down resistance r ss(flt) fault = 1 or v sleep = low C 2 C k electrical characteristics (continued) : valid at 4.0 v v in 35 v; C40oc t a = t j 150oc; unless otherwise specifed. continued on next page... wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 characteristics symbol test conditions min. typ. max. unit soft start pin (continued) soft start frequency foldback f sw(ss) 0 v < v fb < 200 mv C f ocs /4 C C 200 mv < v fb < 400 mv C f ocs /2 C C 400 mv < v fb C f ocs C C soft start delay time 12 t d(ss) c ss = 22 nf C 440 C s soft start output ramp time 12 t ss c ss = 22 nf C 880 C s hiccup modes hiccup, ocp count ocp lim v ss > 2.3 v and ocl = 1 C 120 C counts hiccup, boot undervoltage (shorted) count boot uv C 120 C counts hiccup, boot overvoltage (open) count boot ov C 7 C counts overcurrent protection (ocp) pwm pulse-by-pulse limit i lim(tonmin) t on = t on(min)pwm 4.8 5.5 6.1 a i lim(tonmax) t on = (1/f sw ) C t off(min)pwm , no pwm synchronization 3.0 4.1 5.1 a output voltage protection (ovp) vout overvoltage pwm threshold v out(ov)pwm v fb rising, pwm mode 860 880 902 mv vout overvoltage hysteresis v out(ov)hys v fb falling, relative to v out(ov)pwm C C10 C mv vout undervoltage pwm threshold v out(uv)pwm v fb falling, pwm mode 715 740 765 mv vout undervoltage hysteresis v out(uv)hys v fb rising, relative to v out(uv)pwm C 10 C mv vout undervoltage pfm threshold v out(uv)pfm v fb falling, low-iq pfm mode 665 700 735 mv power-on reset (npor) output npor rising delay t d(npor) v fb rising only 5 7.5 10 ms npor low output voltage v npor(l) i npor = 5 ma C 185 400 mv npor leakage current 11 i npor(lkg) v npor = 5.5 v C1 C 1 a thermal protection thermal shutdown rising threshold 12 t sd pwm stops immediately and comp and ss are pulled low 155 170 185 oc thermal shutdown hysteresis 12 t sdhys C 20 C oc electrical characteristics (continued) : valid at 4.0 v v in 35 v; C40oc t a = t j 150oc; unless otherwise specifed. 11 negative current is defned as coming out of the node or pin, positive current is defned as going into the node or pin. 12 ensured by design and characterization, not production tested. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 characteristic performance 808 806 804 802 800 798 796 794 792 -50 -25 02 55 0 75 100 125 150 temperature (oc) v (mv) vref reference voltage versus temperature 3.50 3.00 2.50 2.00 1.50 1.00 0.20 -50 -25 02 55 0 75 100 125 150 temperature (oc) f (mhz) osc f= 2.44 mhz osc f= 1.00 mhz osc switching frequency versus temperature vin uvlo start and stop thresholds versus temperature v out overvoltage and undervoltage thresholds versus temperature 3.9 3.8 3.7 3.6 3.5 3.4 3.3 -50 -25 02 55 0 75 100 125 150 temperature (oc) vin uvlo thresholds (v) start, v inuv(on) stop, v inuv(off) 950 900 850 800 750 700 650 -50 -25 02 55 0 75 100 125 150 temperature (oc) v ov and uv thresholds (v) out v out(ov)pwm v out(uv)pwm v out(uv)pfm pulse-by-pulse current limit at t on(min)pwm (i lim(tonmin) ) versus temperature error amplifer transconductance versus temperature 6.0 6.2 4.8 5.6 5.8 5.4 5.2 5.0 -40 -20 02 55 0 75 125 100 150 temperature (oc) i (a) lim(tonmin) 900 800 700 600 500 400 300 200 100 -50 -25 02 55 0 75 100 125 150 temperature (oc) transconductance (a/v) v> 400 mv fb v< 400 mv fb wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 1.60 1.55 1.50 1.45 1.40 1.30 1.35 1.25 1.20 1.15 -50 -25 02 55 0 75 100 125 150 temperature (oc) pwm/ thresholds (v) pfm v pwmpfm(h) v pwmpfm(l) pwm/pfm high and low voltage thresholds versus temperature, v bias = 3.3 v 2.3 2.2 2.1 2.0 1.8 1.9 1.7 1.6 -50 -25 02 55 0 75 100 125 150 temperature (oc) pwm/ thresholds (v) pfm v pwmpfm(h) v pwmpfm(l) pwm/pfm high and low voltage thresholds versus temperature, v bias = 5.0 v sleep high and low voltage thresholds thresholds versus temperature ss start and hiccup currents versus temperature 1.60 1.40 1.20 1.00 0.80 0.60 -50 -25 02 55 0 75 100 125 150 temperature (oc) sleep thresholds (v) v sleep(h) v sleep(l) 25.0 20.0 15.0 10.0 5.0 0 -50 -25 02 55 0 75 100 125 150 temperature (oc) current (a) startup, i sssu hiccup, i sshic npor low output voltage at 5 ma versus temperature npor time delay versus temperature 250 400 200 350 150 300 100 50 0 -50 -25 02 55 0 75 100 125 150 temperature (oc) v (mv) npor 7.50 8.00 7.40 7.70 7.80 7.90 7.30 7.60 7.20 7.10 7.00 -50 -25 02 55 0 75 100 125 150 temperature (oc) t (ms) d(npor) wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 functional description overview the a8590 is an asynchronous, current mode, buck regulator that incorporates all the control and protection circuitry necessary to provide the power supply requirements of car audio and infotain- ment systems. the a8590 has three modes of operation. first, the a8590 can deliver up to 3.0 a in pulse width modulation (pwm) mode. second, in low-iq pulse frequency modulation (pfm) mode, the a8590 will draw only tens of microamperes from v in while maintaining v out (at no load). under most conditions, low-iq pfm mode is typically capable of supporting up to 550 ma. third, with the sleep pin low, the a8590 will enter an ultra-low current shutdown (sleep) mode where v out = 0 v and the total current drawn from v in will typically be less than 10 a. the pwm/pfm input pin is used to select either pwm or low- iq pfm mode. in pfm mode the a8590 is able to supply a relatively high amount of current (typically 550 ma). this allows enough current for a microcontroller or dsp to fully power-up. after power-up, to obtain the full current capability of the a8590, the microcontroller or dsp must change the pwm/ pfm input from a logic low to a logic high to force pwm mode. this will provide full current to the remainder of the system. the a8590 was designed to support up to 3.0 a. however, the exact amount of current it will supply, before possible thermal shutdown, depends heavily on: duty cycle, ambient temperature, airflow, pcb layout, and pcb construction. figure 1 shows calculated current ratings versus ambient temperature for v in = 12 v, and v out = 3.3 v and 5.0 v, at both f sw = 425 khz and f sw = 2 mhz. this analysis assumed a 4-layer pcb constructed according to the jedec standard (vielding a thermal resistance of 34c/w), with no nearby heat sources, and no airflow. reference voltage the a8590 incorporates an internal reference that allows output voltages (v out ) as low as 0.8 v. the accuracy of the internal reference is 1.0% from 0c to 85c and 1.5% from ?40c to 150c. the output voltage is programmed by connecting a resis- tor divider from vout to the fb pin of the a8590, as shown in the typical applications schematics. pwm switching frequency the pwm switching frequency of the a8590 is adjustable from 250 khz to 2.4 mhz and has an accuracy of about 10% across the operating temperature range. during startup, the pwm switching frequency changes from 25% to 50% and finally to 100% of f osc , as v out rises from 0 v to the regulation voltage. the startup switching frequency is dis- cussed in more detail in the section describing soft start, below. if the regulator output is shorted to ground, v fb 0 v, the pwm frequency will be 25% of f osc . in this case, the extra low switch- ing frequency allows extra off-time between sw pulses. the extra off-time allows the output inductor current to decay back to 0 a before the next sw pulse occurs. this prevents the inductor current from climbing to a value that could damage the a8590 or the output inductor. sleep input the a8590 has a sleep logic level input pin. to get the a8590 to operate, the sleep pin must be a logic high (>2.1 v). the sleep pin is rated to 40 v, allowing the sleep pin to be con- nected directly to vin if there is no suitable logic signal available to wake up the a8590. when sleep transitions low, the a8590 waits approximately 103 s before shutting down. this delay provides plenty of filtering to prevent the a8590 from prematurely entering sleep mode because of any small glitch coupling onto the pcb trace or sleep pin. 2.00 3.25 1.75 2.50 2.75 3.00 1.50 2.25 1.25 1.00 0.75 65 75 85 95 105 11 5 125 135 ambient temperature (oc) current rating (a) 12 v, 5 v, 425 khz in o 12 v, 5 v, 2 mhz in o 12 v, 3.3 v, 425 khz in o 12 v, 3.3 v, 2 mhz in o figure 1: a8590 typical current derating wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 pwm/pfm input and pwm synchronization the pwm/pfm pin provides two major functions. it is a control input that sets the operating mode, and also an optional clock input for setting pwm frequency. if pwm/ pfm is a logic high, the a8590 operates in pwm mode. if pwm/ pfm is a logic low, the a8590 operates in low-iq pfm (keep alive) mode. when pwm/ pfm transitions from logic high to logic low, the a8590 checks for v ss >2.3 v and npor at logic high. if these two conditions are satisfied, then the a8590 will wait 2048 internal clock cycles and then enter low-iq pfm mode. this delay provides plenty of filtering to prevent the regu- lator from prematurely entering pfm mode because of any small glitch coupling onto the pcb trace or pwm/ pfm pin. also, note that the sleep pin must be a logic high or the pwm/ pfm input has no effect. the interaction between the sleep pin and pwm/ pfm pin is summarized in table 1. table 1: a8590 modes of operation pin inputs operating mode sleep pwm/pfm name description low dont care sleep v out = 0 v high high pwm f sw = f osc v out = ok and i out 3.0 a high f sw = pwm/pfm clock in high enter low-iq pfm after 2048 cycles, if v ss > 2.3 v (typ) and npor = high high low low-iq pfm f sw is vout dependent v out = ok and i out 550 ma (typ) high :ow low-ip pwm fault, i lim at 50% if an external clock is applied to the pwm/ pfm pin, the a8590 synchronizes its pwm frequency to the external clock. the external clock may be used to increase the a8590 base pwm frequency (f osc ) set by r fset . synchronization operates from 1.2 f osc (typ) to 1.5 f osc (typ) . the external clock pulses must satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the electrical characteristics table in this datasheet. bias input functionality, ratings, and con- nections when the a8590 is powering up, it operates from an internal ldo regulator, directly from vin. however, v in can be a rela- tively high voltage and an ldo is very inefficient and generates extra heat. to improve efficiency, especially in low-iq pfm mode, a bias pin is utilized. for most applications, the bias pin should be connected directly to the output of the regulator, v out . when v out rises to an adequate level (approximately 3.1 v), the a8590 will shut down the inefficient ldo and begin running its control circuitry directly from the output of the regulator. this makes the a8590 much more efficient and cooler. the bias pin is designed to operate in the range from 3.2 to 5.5 v. if the output of the regulator is in this range then v out should be routed directly to the bias pin. however, if the output of the regulator is above 5.6 v then a very small ldo, capable of at least 5 ma, must be used to reduce the voltage to either 3.3 v or 5.0 v before routing it to the bias pin. operating with an exter - nal ldo will reduce the efficiency in low-iq pfm mode. the bias pin may be driven by an external power supply. for startup, there are no sequencing requirements between vin and bias. however, for shutdown, vin should be removed before bias. if bias is removed before vin it will cause the a8590 to reset. the reset will cause the a8590 to terminate pwm switch- ing and v out will decay. also, npor, v ss , and v comp will be pulled low. ideally, the sleep pin should be used to set the mode of the a8590 before vin and/or bias are turned on or off. if the bias pin is grounded, the a8590 will simply operate continuously from vin. however, during pfm mode, the input current will increase and the pfm efficiency will be significantly reduced. transconductance error amplifier the transconductance error amplifier primary function is to con- trol the regulator output voltage. the error amplifier is shown in figure 2. here, it is shown as a three-terminal input device with two positive and one negative input. the negative input is simply connected to the fb pin and is used to sense the feedback voltage for regulation. the two positive inputs are used for soft start and steady-state regulation. the error amplifier performs an analog or selection between its two positive inputs. the error amplifier regulates to either the soft start pin voltage (minus 400 mv) or the a8590 internal reference, v ref , whichever is lower. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
14 to stabilize the regulator, a series rc compensation network (rz and cz) must be connected from the error amplifier output (the comp pin) to gnd, as shown in the typical applications schematics. in most instances an additional, relatively low value, capacitor (cp) should be connected in parallel with the rz-cz components to reduce the loop gain at very high frequencies. however, if the cp capacitor is too large, the phase margin of the regulator may be reduced. calculating rz, cz, and cp is covered in detail in the component selection section of this datasheet. if a fault occurs or the regulator is disabled (sleep = low), the comp pin is pulled to gnd via approximately 1 k and pwm switching is inhibited. slope compensation the a8590 incorporates internal slope compensation (s e ) to allow pwm duty cycles above 50% for a wide range of input/out- put voltages and inductor values. the slope compensation signal is added to the sum of the current sense amplifier output and the pwm ramp offset. as shown in the electrical characteristics table, the amount of slope compensation scales with the base switching frequency set by r fset (f osc ). the amount of slope compensation does not change when the regulator is synchro- nized to an external clock. the value of the output inductor should be chosen such that s e is from 0.5 to 1 the falling slope of the inductor current (s f ). current sense amplifier the a8590 incorporates a high-bandwidth current sense ampli- fier to monitor the current in the high-side mosfet. this current signal is used by both the pwm and pfm control circuitry to regulate the peak current. the current signal is also used by the protection circuitry to prevent damage to the a8590. power mosfets the a8590 includes a 40 v, 110 m high-side n-channel mosfet, capable of delivering at least 3.0 a. the a8590 also includes a 10 , low-side mosfet to help ensure the boot capacitor is always charged. the typical r ds(on) increase versus temperature is shown in figure 3. fb pin v ref 800 mv ss pin 400 mv error ampli?er comp pin figure 2: a8590 error amplifer 1.2 1.8 1.0 1.6 0.8 1.4 0.6 0.4 0.2 0.0 -40 -20 02 04 05 0 80 100 120 160 140 temperature (oc) normalized r ds(on) figure 3: typical mosfet r ds(on) versus temperature boot regulator the a8590 contains a regulator to charge the boot capacitor. the voltage across the boot capacitor is typically 5.0 v. if the boot capacitor is missing, the a8590 detects a boot over- voltage. similarly, if the boot capacitor is shorted the a8590 detects a boot undervoltage. also, the boot regulator has a current limit to protect itself during a short circuit condition. the details of how each type of boot fault is handled by the a8590 are shown in figures 13 and 14 and summarized in table 2. pulse width modulation (pwm) mode the a8590 utilizes fixed-frequency, peak current mode control to provide excellent load and line regulation, fast transient response, and ease of compensation. a high-speed comparator and control logic, capable of typical pulse widths of 95 ns, are included in the a8590. the inverting input of the pwm comparator is connected to the output of the error amplifier. the non-inverting input is connected to the sum of the current sense signal, the slope com- pensation, and a dc offset voltage (v pwmoffs , 400 mv (typ) ).at the beginning of each pwm cycle, the clk signal sets the pwm flip flop and the high-side mosfet is turned on. when the summation of the dc offset, slope compensation, and current sense signal rises above the error amplifier voltage, the pwm flip flop is reset and the high-side mosfet is turned off. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
15 the pwm flip flop is reset-dominant, so the error amplifier may override the clk signal in certain situations. for example, at very light loads or extremely high input voltages the error amplifier reduces (temporarily) output voltage below the 400 mv dc offset and the pwm flip flop will ignore one or more of the incoming clk pulses. the high-side mosfet will not turn on, and the regulator will skip pulses to maintain output voltage regulation. in pwm mode all of the a8590 fault detection circuits are active. see figure 13 for a timing diagram showing how faults are han- dled when in pwm mode. also, the protection features section of this datasheet provides a detailed description of each fault and table 2 presents a summary. maximized duty cycle control most fixed frequency pwm controllers have limited maximum duty cycle. this is due to the off-time required to keep the charge pump capacitor charged in order to drive the high-side n-channel mosfet. this limitation becomes significant in high-frequency, low-input regulators. it may cause the output to drop out of regu- lation during stop/start profiles in automotive designs. the a8590 employs a technique that helps extend the maximum duty cycle. without this technique the typical maximum duty cycle would be 74% at 2 mhz switching frequency. utilizing the extend duty cycle technique, the a8590 can achieve typical duty cycles of greater than 95% in 2 mhz designs. low-iq pulse frequency modulation (pfm) mode the a8590 enters low-iq pfm mode after 2048 internal clock cycles, if sleep is high, vss > hic/pfm en (2.3 v (typ)), and npor is high. in low-iq pfm mode, the regulator operates with a switching frequency, f sw , that depends on the load condition. in low-iq pfm mode, a comparator monitors the voltage at the fb pin. if v fb is above about 800 mv, the a8590 remains in coast mode and draws extremely low current from the input supply. if the voltage at the fb pin drops below about 800 mv, the a8590 will fully power-up, delay approximately 2.5 s while it wakes up, and then turn on the high-side mosfet. v out will rise at a rate dependent on the input voltage, inductor value, output capacitance, and load. the high-side mosfet will be turned off when either: ? current in the high-side mosfet reaches i peak(lo_iq) , or ? the high-side mosfet has been on for t on(pfm)max . after the high-side mosfet is turned off, the a8590 will again delay approximately t off(pfm) and either: ? turn on the mosfet again, if v fb < 800 mv, or ? return to the low-iq pfm mode figures 4 and 5 demonstrate low-iq pfm mode operation for a light load (66 ma) and a heavy load (330 ma), respectively . in low-iq pfm mode the average current drawn from the input supply depends primarily on both the load, and how often the a8590 must fully power-up to maintain regulation. in low-iq figure 4: low-iq pfm mode operation at v in = 12 v, v out = 3.3 v, and i out = 66 ma. sw turns on only once every 18.5 s to regulate v out figure 5: low-iq pfm mode operation at v in = 12 v, v out = 3.3 v, and i out = 330 ma. sw turns on only twice every 5 s to regulate v out v out v sw i l i peak(lo_iq) i peak(lo_iq) 18.5 s 3.3 v v out v sw i l i peak(lo_iq) 3.3 v t off(pfm) = 435 ns wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
16 figure 6: transitions between pwm mode and low-iq pfm mode, and load transient responses using circuit in typical application schematic (v in = 12 v, v out = 5 v, f sw = 425 khz) time d: load steps from 0 a to 250 ma in low-iq pfm mode time e: transition from low-iq pfm to pwm mode at 250 ma v out v out v out i out i out i out v pwm/pfm v pwm/pfm v pwm/pfm a a e d b b c c overall waveforms v out v out i out i out v pwm/pfm v pwm/pfm e d time a: transition from pwm to pfm at 250 ma time b: load steps from 250 ma to 0 a in low-iq pfm mode time c: load steps from 0 a to 100 ma and back to 0 a in low-iq pfm mode wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
17 pfm mode the following faults are detected: a missing asynchro- nous diode, an open or shorted boot capacitor, vout shorted to ground, and sw shorted to ground. as described in the next section, if any of these faults occur the a8590 will transition from low-iq pfm mode to low-ip pwm mode, with operation at 50% of the current limit of the pwm switching mode. see figure 14 for a timing diagram showing operation of the a8590 in low- iq pfm mode. in low-iq pfm mode the a8590 dissipates very little power, so the thermal monitoring circuit (tsd) is not needed and is dis- abled to minimize the quiescent current and improve efficiency. figure 6 shows pwm to low-iq pfm transitions for a typical microcontroller or dsp system. the system starts in pwm mode at i out = 250 ma and then transitions to low-iq pfm mode, also at i out = 250 ma (time a). while in low-iq pfm mode the current drops from 250 ma to 0 a (time b) and also cycles from no load to 100 ma (time c). in low-iq pfm mode the load steps from i out = 0 a to 250 ma (time d) and then the a8590 transi- tions back to pwm mode (time e). for this example, the output ripple voltage is always less than 30 mv pp and the transient deflection between modes is always less than 50 mv peak . reduced current (low-ip) pwm mode the a8590 supports two different levels of current limiting in pwm modes: ? 100% current, which is during normal pwm, and ? low-ip , in which the current is limited to about 50% of the typical current limit the low-ip pwm mode is invoked when the a8590 is supposed to be in pfm mode but a fault occurs. the purpose of the low-ip pwm mode is to give priority to maintaining reliable regula- tion of v out while enabling all the protection circuits inside the a8590 that are normally debiased during low-iq pfm mode (high precision comparators, timers, and counters). there are several faults that cause a transition from low-iq pfm to low-ip pwm mode: a missing asynchronous diode, an open or shorted boot capacitor, vout shorted to ground, or sw shorted to ground. see figure 14 for a timing diagram showing operation when the a8590 transitions from low-iq pfm mode to low-ip pwm mode. soft start (startup) and inrush current con- trol inrush current is controlled by a soft start function. when the a8590 is enabled and all faults are cleared, the soft start pin will source i sssu and the voltage on the soft start capacitor, c ss , will ramp upward from 0 v. when the voltage at the soft start pin exceeds approximately 400 mv, the error amplifier will slew its output voltage above the pwm ramp offset (v pwmoffs ). at that instant, the high-side and low-side mosfets will begin switch- ing. as shown in figure 7, there is a small delay (t d(ss) ) between when the enable pin transitions high, and when both the soft start voltage exceeds 400 mv and the error amplifier slews its output high enough to initiate pwm switching. after the a8590 begins switching, the error amplifier will regu- late the voltage at the fb pin to the soft start pin voltage minus approximately 400 mv. during the active portion of soft start, the voltage at the soft start pin rises from 400 mv to 1.2 v (a difference of 800 mv), the voltage at the fb pin rises from 0 v to 800 mv, and the regulator output voltage rises from 0 v to the targeted setpoint, which is determined by the feedback resistor divider on the fb pin. during startup, the pwm switching frequency is reduced to 25% of f osc while v fb is below 200 mv. if v fb is above 200 mv but below 400 mv, the switching frequency is reduced to 50% of f osc . also, if v fb is below 400 mv, the g m of the error amplifier is reduced to g m /2. when v fb is above 400 mv the switching frequency will be f osc and the error amplifier gain will be gm . the reduced switching frequencies and error amplifier gain are necessary to help improve output regulation and stability when vout is at a very low voltage. when v out is very low, the pwm control loop requires on-times near the minimum controlla- ble on-time, as well as extra-low duty cycles that are not possible at the base operating switching frequencies. when the voltage at the soft start pin reaches approximately 1.2 v, the error amplifier will change mode and begin regulating the voltage at the fb pin to the a8590 internal reference, 800 mv. the voltage at the soft start pin will continue to rise to approxi- mately v reg . complete soft start operation from v out = 0 v is shown in figure 7. if the a8590 is disabled or a fault occurs, the internal fault latch will be set and the capacitor on the soft start pin will be dis- charged to ground very quickly by an internal 2 k pull-down resistor. the a8590 will clear the internal fault latch when the voltage at the soft start pin decays to approximately 200 mv (v ssrst ). conversely, if the a8590 enters hiccup mode, the capacitor on the soft start pin is slowly discharged by a current sink, i sshic . therefore, the soft start capacitor (c ss ) not only con- trols the startup time but also the time between soft start attempts in hiccup mode. hiccup mode operation is discussed in more detail in the protection features section of this datasheet. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
18 pre-biased startup if the output of the regulator (v out ) is pre-biased to some volt- age, the a8590 will modify the normal startup routine to prevent discharging the output capacitors. as described previously, the error amplifier usually becomes active when the voltage at the soft start pin exceeds 400 mv. if the output is pre-biased, the fb pin will be at some non-zero voltage. the a8590 will not start switching until the voltage at the soft start pin increases to approximately v fb + 400 mv. when the soft start pin volt - age exceeds this value: the error amplifier becomes active, the voltage at the comp pin rises, pwm switching starts, and v out ramps upward from the pre-bias level. figure 8 shows startup when the output voltage is pre-biased to 1.6 v. not power-on reset (npor) output the a8590 has an inverted power-on reset output (npor) with a fixed delay of its rising edge (t d(npor) ). the npor output is an open drain output so an external pull-up resistor must be used, as shown in the typical applications schematics. npor transitions high when the output voltage (v out ), sensed at the fb pin, is within regulation. in pwm mode, npor is high when the output voltage is typically within 92.5% to 110% of the target value. in pfm mode, npor is high when the output voltage is typically above 87.5% of the target value. the npor overvoltage and undervoltage comparators incorporate a small amount of hyster- esis (10 mv typically) and filtering (5 s typically) to help reduce chattering due to voltage ripple at the fb pin. the npor output is immediately pulled low either: if an output overvoltage or an undervoltage condition occurs, or if the a8590 junction temperature exceeds the thermal shutdown threshold (t sd ). for other faults, npor behavior depends on the output voltage. table 2 summarizes all the a8590 fault modes and their effect on npor. figure 7: normal startup to v out = 3.3 v and i out = 1.6 a; pwm/ pfm pin = high, sleep pin transitions from low to high 3.3 v v ss = 400 mv v ss = 1.2 v v sleep t d(ss) t ss v out v comp f sw /4 f sw /2 f sw v ss i l figure 8: pre-biased startup from v out = 1.6 v to v out = 3.3 v, at i out = 1.6 a v ss v sleep v out v comp i l v out rises from 1.6 v, it is not pulled to 0 v switching delayed until v ss = v fb +400 mv 3.3 v 1.6 v v ss = 400 mv v ss = 1.2 v f sw /2 f sw wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
19 oscillator. the a8590 includes leading edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the high- side mosfet is turned on. because of the addition of the slope compensation ramp to the inductor current, the a8590 delivers more current at lower duty cycles and less current at higher duty cycles. also, the slope compensation is not a perfectly linear function of switching frequency. for a given duty cycle, this results in a little more cur- rent being available at lower switching frequencies than higher frequencies. figure 11 shows the typical and worst case min/max pulse-by-pulse current limits versus duty cycle at f sw = 250 khz and 2.45 mhz. at power-up, npor must be initialized (set to a logic low) when v in is relatively low. figure 9 shows v in ramping up, and also npor being set to a logic low when v in is only 2.2 v. for this test, npor was pulled up to an external 3.3 v supply via a 2 k resistor. at power-down, npor must be held in the logic low state as long as possible. figure 10 shows v in ramping down and also npor being held low until v in is only 1.3 v. for this test, npor was pulled up to an external 3.3 v supply via a 2 k resistor. protection features the a8590 was designed to satisfy the most demanding automo- tive and non-automotive applications. in this section, a descrip- tion of each protection feature is described and table 2 summa- rizes the protection features and operation. undervoltage lockout (uvlo) an undervoltage lockout (uvlo) comparator monitors the volt- age at the vin pin and keeps the regulator disabled if the voltage is below the stop threshold (v inuv(off) ). the uvlo comparator incorporates some hysteresis (v inuv(hys) ) to help reduce on-off cycling of the regulator due to resistive or inductive drops in the v in path during heavy loading or during startup. pulse-by-pulse overcurrent protection (ocp) the a8590 monitors the current in the high-side mosfet and if the current exceeds the pulse-by-pulse overcurrent threshold ( i lim ) then the high-side mosfet is turned off. normal pwm operation resumes on the next clock pulse from the internal figure 9: initialization of npor as v in ramps up v in = 2.2 v v in v npor figure 10: npor being held low as v in ramps down v in = 1.3 v v in v npor 3.0 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.2 2.8 3.4 3.6 3.8 2.6 3.2 2.4 2.2 2.0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 duty cycle (%) i (a) lim min_250 khz typ_250 khz max_250 khz min_2.45 mhz typ_2.45 mhz max_2.45 mhz figure 11: pulse-by-pulse current limit versus duty cycle at f sw = 250 khz (dashed curves) and f sw = 2.45 mhz (solid curves) wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
20 if the synchronization input (pwm/ pfm) is used to increase the switching frequency, the on-time and the current ripple will decrease. this will allow slightly more current than at the base switching frequency ( f osc ). the exact current the buck regulators can support is heavily dependent on: duty cycle (v in , v out , v f ), ambient temperature, thermal resistance of the pcb, airflow, component selection, and nearby heat sources. overcurrent protection (ocp) and hic- cup mode an ocp counter and hiccup mode circuit protect the buck regula- tor when the output of the regulator is shorted to ground or when the load is too high. when the voltage at the soft start pin is below the hiccup ocp threshold ( hic/pfm en ) the hiccup mode counter is disabled. two conditions must be met for the ocp counter to be enabled and begin counting: ? v ss > hic/pfm en (2.3 v (typ)) and ? v comp is clamped at its maximum voltage (ocl =1) as long as these two conditions are met, the ocp counter remains enabled and will count pulses from the overcurrent comparator. if the comp pin voltage decreases ( ocl = 0 ) the ocp counter is cleared. if the ocp counter reaches ocplim counts (120), a hiccup latch is set and the comp pin is quickly pulled down by a relatively low resistance (1 k). the hiccup latch also enables a small cur- rent sink connected to the soft start pin (i sshic ). this causes the voltage at the soft start pin to slowly ramp downward. when the voltage at the soft start pin decays to a low enough level (v ssrst , 200 mv (typ)) the hiccup latch is cleared and the small current sink turned off. at that instant, the soft start pin will begin to source current (i sssu ) and the voltage at the soft start pin will ramp upward. this marks the beginning of a new, normal soft start cycle as described earlier. (note: ocp is the only fault that results in hiccup mode that is ignored when v ss < 2.3 v.) when the voltage at the soft start pin exceeds the soft start offset (typically 400 mv) the error amplifier forces the voltage at the comp pin to quickly slew upward and pwm switching will resume. if the short circuit at the regulator output remains, another hiccup cycle will occur. hiccups will repeat until the short circuit is removed or the regulator is disabled. if the short circuit is removed, the a8590 will soft start normally and the output voltage will automatically recover to the target level, as shown in figure 12. boot capacitor protection the a8590 monitors the voltage across the boot capacitor to detect if the capacitor is missing or short circuited. if the boot capacitor is missing, the regulator will enter hiccup mode after 7 pwm cycles. if the boot capacitor is short circuited, the regulator will enter hiccup mode after 120 pwm cycles, provided there is no vout overvoltage detection. at no load or very light loads, the boot charging circuit will increase the output voltage (via the output inductor) and cause an overvoltage condition to be detected if v in > v out + 5.7 v. for a boot fault, hiccup mode will operate virtually the same as described previously for an output short circuit fault (ocp) with the soft start pin ramping up and down as a timer to initiate repeated soft start attempts. boot faults are a non-latched condi- tion, so the a8590 will automatically recover when the fault is corrected. asynchronous diode protection if the asynchronous diode (d1 in the typical applications sche- matics) is missing or damaged (open) the sw pin will be subject to unusually high negative voltages. these negative voltages may cause the a8590 to malfunction and could lead to damage. the a8590 includes protection circuitry to detect when the asyn- chronous diode is missing. if the sw pin is below typically ?1.25 v for more than about 50 ns, the a8590 will enter hiccup mode after detecting one missing diode fault. also, if the asynchronous diode is short circuited, the a8590 will experience extremely high currents in the high-side mosfet. if this occurs the a8590 will enter hiccup mode after detecting one short circuited diode fault. figure 12: hiccup mode operation and recovery to v out = 3.3 v, i out = 1.6 a v ss v out v comp i l 2.3 v 200 mv i lim(tonmin) 120 ocp counts short removed wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
21 output overvoltage protection (ovp) the a8590 provides a basic level of overvoltage protection by monitoring the voltage level at the fb pin. two overvoltage con- ditions can be detected: ? the fb pin is disconnected from its feedback resistor divider . in this case, a tiny internal current source forces the voltage at the fb pin to rise. when the voltage at the fb pin exceeds the over-voltage threshold (v out(ov)pwm , 880 mv (typ)) pwm switching will stop and npor will be pulled low. ? a higher, external voltage supply is accidently shorted to thea8590s output. v fb will probably rise above the overvoltage threshold and be detected as an overvoltage condition. in this case, the low-side mosfet will continue to operate and can correct the ovp condition, provided that only a few milliamperes of pull-down current are required. in either case, if the condition causing the overvoltage is corrected the regulator will automatically recover. pin-to-ground and pin-to-pin short pro- tections the a8590 is designed to satisfy the most demanding automotive applications. for example, the a8590 has been carefully designed from the very beginning to withstand a short circuit to ground at each pin without suffering damage. in addition, care was taken when defining the a8590 pin-out to optimize protection against pin-to-pin adjacent short circuits. for example, logic pins and high voltage pins are separated as much as possible. inevitably, some low voltage pins are located adja- cent to high voltage pins, but in these instances the low voltage pins are designed to withstand increased voltages, with clamps and/or series input resistance, to prevent damage to the a8590. thermal shutdown (tsd) the a8590 monitors junction temperature and will stop pwm switching and pull npor low if it becomes too hot. also, to pre- pare for a restart, the soft start and comp pins will be pulled low until v ss < v ss(rst) . tsd is a non-latched fault, so the a8590 will automatically recover if the junction temperature decreases by approximately 20c. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
22 table 2: summary of a8590 fault modes and operation fault mode v ss during fault counting, before hiccup mode boot charging npor state latched? reset condition v comp high-side mofset low-side mofset output overcurrent, v fb < 200 mv hiccup, after 120 ocp faults clamped for i lim , then pulled low for hiccup f osc / 4 due to v fb < 200 mv, responds to v comp can be activated if v boot is too low not affected depends on v out no automatic, after remove the short output overcurrent, v fb > 400 mv hiccup, after 120 ocp faults clamped for i lim , then pulled low for hiccup f osc / 4 due to v fb > 400 mv, responds to v comp can be activated if v boot is too low not affected depends on v out no automatic, after decrease load current boot capacitor open/missing (boot ov ) hiccup, after 7 boot ov faults pulled low for hiccup forced off when boot ov fault occurs forced off when boot fault occurs off after boot fault occurs depends on v out no automatic, after replace capacitor boot capacitor shorted (boot uv ) hiccup, after 120 boot uv faults not affected, pulled low for hiccup forced off when boot uv fault occurs forced off only during hiccup off only during hiccup depends on v out no automatic, after unshort capacitor asynchronous diode missing hiccup after 1 fault pulled low for hiccup forced off after 1 fault can be activated if v boot is too low not affected depends on v out no automatic, after install diode asynchronous diode (or sw) hard short to ground hiccup after 1 fault pulled low for hiccup forced off after 1 fault can be activated if v boot is too low not affected depends on v out no automatic, after remove the short asynchronous diode (or sw) soft short to ground hiccup, after 120 ocp faults clamped for i lim , then pulled low for hiccup active, responds to v comp can be activated if v boot is too low not affected depends on v out no automatic, after remove the short fb pin open (fb floats high) begins to ramp up for soft start transitions low via loop response forced off by low v comp active during t off(min)pwm off when v fb is too high pulled low when v fb is too high no automatic, after connect fb pin output overvoltage (v fb > 880 mv) not affected transitions low via loop response forced off by low v comp active during t off(min)pwm off when v fb is too high pulled low when v fb is too high no automatic, after v fb returns to normal range output undervoltage not affected transitions high via loop response active, responds to v comp can be activated if v boot is too low not affected pulled low when v fb is too low no automatic, after v fb returns to normal range thermal shutdown pulled low and latched until v ss < v ssrst pulled low and latched until v ss < v ssrst forced off by low v comp disabled off pulled low no automatic, after part cools down vreg or bias overvoltage (regov) not affected transitions low via loop response forced off by low v comp active during t off(min)pwm off pulled low no automatic, vreg or bias to normal range wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
23 figure 13: operation with sleep = high and pwm/pfm = high (pwm mode) wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
24 figure 14: operation with sleep = high and pwm/pfm = low (low-iq pfm mode and transition to low-ip pwm mode) ~500 mv ~500 mv ~500 mv boot faults low-ip pwm low-ip pwm pwm diode or sw faults mode pwm/ pfmn tsd oc hic_en hiccup oc fault boot fault vin vout ss comp diode fault sw ss lo_iq hiccup oc f sw f sw ss ss lo_iq s s lo_iq x1 pwm oc hiccup x1 f sw lo_iq hicc up hiccup ss ss x1 s s hicc up ss hi c ss hi c f sw ss>2.3v ? fb>0.74v x7 ov x120 uv to 2.3v from 2.3v to 2.3 v from 2 .3v to 2.3v from 2.3v to 2.3v from 2 .3v low-ip pwm 2048 2048 off vout shorted to gnd x120 sleepn f sw /4 ss>2.3v ? fb>0.74v f sw /4 then f sw /2 f sw /4 then f sw /2 f sw /4 then f sw /2 f sw /4 f sw /4 f sw /4 f sw /4 f sw /4 x7 ov x120 uv x7 ov x120 uv hiccup ~500 mv x120 npor 7.5ms 7.5ms 7.5ms 7.5ms 2048 note: npor=1 already, so v ss >hic/pfm en starts the 2048 pfm delay counter ss>2.3v ? fb>0.74v f sw f sw /4 then f sw /2 2048 ss>2.3v ? fb>0.74v note: faster ss shown here, so npor starts the 2048 pfm delay counter, instead of v ss wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
25 application information design and component selection setting the output voltage (v out ) the output voltage of the regulator is determined by connecting a resistor divider from the output node (vout) to the fb pin as shown in figure 15. there are trade-offs when choosing the value of the feedback resistors. if the series combination (rfb1 + rfb2) is too low, then the light load efficiency of the regula- tor will be reduced. so to maximize the efficiency, it is best to choose higher values of resistors. on the other hand, if the paral- lel combination (rfb1 // rfb2) is too high, then the regulator may be susceptible to noise coupling onto the fb pin. the feedback resistors must satisfy the ratio shown in the follow- ing equation to produce the target output voltage, v out : = ? 1 0.8 (v) v out r fb2 r fb1 (1) compared to typical buck regulators, a pfm capable buck regulator presents some unique challenges when determining its feedback divider . this resistor divider must draw minimal current from vout or it will reduce the efficiency during low-iq pfm operation. with this in mind, allegro recommends the resistor values show in table 3 on page 34. for low-iq pfm mode, a feedforward capacitor (cfb) should be connected in parallel with rfb1, as shown in figure 16. the purpose of this capacitor is to offset any stray capacitance (c stray ) from the fb pin to ground. without cfb, the stray capacitance and the relatively high resistor values used for the feedback network form a low pass filter and introduce lag to the low-iq pfm feedback path. the feedforward capacitor helps to maintain sensitivity during low-iq pfm mode and to assure the output voltage ripple is minimized. in general, cfb should be calculated as: c fb > (1.5 c stra ) ( r fb r fb1 ) () where c stray is typically 15 to 25 pf. rfb1 fb pin rfb2 v out figure 15: connecting a feedback resistor divider to set the output voltage rfb1 fb pin rfb2 c stray 15 to 25 pf v out cfb figure 16: adding a cfb to cancel stray capacitance at the fb pin in pfm mode 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 5.0 15 .0 25.0 35 .0 45 .0 55.0 65 .0 75.0 85 .0 95 .0 frequency (mhz) r fset (k ? ) figure 17: pwm switching frequency versus r fset wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
26 pwm base switching frequency (f osc , r fset ) the pwm base switching frequency, f osc , is set by connecting a resistor from the fset pin to ground. figure 17 is a graph show- ing the relationship between the typical switching frequency and the fset resistor. the base frequency is the output frequency, fsw , when pwmpfm is high (no external clocking signal). for a given base switching frequency ( f osc ), the fset resistor can be calculated as follows: = ? 2.75 f osc 26385 r fset (3) where f osc is in khz and r fset is in k. when the pwm base switching frequency is chosen the designer should be aware of the minimum controllable on-time, t on(min) pwm of the a8590. if the system required on-time is less than the a8590 minimum controllable on-time, switch node jitter occurs and the output voltage will have increased ripple or oscillations. the pwm base switching frequency required should be calcu- lated as follows: < f osc v out t on(min)pwm v in(max)req (4) where v out is the output voltage, t on(min)pwm is the minimum controllable on-time of the a8590 (95 ns (typ), 135 ns (max)), and v in(max)req is the maximum required operational input volt- age (not the peak surge voltage). if the a8590 pwm synchronization function is employed, then the base switching frequency should be chosen such that jitter will not result at the maximum synchronized switching fre- quency, determined from equation 4: < f osc 0.66 v out t on(min)pwm v in(max)req (5) output inductor (l o ) for a peak current mode regulator it is common knowledge that, without adequate slope compensation, the system will become unstable when the duty cycle is near or above 50%. however, the slope compensation in the a8590 is a fixed value (s e ). therefore, it is important to calculate an inductor value such that the falling slope of the inductor current (s f ) will work well with the a8590 slope compensation. the following equation can be used to cal- culate a range of values for the output inductor based on the well known approach of providing slope compensation that matches 50% to 100% of the falling slope of the inductor current: ? l o 2 s e v out + v f s e v out + v f (6) where v f is the forward voltage of the asynchronous diode, and l o is in h. in equation 6, the slope compensation (s e ) is a function of switching frequency according the following: s e = 0.253 f osc 2 + 0.726 f osc + 0.021 (7) where s e is in a/s and f osc is in mhz. more recently, dr. raymond ridley presented a formula to calcu- late the amount of slope compensation required to critically damp the double poles at half the pwm switching frequency: s e l o 1? s e 1?0.18 = v+ v out f 0.18 d (v (min)+v ) in f v+ v out f v+ v out f (8) this formula allows the inclusion of the duty cycle (d), which should be calculated at the minimum input voltage to insure optimal stability . also, to avoid dropout (that is, saturation of the buck regulator), v in(min) must be approximately 1 to 1.5 v above v out when calculating the inductor value with equation 8. if equations 7 or 8 yield an inductor value that is not a standard value, then the next highest available value should be used. the final inductor value should allow for 10% to 20% of initial toler - ance and 20% to 30% of inductor saturation. the saturation current of the inductor should be higher than the peak current capability of the a8590. ideally, for output short cir- cuit conditions, the inductor should not saturate even at the high- est pulse-by-pulse current limit at minimum duty cycle, 6.1 a. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
27 this may be too costly. at the very least, the inductor should not saturate at the peak operating current according to the following: s e (v +v ) out f 1.15 f (v (max)+v ) osc in f i 6.1 peak = C (9) where v in(max) is the maximum continuous input voltage, such as 18 v (not a surge voltage, such as 40 v). starting with equation 9, and subtracting half of the inductor ripple current, provides us with an interesting equation to predict the typical dc load capability of the regulator at a given duty cycle (d): s e d f osc 2 f l osc o v out (1? d) i 6.1 out(dc) = C (10) after an inductor is chosen, it should be tested during output short circuit conditions. the inductor current should be monitored using a current probe. a good design would ensure neither the inductor nor the regulator are damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. output capacitors the output capacitors filter the output voltage to provide an acceptable level of ripple voltage and they store energy to help maintain voltage regulation during a load transient. the voltage rating of the output capacitors must support the output voltage with sufficient design margin. the output voltage ripple ( vout ) is a function of the output capacitor parameters: c out , esr cout , and esl cout : = ?v out ?i l esr cout ?i l esl cout v in ?v out l o 8 f sw c out + + (11) the type of output capacitors will determine which terms of equation 11 are dominant. for ceramic output capacitors the esr - cout and esl cout are virtually zero, so the output voltage ripple will be dominated by the third term of equation 11: = ?v out ?i l 8 f sw c out (12) to reduce the voltage ripple of a design using ceramic output capacitors, simply: increase the total capacitance, reduce the inductor current ripple (that is, increase the inductor value), or increase the switching frequency. for electrolytic output capacitors the value of capacitance will be relatively high, so the third term in equation 11 will be very small. the output voltage ripple will be determined primarily by the first two terms of equation 11: = ?v out ?i l esr cout esl cout v in ?v out l o + (13) to reduce the voltage ripple of a design using electrolytic output capacitors, simply: decrease the equivalent esr co and esl co by using a high(er) quality capacitor, or add more capacitors in parallel, or reduce the inductor current ripple (that is, increase the inductor value). the esr of some electrolytic capacitors can be quite high so allegro recommends choosing a quality capacitor for which the esr or the total impedance is clearly documented in the data- sheet. also, the esr of electrolytic capacitors usually increases significantly at cold ambients, as much as 10, which increases the output voltage ripple and, in most cases, reduces the stability of the system. the transient response of the regulator depends on the quantity and type of output capacitors. in general, minimizing the esr of the output capacitance will result in a better transient response. the esr can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. at the instant of a fast load transient (di/dt), the output voltage will change by the amount: = + ?v out ?i load di dt esl cout esr cout (14) after the load transient occurs, the output voltage will deviate from its nominal value for a short time. this time will depend on the system bandwidth, the output inductor value, and output capacitance. eventually, the error amplifier will bring the output voltage back to its nominal value. the speed at which the error amplifier brings the output voltage back to its setpoint depends mainly on the closed-loop bandwidth of the system. a higher bandwidth usually results in a shorter time to return to the nominal voltage. however, with a higher wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
28 bandwidth system, it may be more difficult to obtain acceptable gain and phase margins. selection of the compensation com- ponents (rz, cz, and cp) are discussed in more detail in the compensation components section of this datasheet. low-iq pfm output voltage ripple calcu- lation after choosing an output inductor and output capacitor(s), its important to calculate the output voltage ripple (v out (pfm) ) that will occur during low-iq pfm mode. with ceramic output capacitors the output voltage ripple in pwm mode is usually negligible, but that is not the case during low-iq pfm mode. first, calculate the high-side mosfet on-time and off-time. the on-time is defined as the time it takes for the inductor current to reach the peak current threshold, i peak(lo_iq) : = t on v in ? v out ? i peak(lo_iq) ( r ds(on)hs + dcr lo ) i peak(lo_iq) l o (15) where r ds(on) is the on-resistance (110 m (typ)) of the high- side mosfet and dcr lo is the dc resistance of the output inductor, lo. for relatively low input voltages, the on-time dur- ing low-iq pfm mode is internally limited to about 4.1 s. the off-time is defined as the time it takes for the inductor cur- rent to decay from i peak(lo_iq) to 0 a: = t off i peak(lo_iq) l o v out +v f (16) finally , the low-iq pfm output voltage ripple can be calculated: = ?v out(lo_iq) i peak(lo_iq) (t on + t off ) 2 c out (17) if the low-iq pfm output voltage ripple appears to be too high, then the output capacitance should be increased and/or the output inductance should be decreased. decreasing the inductor value has the drawback of increasing the ripple current, so a higher load current will be required to transition from discontinuous conduc- tion mode (dcm) to continuous conduction mode (ccm). this might not be acceptable. in general, the low-iq pfm output voltage ripple increases as the input voltage decreases. also, from equation 15, note that t on increases as the v out /v in ratio increases (that is, as v in decreases). if the v out /v in ratio is too high, the system is not able to achieve i peak(lo_iq) in only one pfm pulse. in this case the on-time is limited to approximately 4.1 s and a second pfm pulse is required, about t off(pfm) later, as shown in figure 5. input capacitors three factors should be considered when choosing the input capacitors. first, they must be chosen to support the maximum expected input surge voltage with adequate design margin. second, the capacitor rms current rating must be higher than the expected rms input current to the regulator. third, they must have enough capacitance and a low enough esr to limit the input voltage dv/dt to something much less than the hysteresis of the vin pin uvlo circuitry (v inuv(hys) , nominally 400 mv for the a8590), at maximum loading and minimum input voltage. the input capacitors must deliver the rms current according to: = i rms i out d (1? d) (18) where the duty cycle is: d (v out + v f )/(v in + v f ) (19) and v f is the forward voltage of the asynchronous diode, d1 . figure 18 shows the normalized input capacitor rms current versus duty cycle. to use this graph, simply find the operational duty cycle (d) on the x-axis and determine the input/output cur - rent multiplier on the y-axis. for example, at a 20% duty cycle, the input/output current multiplier is 0.40. therefore, if the regulator is delivering 3.0 a of steady-state load current, the input capacitor(s) must support 0.40 3.0 a, or 1.2 a rms . the input capacitor(s) must limit the voltage deviations at the vin pin to something significantly less than the a8590 vin pin uvlo hysteresis during maximum load and minimum input 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 10 20 30 50 60 70 80 10090 40 duty cycle (%) i r m s / i out figure 18: input capacitor ripple versus duty cycle wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
29 voltage. the minimum input capacitance can be calculated as follows: c in i out ?v in(min) f osc 0.85 d (1? d) (20) where v in(min) is chosen to be much less than the hysteresis of the vin pin uvlo comparator (v in(min) 150 mv is recom - mended). the d (1-d) term in equation 20 has an absolute maximum value of 0.25 at 50% duty cycle. so, for example, a very conser- vative design, based on: i out = 3.0 a, f osc = 85% of 425 khz, d (1-d) = 0.25, and v in = 150 mv, yields: 361 (khz) 150 (mv) 0.25 c in a good design should consider the dc bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. this effect is very pronounced with the y5v and z5u temperature characteristic devices (as much as 90% reduction) so these types should be avoided. the x5r and x7r type capacitors should be the primary choices due to their stability versus both dc bias and temperature. for all ceramic capacitors, the dc bias effect is even more pro- nounced on smaller sizes of device case, so a good design uses the largest affordable case size (such as 1206 or 1210). also, it is advisable to select input capacitors with plenty of design margin in the voltage rating to accommodate the worst case transient input voltage (such as a load dump as high as 40 v for automo- tive applications). asynchronous diode (d1) there are three requirements for the asynchronous diode. first, the asynchronous diode must be able to withstand the regulator input voltage when the high-side mosfet is on. therefore, one should choose a diode with a reverse voltage rating (v r ) higher than the maximum expected input voltage (that is, the surge volt- age). second, the forward voltage of the diode (v f ) should be mini- mized or the regulator efficiency suffers. also if v f is too high, the a8590 missing diode protection function could be falsely activated. a schottky type diode that can maintain a very low v f when the regulator output is shorted to ground, at the coldest ambient temperature, is highly recommended. third, the asynchronous diode must conduct the output current when the high-side mosfet is turned off. therefore, the average forward current rating of this diode (i f(avg) ) must be high enough to deliver the load current according to i f (avg) i out(max) ( 1 C d min ) (21) where d min is the minimum duty cycle defined in equation 19, and i out(max) is the maximum continuous output current of the regulator. bootstrap capacitor a bootstrap capacitor must be connected between the boot and sw pins to provide the floating gate drive to the high-side mos- fet. usually, 47 nf is an adequate value. this capacitor should be a high-quality ceramic capacitor, such as an x5r or x7r, with a voltage rating of at least 16 v. the a8590 incorporates a 10 low-side mosfet to ensure that the bootstrap capacitor is always charged, even when the regula- tor is lightly loaded or pre-biased. soft start and hiccup mode timing (c ss ) the soft start time of the a8590 is determined by the value of the capacitance at the soft start pin, css . when the a8590 is enabled, the voltage at the soft start pin starts from 0 v and is charged by the soft start current, i sssu . however, pwm switch - ing does not begin instantly because the voltage at the soft start pin must rise above 400 mv. the soft start delay (t d(ss) ) can be calculated as: = t d(ss) c ss i sssu 400 (mv) (22) if the a8590 is starting with a very heavy load, a very fast soft start time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. this occurs because the total of the full load current, the inductor ripple current, and the additional cur- rent required to charge the output capacitors: i co = c out v out /t ss (23) is higher than the pulse-by-pulse current threshold, as shown in figure 19. this phenomena is more pronounced when using high value electrolytic type output capacitors. to avoid prematurely triggering hiccup mode the soft start capacitor, c ss , should be calculated according to: c ss c out v out i sssu 0.8 (v) i co (24) wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
30 where v out is the output voltage, c out is the output capaci- tance, i co is the amount of current allowed to charge the output capacitance during soft start (recommended: 0.1 a < i co < 0.3 a). higher values of i co result in faster soft start times. how - ever, lower values of i co ensure that hiccup mode is not falsely triggered. allegro recommends starting the design with an i co of 0.1 a and increasing it only if the soft start time is too slow. if a non-standard capacitor value for c ss is calculated, the next larger value should be used. the output voltage ramp time, t ss , can be calculated by using either of the following methods: = = t ss t ss c out c ss i sssu v out 0.8 (v) or i co when the a8590 is in hiccup mode, the soft start capacitor is used as a timing capacitor and sets the hiccup period. the soft start pin charges the soft start capacitor with i sssu during a startup attempt and discharges the same capacitor with i sshic between startup attempts. because the ratio i sssu / i sshic is approximately 4:1, the time between hiccups will be about four times as long as the startup time. therefore, the effective duty- cycle of the a8590 will be very low and the junction temperature will be kept low. compensation components (rz, cz, and cp) to properly compensate the system, it is important to understand where the buck power stage, load resistance, and output capaci- tance form their poles and zeros in frequency. also, it is impor- tant to understand that the (type ii) compensated error amplifier introduces a zero and two more poles, and where these should be placed to maximize system stability, provide a high bandwidth, and optimize the transient response. first, consider the power stage of the a8590, the output capaci- tors, and the load resistance. this circuitry is commonly referred as the control-to-output transfer function. the low frequency gain of this circuitry depends on the comp to sw current gain (g mpower ), and the value of the load resistor (r l ). the dc gain (g co(0hz) ) of the control-to-output is: g co(0hz) =g mpower r l (27) the control-to-output transfer function has a pole (f p1 ), formed by the output capacitance (c out ) and load resistance (r l ), located at: = f p1 c out r l 2? 1 (28) the control-to-output transfer function also has a zero (f z1 ) formed by the output capacitance (c out ) and its associated esr: = f z1 c out esr 2? 1 (29) for a design with very low-esr type output capacitors (such as ceramic or os-con? output capacitors), the esr zero (f z1 ) is usually at a very high frequency, so it can be ignored. on the other hand, if the esr zero falls below or near the 0 db crossover frequency of the system (as is the case with electrolytic output capacitors), then it should be cancelled by the pole formed by the cp capacitor and the rz resistor (discussed and identified later as f p3 ). a bode plot of the control-to-output transfer function for the con- figuration shown in typical application schematic b (v out = 5.0 v, i out = 3.0 a, r l = 1.67 ) is shown in figure 20. the pole at f p1 can easily be seen at 1.8 khz while the esr zero (f z1 ) occurs at a very high frequency, 630 khz (this is typical for a design using ceramic output capacitors). note: there is more than 90 of total phase shift because of the double-pole at half the switching frequency. 60 0 -60 780 d 0 d sel>> -180 d 10 hz 100 hz 1.0 khz 10 khz 100 khz 1.0 mhz g= 16.6 db co(0hz) f= 1.8 khz p1 f= 630 khz z1 figure 20: control-to-output bode plot next, consider the feedback resistor divider (rfb1 and rfb2), and the error amplifier (g m ) and compensation network rz-cz- cp. it greatly simplifies the transfer function deriva-tion if r o >> r z , and c z >> c p . in most cases, r o > 2 m, 1 k < r z < 100 (25) (26) wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
31 k, 220 pf < c z < 47 nf, and c p < 50 pf, so the following equa- tions are very accurate. the low frequency gain of the control section (g c(0hz) ) is formed by the feedback resistor divider and the error amplifier. it can be calculated using: = g c(0hz) r fb2 r o r fb1 +r fb2 g m = v fb r o v out g m = v fb v out a vol (30) where v out is the output voltage, v fb is the reference voltage (0.8 v), g m is the error amplifier transconductance (750 a/v ), and r o is the error amplifier output impedance (avol/gm ). the transfer function of the type-ii compensated error amplifier has a (very) low frequency pole (f p2 ) dominated by the output error amplifier output impedance (r o ) and the c z compensation capacitor: = f p2 c z r o 2? 1 (31) the transfer function of the type-ii compensated error amplifier also has frequency zero (f z2 ) dominated by the r z resistor and the c z capacitor: = f z2 c z r z 2? 1 (32) lastly, the transfer function of the type-ii compensated error amplifier has a (very) high frequency pole (f p3 ) dominated by the r z resistor and the c p capacitor: = f p3 c p r z 2? 1 (33) a bode plot of the error amplifier and its compensation network is shown in figure 21, f p2 , f p3 , and f z2 are indicated on the mag- nitude plot. notice that the zero (f z2 at 4.5 khz) has been placed so that it is just above the pole at f p1 previously shown in the control-to-output bode plot (figure 20) at 1.8 khz. placing f z2 just above f p1 will result in excellent phase margin, but relatively slow transient recovery time, as will be shown later. finally, consider the combined bode plot of both the control-to- output and the compensated error amplifier (figure 22). 80 50 0 sel>> -60 180 d 0 d -180 d 10 hz 100 hz 1.0 khz 10 khz 100 khz 1.0 mhz g= 48.7 db c(0hz) f= 4.5 khz z2 f= 280 khz p3 f= 40 hz p2 figure 21: type ii compnesator error amplifer 80 50 0 -50 180 d 0 d sel>> -180 d 10 hz 100 hz 1.0 khz 10 khz 100 khz 1.0 mhz f= 35 khz c pm = 63o gm = 16 db figure 22: bode plot of the complete system (red curves) careful examination of this plot shows that the magnitude and phase of the entire system (red curve) are simply the sum of the error amplifier response (blue curve) and the control-to-output response (green curve). the bandwith of this system (f c ) is 35 khz, the phase margin is 63o, and the gain margin is 16 db. complete designs for several common output voltages, at f sw of 350 khz, 1 mhz, and 2 mhz are provided in table 3 on page 34. wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
32 a generalized tuning procedure this section presents a methodology to systematically apply the design considerations provided above. 1. choose the system bandwidth (f c ). this is the frequency at which the magnitude of the gain crosses 0 db. recommended values for f c , based on the pwm switching frequency, are in the range f sw /20 < f c < f sw /7.5. a higher value of f c gener- ally provides a better transient response, while a lower value of f c generally makes it easier to obtain higher gain and phase margins. 2. calculate the r z resistor value. this sets the system bandwidth(f c ): = r z f c g mpowerx g m c out v out v fb 2? (34) 3. determine the frequency of the pole (f p1 ). this pole is formedby c out and r l . use equation 28 (repeated here): = f p1 c out r l 2? 1 4. calculate a range of values for the c z capacitor. use the fol- lowing: < < c z f c r z 2? 4 f p1 r z 2? 1.5 1 (35) to maximize system stability (that is, to have the greatest gain margin), use a higher value of c z . to optimize transient recovery time, although at the expense of some phase margin, use a lower value of c z . figure 23 compares the output voltage recovery time due to a 1 a load transient for the system shown in figure 22 (f z2 = 4.5 khz, 63o phase margin) and a system with f z2 at 15 khz. the system with f z2 at 15 khz has 51o phase margin, but recovers much faster (about x3) than the other system. 5. calculate the frequency of the esr zero (f z1 ) formed by the- output capacitor(s). use equation 29 (repeated here): = f z1 c out esr 2? 1 if f z1 is at least one decade higher than the target crossover frequency (f c ) then f z1 can be ignored. this is usually the case for a design using ceramic output capacitors. use equa- tion 33 to calculate the value of c p by setting f p3 to either 5 f c or f sw /2, whichever is higher. alternatively, if f z1 is near or below the target crossover fre-quency (f c ), then use equation 33 to calculate the value of c p by setting f p3 equal to f z1 . this is usually the case for a design using high esr electrolytic output capacitors. 5.00 4.99 4.98 4.97 4.96 4.95 4.94 4.93 04 08 0 120 160 200 240 time (s) voltage (v) f= 15 khz z2 f= 4.5 khz z2 )ljxuh7udqvlhqw5hfryhu\&rpsdulvrqirui z2 at 4.5 n+dqgn+ wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
33 table 3: recommended component values v out (v) f sw (mhz) r fset (k) l o (h) c o (2) (f) r z + c z // c p r fb1 // c fb + r fb2 bias pin 1.5 (1) 0.35 73.2 2.2 (ihlp2525czer2r2m01) 80 14.0 k?+1500pf// 33pf 68.1 k?//8pf+76.8 k? external 3.3v 5.0 10h (74437368100) 60 34.8 k?+1500pf // 15pf 221 k?//8pf+42.2 k? connected to vout 8.0 16h (7443251600) 60 56.2k?+1500pf // 6.8pf 357 k?//8pf+39.2 k? 3.3v or 5.0v ldo 3.3 1 23.7 2.2 (ihlp2525czer2r2m01) 50 28.0k?+1500pf // 10pf 147 k?//10pf+46.4 k? connected to vout 5.0 4.7 (74437349047) 50 42.2k?+1500pf // 10pf 221 k?//4.7pf+42.2 k? connected to vout 8.0 6.8 (74437368068) 50 68.1k?+1500pf // 4.7pf 357 k?//2.7pf+39.2 k? 3.3v or 5.0v ldo 3.3 2 10.5 1.0 (74437346010) 30 26.1k?+1000pf // 6.8pf 147 k?//10pf+46.4 k? connected to vout 5.0 1.5 (74437346015) 30 39.2k?+1000pf // 2.7pf 221 k?//4.7pf+42.2 k? connected to vout 8.0 2.2 (ihlp2525czer2r2m01) 30 61.9k?+1000pf // 2.7pf 357 k?//2.7pf+39.2 k? 3.3v or 5.0v ldo 1 if bias is not connected to vout, then the minimum external load must be 75 a at all temperatures. no load operation is ok at approximately 25c to 75c only. 2 negative tolerance and dc-bias effect must be considered when choosing components to obtain c o . wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
34 the power dissipated in the a8590 is the sum of the power dis- sipated from the v in supply current (p in ), the power dissipated due to the switching of the high-side power mosfet (p sw ), the power dissipated due to the rms current being conducted by the high-side power mosfet (p cond ), and the power dissipated by the gate driver (p driver ). the power dissipated from the v in supply current can be calcu- lated using the following equation: p in = v in i q + (v in C v gs ) q g f sw (36) where v in is the input voltage, i q is the input quiescent current drawn by the a8590 (nomi- nally 2.5 ma), v gs is the mosfet gate drive voltage (typically 5 v), q g is the mosfet gate charge (approximately 2.5 nc), and f sw is the pwm switching frequency. the power dissipated by the high-side mosfet during pwm switching can be calculated using the following equation: = p sw v in i out f sw (t r + t f ) 2 (37) where v in is the input voltage, i out is the regulator output current, f sw is the pwm switching frequency, and t r and t f are the rise and fall times measured at the sw node. the exact rise and fall times at the sw node depend on the external components and pcb layout so each design should be measured at full load. approximate values for both t r and t f range from 10 to 15 ns. the power dissipated by the internal high-side mosfet while it is conducting can be calculated using the following equation: = p cond i rms(fet) r ds(on)hs v out + v f v in + v f + 12 2 ?i l 2 i out 2 = r ds(on)hs (38) where i out is the regulator output current, i l is the peak-to-peak inductor ripple current, r ds(on)hs is the on-resistance of the high-side mosfet, and v f is the forward voltage of the asynchronous diode. the r ds(on) of the high-side mosfet has some initial tolerance plus an increase from self-heating and elevated ambient tempera- tures. a conservative design should accommodate an r ds(on) with at least a 15% initial tolerance plus 0.39%/c increase due to temperature. the sum of the power dissipated by the internal gate driver can be calculated using the following equation: p driver = q g v gs f sw (39) where v gs is the gate drive voltage (typically 5 v), q g is the gate charge to drive mosfet to v gs = 5 v (about 2.5 nc), and f sw is the pwm switching frequency. finally, the total power dissipated (p total ) is the sum of the previous equations: p total = p in + p sw + p cond + p driver (40) the average junction temperature can be calculated with the fol- lowing equation: t j = p total + r ja + t a (41) where p total is the total power dissipated as described in equation 40, r ja is the junction-to-ambient thermal resistance (34c/w on a 4-layer pcb), and t a is the ambient temperature. the maximum junction temperature will be dependent on how efficiently heat can be transferred from the pcb to ambient air. it is critical that the thermal pad on the bottom of the ic should be connected to a at least one ground plane using multiple vias. as with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. there are tradeoffs between: ambient operating temperature, input voltage, output voltage, output current, switching frequency, pcb thermal resistance, airflow, and other nearby heat sources. even a small amount of airflow will reduce the junction temperature consider- ably. power dissipation and thermal calculations wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
35 a good pcb layout is critical if the a8590 is to provide clean, stable output voltages. follow these guidelines to insure a good pcb layout. figure 24 shows a typical buck converter schematic with the critical power paths/loops. figure 25 shows an example pcb component placement and routing with the same critical power paths/loops as shown in the schematic. 1. by far , the highest di/dt in the asynchronous buck regulato - roccurs at the instant the high-side mosfet turns on and the capacitance of the asynchronous schottky diode (200 to 1000 pf) is quickly charged to v in . the ceramic input capacitors must deliver this fast, short pulse of current. therefore the loop, from the ceramic input capacitors through the high-side mosfet and into the asynchronous diode to ground, must be minimized. ideally these components are all connected using only the top metal layer (that is, do not use vias to other power/signal layers). 2. when the high-side mosfet is on, current fows from thein- put supply and capacitors, through the high-side mosfet, into the load via the output inductor, and back to ground. this loop should be minimized and have relatively wide traces. 3. when the high-side mosfet is off, free-wheeling current- fows from ground, through the asynchronous diode, into the load via the output inductor, and back to ground. this loop should be minimized and have relatively wide traces. 4. the voltage on the sw node transitions from 0 v to v in veryquickly and is the root cause of many noise issues. it is best to place the asynchronous diode and output inductor close to the a8590 to minimize the size of the sw polygon. also, keep low level analog signals (like fb and comp) away from the sw polygon. 5. place the feedback resistor divider (rfb1 and rfb2) very - close to the fb pin. ground this resistor divider as close as pos-sible to the a8590. 6. t o have the highest output voltage accuracy, the output volt- agesense trace (from vout to rfb1) should be connected as close as possible to the load. 7. place the compensation components (rz, cz, and cp ) as closeas possible to the comp pin. place vias to the gnd plane as close as possible to these components. 8. place the soft start capacitor (c ss ) as close as possible to thess pin. place a via to the gnd plane as close as possible to this component. 9. place the boot strap capacitor (cboot) near the boot pinand keep the routing from this capacitor to the sw poly- gon as short as possible. 10. when connecting the input and output ceramic capacitors, usemultiple vias to gnd and place the vias as close as pos- sible to the pads of the components. 1 1. t o minimize pcb losses and improve system effciency, theinput and output traces should be as wide as possible and be duplicated on multiple layers, if possible. 12. t o improve thermal performance, place multiple vias to thegnd plane around the anode of the asynchronous diode. 13. the thermal pad under the a8590 must connect to the gnd- plane using multiple vias. more vias will ensure the lowest junc-tion temperature and highest effciency. 14. emi/emc issues are always a concern. allegro recommend - shaving component locations for an rc snubber from sw to ground. the resistor should be 1206 size. pcb component placement and routing wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
36 d1 co3 l o v out co4 co2 co1 sw cin1 cin3 cin2 r s nub c s nub q1 vin load 2 1 3 figure 24: typical buck converter with critical paths/loops shown loop 1 (red). at the instant q1 turns on, schottky diode d1, which is very capacitive, must be very quickly shut off (only 5 to 15 ns of charging time). this spike of charging current must come from the local input ceramic capacitor, cin1. this spike of current is quite large and will be an emi/emc issue if loop 1 (red) is not minimized. therefore, the input capacitor cin1 and schottky diode d1 must be placed be on the same (top) layer, be located near each other, and be grounded at virtually the same point on the pcb. loop 2 (magenta). when q1 is off, free-wheeling inductor current must fow from ground through diode d1 (sw will be at Cv f ), into the output inductor, out to the load and return via ground. while q1 is off, the voltage on the output capacitors decreases. the output capacitors and schottky diode d1 should be placed on the same (top) layer, be located near each other, and be sharing a good, low inductance ground connection. loop 3 (blue). when q1 is on, current will fow from the input supply and input capacitors through the output inductor and into the load and the output capacitors. at this time the voltage on the output capacitors increases. 2 1 3 figure 25: example pcb component placement and routing wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
37 package outline drawing a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 16x 0.65 bsc 0.25 bsc 21 16 5.00 0.10 4.40 0.10 6.40 0.20 gauge plane seating plane a b b c d exposed thermal pad (bottom surface); dimensions may vary with device 6.10 0.65 0.45 1.70 3.00 3.00 16 21 1 c d branded face 3 nom 3 nom for reference only ? not for tooling use (reference mo-153 abt) dimensions in millimeters. not to scale dimensions exclusive of mold ash, gate burrs, and dambar protrusions exact case and lead conguration at supplier discretion within limits shown pcb layout reference vi ew terminal #1 mark area reference land pattern layout (reference ipc7351 sop65p640x110-17m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) branding scale and appearance at supplier discretion standard branding reference view yyww nnnnnnn llll = device part number = supplier emblem = last two digits of year of manufacture = week of manufacture = characters 5-8 of lot number n y w l figure 26: package lp, 16-pin tssop with exposed thermal pad wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
38 copyright ?2015, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however , allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision C september 5, 2014 initial release 1 february 11, 2015 revised table 2 and pwm base frequency section 2 december 16, 2015 updated table 3 footnotes wide input voltage, 2.4 mhz, 3.0 a asynchronous buck regulator with low-iq standby, sleep mode, external synchronization, and npor output a8590 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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