View STMPE1601TBR_8833388.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

june 2008 rev 4 1/61 61 stmpe1601 16-bit enhanced port expander with keypad and pwm controller xpander logic features 16 gpios (8 operate at core supply v cc , 8 operate at io supply v io ) operating voltage 1.8 ? 3.3 v hardware keypad contro ller (8*8 matrix with 4 optional dedicated keys max) keypad controller capable of detecting key- press in hibernation mode 4 basic pwm controller for led brightness control interrupt output (open drain) pin optional 32 khz clock input 8-channel programmable level translator advanced power management system ultra-low standby-mode current package tfbga25 (3 x 3 mm) description the stmpe1601 is a gpio (general purpose input/output) port expander able to interface a main digital asic via the two-line bidirectional bus (i 2 c). a separate gpio expander ic is often used in mobile multimedia platforms to solve the problems of the limited number of gpios typically available on the digital engine. the stmpe1601 offers great flexibility, as each i/o can be configured as input, output or specific functions. the device is able to scan a keyboard, also provides pwm outputs for brightness control in backlight, and gpio. this device has been designed to include very low quiescent current, and a wake-up feature for each i/o, to optimize the power consumption of the ic. potential applications of the stmpe1601 include portable media players, game consoles, mobile and smart phones. tfbga25 table 1. device summary order code package packaging STMPE1601TBR tfbga25 tape and reel www.st.com
contents stmpe1601 2/61 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pin assignment and tfbga ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 pin mapping to tfbga (top through view) . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 gpio pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 input/output dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 5 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 minimizing current drain on i 2 c address lines . . . . . . . . . . . . . . . . . . . . . 13 6.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.6 slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.8 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.9 general call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 states of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 autosleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 keypress detect in the hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21
stmpe1601 contents 3/61 8 clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.2 power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 interrupt system register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1.1 interrupt latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 gpio controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.1 gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2 gpio alternate function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.3 hotkey feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3.1 programming sequence for hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3.2 minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.4 level translator feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 basic pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 interrupt on basic pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.2 trigger feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.1 keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.2 registers in keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14 keypad combination key register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15 miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.2 under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 16 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
block diagram stmpe1601 4/61 1 block diagram figure 1. stmpe1601 block diagram keyp a d controller m a in f s m pwm gpio control s clk s dat int clk_in mux por i c interf a ce 2 a0 a1 a2 v io v cc gnd2 gnd1 keyp a d o u tp u t (row y0-y7) /addr 0-2 /gpio 8 -15 keyp a d inp u t (col u mn x0-x7) /gpio 0-7 /pwm 0- 3 mux c s 00024 (powered b y vcc) (powered b y vio)
stmpe1601 pin settings 5/61 2 pin settings 2.1 pin connection figure 2. pin connection (bottom view) 2.2 pin assignment an d tfbga ball location 1 2 3 4 5 tfbga25 table 2. pin assignment ball name name type description e5 gpio_0 i/o gpio 0/ kp_x0/ pwm_0 d4 gpio_1 i/o gpio 1/ kp_x1/ pwm_1 d5 gpio_2 i/o gpio 2/ kp_x2/ pwm_2 c4 gpio_3 i/o gpio 3/ kp_x3/ pwm_3 a5 gpio_4 i/o gpio 4/ kp_x4 a4 gpio_5 i/o gpio 5/ kp_x5 b3 gpio_6 i/o gpio 6/ kp_x6 a3 gpio_7 i/o gpio 7/ kp_x7 a2 gpio_8 i/o gpio 8/ kp_y0 a1 gpio_9 i/o gpio 9/ kp_y1 b2 gpio_10 i/o gpio 10/ kp_y2
pin settings stmpe1601 6/61 2.3 pin mapping to tfbga (top through view) ball name name type description b1 gpio_11 io gpio 11/ kp_y3 d1 gpio_12 io gpio 12/ kp_y4 d2 gpio_13 io gpio 13/ kp_y5/ addr0 e1 gpio_14 io gpio 14/ kp_y6/ addr1 e2 gpio_15 io gpio 15/ kp_y7/ addr2 b5 int o open drain interrupt output pin e4 reset_n i external reset input, active low. reset_n pulse width must be 20 s. e3 sdata a i 2 c data d3 sclk a i 2 c clock b4 clk_in a 32 khz input c5 vcc - 1.8 ? 3.3 v input for i 2 c module and digital core c1 vio - 1.8 ? 3.3 v input for gpio. the vio must be v cc . c2 gnd - ground c3 gnd - ground table 2. pin assignment (continued) table 3. pin mapping 12345 a gpio_9 gpio_8 gpio_7 gpio_5 gpio_4 b gpio_11 gpio_10 gpio_6 clk_in int c vio gnd gnd gpio_3 vcc d gpio_12 gpio_13 sclk gpio_1 gpio_2 e gpio_14 gpio_15 sd ata reset_n gpio_0
stmpe1601 pin settings 7/61 2.4 gpio pin functions table 4. gpio pin functions name primary function alternate function 1 alternate function 2 note gpio_0 gpio keypad pwm gpio_1 gpio keypad pwm gpio_2 gpio keypad pwm gpio_3 gpio keypad pwm gpio_4 gpio keypad gpio_5 gpio keypad gpio_6 gpio keypad gpio_7 gpio keypad gpio_8 gpio keypad gpio_9 gpio keypad gpio_10 gpio keypad gpio_11 gpio keypad gpio_12 gpio keypad gpio_13 gpio keypad i 2 c addr during reset gpio_14 gpio keypad i 2 c addr during reset gpio_15 gpio keypad i 2 c addr during reset
maximum rating stmpe1601 8/61 3 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 3.1 absolute maximum rating 3.2 thermal data table 5. absolute maximum rating symbol parameter value unit v cc supply voltage 4.5 v v in input voltage on gpio pin 4.5 v vesd (hbm) esd protection on each gpio pin 2 kv table 6. thermal data symbol parameter min typ max unit r thja thermal resistance junction-ambient 100 c/w t a operating ambient temperature -40 25 85 c t j operating junction temperature -40 25 125 c
stmpe1601 electrical specification 9/61 4 electrical specification 4.1 dc electrical characteristics table 7. dc electrical characteristics symbol parameter test conditions value unit min typ max v cc 1.8 v supply voltage 1.65 3.6 v v io io supply voltage 1.65 3.6 v i cc active current v io v cc =1.8v t= 25 c 1.2 1.6 ma i sleep sleep current 18 25 a i hibernate hibernate current 0.5 1.5 a i cc active current v io v cc =3.3v t= 25 c 3.0 3.8 ma i sleep sleep current 50 60 a i hibernate hibernate current (1) 1. if only the basic gpio function is required, the st mpe1601 could be designed to work mostly in hibernate mode. active mode is used only when t here are any changes in the i/o status. 1.2 3 a i cc active current v io v cc =1.8v t= 85 c 2ma i sleep sleep current 32 a i hibernate hibernate current 2 a i cc active current v io v cc =3.3v t= 85 c 4.8 ma i sleep sleep current 75 a i hibernate hibernate current (1) 5 a int open drain output current 4ma
electrical specification stmpe1601 10/61 4.2 input/output dc electrical characteristics the 1.8 v i/o complies to the eia/jedec standard jesd8-7. table 8. i/o dc electrical characteristic symbol parameter value unit min typ max v il low level input voltage v io = 1.8 v 0.63 v v ih high level input voltage v io =1.8v 1.17 v v hyst schmitt trigger hysteresis v io =1.8v 0.10 v v il low level input voltage v io = 3.3 v 1.15 v v ih high level input voltage v io =3.3v 2.14 v v hyst schmidt trigger hysteresis v io =3.3v 0.20 v table 9. dc input specification (1.55 v < v cc <1.95v) symbol parameter test conditions value unit min typ max v ol low level output voltage i ol =4ma v io =1.8v 0.45 v v oh high level output voltage i oh =4ma v io =1.8v 1.35 v v ol low level output voltage i ol =4ma v io =3.3v 0.83 v v oh high level output voltage i oh =4ma v io =3.3v 2.48 v table 10. dc output specification (1.55 v < v cc < 1.95 v) symbol parameter test conditions value unit min typ max i pu pull-up current vi = 0 v 15 35 65 a r up (1) 1. applicable to gpio_0 to gpio_7. equivalent pull-up resistance v cc =3.3v 306090k v cc = 1.8 v 50 100 150 k r up (2) 2. applicable to gpio_8 to gpio_15. equivalent pull-up resistance v io =3.3v 306090k v io = 1.8 v 50 100 150 k
stmpe1601 register map 11/61 5 register map all the registers have the size of 8-bit. for each of the module, their registers are residing within the given address range. table 11. register map summary table address module register description auto-increment (during read/write) 0x00 ? 0x07 0x80 ? 0x81 clock and power manager module clock and power manager register range ye s 0x10 ? 0x1f interrupt controller module interrupt controller register range yes 0x30 ? 0x37 pwm controller module pwm controller register range yes 0x38 ? 0x3f pwm controller module pwm controller register range no 0x60 ? 0x6f keypad controller module keypad controller register range yes 0x70 ? 0x77 rotator controller module rotator controller register range yes 0x82 ? 0xbf gpio controller module gpio controller register range yes
i2c interface stmpe1601 12/61 6 i 2 c interface the features that are supported by the i 2 c interface are listed below: i 2 c slave device operates at v cc (1.8 - 3.3 v) compliant to philips i 2 c specification version 2.1 supports standard (up to 100kbps) and fast (up to 400 kbps) modes 7-bit and 10-bit device addressing modes general call start/restart/stop address up to 8 stmpe1601 devices via the i 2 c interface the address is selected by the state of 3 pins. the state of the pins is read upon reset and then the pins can be configured for normal operation. the pins have a pull-up or down to set the address. the i 2 c interface module allows the connected host system to access the registers in the stmpe1601. table 12. i 2 c addresses a2 a1 a0 7-bit address 00040h 00141h 01042h 01143h 10044h 10145h 11046h 11147h
stmpe1601 i2c interface 13/61 6.1 minimizing current drain on i 2 c address lines the gpios 13-15 are used as i 2 c address input during por. pull-up/down resistor of 500 k-1.5 m is recommended for these address lines . in the case that these pins are driven to an opposite logic level during device operation, there would be a current drain of vio/r. this amounts to a significant current for portable devices. to minimize the current drain on i 2 c lines, a few methods are recommended. 1. if maximum keypad size is not required, these shared lines should not be used for keypad operation. 2. if the maximum keypad si ze is required, choose i 2 c address 0x40, as this requires that all 3 address lines to be pulled to ground, minimizing the current drain in keypad operation. in this mode of operation, the pull up/down resistors on the i 2 c lines should be: a reset circuit with longer rc is used to ensure enough time for the address lines to settle to the final values. 3. in system-controlled idle state, all keypad pi ns to be configured as hotkey with interrupt enabled. if any key is pressed, system initiates keypad co ntroller for scanning operation. table 13. recommended pull up/down resistors on the i 2 c lines vio 1.8 v 2.5 v 3.3 v reset rc or pulse width (1) 1. recommended values are chosen to minimize leakage current. note rpu/rpd 1.5 m 1.2 m 1 m 270 k/0.47 f 120 ms all 3 address lines are used for keypad controller rpu/rpd 1.0 m 800 k 660 k 180 k/0.47 f 80 ms 2 address lines are used for keypad controller rpu/rpd 500k 400k 330k 90k/0.47 f 40 ms 1 address line is used for keypad controller
i2c interface stmpe1601 14/61 6.2 start condition a start condition is identified by a falling edge of sdata while sclk is stable at high state. a start condition must precede any data/command transfer. the device continuously monitors for a start condition and does not respond to any transaction unless one is encountered. 6.3 stop condition a stop condition is identified by a rising edge of sdata while sclk is stable at high state. a stop condition terminates the communication between the slave device and bus master. a read command that is followed by noack can be followed by a stop condition to force the slave device into idle mode. when the slave device is in idle mode, it is ready to receive the next i 2 c transaction. a stop condition at the end of a write command stops the write operation to the registers. 6.4 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sdata after sending eight bits of da ta. during the ninth bit, the receiver pulls the sdata low to acknowledge the receipt of the eight bits of data. the receiver may leave the sdata in high state if it would to not acknowledge the receipt of the data. 6.5 data input the device samples the data input on sdata on the rising edge of the sclk. the sdata signal must be stable during the rising edge of sclk and the sdata signal must change only when sclk is driven low. 6.6 slave device address the slave device address is a 7 or 10-bit address, where the least significant 3-bit are programmable. these 3-bit values will be load ed in once upon reset and after that these 3 pins no longer be needed with the exception during general call. up to 8 stmpe1601 devices can be connected on a single i 2 c bus. 6.7 memory addressing for the bus master to communicate to the slave device, the bus master must initiate a start condition and followed by the slave device address. accompanying the slave device address, there is a read/write bit (r/w ). the bit is set to 1 for read and 0 for write operation. if a match occurs on the slave device address, the corresponding device gives an acknowledgement on the sda during the 9 th bit time. if there is no match, it deselects itself from the bus by not responding to the transaction.
stmpe1601 i2c interface 15/61 6.8 operating modes figure 3. i 2 c transaction table 14. operating modes mode bytes programming sequence read 1 start, device address, r/w = 0, register address to be read restart, device address, r/w = 1, data read, stop if no stop is issued, the data read can be continuously performed. if the register address falls within the range that allows address auto- increment, then register address auto-increments internally after every byte of data being read. for regist er address that falls within a non- incremental address range, the address will be kept static throughout the entire read operations. refer to the memory map table for the address ranges that are auto and non-increment. an example of such a non-increment address is fifo. write 1 start, device address, r/w = 0, register address to be written, data write, stop. if no stop is issued, the data write can be continuously performed. if the register address falls within the range that allows address auto- increment, then register address auto-increments internally after every byte of data being written. for those register addresses that fall within a non-incremental address range, the address will be kept static throughout the all write operations. refer to the memory map table for the address ranges that are auto and no n-increment. an example of a non-increment address is data port for initializing the pwm commands. start r/w=0 ack device address reg address ack restart device address ack r/w=1 data read no ack stop one byte read start r/w=0 ack device address reg address ack restart device address ack r/w=1 data read ack more than one byte read ack no ack stop data read + 1 data read + 2 start r/w=0 ack device address reg address ack restart data to be written ack stop one byte write more than one byte read start r/w=0 ack device address reg address ack restart data to write ack stop data to write + 2 ack ack data to write + 1 master slave
i2c interface stmpe1601 16/61 6.9 general call address a general call address is a transaction with the slave address of 0x00 and r/w = 0. when a general call address is made, stmpe1601 responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. the meaning of a general call address is defined in the second byte sent by the master-transmitter. note: all other second by te values will be ignored. table 15. general call address r/w second byte value definition 0 0x06 a 2-byte transaction in which the second byte tells the slave device to reset and write (or latch in) the 2-bit programmable part of the slave address. 0 0x04 a 2-byte transaction in which the second byte tells the slave device not to reset and write (or latch in) the 2-bit programmable part of the slave address. 0 0x00 not allowed as second byte.
stmpe1601 system controller 17/61 7 system controller the system controller is the heart of the stmpe1601. it contains the registers for power control, and the registers for chip identification. the system registers are: chip_id chip ident ification register version_id version iden tification register table 16. system registers address register_name 0x80 chip_id 0x81 version_id 0x02 sys_ctrl 0x03 sys_ctrl_2 76543210 8-bit msb of chip_id rrrrrrrr 00000010 76543210 8-bit version_id rrrrrrrr 00010000
system controller stmpe1601 18/61 sys_ctrl system con trol register address: 0x02 type: r/w reset: 0x0b description: system control register. 7 6543210 soft_reset clock source dis_32khz sleep en_gpio reserved en_kpc en_spwm w rwrwrwrwrwrwrw rwrrrwrrrr 0 0001011 [7] soft_reset writing a ?1? to this bit will do a soft reset of the device. once the reset is done, this bit will be cleared to ?0? by the hw. [6] clock_source set to ?1? if external 32 khz clock were to be used. ?0? by default. [5] dis_32 khz : set this bit to disable the 32 khz osc, thus putting the device in hibernate mode. [4] sleep : writing a ?1? to this bit will put the device in sleep mode. on going to sleep mode, this mode is reset internally. when in sleep mode, the internal rc oscillator will output a slower sleep clock which will be used in the device. [3] en_gpio : writing a ?0? to this bit will gate off the cloc k to the gpio module, thus stopping its operation [2] reserved [1] en_kpc : writing a ?0? to this bit will gate off the clock to the keypad controller module, thus stopping its operation [0] en_spwm writing a ?0? to this bit will gate off the clock to the simple pwm controller module, thus stopping its operation
stmpe1601 system controller 19/61 sys_ctrl_2 system con trol register 2 address: 0x03 type: r/w reset: 0x00 description: system control register 7654 3 210 reserved vio_off autosleep_en sleep_2 sleep_1 sleep_0 r r rw rw rw rw 0 0 0 000 [7] reserved [6] reserved [5] reserved [4] vio_off : writing a ?1? to this bit is mandatory before shuting off the vio supply while maintaining the vcc supply. this ensure that the level shifters for gpios 15-8 are properly powered down so as not to induce high current and also not to affect the in tegrity of any external signals that are on the bus where these gpios are connected. [3] autosleep_en : ?1? to enable auto-sleep feature. ?0? to disable auto-sleep. [2:0] sleep : 000 for 4 ms delay 001 for 16 ms delay 010 for 32 ms delay 011: for 64 ms delay 100: for 128 ms delay 101: for 256 ms delay 110: for 512 ms delay 111: for 1024 ms delay
system controller stmpe1601 20/61 7.1 states of operation figure 4. modes of operation the device has three main modes of operation: operational mode : this is the mode, whereby normal operation of the device takes place. in this mode, the rc clock is availabl e and the main fsm unit routes this clock and the 32 khz clock to all the device blocks that are enabled. in this mode, individual blocks that need not to be working can be turned off by the master by programming the bits 3 to 0 of the sys_ctrl register. sleep mode : in this low-power mode, the rc oscilla tor is powered down. all the blocks which need clocks derived from the 32khz clock will continue getting a 32 khz clock. in this mode also, iindividual blocks can be turned off by the master by programming the bits 3 to 0 of the sys_ctrl register. however, the master needs to program the sys_ctrl register before co ming into this mode, as in the sleep mode, the iic interface is not active except to detect traffic for wakeup. any activity on the i 2 c port (intended i 2 c transaction for the device) or wakeup pin or hotkey activity will cause the device to leave this mode and go into the operational mode. when leaving this mode, the i 2 c will need to hold the sclk till the rc clock is ready. hibernate mode: this mode is entered when the system writes a ?1? to bit 5 of the sys_ctrl register. in this mode, the device is completely inac tive as there is absolutely no clock. only a reset or a wake up on iic will bring back the system to operational mode. a keypress detect will bri ng the system to sleep mode, in which the debounce of the key will take place. note: the 32 khz clock mentioned in this section can be (1) an externally fed 32 khz clock, or (2) an internally generated (from rc osc) clock. in case the internal clock is used, the clock has a range of 25 to 45 khz. operational sleep 2 set disable_32k bit reset hibernate 32k: off rc: off set sleep bit or autosleep valid keypress detect i 2 c transaction keypad, interrupts & i c transaction 32k: on rc: off 32k: on rc: off
stmpe1601 system controller 21/61 7.2 autosleep the host system may configure the stmpe1601 to go into sleep mode automatically whenever there is a period of inactivity following a complete i 2 c transaction with the stmpe1601. this inactivity means there is no intended i 2 c transaction for the device. for example, if there is an i 2 c transaction sent by the host to other slave devices, the stmpe1601 device will still be counting down for the auto-sleep. the stmpe1601 device resets the autosleep time-out counter only when it receives an i 2 c transaction meant for the device itself. this autosleep feature is controlled by the sys_ct rl_2 (system control register 2). all those events that trigger an interrupt (kpc, hot-key) would result in a transition from sleep state to operational state automatically. the wakeup can also be performed through the i 2 c transaction intended for the device. 7.3 keypress detect in the hibernate mode when in hibernate mode, a keypress detect causes the system to go into sleep mode. the sleep clock (32 khz) is then used to debounce the key to detect a valid key. if the keypress is detected to be valid, the system stays in sleep mode. if the key is detected to be invalid, the system goes back into hibernate mode.
clocking system stmpe1601 22/61 8 clocking system figure 5. clocking system the decision on clocks is based on the bits written into the sys_ ctrl registers. bits 0 to 4 of the sys_ctrl register allo w to control the gating of cl ocks to the rotator, keypad controller, pwm and gpio respectively in the operational mode. 8.1 clock source by default, when the stmpe1601 powers up, it derives a 32 khz clock from the internal rc oscillator for its operation. if an external clock source is availa ble, it must be configured to accept an external clock th rough the sys_ctrl register. reset control: there are 4 sources of reset: reset_n pin lvd reset soft reset bit of th e sys_ctrl register i 2 c reset from the i 2 c block. internal rc osc clock control system control register sclk pin clk_in system clock
stmpe1601 clocking system 23/61 8.2 power mode programming sequence to put the device in sleep mode, the following needs to be done by the host: ? write a '1' to bit 4 of the sys_ctrl register. to wake up the device, the host is required to: ? assert a wakeup routine on the i 2 c bus by sending the start bit, followed by the device address and the write bit. subsequently, proceed with sending the base register address and continue with a normal i 2 c transaction. the device wakes up upon receiving the correct device address and in write direction. in other words, the procedure of waking up the device is performed by just sending an i 2 c transaction to the device. this procedure can be extended to wake up the device that is in hibernate mode. to do a soft reset to the device, the host needs to do the following: ? write a '1' to bit 7 of the sys_ctrl register. this bit is automatically cleared upon reset. to go into hibernate mode, the following needs to be done by the host: ? set the disable_32k bit to '1' to come out of the hibernate mode, the following needs to be done by the host: ? assert a system reset ? or put a wakeup on the i 2 c
interrupt system stmpe1601 24/61 9 interrupt system the stmpe1601 uses a highly flexible interrupt system. it allows the host system to configure the type of system events that should result in an interrupt, and pinpoints the source of interrupt by status register. the int pin can be configured as active high, or active low. once asserted, the int pin would de-assert only if the corresponding bit in the interrupt status register is cleared. figure 6. interrupt system 9.1 interrupt syste m register map keypad controller pwm controller gpio controller interrupt status register interrupt enable register interrupt generation interrupt polarity control (system control register) table 17. register map address register name description auto-increment (during sequential r/w) 0x10 int_ctrl_msb interrupt control register ye s 0x11 int__ctrl_lsb yes 0x12 int_en_mask_msb interrupt enable mask register ye s 0x13 int_en_mask_lsb yes 0x14 int_sta_msb interrupt status register ye s 0x15 int_sta_lsb yes 0x16 int_en_gpio_mask _msb interrupt enable gpio mask register ye s 0x17 int_en_gpio_mask _lsb ye s 0x18 int_sta_gpio_msb interrupt status gpio register ye s 0x19 int_sta_gpio_lsb yes
stmpe1601 interrupt system 25/61 9.1.1 interrupt latency when the generation of interrupts by the gpio as input is enabled, the latency (time taken from actual transition at gpio to time of int pin assertion) is shown in the following table: int_ctrl interrupt control register address: 0x10, 0x11 type: r, r/w reset: 0x00 description: the interrupt control register is used to configure the interrupt controller. it has a global enable interrupt mask bit that controls the interruption to the host. table 18. interrupt latency state of operation interrupt latency hibernation 10 us max sleep 5 us max active 2 us max 1514131211109876543210 int_ctrl_msb int_ctrl_lsb reserved ic2 ic1 ic0 rrrrrrrrrrrrrrwrwrw 0000000000000000 [15:3] reserved [2] ic2: output interrupt polarity ?0? = active low/falling edge ?1? = active high/rising edge [1] ic1 : output interrupt type ?0? = level interrupt ?1? = edge interrupt [0] ic0 : global interrupt mask bit when this bit is written a ?1?, it will allow interruption to the host. if it is written with a ?0?, then, it disables all interruption to the host. writing to this bit does not affe ct the int_en_mask value.
interrupt system stmpe1601 26/61 int_en_mask interrupt enable mask register address: 0x12, 0x13 type: r, r/w reset: 0x00 description: the interrupt enable mask register is used to enable the interruption from a particular interrupt source to the host. 15141312111098 7 6 543210 int_en_mask_msb int_en_mask_lsb ie8 ie7 ie6 ie5 ie4 ie3 ie2 ie1 ie0 r r r rrrrrwr/wr/wrwrwrwrwrwrw 00000000 0 0 000000 [15:9] reserved [8] ie[x] : interrupt enable mask (where x = 8 to 0) ie0: wake-up interrupt mask ie1: keypad controller interrupt mask ie2: keypad controller fifo overflow interrupt mask ie3: reserved ie4: basic pwm controller 0 interrupt mask ie5: basic pwm controller 1 interrupt mask ie6: basic pwm controller 2 interrupt mask ie7: basic pwm controller 3 interrupt mask ie8: gpio controller interrupt mask writing a ?1? to the ie[x] bit enables the interruption to the host.
stmpe1601 interrupt system 27/61 int_sta interrupt status register address: 0x14, 0x15 type: r, r/w reset: 0x00 description: the interrupt status register monitors the status of the interruption from a particular interrupt source to the host. regardless whether the int_en bits are enabled or not, the int_sta bits are still updated. 15 14 13 12 11 109876543210 isr_msb isr_lsb is8is8is8is5is4is3is2is1is0 rrrrrrrrwrwrwrwrwrwrwrwrw 00000000 00000000 [15:9] reserved [8:0] is[x] : interrupt status (where x = 8 to 0) read: ie0: wake-up interrupt status ie1: keypad controller interrupt status ie2: keypad controller fifo overflow interrupt status ie3: reserved ie4: basic pwm controller 0 interrupt status ie5: basic pwm controller 1 interrupt status ie6: basic pwm controller 2 interrupt status ie7: basic pwm controller 3 interrupt status ie8: gpio controller interrupt status write: a write to a is[x] bit with a value of ?1? w ill clear the interrupt and a write with a value of ?0? has no effect on the is[x] bit.
interrupt system stmpe1601 28/61 int_en_gpio_mask interrupt enable gpio mask register address: 0x16, 0x17 type: r/w reset: 0x00 description: the interrupt enable gpio mask register is used to enable the interruption from a particular gpio interrupt source to the host. the ieg[15:0] bits are the interrupt enable mask bits correspond to the gpio[15:0] pins . int_sta_gpio interrupt status gpio register address: 0x18, 0x19 type: r/w reset: 0x00 description: the interrupt status gpio register monitors the status of the interruption from a particular gpio pin interrupt source to the host. regardless whether the int_en_gpio_mask bits are enabled or not, the int_sta_gpio bits are still updated. the int_sta_g[15:0] bits are the interrupt status bits correspond to the gpio[15:0] pins. 15 14 13 12 11 109876543210 int_en_gpio_mask_msb int_en_gpio_mask _lsb ieg15 ieg14 ieg13 ieg12 ieg11 ieg10 ieg9 ieg8 ieg7 ieg6 ieg5 ieg4 ieg3 ieg2 ieg1 ieg0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 000000000000 0000 [15:0] ieg [x]: interrupt enable gpio mask (where x = 15 to 0) writing a ?1? to the ie[x] bit will enable the interruption to the host. 15 14 13 12 11 109876543210 int_sta_gpior_msb int_sta_gpior _lsb isg15 isg14 isg13 isg12 isg11 isg10 isg9 isg8 isg7 isg6 isg5 isg4 isg3 isg2 isg1 isg0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0000000000 [15:0] isg[x] interrupt status gpio (where x = 15 to 0) read: interrupt status of the gpio[x]. write: a write to a isg[x] bit with a value of ?1? will clear the interrupt and a write with a value of ?0? has no effect on the isg[x] bit.
stmpe1601 interrupt system 29/61 9.2 programming sequence to configure and initialize the interrupt controller to allow interruption to host, observe the following steps: set the int_en_mask and int_en_gpio_mask registers to the desired values to enable the interrupt sources that are to be expected to receive from. configure the output interrupt type and polarity and enable the global interrupt mask by writing to the int_ctrl. wait for interrupt. upon receiving an interrupt, the int pin is asserted. the host comes to read the int_sta register through the i 2 c interface. a ?1? in the int_sta bits indicates that the corresponding interrupt source is triggered. if the is8 bit in int_sta register is set, the interrupt is coming from the gpio controller. then, a subsequent read is performed on the int_sta_gpio register to obtain the interrupt status of all 16 gpios to locate the gpio that triggers the interrupt. this is a feature so-called ?hot key?. after obtaining the interrupt source that triggers the interrupt, the host performs the necessary processing and operations related to the interrupt source. if the interrupt source is from the gpio controller, two write operations with value of ?1? are performed to the isg[x] bit (int_sta_gpio) and the is[8] (isr) to clear the corresponding gpio interrupt. if the interrupt source is from other module, a write operation with value of ?1? is performed to the is[x] (isr) to clear the corresponding interrupt. once the interrupt is being cleared, the int pin will also be de-asserted if the interrupt type is level interrupt. an edge interr upt will only assert a pulse width of 250ns. when the interrupt is no longer required, the ic0 bit in int_ctrl may be set to ?0? to disable the global interrupt mask bit.
gpio controller stmpe1601 30/61 10 gpio controller a total of 16 gpios are available in the stmpe1601 port expander ic. most of the gpios are sharing physical pins with some alternate functions. the gpio controller contains the registers that allow the host system to configure each of the pins into either a gpio, or one of the alternate functions. unused gpios shoul d be configured as outputs to minimize the power consumption. table 19. gpio controller offset address register name description auto-increment (during sequential r/w) 0x02 gpio_set_msb gpio set pin state register ye s 0x03 gpio_set_lsb yes 0x04 gpio_clr_msb gpio clear pin state register ye s 0x05 gpio_clr_lsb yes 0x06 gp_mp_msb gpio monitor pin state register ye s 0x07 gpio_mp_lsb yes 0x08 gpio_set_dir_msb gpio set pin direction register ye s 0x09 gpio_set_dir_lsb yes 0x0a gpio_ed_msb gpio edge detect status register ye s 0x0b gpio_ed_lsb yes 0x0c gpio_re_msb gpio rising edge register ye s 0x0d gpio_re_lsb yes 0x0e gpio_fe_msb gpio falling edge register ye s 0x0f gpio_fe_lsb yes 0x10 gpio_pull_up_ms b gpio pull up register ye s 0x11 gpio_pull_up_lsb yes 0x12 gpio_af_u_msb gpio alternate function register (upper word) ye s 0x13 gpio_af_u_msb yes 0x14 gpio_af_l_msb gpio alternate function register (lower word) ye s 0x15 gpio_af_l_lsb yes 0x16 gpio_lt_en gpio level translator enable yes 0x17 gpio_lt_dir gpio level translator direction yes 0x18-1f reserved reserved yes
stmpe1601 gpio controller 31/61 10.1 gpio control registers a group of registers is used to control the exact function of each of the 16 gpios. all the gpio registers are named as gpxxx_yyy, where: ? xxx represents the functional group ? yyy represents the byte position of the gpio ? lsb registers control gpio[7:0] ? msb registers control gpio[8:15] the function of each bit is shown in the following table: table 20. bit description 76543210 gpxxx_msb io-15 io-14 io-13 io-12 io-11 io-10 io-9 io-8 gpxxx_lsb io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 table 21. register description register name function gpio monitor pin state reading this bit yields th e current state of the bi t. writing has no effect. gpio set pin state writing ?1? to this bit causes the corre sponding gpio to go to ?1? state. writing ?0? has no effect. gpio clear pin state writing ?1? to this bit causes the corre sponding gpio to go to ?0? state. writing ?0? has no effect. gpio set pin direction ?0? sets the corresponding gpio to input state, and ?1? sets it to output state gpio edge detect status set to ?1? by hardware when there is a rising/falling edge on the corresponding gpio. writing ?1? clears the bit. writing ?0? has no effect. gpio rising edge set to ?1? to enable rising edge detection on the corresponding gpio. gpio falling edge set to ?1? to enable falling edge detection on the corresponding gpio. gpio pull up set to ?1? to enable internal pull-up resistor
gpio controller stmpe1601 32/61 10.2 gpio alternate function registers each gpio may be configured to one or more functions. a 2-bit field for each gpio is used for the configuration. table 22. gpio alternate function registers gpio alternate function (upper word) ?00? for primary function ?01? for alternate function 1 ?10? for alternate function 2 ?11? - reserved gpio alternate function (lower word) gpio alternate funct ion registers (upper) 1514131211109876543210 af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] gpio-15 gpio-14 gpio-13 gpio-12 gpio-11 gpio-10 gpio-9 gpio-8 gpio alternate functi on registers (lower) 1514131211109876543210 af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] af[1:0] gpio-7 gpio-6 gpio-5 gpio-4 gpio-3 gpio-2 gpio-1 gpio-0
stmpe1601 gpio controller 33/61 10.3 hotkey feature a gpio is known as ?hotkey? when it is configured to trigger an interruption to the host whenever the gpio input is being asserted. this feature is applicable in operational mode (4 mhz clock is present) as well as sleep mode (32 khz clock is present). 10.3.1 programming sequence for hotkey 1. configure the gpio pin into gpio mode by setting the corresponding bits in the gpafr. 2. configure the gpio pin into input direction by setting the corresponding bit in gpdr. 3. set the gprer and gpfer to the desired va lues to enable the rising edge or falling edge detection. 4. configure and enable the interrupt controller to allow the interruption to the host. 5. now, the gpio expander may be put into sleep mode if it is desired. 6. upon any hot-key being asserted, the device will wake up and issue an interrupt to the host. below are the conditions to be fulfilled in order to configure a hot key: 1. the pin is configured into gpio mode and as input pin. 2. the global interrupt mask bit is enabled. 3. the corresponding gpio interrupt mask bit is enabled. 10.3.2 minimum pulse width the minimum pulse width of the assertion of the hotkey must be at least 62.5 us. any pulse width less than the stated value may not be registered.
gpio controller stmpe1601 34/61 10.4 level translator feature figure 7. level translator feature when enabled, the gpio 0-7 bits are internally mapped to gpio 8-15 bits. the stmpe1601 becomes an 8-channel level translator where each of the channels may have its direction set individually. as gpio 0-7 operates from vcc, and gpio 8-15 operates from vio, this allows the 2 groups of gpio to work as a level translator. warning: when the level translator feature is enabled, the ?set pin?, ?clear pin? and ?set direct ion? bits in the corresponding registers will be ignored. however, the ?monitor pin?, ?edge detect?, ?pull-up? features are still available in the gpios used as level translator. gpio 0-7 gpio 8-15 direction & enable
stmpe1601 basic pwm controller 35/61 11 basic pwm controller the advanced pwm allows complex brightness and blinking control of an led. the basic pwm controller allows simple r brightness control and basic blinking patterns. the stmpe1601 is fitted with a 4-channel basic pwm controller. table 23. basic pwm controller address register name description auto-increment (during sequential r/w) 0x40 pwm_off_out set the output level when pwm is disabled ye s 0x41 channel_funct_en enable/disable individual basic pwm channels ye s 0x50 pwm_0_set pwm_0 brightness and timing setting ye s 0x51 pwm_0_ctrl pwm_0 blinking control yes 0x52 pwm_0_trigger enable use trigger on pwm 0 yes 0x54 pwm_1_set pwm_1 brightness and timing setting ye s 0x55 pwm_1_ctrl pwm_1 blinking control yes 0x56 pwm_1_trigger enable use trigger on pwm 1 yes 0x58 pwm_2_set pwm_2 brightness and timing setting ye s 0x59 pwm_2_ctrl pwm_2 blinking control yes 0x5a pwm_2_trigger enable use trigger on pwm 2 yes 0x5c pwm_3_set pwm_3 brightness and timing setting ye s 0x5d pwm_3_ctrl pwm_3 blinking control yes 0x5e pwm_3_trigger enable use trigger on pwm 3 yes
basic pwm controller stmpe1601 36/61 pwm_off_output pwm off output address: 0x40 type: r/w reset: 0x00 description: set the output level when the pwm is disabled channel_funct_en channel function enabling address: 0x41 type: r/w reset: 0x00 description: enable/disable individual basic pwm channels. 76543210 - - - - out3 out2 out1 out0 rw rw rw rw rw rw rw rw 00000000 [3:0] output3~0 : default is ?0? 1: pwm channel outputs ?1? when disabled 0: pwm channel outputs ?0? when disabled 76543210 alt_3 alt_2 alt_1 alt_0 en_3 en_2 en_1 en_0 rw rw rw rw rw rw rw rw 00000000 [7:4] alt [3:0] : alternate mode default is ?0? hw writes to ?1? if alternate operating feature (one-shot/wdt) is required [3:0] en [3:0] : pwm channel enable default is ?0? sw writes ?1? to start pwm channel hw writes ?0? when pwm blinking is completed. sw writes ?0? to stop the pwm channel.
stmpe1601 basic pwm controller 37/61 pwm_n_trigger_n = 0 - 3 pwm tr igger register n = 0 - 3 address: 0x52, 0x56, 0x5a, 0x5e type: reset: 0x00 description: enable use of trigger on pwm_n. 76543210 reset edge - mode reload gs2 gs1 gs0 rw rw rw rw rw rw rw rw 00000000 [7] reset : always read ?0? s/w writes ?1? to reset counter in wdt mode writing ?1? in pwm/one-shot has no effect. writing ?0? has no effect in all modes. [6] edge :type of logic transition to be detected for trigger source. 0: low-to-high 1: hi-to-low [5] reserved [4] mode : 0: one-shot trigger mode 1: watch-dog timer mode this bit is only valid if the alt bits in the channel_function_en register is set to ?1?. ?1? for manual reload [3] reload: ?0? for auto-reload ?1? for manual reload [2:0] gs2:0 : trigger source select 000: gpio-4 001: gpio-5 010: gpio-6 011: gpio-7 100: gpio-9 101: gpio-10 110: gpio-11 111: gpio-12
basic pwm controller stmpe1601 38/61 pwm_n_set n=0-3 p wm_n_setup n=0-3 address: 0x50, 0x54, 0x58, 0x5c type: rw reset: 0x00 description: pwm blinking control and brightness setting. 76543210 brightness timing r/wr/wr/wr/wr/wr/wr/wr/w 00000000 [7:4] brigthness : duty cycle of pwm outp ut during period 0 0000: duty cycle ratio 1:15 ( 6.25%, minimum brightness) 0001: duty cycle ratio 2:14 (12.50%) 0010: duty cycle ratio 3:13 (18.75%) 0011: duty cycle ratio 4:12 (25.00%) 0100: duty cycle ratio 5:11 (31.25%) 0101: duty cycle ratio 6:10 (37.50%) 0110: duty cycle ratio 7: 9 (43.75%) 0111: duty cycle ratio 8: 8 (50.00%) 1000: duty cycle ratio 9: 7 (56.25%) 1001: duty cycle ratio 10: 6 (62.50%) 1010: duty cycle ratio 11: 5 (68.75%) 1011: duty cycle ratio 12: 4 (75.00%) 1100: duty cycle ratio 13: 3 (81.25%) 1101: duty cycle ratio 14: 2 (87.50%) 1110: duty cycle ratio 15: 1 (93.75%) 1111: duty cycle ratio 16: 0 (100.00%, maximum brightness)
stmpe1601 basic pwm controller 39/61 [3:0] timing : in pwm mode: time unit of each on or off period in wdt mode: wait time in one-short mode: pulse width 0000 = 5 ms 0001 = 10 ms 0010 = 20 ms 0011 = 40 ms 0100 = 80 ms 0101 = 160 ms 0110 = 320 ms 0111 = 640 ms 1000 = 1280 ms 1001 = 2560 ms 1010 = 5120 ms 1011 = 10 s 1100 = 20 s 1101 = 40 s 1110 = 80 s 1111 = 160 s
basic pwm controller stmpe1601 40/61 pwm_n_ctrl_n=0-3 pwmn cont rol register n=0-3 address: 0x51, 0x55, 0x59, 0x5d type: r/w reset: 0x00 description: pwm blinking control register 76543210 period 0 period 1 repetition int_en frame rw rw rw rw rw rw rw rw 00000000 [7:6] period 0 : 1-4 time units of period 0 total length of period 0: (period 0 [1:0] + 1) * timing [5:4] period 1 : 0-3 time units of period 1 total length of period 1: (period 0 [1:0]) * timing [3:2] repetition : number of repetition 0 for infinite repetition [1] int_en : ?0? to disable interrupt generation on completion of sequence ?1? to enable interrupt generation on completion of sequence [0] frame : ?0? will output period 0 first ?1? will output period 1 first
stmpe1601 basic pwm controller 41/61 11.1 interrupt on basic pwm controller a basic pwm controller can be programmed to generate interrupts at the completion of a blinking sequence. however, there are some limitations: a) each basic pwm controller has its own bit in the interrupt enable/status registers. b) if enabled, completion in any of the pw m controller triggers interrupts. no interrupt will be generated if infinite repetition is set. c) in wdt mode, an interrupt is generated when timeout occurs d) in one-shot mode if auto-reload, interrupt is generated every time a valid trigger is detected if non-auto-reload, an interrupt is generated just once 11.2 trigger feature the basic pwm controller can be programmed to be controlled by an external ?trigger? signal. this feature can be used to implement: ? one-shot trigger circuit ? watchdog timer in one-shot trigger mode, a single pulse which the length is defined by timing[3:0] is sent to the pwm output, when a level transition is detected at the trigger source. in watchdog mode, a 120 s pulse is generated at pwm output when the programmed timer has elapsed without getting any trigger for the trigger source.
keypad controller stmpe1601 42/61 12 keypad controller the keypad controller consists of: ? 4 dedicated key controllers that support up to 4 simultaneous dedicated key presses; ? a keyscan controller support a maximum of 8 x 8 key matrix with detection of three simultaneous key presses; ? 8 special function key controllers that support up to 8 simultaneous ?special function? key presses. four of the column inputs can be configured as dedicated keys through the setting of dkey0~3 bits of the kpc_ctrl register. the normal key matrix size can be configured through the setting of kpc_row and kpc_col registers. the scanning of each individual row output and column input can be enabled or masked to support a key matrix of variable size from 1 x 1 to 8 x 8. it is allowed to have other 8 special function keys incorporated in the key matrix. the operation of the keypad controller is enabled by the scan bit of kpc_ctrl register. every key activity detected will be de-bounced for a period set by the db_0~7 bits of kpc_ctrl register before a key press or key release is confirmed and updated into the output fifo. the key data, indicating the key coordinates and its status (up or down), is loaded into the fifo at the end of a specif ied number of scanning cycles (set by scan_count0~3 bits of kpc_row_msb register ). an interrupt will be generated when a new set of key data is loaded. the fifo has a capacity for ten sets of key data. each set of key data consists of 5 bytes of information when any of the four dedicated keys is enabled. it is reduced to 4 bytes when no dedicated key is involved. when the fifo is full before its content is read, an overflow signal will be gen erated while the fifo will continue to hold its content but forbid loading of new key data set. figure 8. keypad controller the keypad column inputs enabled by the kpc_col register are normally 'high', with the corresponding input pins pulled up by resistors internally. after reset, all the keypad row outputs enabled by the kpc_row register are driven 'low'. if a key is pressed, its input 0-7 output 0-7 keypad matrix
stmpe1601 keypad controller 43/61 corresponding column in put will become 'low' after making contact with the 'low' voltage on its corresponding row output. once the keyscan controller senses a 'low' input on any of the column inputs, the scanning cycles will then start to determin e the exact key that has bee n pressed. the twelve row outputs will be driven 'low' on e by one during each scanning cycle. while one row is driven 'low', all other rows are in tri-state and pulled up. if there is any column input sensed as 'low' when a row is driven 'low', the key scan cont roller will then decode the key coordinates (its corresponding row number and column number), save the key data into a de-bounce buffer if available, confirm if it is a valid key press after de-bouncing, and update the key data into output data fifo if valid. 12.1 keypad configurations the keypad controller supports the following types of keys: up to 8 input * 8 output matrix keys up to 8 special function keys up to 4 dedicated keys figure 9. maximum configuration stmpe1601 matrix keypad (8*8) output 0-7 input 0-7 special function keys 8*8 (64) matrix keys 8 special function keys 0 dedicated ke y s
keypad controller stmpe1601 44/61 figure 10. maximum configuration stmpe1601 matrix keypad (4*8) output 0-7 input 4-7 special function keys 4*8 (32) matrix keys 4 special function keys 4 dedicated keys dedicated keys input 0-3
stmpe1601 keypad controller 45/61 12.2 registers in keypad controller table 24. registers in keypad controller address register name description auto-increment (during sequential r/w) 0x60 kpc_col keypad column scanning register yes 0x61 kpc_row_msb keypad row scanning register ye s 0x62 kpc_row_lsb yes 0x63 kpc_ctrl_msb keypad control register ye s 0x64 kpc_ctrl_lsb yes 0x65 kpc_combi_key_0 keypad combination key mask 0 yes 0x66 kpc_combi_key_1 keypad combination key mask 1 yes 0x67 kpc_combi_key_2 keypad combination key mask 2 yes 0x68 kpc_data_byte0 keypad data register ye s 0x69 kpc_data_byte1 yes 0x6a kpc_data_byte2 yes 0x6b kpc_data_byte3 yes 0x6c kpc_data_byte4 yes
keypad controller stmpe1601 46/61 kpc_col keypad colum register address: 0x60 type: r/w reset: 0x00 description: keypad column scanning 7 6543210 input column 0 ~ 7 rw rw rw rw rw rw rw rw 0 0000000 [7] input column : 1: turn on scanning of column 7 0: turn off [6] input column : 1: turn on scanning of column 6 0: turn off [5] input column : 1: turn on scanning of column 5 0: turn off [4] input column : 1: turn on scanning of column 4 0: turn off [3] input column : 1: turn on scanning of column 3 0: turn off [2] input column : 1: turn on scanning of column 2 0: turn off [1] input column : 1: turn on scanning of column 1 0: turn off [0] input column : 1: turn on scanning of column 0 0: turn off
stmpe1601 keypad controller 47/61 kpc_row_msb keypad row msb address: 0x61 type: r/w, r reset: description: keypad row scanning register 7 6543210 scan_pw1 scan_pw0 hib_wk - reserved r/w r/w r/w r r r r r 1 1000000 [7:6] scan_pw[1:0] : row output scanning pulse width setting: 00: 1x period of internal clock 01: 16x period of internal clock 10: 64x period of internal clock 11: 128x period of internal clock (default) (this setting is only applicable during normal operation mode. the scanning pulse width is 1x period of 32 khz clock during sleep mode.) [5] hib_wk : 1: to enable the keypad wake-up from hibernate mode 0: to disable [4:0] reserved
keypad controller stmpe1601 48/61 kpc_row_lsb keypad controller row (lsb) address: 0x62 type: reset: 0x00 description: keypad row scanning register. kpc_ctrl_msb keypad con troller control (msb ) address: 0x63 type: r/w reset: 0x00 description: keypad control register. 7 6543210 output row 0 ~ 7 r/w r/w r/w r/w r/w r/w r/w r/w 0 0000000 [7:0] output row 0 ~ 7 : ?1? to turn on scanning of the corresponding row; ?0? to turn off 7 6543210 scan_count_0 ~ 3 dkeyy_0 ~ 3 rw rw rw rw rw rw rw rw 0 0000000 [7:4] scan_count_0~ 3 : number of key scanning cycles elapsed before a confirmed key data is updated into output data fifo (0 ~ 15 cycles) [3] dkey_3 : set ?1? to use input column 3 as dedicated key [2] dkey_2 : set ?1? to use input column 2 as dedicated key [1] dkey_1: set ?1? to use input column 1 as dedicated key [0] dkey_0: set ?1? to use input column 0 as dedicated key
stmpe1601 keypad controller 49/61 kpc_ctrl_lsb keypad con troller control (lsb) address: 0x64 type: r/w reset: 0x00 description: keypad control register. 7 6543210 db[6:0] scan r/w r/w r/w r/w r/w r/w r/w r/w 0 0000000 [7:1] db_6:0 : 0-128 ms of de-bounce time [0] scan : 1: to start scanning 0: to stop
data registers stmpe1601 50/61 13 data registers the kpc_data register contains three bytes of information. the first two bytes store the key coordinates and status of any two keys from the normal key matrix, while the third byte store the status of dedicated keys. kpc_data_byte0 keypad data byte 0 address: 0x68 type: r reset: 0xf8 description: keypad data register. 7 6543210 up/downr3r2r1r0c2c1c0 r rrrrrrr 1 1111000 [7] up/down : 0: key-down 1: key-up [6:3] r[3:0] row number of key 1 (valid range: 0-7) 0x1111: no key [2:0] c[2:0} : column number of key 1 (valid range: 0-7)
stmpe1601 data registers 51/61 kpc_data_byte1 keypad data byte 1 address: 0x69 type: r reset: 0xf8 description: keypad data register. 7 6543210 up/downr3r2r1r0c2c1c0 r rrrrrrr 1 1111000 [7] up/down : 0: key-down 1: key-up [6:3] r[3:0] row number of key 2 (valid range: 0-7) 0x1111: no key [2:0] c[2:0} : column number of key 1 (valid range: 0-7)
data registers stmpe1601 52/61 kpc_data_byte2 keypad data byte 2 address: 0x6a type: r reset: 0xf8 description: keypad data register. 7 6543210 up/downr3r2r1r0c2c1c0 r rrrrrrr 1 1111000 [7] up/down : 0: key-down 1: key-up [6:3] r[3:0] row number of key 3 (valid range: 0 - 7) 0x1111: no key [2:0] c[2:0} : column number of key 3 (valid range: 0 -7)
stmpe1601 data registers 53/61 kpc_data_byte3 keypad data byte 3 address: 0x6b type: r reset: 0xff description: keypad data register. kpc_data_byte4 keypad data byte 4 address: 0x6c type: r reset: description: keypad data register. 7 6543210 sf7 sf6 sf5 sf4 sf3 sf2 sf1 sf0 r rrrrrrr 1 1111111 [7:0] sf[7:0] : 0: key-down 1: key-up 7 6543210 reserved dedicated key 0 ~ 3 r rrrrrrr 0 0001111 [7:4] reserved: [3:0] dedicated key [3:0] : 0: key-down 1 key-up
keypad combination key registers stmpe1601 54/61 14 keypad combination key registers the 3 kpc mask registers contains the key combination to be used to wake up the kpc and send an interrupt to the host system. kpc_comb_key_0-2 ke ypad combination 0-2 address: 0x65, 0x66, 0x67 type: r/w reset: 0xf8 description: keypad combination key mask registers. 7 6543210 active active r2 r1 r0 c2 c1 c0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1111000 [7:6] active : 00: key defined by bits 5:0 to be used for combination key wakeup but [7:0] must be ?f8? for no key from this register to be used for combination key wakeup [5:3] r[2:0] : row number of key 1 (valid range: 0 -7) [2:0] c[2:0] : column number of key 1 (valid range : 0-7)
stmpe1601 keypad combination key registers 55/61 resistance the maximum resistance between keypad outputs and inputs, inclusive of switch resistance, protection circuit resistance and connection, must be less than 3.2 k using the keypad controller it is not necessary to explicitly enable the internal pull-up and direction by configuring the gpio control registers. once a gpio is enabled for the keypad function, its internal pull-up and direction is controlled automatically. the scanning of column inputs should then be enabled for those gpio ports that are configured as keypad inputs by writing '1's to the corresponding bits in the kpc_col register. if any of the first three column inputs is to be used as dedicated key input, the corresponding bits in the kpc_ctrl_msb register should be set to '1'. the bits in the kpc_row_msb and kpc_row_lsb registers should also be set correctly to enable the row output scanning for the corresponding gpio ports programmed as keypad outputs. the scan count and de-bounce count should also be programmed into the keypad control registers before enabling the keypad controller operation. to enable the keypad controller operation, the en_kpc bit in the system control register must be set to '1' to provide the required clock signals. the ke ypad controller will then start its operation by setting the scan bit in the kpc_ctr l_lsb register to '1'. the keypad controller operation can be disabled by setting the scan bit back to '0'. to further reduce the power consumption, the clock signals can be cut off from the keypad controller by setting the en_kpc bit to '0'. as long as there is any un-read key-press in the keypad controller buffer, the kpc interrupt will always be asserted. ghost key handling the ghost key is an inherent in keypad matrix that is not equipped with a diode at each of the keys. while it is not possible to avoid ghost key occurrence, the stmpe1601 allows the detection of possible ghost keys by the capab ility of detecting 3 simu ltaneous key-presses in the key matrix. the ghost key is only possible if 3 keys are pressed and held down together in a keypad matrix. if 3 keys are reported by the stmpe1601 keypad controller, it indicates a potential ghost key situation. the system may check for the possibility of a ghost key by analyzing the coordinates of the 3 keys. if the 3 keys form 3 corners of a rectangle, it could be a ghost key situation. a ghost key may also occur in the ?special function keys?. the keypad controller does not attempt to avoid the occurrence of ghost keys. however, the system should be aware that if more than one special fu nction key is reported, then ther e is a possibility of ghost keys. key detection priority a dedicated key is always detected, if this is enabled. when a special function key is detected, the matrix key scanning on the same input line is disabled. up to 3 matrix keys can be detected. matrix keys that fall on activated special function keys will not be counted. as a result of these priority rules, a matrix key is ignored by the keypad controller when the special function key on the same input line is detected, even if the matrix key is being
keypad combination key registers stmpe1601 56/61 pressed down before the special function key. hence, when a matrix is reported "key-down" and it is being held down while the correspondi ng special function is being pressed, a "no- key" status will be reported for the matrix key wh en the special function key is reported "key- down". if the matrix key is released while the special function key is still being held down, no "key-up" will be reported for the matrix key. on the other hand, if the matrix key is released after the special function key is reported "key -up", then a new "key-down" will be reported for the matrix key, followed by "key-up". keypad wakeup from sleep and hibernate modes the keypad controller is functional in sleep mode as long as it is enabled before entering the sleep mode. it will then wake the system up in to operational mode if a valid key press is detected. in the case of hibernate mode, the 'hib_wk' bit in 'kpc_row_msb' register must be set to '1' in order to enable the system wakeup by me ans of a valid key press. when this is enabled, an asynchronous detection of the keypad column input activity is turned on during the hibernate mode. if any key activity is detected, the system is expected to enter the sleep mode temporarily to allow a debouncing of key press to take place. if a valid key is detected, the system will then wake up in to operational mode; otherwise, the device will go back into hibernate mode. keypad controller combination-key interrupt the keypad controller (kpc) can be programmed to wake up from sleep mode if a unique combination keys is detected. th is combination keys of up to 3 keys is specified in the kpc combination set 0-2 registers. note that the sequence of the key press is not relevant, as long as the 1-3 keys specified in the kpc _combikey are detected, the kpc will wake up and interrupt the host. if any other keys (beside those specified in the kpc_combikey registers) are pressed, it would be considered invalid combinatio n and interrupt will not be generated. all the "active" keys must be pressed and held together, for the combi-key interrupt to be generated.
stmpe1601 miscellaneous features 57/61 15 miscellaneous features 15.1 reset the stmpe1601 is equipped with an internal por circuit that holds the device in reset state, until the clock is steady and v cc input is valid. the host system may choose to reset the stmpe1601 by asserting the reset_n pin. 15.2 under voltage lockout the stmpe1601 is equipped with an internal uvlo (under voltage lockout) circuit that generates a reset signal, when the main supply voltage falls below the allowed threshold.
package mechanical data stmpe1601 58/61 16 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com figure 11. tfbga25 package outline table 25. tfbga25 mechanical data dim. mm. inch min typ max min typ max a 1.0 1.1 1.16 39.4 43.3 45.7 a1 0.25 9.8 a2 0.78 0.86 30.7 33.9 b 0.25 0.30 0.35 9.8 11.8 13.8 d 2.9 3.0 3.1 114.2 118.1 122.0 d1 2 78.8 e 2.9 3.0 3.1 114.2 118.1 122.0 e1 2 78.8 e 0.5 19.7 se 0.25 9.8
stmpe1601 package mechanical data 59/61 figure 12. tape and reel dimension table 26. tfbga25 tape and reel mechanical data symbol millimeters inches min typ max min typ max a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 14.4 0.567 ao 3.3 0.130 bo 3.3 0.130 ko 1.60 0.063 po 3.9 4.1 0.153 0.161 p 7.9 8.1 0.311 0.319
revision history stmpe1601 60/61 17 revision history table 27. document revision history date revision changes 10-jan-2008 1 initial release. 15-feb-2008 2 modified figure 1 on page 4 , added info on register description: on page 40 and section 6.1: minimizing curre nt drain on i2c address lines on page 13 , updated table 7: dc electrical characteristics on page 9 , minor text changes. 14-mar-2008 3 updated table 7: dc electrical characteristics on page 9 02-june-2008 4 document status prom oted from preliminary data to datasheet. modified: figure 1 on page 4 , r up values in ta b l e 1 0 , channel function enabling and pwm trigger register n = 0 - 3 registers. updated: section 6: i2c interface , section 7: system controller , section 9: interrupt system , section 10: gpio controller , section 11: basic pwm controller , section 12: keypad controller
stmpe1601 61/61 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STMPE1601TBR

	To Download STMPE1601TBR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .