View ISL29125IROZ-T7_8782546.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 digital red, green and blue color light sensor with ir blocking filter isl29125 the isl29125 is a low power, high sensitivity, red, green and blue color light sensor (rgb) with an i 2 c (smbus compatible) interface. its state-of-the-art photodiode array provides an accurate rgb spectral response and excellent light source to light source variation (ls2ls). the isl29125 is designed to reject ir in light sources allowing the device to operate in environments from sunlight to dark rooms. the integrating adc rejects 50hz and 60hz flicker caused by artificial light sources. a selectable range allows the user to optimize sensitivity suitable for the specific application. in normal operation mode the device co nsumes 56a, which reduces to 0.5a in power-down mode. the isl29125 supports hardware and software user programmable interrupt thresholds. the interrupt persistency feature redu ces false trigger notification. the device operates on supplies (vdd) from 2.25v to 3.63v, i 2 c supply from 1.7v to 3.63v, and operating temperature over the -40c to +85c. features ? 56a operating current, 0.5a shutdown current ? selectable range (via i 2 c) ?i 2 c (smbus compatible) output ? adc resolution 16 bits ? programmable interrupt windows ? two optical sensitivity ranges - range 0 = 5.7m lux to 375 lux - range 1 = 0.152 lux to 10,000 lux ? operating power supply 2.25 to 3.63v ?i 2 c power supply 1.7v to 3.63v ? 6 ld odfn (1.65x1.65x0.7mm) package applications ? smart phone, pda, gps, tablet pcs, lcd-tvs, digital picture frames, digital cameras ? dynamic display color balancing ? printer color enhancement ? industrial/commercial led lighting color management ? ambient light color detection/correction ? oled display aging compensation related literature an1914 , ?evaluation hardware/software user manual for rgb sensor? figure 1. typical application diagram figure 2. normalized spectral response for red, green and blue sensing isl29125 mcu scl sda 4 6 1 3 5 vdd gnd scl sda gpio int vbus 2 nc r2 r3 r4 vdd r1 c1 c2 r1 ? 100 r2 ? 2.7k to 10k r3 ? 2.7k to 10k r4 ? 2.7k to 10k c1 ? 1f c2 ? 0.1f 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830 normalized to green wavelength red green blue 1931 std red 1931 std green 1931 std blue normalized to green caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013, 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. january 24, 2014 fn8424.2
isl29125 2 fn8424.2 january 24, 2014 submit document feedback block diagram pin configuration isl29125 (6 ld odfn) top view scl sda 4 6 r integrating adc cmd register data register interrupt i ref f osc command register light data process 5 int 3 gnd 1 vdd i 2 c/smb red green blue sda scl vdd gnd 5 6 1 2 nc 4 3 in t pin descriptions pin number pin name description 1 vdd positive supply 2 nc no connect 3gndground 4sdai 2 c serial data 5int interrupt; low for interrupt alarming. int pin is open drain. int remains asserted until the interrupt status bit is reset. int also become a input when it is set in sync mode 6scli 2 c serial clock ordering information part number (notes 1, 2, 3) temp range (c) package tape & reel (pb-free) pkg. dwg. # ISL29125IROZ-T7 -40 to +85 6 ld odfn l6.1.65x1.65 isl29125eval1z evaluation board . notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free sold ering operations. intersil pb-fr ee products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product information page for isl29125. for more information on msl please see tech brief tb477 .
isl29125 3 fn8424.2 january 24, 2014 submit document feedback absolute maximum rating s thermal information vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0v i 2 c bus (scl, sda) and int pin voltage. . . . . . . . . . . . . . . . . . -0.2v to 4.0v i 2 c bus (scl, sda) and int pin current. . . . . . . . . . . . . . . . . . . . . . . <10ma input voltage slew rate (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1v/s esd ratings human body model (hbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5kv machine model (mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300v charged device model (cdm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv thermal resistance (typical) ja (c/w) 6 ld odfn package (note 4) . . . . . . . . . . . . . . . . . . . . . 260 maximum junction temperature (tj max ). . . . . . . . . . . . . . . . . . . . . . . +90c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . electrical specifications v dd = 3.0v, t a = +25c, 16-bit adc operation, unless otherwise specified. symbol parameter condition min (note 6) typ max (note 6) unit v dd power supply range 2.25 3.63 v i dd supply current 56 85 a i dd1 supply current when standby software disabled 29 37 a i dd2 supply current when powered down software disabled 0.5 1.45 a v i2c supply voltage range for i 2 c interface 1.7 3.63 v t int adc integration/conversion time 16-bit adc data 101 ms f i2c i 2 c clock rate range 500 khz d dark count output when dark lux = 0 lux, range = 0 (375lux) 1 5 counts cct corrected color temperature accuracy illuminant a is at 300 lux (see note 11 onpage 11 and ?references? on page 15 about cie 1931, planckian locus and standard illuminants) 5 % d fs full scale adc code adc 16 bits 65535 counts fullscale on range 0 green = 565nm 18 w/cm 2 red = 620nm 20 w/cm 2 blue = 485nm 30 w/cm 2 notes: 5. 565nm green, 620nm red led, 485nm blue in wh ite led is used in production test. it?s irradiance is calibrated to produce the same data count against an illuminance level of 130 lux fluorescent light. 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 7. sda and int current sinking capability are guaranteed by design.
isl29125 4 fn8424.2 january 24, 2014 submit document feedback i 2 c interface specifications v dd = 3.0v, t a = +25c, 16-bit adc operation, unless otherwise specified. symbol parameter conditions min (note 6) typ max (note 6) units vil sda and scl input buffer low voltage 0.55 v vih sda and scl input buffer high voltage 1.25 v vhys (note 8) sda and scl input buffer hysteresis 0.05xvdd v vol (note 8) sda output buffer low voltage (open-drain), sinking 4ma 00.4v cpin (note 8) sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf fscl scl frequency 500 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid 900 ns t buf time the bus must be free before the start of a new transmission 1300 ns t low scl low time 1300 ns t high scl high time 600 ns t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:dat input data setup time 100 ns t hd:dat input data hold time 30 ns t su:sto stop condition setup time 600 ns t hd:sthd:st stop condition hold time 600 ns t hd:st output data hold time 0ns t hd:st (note 8) sda and scl rise time 20+0.1xcb ns t hd:st (note 8) sda and scl fall time 20+0.1xcb ns cb (note 8) capacitive loading of sda or scl total on-chip and off-chip 400 pf r pu (note 8) sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for c b = 400pf, max is about 2k ? ~ 2.5k ? . for c b = 40pf, max is about 15k ? ~ 20k ? 1k ? notes: 8. limits should be considered typi cal and are not production tested. 9. these are i 2 c specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specificatio n. 10. c b is the capacitance of the bus in pf.
isl29125 5 fn8424.2 january 24, 2014 submit document feedback sda vs scl timing figure 3. i 2 c bus timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:sto figure 4. i 2 c write cycle timing scl sda t wc 8th bit of last byte ack stop condition start condition typical performance curves figure 5. normalized spectral response for ambient light sensing figure 6. radiation pattern 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830 normalized to green wavelength red green blue 1931 std red 1931 std green 1931 std blue normalized to green 0 0.2 0.4 0.6 0.8 1.0 1.2 -90 0 10 20 30 40 50 60 70 80 90 normalized angle ( ) red green blue -10 -20 -30 -40 -50 -60 -70 -80
isl29125 6 fn8424.2 january 24, 2014 submit document feedback principles of operation photodiodes and adc the isl29125 contains three photodiode arrays, which convert light into current. the spectral response for red, green and blue color ambient intensity sens ing is, as shown in figure 2. after light is converted to current during the light to signal process, the current output is converted to a digital count by an on-chip analog-to-digital converter (adc). the adc converter resolution is selectable from 12 or 16 bits. the adc conversion time is inversely proportion al to the adc resolution. the adc converter uses an integrating architecture. this conversion method is ideal for converting small signals in the presence of a periodic noise. a 100ms integration time (16-bit mode) for instance, rejects 50hz an d 60hz power line as well as florescent flicker noise. the adc integration time is determ ined by an internal oscillator and the n-bit (n = 12, 16) counter inside the adc. a good balancing act of integration time and resolution depends on the application for optimu m system performance. the adc provides two programmable ranges to dynamically accommodate different lighting conditions. for dim conditions, the adc can be configured at its high sensitivity (low optical) range. for bright conditions, the adc can be configured at its low sensitivity (higher optical) range. note that the effective optical sensitivity of the isl29125 in terms of counts/w/cm 2 is directly proportional to the adc integration time. sync mode sync mode is when b5 at reg0x1 is set to ?1?, the int pin becomes an input pin. this mode is beneficial for some systems which have multiple sensors on i 2 c bus. once b5 is set, on the rising edge of int, adc starts conversion, so that multiples devices would measure at exactly the same time. yet, to read data out, the system needs to have a different i 2 c address for each sensor or have a multiplexer. moreover, b5 is set to ?0?, the int pin will be asserted whenever the sensor has interrupt trigger. interrupt function the active low interrupt pin is an open drain pull-down configuration. the interrupt pin se rves as an alarm or monitoring function to determine whether the ambient light level exceeds the upper threshold or goes below the lower threshold. it should be noted that the function of adc conversion continues without stopping after interrupt is asserted. if the user needs to read the adc count that triggers the interrupt, the reading should be done before the data registers are refreshed by the following conversions. the user can also configure the persistency of the interrupt pin. this reduces the possibility of false triggers, such as noise or sudden spikes in ambient light conditions. an unexpected camera flash, for example, can be ignored by setting the persistency to 8 integration cycles. isl29125 interrupt modes can be selected at bit[1:0] at reg0x03 table11. user can select red or green or blue to be the interrupt target. an interrupt event (rgbthf) bit at reg0x08 is governed by registers 4 through 7. the user writes a high and low threshold value to these registers and the isl29125 will issue an interrupt flag if the actual count stored in registers 0x9 and 0xa for green or registers 0xb and 0xc for red or register 0xd and 0xe for blue are outside the user?s programmed window. once isl29125 issues the interrupt flag, the interrupt status (rgbthf) bit at reg0x08 is asserted to logic high and the int pin goes low. both the int pin and the interrupt status bit are automatically cleared at the end of the 8-bit device register byte (0x08) transfer. by default (rgbthf) bit is low or it is within the interrupt thresholds window. power-on reset the power-on reset (por) circuitr y protects the internal logic against powering up in the in correct state. the isl29125 will power-up into standby mode after vdd exceeds the por trigger level and will power-down into reset mode when vdd drops below the por trigger level. this bidirectional por feature protects the device against ?brown-out? failure following a temporary loss of power. the por is an important feature because it prevents the isl29125 from starting to operate with insufficient power supply voltage. the isl29125 prevents communication to its registers and reduces the likelihood of da ta corruption on power-up. serial interface the isl29125 supports the inter-integrated circuit (i 2 c) bus data transmission protocol. the i 2 c bus is a two wire serial bidirectional interface consisting of scl (clock) and sda (data). both the wires are connected to the device supply via pull-up resistors. the i 2 c protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the transmitting device pulls down the sda line to transmit a ?0 ? and releases it to transmit a ?1?. the master always initiates the data transfer, only when the bus is not busy and provides the clock for both transmit and receive operations. the isl29125 operates as a slave device in all applications. the serial communication over the i 2 c interface is conducted by sending the most significant bit (msb) of each byte of data first. start condition during data transfer, the sda line must remain stable while the scl line is high. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high (refer to figure 9). the isl29125 continuously monitors the sda and scl lines fo r the start condition and does not respond to any command until this condition is met (refer to figure 9). a start condition is ignored during the power-up sequence. stop condition all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (refer to figure 9). a stop condition at the end of a read/write operation places the de vice in its standby mode. if a stop is issued in the middle of a data byte, or before 1 full data byte and ack is sent, then the serial communication of isl29125
isl29125 7 fn8424.2 january 24, 2014 submit document feedback resets itself without performing the read/wri te. the contents of the register array are not affected. acknowledge an acknowledge (ack) is a software convention used to indicate a successful data transfer. the tr ansmitting device releases the sda bus after transmitting 8-bits . during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (refer to figure 9). the isl29125 responds with an ack after re cognition of a start condition followed by a valid identificati on byte and once again, after successful receipt of an address byte. the isl29125 also responds with an ack after receiving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation device addressing following a start condition, the master must output a device address byte. the 7 msbs of the device address byte are known as the device identifier. the device identifier bits of isl29125 are internally hard-wired as ?1000100?. the lsb of the device address byte is defined as read or write (r/w ) bit. when this r/w bit is a ?1?, a read operation is selected and when ?0?, a write operation is selected (refer to figure 7). the master generates a start condition followed by device address byte 1000100x (x as r/w ) and the isl29125 compares it with the internal device identifier. upon a correct comparison, the device outputs an acknowledge (low) on the sda line (refer to figure 9). write operation byte write in a byte write operation, isl29125 requires the device address byte, register address byte and the data byte. the master starts the communication with a start co ndition. upon receipt of the device address byte, register ad dress byte and the data byte, the isl29125 responds with an acknowledge (ack). following the isl29125 data acknowledge response, the master terminates the transfer by generating a stop condition. isl29125 then begins an internal write cycle of the data to the volatile memory. during the internal write cycle, the device inputs are disabled and the sda line is in a high impedance state, so the device will not respond to any requests from the master (refer to figure 8). burst write the isl29125 has a burst write operation, which allows the master to write multiple consecutive bytes from a specific address location. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data byte is transferred, the master can write to the whole register array. after the receipt of each byte, the isl29125 responds with an acknowledge and the address is internally incremented by one. the addre ss pointer remains at the last address byte written. when the counter reaches the end of the register address list, it ?rolls over? and goes back to the first register address. figure 7. device address, register address and data byte device address byte register address byte data byte 1 0 0 0 1 0 0 r/w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 figure 8. byte write sequence 10001000 a c k a c k a c k s t o p s t a r t device address byte address byte data byte signal from master device signal at sda signals from slave device
isl29125 8 fn8424.2 january 24, 2014 submit document feedback read operation isl29125 has two basic read oper ations: byte read and burst read. byte read byte read operations allows th e master to access any register location in the isl29125. the byte read operation is a two step process. the master issues the start condition and the device address byte with the r/w bit set to ?0?, receives an acknowledge, then issues the register address byte. after acknowledging receipt of the register address byte, the master immediately issues another start condition and the device address byte with the r/w bit set to ?1?. this is followed by an acknowledge from the device and then by the 8-bit data word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 10. burst read burst read operation is identica l to the byte read operation. after the first data byte is transmitted, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read op eration by not responding with an acknowledge but issuing a stop condition (refer to figure 11). for more information about the i 2 c standard, please consult the phillips ? i 2 c specification documents. figure 9. start, data stable, acknowledge and stop condition figure 10. byte address read sequence sda from receiver sda from transmitter scl from master start data change data stable data stable ack stop 8 th clk 9 th clk high impedance 10001000 a c k a c k s t a r t device address write address byte signal from master device signal at sda signals from slave device a c k s t o p device address read data byte s t a r t 10001001 figure 11. burst read sequence 10001000 a c k a c k s t a r t device address write address byte signal from master device signal at sda signals from slave device a c k s t o p device address read data byte 1 s t a r t 10001001 a c k data byte 2 a c k data byte n (?n? is any integer greater than 1)
isl29125 9 fn8424.2 january 24, 2014 submit document feedback register description following are detailed descriptions of the control registers rela ted to the operation of the isl29125 ambient light sensor devi ce. these registers are accessed by the i 2 c serial interface. for details on the i 2 c interface, refer to ?serial interface? on page 6. all the features of the device are controlled by the registers. the adc data can also be read. the following sections explain t he details of each register bit. all reserved bits are intersil used bits on ly. the value of the reserved bit can change without any notice. device register (address: 0x00) register 0x00 performs two functions. if reg 0x00 is in read only mode then it will be a device id. by default, the device id i s 0x7d in hex. write 46h to register 0x00 in the write only, the device will reset all registers to their default states. configuation-1 register (address: 0x01) table 1. register map name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 device id 00x00 id[7] id[6] id[5] id[4] id[3] id[2] id[1] id[0] 0x7d ro device reset id[7] id[6] id[5] id[4] id[3] id[2] id[1] id[0] na wo configuration - 1 1 0x01 reserved sync bits rng mode[2] mode[1] mode[0] 0x00 rw configuration - 2 2 0x02 ircom reserved alscc[5] alscc[4] alscc[3] alscc[2] alscc[1] alscc[0] 0x00 rw configuration - 3 3 0x03 reserved conven pr st[1] prst[0] intsel[1] intsel[0] 0x00 rw low threshold - low byte 4 0x04 thl[7] thl[6] thl[5] thl[4] thl[3] thl[2] thl[1] thl[0] 0x00 rw low threshold - high byte 5 0x05 thl[15] thl[14] thl[13] thl[12] thl[11] thl[10] thl[9] thl[8] 0x00 rw high threshold - low byte 6 0x06 thh[7] thh[6] thh[5] thh[4] thh[3] thh[2] thh[1] thh[0] 0xff rw high threshold - high byte 7 0x07 thh[15] thh[14] thh[13] thh[12] thh[11] thh[10] thh[9] thh[8] 0xff rw status flags 8 0x08 reserved grbcf[1] grbcf[0] reserved boutf convenf rgbthf 0x04 ro green data - low byte 9 0x09 green[7] green[6] green[5] green[4] g reen[3] green[2] green[1] green[0] 0x00 rw green data - high byte 10 0x0a green[15] green[14] green[13] green[12] gr een[11] green[10] green[9] green[8] 0x00 rw red data - low byte 11 0x0b red[7] red[6] red[5] red[4] red[3] red[2] red[1] red[0] 0x00 rw red data - high byte 12 0x0c red[15] red[14] red[13] red[12] red[11] red[10] red[9] red[8] 0x00 rw blue data - low byte 13 0x0d blue[7] blue[6] blue[5] blue[4] blue[3] blue[2] blue[1] blue[0] 0x00 rw blue data - high byte 14 0x0e blue[15] blue[14] blue[13] blue[12] blue[11] blue[10] blue[9] blue[8] 0x00 rw table 2. device id register address name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 device id 00x00 id[7] id[6] id[5] id[4] id[3] id[2] id[1] id[0] 0x7d ro device reset id[7] id[6] id[5] id[4] id[3] id[2] id[1] id[0] na wo table 3. configuration-1 name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 configuration-1 1 0x01 reserved reserved sy nc bits rng mode[2] mode[1] mode[0] 0x00 rw
isl29125 10 fn8424.2 january 24, 2014 submit document feedback rgb operating modes [b2:b0] this device has various rgb operating modes. these modes are selected by setting b2:b0 bits in table 4. the device powers up on a disable mode. all operating modes are in continuous adc conversion. the following bits ar e used to enable the operating mode rgb data sensing range [b3] the full scale rgb range has two different selectable ranges at bit 3. the range determines the adc resolution (12 bits and 16 bits). each range has a maximum allowable lux value. higher range values offer better resolution and wider lux value. adc resolution [b4] adc?s resolution and the number of clock cycles per conversion is determined by this bit in table 6. changing the resolution of the adc, changes the number of clock cycles of the adc which in turn changes the integration time. integration time is the period the adc samples the photodiode curre nt signal for a measurement rgb start synced at int pin sync has two different selectable modes at bit 5. b5 sets to 0 then the int pin gets asserted whenever the sensor interrupts. b5 sets to 1 then the int pin becomes input pin. on the rising edge at int pin, sync starts adc conversion. the int pin sets to interrupt mode by default. more information about sync at ?principles of operation? on page 6. configuration-2 register (address: 0x02) active infrared (ir) compensation the device is designed for operation under dark glass cover wh ich significantly attenuates visi ble light and pass the infrared light without much attenuation. the device has an on chip passive opti cal filter designed to block (rej ect) most of the incident infr a red. in addition, the device provides a pr ogrammable active ir compensation which allows fine tuning of residual infrared components fr om the output which allows optimizing the measurement variation betw een differing ir-content light sources. b7 is ?ir comp offset? and b[5:0] is ?ir comp adjust? which provides means for adjusting ir compensation. b7=?0? + b[5:0] is the effective ir compensation from 0 to 63 codes and b7set to ?1?+b[5:0] the effective ir compensati on is from 106 to 169. table 9 shows lightweight for each ir compensation bit and figure 12 is a typical system measure for bo th ir comp adjust and ir comp offset. more detail about how to ir compensation, see ir compensation in ?applications information? on page 13. recommended to set bf at register 0x02 to max out ir compensation value. it make high range reach more than 10,000lux. table 4. operation modes b2:b0 operation 000 power down (adc conversion) 001 green only 010 red only 011 blue only 100 stand by (no adc conversion) 101 green/red/blue 110 green/red 111 green/blue table 5. sensing ranges b3 ranges 0 375 lux 1 10,000 lux table 6. adc resolutions b4 resolution 016 bits 112 bits table 7. synced at int b5 operation 0 adc start at i 2 c write 0x01 1 adc start at rising int table 8. configuration-2 name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 configuration-2 2 0x02 ir-com reserved alscc[5] alscc[4] alscc[3] alscc[2] alscc[1] alscc[0] 0x00 rw
isl29125 11 fn8424.2 january 24, 2014 submit document feedback . configuration-3 register (address: 0x03) interrupt threshold assignment [b1:0] the interrupt status bit (rgbthf) bit0 at reg0x08 is a status bit for light intensity detection. the bi t is set to logic high when the light intensity crosses the interrupt thresholds window (register address 0x04 - 0x07) and set to logic low when its within the interrupt thresholds window. once the interrupt is triggered, the int pin goes low and the interrupt status bit goes high until the status bit is polled through the i 2 c read command. both the int pin and the interrupt status bit are automatically cleared at the end of the 8-bit device register byte (0x08) transfer. table 11 shows selectable inte rrupt for the device. interrupt persist control [b3:2] to minimize interrupt events du e to 'transient' conditions, an interrupt persistency option is available. in the event of transient condition an 'x-consecutive' numb er of interrupt must happen before the interrupt flag and pint (int ) pin gets driven low. the interrupt is active-low and rema ins asserted until the status register (addr: 0x08) is read to clear the bit(s). rgb conversion done to int control [b4] table 9. b7 b6 b5 b4 b3 b2 b1 b0 light-weight ir-com reserved alscc[5] alscc[4] alscc[3] alscc[2] alscc[1] alscc[0] 106 32168421codes figure 12. ir compensation set 0 10 20 30 40 50 60 70 80 90 100 0 32 64 96 128 160 192 224 256 compensation value compensation register (0x02) set value (decimal) ir comp adjust ir comp offset 0x80-0xbf-ir 0x00-0x3f (% range adjust) b[5:0] b7 is ?0? or ?1? notes: 11. a illuminant is intended to represent typical, dome stic, tungsten-filament lighting. its cct is about 2856k. 12. d series of illuminants are constructed to represent natural daylight. d65 is used in lab to represent as noon light to test . its cct is 6504k. 13. f series of illuminants represent various types of fluorescen t lighting. f2 is cool white fluorescent using in lab to test. its cct is 4230k. table 10. configuration-3 name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 configuration-3 3 0x03 reserved reserved reserved conven prst[1] prst[0] intsel[1] intsel[0] 0x00 rw table 11. interrupt status b1:0 interrupt status 00 no interrupt 01 green interrupt 10 red interrupt 11 blue interrupt table 12. interrupt persist b3:2 number of integration cycle 00 1 01 2 10 4 11 8 table 13. b4 conversion done 0disable 1enable
isl29125 12 fn8424.2 january 24, 2014 submit document feedback lower interrupt register (address: 0x04 and 0x 05) and higher interrupt register (address: 0x06 and 0x07) interrupt threshold (reg 0x4, reg0x5, reg0x6 and reg0x7) the interrupt threshold level is a 16-bit number (low threshol d-1 and low threshold-2). the lower interrupt threshold registers are used to set the lower trigger point for interrupt generation. if the als value crosses below or is equal to the lower threshold, an interrupt is asserted on the interrupt pin (low) and the interrupt status bi t (high). registers low threshold- 1 (0x04 or 0x6) and low thresh old-2 (0x05 or 0x7) provide the low and high bytes, respectively, of the lower interrupt threshold. the interrupt threshold registers default to 0x00 upon power up. the user can also configure the persistenc y for the interrupt pin. this reduces the possibility of false tr iggers, such as noise or sudden spikes in ambient light conditions or an unex pected camera flash, for example, can be ignored by setting the persistency to 8 integration cycles. status flag register (address: 0x08) rgbthf [b0] this is the status bit of the interr upt. the bit is set to logic high when the interrupt thresholds have been triggered (out of threshold window) and logic low when not yet triggered. once activated and the interrupt is triggered, the int pin goes low and the interrupt status bit goes high until the status bit is polled through the i 2 c read command. both the int output and the interrupt status bit are automati cally cleared at the end of the 8-bit (00h) command register transfer convenf [b1] this is the status bit of conversion. the bit is set to logic high when the conversion have been completed and logic low when the conversion is not done or not conversion. boutf [b2] bit2 on register address 0x08 is a status bit for brownout condition (bout). the default value of this bit is high, bout = 1, during the initial power up. this indicates the device may possibly have gone through a brownout condition. therefore, the status bit should be reset to low, bout = 0, by an i 2 c write command during the initial configuration of the device. the default register value is 0x04 at power-on. rgbcf [b5:b4] b[5:4] are flag bits to display either red or green or blue is under conversion process at table 19. table 14. configuration-3 name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 low threshold-low byte 4 0x04 thl[7] thl[6] thl[5] thl[4] thl[3] thl[2] thl[1] thl[0] 0x00 rw low threshold- high byte 5 0x05 thh[7] thh[6] thh[5] thh[4] thh[3] thh[2] thh[1] thh[0] 0x00 rw high threshold- low byte 6 0x06 thl[7] thl[6] thl[5] thl[4] thl[3] thl[2] thl[1] thl[0] 0xff rw high threshold-high byte 7 0x07 thh[7] thh[6] thh[5] thh[4] thh[3] thh[2] thh[1] thh[0] 0xff rw table 15. status flag register name register address register bits default access status flag dec hex b7 b6 b5 b4 b3 b2 b1 b0 8 0x08 reserved reserved rgbcf[1] rgbcf[0] reserved boutf convenf rgbthf 0x04 ro table 16. interrupt flag b0 operation 0 interrupt is cleared or not triggered yet 1 interrupt is triggered table 17. conversion flag b1 operation 0 still convert or cleared 1 conversion completed table 18. brownout flag b2 operation 0no brownout 1 power down or brownout occurred table 19. conversion flag b5:4 rgb under conversion 00 no operation 01 green 10 red 11 blue
isl29125 13 fn8424.2 january 24, 2014 submit document feedback data register (address: 0x09,0x0a,0xb,0xc,0xd and 0xe) the isl29125 has two 8-bit read-o nly registers to hold the higher and lower byte of the adc value. the lower byte and higher by tes are accessed at address respectively. for 16-bit resolution, the data is from d0 to d15; for 12-bit resolution, the data is from d0 to d11. the registers are refreshed after every conversion cycle. the de fault register value is 0x00 at power-on. because all the regis ter are double buffered the data is always valid on the data registers. applications information below is a plot of the 1931 standard normalized spectral response of various types of light sources for reference. system compensation and rgb to xyz transform (chroma meter) the accuracy of the rgb sensor is extremely sensitive to the opto-mechanical design of the sy stem in which it resides. the compensation setting and calculation of rgb to xyz transform should be characterized within that environment with as many standard illuminants as possibl e. a minimal recommended set would include a, f2 and d65 illuminants (see notes 11, 12, 13 and ?references? on page 15 about iec 1931, planckian locus and standard illuminants) . the two most important opto-mechnical features are fo v (field of view fwhm) and optical filters as example of tinted cell phone glass through which the sensor will detect the ambient lighting. with the combination of the fov and a large sample for the filter (30x30mm) it is possible to de termine the best compensation and xyz transform coefficients. it is also possible to project the accuracy of the measurement system. rgb xyz transform once the proper compensation setting is determined measure the rgb values of the various illuminates at this value. calculate the rgb to xyz transform coefficients based on the measured result against appropriate chroma meter standard (using x and y values) as shown in equation 1. x, y and z are in the iec system which specifies the color and brightness of a particular ho mogeneous visual stimulus. r, g and b are digital output from the sensor. cs are coefficents. these co efficients will be changed respectively depending on the system setup. compensation the compensation adjustment is used to balance the various illuminates of interest (a, f2 and d65 recommended) such that the value measured at the same power level (measured with a lux meter) is the closed value. since the compensation table 20. configuration-3 name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 green data-low byte 9 0x09 green[7] green[6] green[5] green[4] g reen[3] green[2] green[1] green[0] 0x00 rw green data-high byte 10 0x0a green[15] green[14] green[13] green[12] green[11] green[10] green[9] green[8] 0x00 rw red data-low byte 11 0x0b red[7] red[6] red[5] red[4] red[3] red[2] red[1] red[0] 0x00 rw red data-high byte 12 0x0c red15] red[14] red[13] red[12] red[11] red[10] red[9] red[8] 0x00 rw red data-low byte 13 0x0d blue[7] blue[6] blue[5] blue[4] blue[3] blue[2] blue[1] red[0] 0x00 rw red data-high byte 14 0x0e blue[15] blue[14] blue[13] blue[12] blue[11] blue[10] blue[9] red[8] 0x00 rw figure 13. 1931 standard normalized spectral response of light sources 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830 normalized to green wavelength red green blue 1931 std red 1931 std green 1931 std blue normalized to green x y z c xr c xg c xb c yr c yg c yb c zr c zg c zb x r g b = (eq. 1)
isl29125 14 fn8424.2 january 24, 2014 submit document feedback adjustment is piecewise linear the proper setting can be determined by extrapolating from a pair of measurements and calculating the closest intersecti on of the sources of interest. the configuration register (reg 0x02[7:0]) allows coarse tuning b7 and fine tuning (b[5:0] of the residual infr ared component from the als output. the recommended procedure for determining als ir compensation is as follows: ? illuminate the isl29125 based de sign configuration with a no ir f2 light source. record the als measurement and the lux level. ? illuminate the device with a an d d65 with heavy ir and the f2 light sources. take an als measurement and lux level measurement. ? it really depends on the system setup in order to adjust the configuration register (reg 0x02, b7 and b[5:0]) to compensate for the ir contribution. ? repeat steps above until the ir light source contribution to the als measurement is under 10 pe rcent assuming no change in lux level due to ir light source. figure 14 is an example shows how to calculate the compensation for varying level of infrared components such as a, f2 and d65 (see notes 11, 12 and 13). with compensation adjustment from 0% to 100%. the crossing point is the ir compensation value which makes tighter variation of varying level of infrared components. this setup system is sensor without ir tinted glass and illuminates with 3 different light sources. since it is not under ir tinted glass, then reg0x2 setups like b7 = ?0? and b[5:0] is at about 25% compensation adjust(%/range) which means about 40 codes. calculating lux y-coordinate is ev measured in lux. the data can be converted to lux by using an equation. there are two different data sensing ranges (375 lux and 10,000 lux) and also two different resolution selections (16 bits and 12 bits) on this device. equation 2 is dependent on both these parameters. noise rejection electrical ac power worldwide is distributed at either 50hz or 60hz. artificial light sources vary in intensity at the ac power frequencies. the undesired interference frequencies are infused on the electrical signals. this variation is one of the main sources of noise for the light sensors. integrating type adc?s have excellent noise-rejection characteristics for periodic noise sources whose frequency is an integer multiple of the conversion rate. by setting the sensor?s integration time to an integer multiple of periodic noise signal, the performance of an ambient light sensor can be improved greatl y in the presence of noise. in order to reject the ac noise, the integration time of the sensor must to adjusted to match the ac noise cycle. for instance, a 60hz ac unwanted signal?s sum from 0ms to k*16.66ms (k = 1,2...k i ) is zero. similarly, setting the device?s integration time to be an integer multiple of the periodic noise signal greatly improves the light sensor output signal in the presence of noise. digital inputs and termination the isl29125 digital inputs are guaranteed to cmos levels. the internal register is updated on the rising edge of the clock. to minimize reflections, prop er termination should be implemented. if the lines driving the clock and the digital inputs are 50 ? lines, then 50 ? termination resistor s should be placed as close to the sensor inputs as possible, connected to the digital ground plane (if separate grounds are used). temperature coefficient the limits stated for temperature coefficient (tempco) are governed by the method of measurement. the overwhelming standard for specifying the temper ature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (v high - v low ) and divide by the temperature extremes of measurement (t high - t low ). the result is divided by the nominal reference voltage (a t t = +25c) and multiplied by 106 to yield ppm/c. this is the "box" method for specifying temperature coefficient. layout and board mounting considerations suggested pcb footprint it is important that users check tb477 ?surface mount assembly guidelines for optical dual flat pack no lead (odfn) package? before starting odfn product board mounting. board mounting for applications requiring the light measurement, the board mounting location should be reviewed. the device uses an optical dual flat pack no lead (odfn) package, which subjects the die to mild stresses when th e printed circuit (pc) board is heated and cooled, which slightly changes the shape. because of these die stresses, placing the devi ce in areas subject to slight twisting can cause degradation of reference voltage accuracy. it is normally best to place the devi ce near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. figure 14. ir compensation value 0 2000 4000 6000 8000 10000 12000 020406080100 system measurement range (lux) compensation adjustment (% range) d65 a f2 ev y cyrxred cygxgreen cybxblue ++ () xrange == (eq. 2)
isl29125 15 fn8424.2 january 24, 2014 submit document feedback layout the isl29125 is relatively insensitive to layout. similar to other i 2 c devices, it is intended to provide excellent performance even in significantly noisy environments. there are only a few considerations that will ensure best performance. route the supply and i 2 c traces as far as possible from all sources of noise. use two power-supply decoupling capacitors, 1f and 0.1f, placed close to the device. soldering convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. the plastic odfn package does not require a custom reflow soldering profile and is qualified to +260c. a standard re flow soldering profile with a +260c maximum is recommended. typical circuit a typical application for the isl29125 is shown in figure 15. the isl29125?s i 2 c address is internally hard-wired as 1000100. the device can be tied onto a system?s i 2 c bus together with other i 2 c compliant devices. references [1] standard illuminants [2] planckian locus approximation [3] cie 1931 2, xyz cmfs modified by judd (1951) and vos (1978) figure 15. isl29125 typical circuit isl29125 mcu scl sda 4 6 1 3 5 vdd gnd scl sda gpio int vbus 2 nc r2 r3 r4 vdd r1 c1 c2 r1 ? 100 r2 ? 2.7k to 10k r3 ? 2.7k to 10k r4 ? 2.7k to 10k c1 ? 1f c2 ? 0.1f figure 16. 6 ld odfn sensor location outline sensor 1 2 6 5 3 4 sensor offset 0.17 0.24 yyyyyyy 0.11 0.49 0.48 0.13 0.15 0.15 0.04 vss scl intb sda vdd
isl29125 16 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8424.2 january 24, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change january 24, 2013 fn8424.2 page 2, ordering information table: changed evaluation board part # from: isl29125iroz-evalz to: isl29125eval1z page 9 - added device reset row to tables 1 and 2. december 23, 2013 fn8424.1 added related literature on page 1. updated ?interrupt function? on page 6. edited last two rows in table 20 on page 13. changed red to blue and register dec column from 11 and 12 to 13 and 14. november 20, 2013 fn8424.0 initial release
isl29125 17 fn8424.2 january 24, 2014 submit document feedback package outline drawing l6.1.65x1.65 6 lead optical dual flat no-lead plastic package (odfn) rev 1, 4/13 bottom view side view typical recommended land pattern top view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 5 0.70 0.05 1.65 1.65 pin 1 6 (4x) 0.10 detail ?x? 4 0.75 0.70 0.25 0.50 1.02 0.20 0.62 0.60 package outline 0.70 0.55 0.50 0.25 0.85 0.40 pin #1 index area cab 0.10 m

▲Up To Search▲

Price & Availability of ISL29125IROZ-T7

	To Download ISL29125IROZ-T7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .