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| this is information on a product in full production. december 2015 docid025743 rev 4 1/106 stm32f031x4 stm32f031x6 arm ? -based 32-bit mcu with up to 32 kbyte flash, 9 timers, adc and communication in terfaces, 2.0 - 3.6 v datasheet - production data features ? core: arm ? 32-bit cortex ? -m0 cpu, frequency up to 48 mhz ? memories ? 16 to 32 kbytes of flash memory ? 4 kbytes of sram with hw parity ? crc calculation unit ? reset and power management ? digital and i/os supply: 2.0 to 3.6 v ? analog supply: v dda = from v dd to 3.6 v ? power-on/power-down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop and standby ?v bat supply for rtc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator ? up to 39 fast i/os ? all mappable on external interrupt vectors ? up to 26 i/os with 5 v tolerant capability ? 5-channel dma controller ? 1 12-bit, 1.0 s adc (up to 10 channels) ? conversion range: 0 to 3.6v ? separate analog supply from 2.4 up to 3.6 v ? up to 9 timers ? 1 x 16-bit 7-channel advanced-control timer for 6 channels pwm output, with deadtime generation and emergency stop ? 1 x 32-bit and 1 x 16-bit timer, with up to 4 ic/oc, usable for ir control decoding ? 1 x 16-bit timer, with 2 ic/oc, 1 ocn, deadtime generation and emergency stop ? 1 x 16-bit timer, with ic/oc and ocn, deadtime generation, emergency stop and modulator gate for ir control ? 1 x 16-bit timer with 1 ic/oc ? independent and system watchdog timers ? systick timer: 24-bit downcounter ? calendar rtc with alarm and periodic wakeup from stop/standby ? communication interfaces ? 1 x i 2 c interface, supporting fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, and wakeup from stop mode ? 1 x usart supporting master synchronous spi and modem control, iso7816 interface, lin, irda capability, auto baud rate detection and wakeup feature ? 1 x spi (18 mbit/s) with 4 to 16 programmable bit frames, with i 2 s interface multiplexed ? serial wire debug (swd) ? 96-bit unique id ? extended temperature range: -40 to +105c ? all packages ecopack ? 2 table 1. device summary reference part number stm32f031x6 stm32f031c6, stm32f031e6, stm32f031f6, stm32f031g6, stm32f031k6 stm32f031x4 stm32f031c4, STM32F031F4, stm32f031g4, stm32f031k4 ufqfpn32 5x5 mm tssop20 ufqfpn28 4x4 mm lqfp32 7x7 mm lqfp48 7x7 mm wlcsp25 2.1x2.1 mm 6.5x4.4 mm www.st.com
contents stm32f031x4 stm32f031x6 2/106 docid025743 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 arm ? -cortex ? -m0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 12 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 15 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 15 3.10 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11.2 general-purpose timers (tim2, 3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . 17 3.11.3 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.4 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.5 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19 3.13 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 universal synchronous/asynchronous receiver/transmitter (usart) . . . 20 docid025743 rev 4 3/106 stm32f031x4 stm32f031x6 contents 4 3.15 serial peripheral interface (spi) / inter-integrated sound interface (i2s) . 22 3.16 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 42 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 42 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.18 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.19 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 contents stm32f031x4 stm32f031x6 4/106 docid025743 rev 4 6.3.20 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.1 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2 lqfp32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3 ufqfpn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.4 ufqfpn28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5 wlcsp25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6 tssop20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.7 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 100 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 docid025743 rev 4 5/106 stm32f031x4 stm32f031x6 list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f031x4/x6 family device features and perip heral counts . . . . . . . . . . . . . . . . . . . . . 9 table 3. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. stm32f031x4/x6 i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. stm32f031x4/x6 usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. stm32f031x4/x6 spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. alternate functions selected through gpioa_af r registers for port a . . . . . . . . . . . . . . . 31 table 13. alternate functions selected through gpiob_af r registers for port b . . . . . . . . . . . . . . . 32 table 14. stm32f031x4/x6 peripheral register boundary addres ses . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 17. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 table 23. typical and maximum current consumption from v dd at 3.6 v . . . . . . . . . . . . . . . . . . . . . 44 table 24. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . 45 table 25. typical and maximum current consumption in stop and standby modes . . . . . . . . . . . . 46 table 26. typical and maximum current consumption from the v bat supply. . . . . . . . . . . . . . . . . . . 47 table 27. typical current consumption, code executing from flash memory, running from hse 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 28. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 32. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 33. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 34. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 35. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 36. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 37. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 39. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 40. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 41. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 42. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 43. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 44. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 45. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 46. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 47. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 list of tables stm32f031x4 stm32f031x6 6/106 docid025743 rev 4 table 48. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 49. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 50. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 51. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 52. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 53. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 54. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 55. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 56. iwdg min/max timeout period at 40 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 57. wwdg min/max timeout value at 48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 58. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 59. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 60. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 61. lqfp48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 62. lqfp32 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 63. ufqfpn32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 64. ufqfpn28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 65. wlcsp25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 66. wlcsp25 recommended pcb design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 67. tssop20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 68. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 69. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 70. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 docid025743 rev 4 7/106 stm32f031x4 stm32f031x6 list of figures 7 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. lqfp48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. lqfp32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. ufqfpn32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. ufqfpn28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. wlcsp25 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. tssop20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. stm32f031x6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 15. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 16. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 17. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 18. hsi oscillator accuracy char acterization results for soldered parts . . . . . . . . . . . . . . . . . . 58 figure 19. hsi14 oscillator accuracy charac terization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 20. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 21. five volt tolerant (ft and ftf) i/o input characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 22. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 23. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 24. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 25. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 26. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 27. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 28. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 29. i2s slave timing diagram (philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 30. i2s master timing diagram (philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 31. lqfp48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 32. recommended footprint for lqfp48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 33. lqfp48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 34. lqfp32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 35. recommended footprint for lqfp32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 36. lqfp32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 37. ufqfpn32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 38. recommended footprint for ufqfpn32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 39. ufqfpn32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 40. ufqfpn28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 41. recommended footprint for ufqfpn28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 42. ufqfpn28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 43. wlcsp25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 44. recommended footprint for wlcsp25 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 45. wlcsp25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 46. tssop20 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 47. recommended footprint for tssop20 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 48. tssop20 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 introduction stm32f031x4 stm32f031x6 8/106 docid025743 rev 4 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32f031x4/x6 microcontrollers. this document should be read in conjunct ion with the stm32f0xxxx reference manual (rm0091). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m0 core, please refer to the cortex ? -m0 technical reference manual, available from the www.arm.com website. docid025743 rev 4 9/106 stm32f031x4 stm32f031x6 description 22 2 description the stm32f031x4/x6 microcontrollers incorporate the high-performance arm ? cortex ? -m0 32-bit risc core operating at up to 48 mhz frequency, high-speed embedded memories (up to 32 kbytes of flas h memory and 4 kbytes of sram), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (one i 2 c, one spi/ i 2 s and one usart), one 12-bit adc, five 16-bit timers, one 32-bit timer and an advanced-control pwm timer. the stm32f031x4/x6 microcontrollers operate in the -40 to +85 c and -40 to +105 c temperature ranges, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the stm32f031x4/x6 microcontrollers include devices in six different packages ranging from 20 pins to 48 pins with a die form also available upon request. depending on the device chosen, different sets of peripherals are included. these features make the stm32f031x4/x6 micr ocontrollers suitable for a wide range of applications such as applic ation control and user interfaces, hand-held equipment, a/v receivers and digital tv, pc peripherals, gami ng and gps platforms, industrial applications, plcs, inverters, printers, scanners, al arm systems, video intercoms and hvacs. table 2. stm32f031x4/x6 family device features and peripheral counts peripheral stm32f031fx stm32f031ex stm32f031gx stm32f031kx stm32f031cx flash memory (kbyte) 16 32 32 16 32 16 32 16 32 sram (kbyte) 4 timers advanced control 1 (16-bit) general purpose 4 (16-bit) 1 (32-bit) comm. interfaces spi [i 2 s] (1) 1 [1] i 2 c1 usart 1 12-bit adc (number of channels) 1 (9 ext. + 3 int.) 1 (10 ext. + 3 int.) gpios 15 20 23 25 (on lqfp32) 27 (on ufqfpn32) 39 max. cpu frequency 48 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: -40c to 85c / -40c to 105c junction temperature: -40c to 105c / -40c to 125c packages tssop20 wlcsp25 ufqfpn28 lqfp32 ufqfpn32 lqfp48 1. the spi interface can be used either in spi mode or in i 2 s audio mode. description stm32f031x4 stm32f031x6 10/106 docid025743 rev 4 figure 1. block diagram 0 6 y 9 6 8 3 3 / < 6 8 3 ( 5 9 , 6 , 2 1 3 2 : ( 5 3 r z h u g r p d l q r i d q d o r j e o r f n v 9 % $ 7 9 ' ' $ 9 ' ' f k d q q h o v f r p s o f k d q q h o v % 5 . ( 7 5 l q s x w d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 6 & / 6 ' $ 6 0 % $ p $ ) 0 d v $ ) # 9 ' ' # 9 ' ' $ 6 \ v w h p d q g s h u l s k h u d o f o r f n v $ ) 0 2 6 , 6 ' 0 , 6 2 0 & . 6 & . & . 1 6 6 : 6 d v $ ) # 9 ' ' $ 9 ' ' $ 9 6 6 $ 6 : & / . 6 : ' , 2 d v $ ) [ $ ' l q s x w # 9 ' ' $ # 9 ' ' 9 ' ' 3 2 5 5 h v h w , q w 9 ' ' w r 9 9 6 6 1 5 6 7 9 ' ' $ 9 6 6 $ 2 6 & b , 1 2 6 & b 2 8 7 9 % $ 7 w r 9 2 6 & b , 1 2 6 & b 2 8 7 7 $ 0 3 ( 5 5 7 & $ / $ 5 0 2 8 7 # 9 % $ 7 9 ' ' + 6 , + 6 , / 6 , 3 / / & / . 9 ' ' , 5 b 2 8 7 d v $ ) f k d q q h o f r p s o % 5 . d v $ ) f k d q q h o f r p s o % 5 . d v $ ) f k d q q h o d v $ ) f k ( 7 5 d v $ ) f k ( 7 5 d v $ ) * 3 ' 0 $ f k d q q h o v & 2 5 7 ( ; 0 & 3 8 i 0 $ ; 0 + ] 6 h u l d o : l u h ' h e x j 1 9 , & ( ; 7 , 7 : . 8 3 6 3 , , 6 6 < 6 & ) * , ) ' % * 0 & 8 : l q g r z : ' * $ 3 % $ + % & 5 & 5 ( 6 ( 7 & / 2 & . & 2 1 7 5 2 / 3 : 0 7 , 0 ( 5 7 , 0 ( 5 e l w 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 8 6 $ 5 7 , & 3 r z h u & r q w u r o o h u ; 7 $ / 2 6 & 0 + ] , q g : l q g r z : ' * 3 9 ' 3 2 5 3 ' 5 ) o d v k p h p r u \ l q w h u i d f h ) o d v k * 3 / 8 s w r . % e l w 2 e o 6 5 $ 0 . % 7 h p s v h q v r u , ) e l w $ ' & 5 7 & % d f n x s u h j 5 7 & l q w h u i d f h 5 & 0 + ] 5 & 0 + ] 5 & n + ] 3 / / $ + % g h f r g h u ; 7 $ / n + ] 6 5 $ 0 f r q w u r o o h u % x v p d w u l [ 9 2 / 7 5 ( * 9 w r 9 3 ) > @ * 3 , 2 s r u w ) 3 & > @ * 3 , 2 s r u w & 3 % > @ * 3 , 2 s r u w % 3 $ > @ * 3 , 2 s r u w $ docid025743 rev 4 11/106 stm32f031x4 stm32f031x6 functional overview 22 3 functional overview figure 1 shows the general block diagram of the stm32f031x4/x6 devices. 3.1 arm ? -cortex ? -m0 core the arm ? cortex ? -m0 is a generation of arm 32-bit risc processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm ? cortex ? -m0 processors feature exceptional code-efficiency, delivering the high performance expected from an arm core, with me mory sizes usually associated with 8- and 16-bit devices. the stm32f031x4/x6 devices embed arm core and are compatible with all arm tools and software. 3.2 memories the device has the following features: ? 4 kbytes of embedded sram accessed (read/ write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. ? the non-volatile memory is divided into two arrays: ? 16 to 32 kbytes of embedded flash memory for programs and data ? option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, th e flash memory cannot be read from or written to if either debug features ar e connected or boot in ram is selected ? level 2: chip readout protec tion, debug features (cortex ? -m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boot selector opti on bit are used to select one of the three boot options: ? boot from user flash memory ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart on pins pa14/pa15 or pa9/pa10. functional overview stm32f031x4 stm32f031x6 12/106 docid025743 rev 4 3.4 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a crc-32 (ethernet) polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v dd = v ddio1 = 2.0 to 3.6 v: external power supply for i/os (v ddio1 ) and the internal regulator. it is provided externally through vdd pins. ? v dda = from v dd to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). it is provided externally through vdda pin. the v dda voltage level must be always greater or equal to the v dd voltage level and must be established first. ? v bat = 1.65 to 3.6 v: power supply for rt c, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 12: power supply scheme . 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.5.3 voltage regulator the regulator has two operating modes and it is always enabled after reset. ? main (mr) is used in normal operating mode (run). ? low power (lpr) can be used in stop mode where the power demand is reduced. docid025743 rev 4 13/106 stm32f031x4 stm32f031x6 functional overview 22 in standby mode, it is put in po wer down mode. in this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and sram are lost). 3.5.4 low-power modes the stm32f031x4/x6 microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the volt age regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines, the pvd output, rtc, i2c1 or usart1. usart1 and i2c1 peri pherals can be configured to ena ble the hsi rc oscillator so as to get clock for processing in coming data. if this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for registers in the rtc domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pins, or an rtc event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 3.6 clocks and startup system clock selection is perf ormed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resona tor or oscillator). several prescalers allow the ap plication to configure the fr equency of the ahb and the apb domains. the maximum freq uency of the ahb and t he apb domains is 48 mhz. functional overview stm32f031x4 stm32f031x6 14/106 docid025743 rev 4 figure 2. clock tree 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 0 6 y 9 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 , : ' * 3 / / 0 8 / 0 & 2 0 d l q f o r f n r x w s x w 3 / / & / . + 6 , + 6 ( + & / . 3 / / & / . $ + % f r u h p h p r u \ ' 0 $ & r u w h [ ) & / . i u h h u x q f o r f n $ ' & d v \ q f k u r q r x v f o r f n l q s x w / 6 ( / 6 , + 6 , + 6 ( 5 7 & 3 / / 6 5 & 6 : 0 & 2 5 7 & & / . 5 7 & 6 ( / 6 < 6 & / . 7 , 0 ) / , 7 ) & / . ) o d v k p h p r u \ s u r j u d p p l q j l q w h u i d f h + 6 , + 6 , , & 8 6 $ 5 7 / 6 ( + 6 , 6 < 6 & / . 3 & / . 6 < 6 & / . + 6 , 3 & / . , 6 & r u w h [ v \ v w h p w l p h u $ 3 % s h u l s k h u d o v / 6 , / 6 ( 3 5 ( ' , 9 3 / / 1 2 ' , 9 0 & 2 3 5 ( w r 7 , 0 / 6 ( + 6 ( & 6 6 / h j h q g z k l w h f o r f n w u h h f r q w u r o h o h p h q w f o r f n o l q h f r q w u r o o l q h e o d f n f o r f n w u h h h o h p h q w 0 + ] + 6 ( 2 6 & 0 + ] 5 & + 6 , ? ? n + ] / 6 ( 2 6 & n + ] / 6 , 5 & 3 / / [ [ [ [ [ 8 6 $ 5 7 6 : 3 3 5 ( 3 3 5 ( + 3 5 ( , & 6 : 6 < 6 & / . + 6 , + 6 , 0 + ] + 6 , 5 & docid025743 rev 4 15/106 stm32f031x4 stm32f031x6 functional overview 22 3.8 direct memory a ccess controller (dma) the 5-channel general-purpose dmas manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardw are dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spix, i2sx, i2cx, usartx, all timx timers (except tim14) and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex ? -m0) and 4 priority levels. ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 24 edge det ector lines used to generate interrupt/event requ ests and wake-up the system. ea ch line can be independently configured to select the trig ger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains t he status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 39 gpios can be connected to the 16 external interrupt lines. 3.10 analog-to-digita l converter (adc) the 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, vbat voltage measurement) channels and performs conversions in single-shot or scan modes. in scan mode , automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. functional overview stm32f031x4 stm32f031x6 16/106 docid025743 rev 4 an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in 17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. 3.10.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in18. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. table 3. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( 5 c), v dda = 3.3 v ( 10 mv) 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at a temperature of 110 c ( 5 c), v dda = 3.3 v ( 10 mv) 0x1fff f7c2 - 0x1fff f7c3 table 4. internal voltage reference calibration values calibration value name description memory address vrefint_cal raw data acquired at a temperature of 30 c ( 5 c), v dda = 3.3 v ( 10 mv) 0x1fff f7ba - 0x1fff f7bb docid025743 rev 4 17/106 stm32f031x4 stm32f031x6 functional overview 22 3.11 timers and watchdogs the stm32f031x4/x6 devices include up to fi ve general-purpose timers and an advanced control timer. table 5 compares the features of the different timers. 3.11.1 advanced-c ontrol timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on six channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the four independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) ? one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can t herefore work together with the other timers via the timer link feature for sy nchronization or event chaining. 3.11.2 general-purpose time rs (tim2, 3, 14, 16, 17) there are five synchronizable general-purpose timers embedded in the stm32f031x4/x6 devices (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down integer from 1 to 65536 yes 4 3 general purpose tim2 32-bit up, down, up/down integer from 1 to 65536 yes 4 - tim3 16-bit up, down, up/down integer from 1 to 65536 yes 4 - tim14 16-bit up integer from 1 to 65536 no 1 - tim16 tim17 16-bit up integer from 1 to 65536 yes 1 1 functional overview stm32f031x4 stm32f031x6 18/106 docid025743 rev 4 tim2, tim3 stm32f031x4/x6 devices feature two synchronizable 4-channel general-purpose timers. tim2 is based on a 32-bit auto-reload up/downc ounter and a 16-bit prescaler. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output comp are, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2 and tim3 general-purpose timers ca n work together or with the tim1 advanced- control timer via the timer link feature for synchronization or event chaining. tim2 and tim3 both have indepen dent dma request generation. these timers are capable of handling quadrat ure (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. their counters can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-re load upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim16 and tim17 both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. they each have a single channel for input capture/output compare, pwm or one-pulse mode output. tim16 and tim17 have a complementary output with dead-time generation and independent dma request generation. their counters can be frozen in debug mode. 3.11.3 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.11.4 system win dow watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. docid025743 rev 4 19/106 stm32f031x4 stm32f031x6 functional overview 22 3.11.5 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source (hclk or hclk/8) 3.12 real-time clock (rtc ) and backup registers the rtc and the five backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or at wake up from standby mode. the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format ? automatic correction for 28, 29 (leap year), 30, and 31 day of the month ? programmable alarm with wake up fr om stop and sta ndby mode capability ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize the rtc with a master clock ? digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy ? two anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillato r (typical frequency of 40 khz) ? the high-speed external clock divided by 32 3.13 inter-integrated circuit interface (i 2 c) the i 2 c interface (i2c1) can operate in multimaster or slave modes. it can support standard mode (up to 100 kbit/s), fast mode (up to 40 0 kbit/s) and fast mode plus (up to 1 mbit/s) with 20 ma output drive. it supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). it also includes programmable analog and digital noise filters. functional overview stm32f031x4 stm32f031x6 20/106 docid025743 rev 4 in addition, i2c1 provides hardware su pport for smbus 2.0 and pmbus 1.1: arp capability, host notify prot ocol, hardware crc ( pec) generation/verification, timeouts verifications and alert protocol management. i2c1 also has a clock domain independent from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c peripheral can be served by the dma controller. 3.14 universal synchronous/asyn chronous receiver/transmitter (usart) the device embeds one universal synchronous/asynchronous receiver/transmitter (usart1) which communicates at speeds of up to 6 mbit/s. it provides hardware management of the cts, rts and rs485 de signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. usart1 supports also smartcard communication (iso 7816), irda sir endec, lin master/slave capability and auto baud rate feature, and has a clock domain independent of the cpu clock, allowing to wake up the mcu from stop mode. the usart interface can be served by the dma controller. table 6. comparison of i 2 c analog and digital filters aspect analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2cx peripheral clocks benefits available in stop mode ?extra filtering capability vs. standard requirements ?stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 7. stm32f031x4/x6 i 2 c implementation i 2 c features (1) 1. x = supported. i2c1 7-bit addressing mode x 10-bit addressing mode x standard mode (up to 100 kbit/s) x fast mode (up to 400 kbit/s) x fast mode plus with 20 ma output drive i/os (up to 1 mbit/s) x independent clock x smbus x wakeup from stop x docid025743 rev 4 21/106 stm32f031x4 stm32f031x6 functional overview 22 table 8. stm32f031x4/x6 usart implementation usart modes/features (1) 1. x = supported. usart1 hardware flow control for modem x continuous communication using dma x multiprocessor communication x synchronous mode x smartcard mode x single-wire half-duplex communication x irda sir endec block x lin mode x dual clock domain and wakeup from stop mode x receiver timeout interrupt x modbus communication x auto baud rate detection x driver enable x functional overview stm32f031x4 stm32f031x6 22/106 docid025743 rev 4 3.15 serial peripheral interface (spi) / inter-integrated sound interface (i 2 s) the spi is able to communicate up to 18 mbit/s in slave and master modes in full-duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. one standard i 2 s interface (multiplexed with spi1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. it can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by an 8-bit programmable linear prescaler. when operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency. 3.16 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. table 9. stm32f031x4/x6 spi/i 2 s implementation spi features (1) 1. x = supported. spi hardware crc calculation x rx/tx fifo x nss pulse mode x i 2 s mode x ti mode x docid025743 rev 4 23/106 stm32f031x4 stm32f031x6 pinouts and pin description 32 4 pinouts and pin description figure 3. lqfp48 package pinout figure 4. lqfp32 package pinout 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 % $ 7 3 & 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 3 ) 3 ) 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % % 2 2 7 3 % 3 % 9 6 6 9 ' ' 7 r s y l h z / 4 ) 3 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 9 6 6 9 ' ' 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 3 $ 3 % 3 % 3 % 3 % 3 % % 2 2 7 9 6 6 7 r s y l h z / 4 ) 3 pinouts and pin description stm32f031x4 stm32f031x6 24/106 docid025743 rev 4 figure 5. ufqfpn32 package pinout figure 6. ufqfpn28 package pinout 0 6 y 9 ( [ s r v h g s d g 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 9 ' ' 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 3 $ 3 % 3 % 3 % 3 % 3 % % 2 2 7 3 % 7 r s y l h z ( [ s r v h g s d g 8 ) 4 ) 3 1 9 6 6 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % % 2 2 7 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 7 r s y l h z 8 ) 4 ) 3 1 docid025743 rev 4 25/106 stm32f031x4 stm32f031x6 pinouts and pin description 32 figure 7. wlcsp25 package pinout 1. the above figure shows the package in top view, c hanging from bottom view in the previous document versions. figure 8. tssop20 package pinout 0 6 y 9 $ % & ' ( 3 ) 3 ) 1 5 6 7 9 ' ' $ 3 $ % 2 2 7 3 $ 3 $ 3 $ 3 $ 3 % 3 $ 3 $ 3 $ 3 % 3 $ 3 % 3 % 3 $ 3 % 3 $ 3 $ 3 $ 9 ' ' 9 6 6 7 r s y l h z : / & 6 3 0 6 y 9 3 ) 2 6 & b , 1 % 2 2 7 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 3 $ 3 $ 9 ' ' 3 $ 3 $ 3 $ 3 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 7 r s y l h z 7 6 6 2 3 pinouts and pin description stm32f031x4 stm32f031x6 26/106 docid025743 rev 4 table 10. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input-only pin i/o input / output pin i/o structure ft 5 v-tolerant i/o ftf 5 v-tolerant i/o, fm+ capable tta 3.3 v-tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers table 11. pin definitions pin number pin name (function upon reset) pin type i/o structure notes pin functions lqfp48 lqfp32 ufqfpn32 ufqfpn28 wlcsp25 tssop20 alternate functions additional functions 1 - - - - - vbat s - - backup power supply 2----- pc13 i/otc (1)(2) - rtc_tamp1, rtc_ts, rtc_out, wkup2 3----- pc14-osc32_in (pc14) i/o tc (1)(2) - osc32_in 4----- pc15- osc32_out (pc15) i/o tc (1)(2) - osc32_out 5222a52 pf0-osc_in (pf0) i/o ft - - osc_in docid025743 rev 4 27/106 stm32f031x4 stm32f031x6 pinouts and pin description 32 6333b53 pf1-osc_out (pf1) i/o ft - - osc_out 7 4 4 4 c5 4 nrst i/o rst - device reset input / internal reset output (active low) 8 16 (3) 0 (3) 16 (3) e1 (3) 15 (3) vssa s - analog ground 9 5 5 5 d5 5 vdda s - analog power supply 10 6 6 6 b4 6 pa0 i/o tta - tim2_ch1_etr, usart1_cts adc_in0, rtc_tamp2, wkup1 11 7 7 7 c4 7 pa1 i/o tta - tim2_ch2, eventout, usart1_rts adc_in1 12 8 8 8 d4 8 pa2 i/o tta - tim2_ch3, usart1_tx adc_in2 13 9 9 9 e5 9 pa3 i/o tta - tim2_ch4, usart1_rx adc_in3 14 10 10 10 b3 10 pa4 i/o tta - spi1_nss, i2s1_ws, tim14_ch1, usart1_ck adc_in4 15 11 11 11 c3 11 pa5 i/o tta - spi1_sck, i2s1_ck, tim2_ch1_etr adc_in5 16 12 12 12 d3 12 pa6 i/o tta - spi1_miso, i2s1_mck, tim3_ch1, tim1_bkin, tim16_ch1, eventout adc_in6 table 11. pin definitions (continued) pin number pin name (function upon reset) pin type i/o structure notes pin functions lqfp48 lqfp32 ufqfpn32 ufqfpn28 wlcsp25 tssop20 alternate functions additional functions pinouts and pin description stm32f031x4 stm32f031x6 28/106 docid025743 rev 4 17 13 13 13 e4 13 pa7 i/o tta - spi1_mosi, i2s1_sd, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, eventout adc_in7 18 14 14 14 e3 - pb0 i/o tta - tim3_ch3, tim1_ch2n, eventout adc_in8 19 15 15 15 e2 14 pb1 i/o tta - tim3_ch4, tim14_ch1, tim1_ch3n adc_in9 20 - 16 - - - pb2 i/o ft (4) -- 21----- pb10 i/oftf - tim2_ch3, i2c1_scl - 22----- pb11 i/oftf - tim2_ch4, eventout, i2c1_sda - 23 16 0 16 e1 15 vss s - - ground 24 17 17 17 d1 16 vdd s - - digital power supply 25----- pb12 i/oft - tim1_bkin, eventout, spi1_nss - 26----- pb13 i/oft - tim1_ch1n, spi1_sck - 27----- pb14 i/oft - tim1_ch2n, spi1_miso - 28----- pb15 i/oft - tim1_ch3n, spi1_mosi rtc_refin 29 18 18 18 d2 - pa8 i/o ft - usart1_ck, tim1_ch1, eventout, mco - table 11. pin definitions (continued) pin number pin name (function upon reset) pin type i/o structure notes pin functions lqfp48 lqfp32 ufqfpn32 ufqfpn28 wlcsp25 tssop20 alternate functions additional functions docid025743 rev 4 29/106 stm32f031x4 stm32f031x6 pinouts and pin description 32 30 19 19 19 c1 17 pa9 i/o ftf - usart1_tx, tim1_ch2, i2c1_scl - 31 20 20 20 b1 18 pa10 i/o ftf - usart1_rx, tim1_ch3, tim17_bkin, i2c1_sda - 32 21 21 - - - pa11 i/o ft - usart1_cts, tim1_ch4, eventout - 33 22 22 - - - pa12 i/o ft - usart1_rts, tim1_etr, eventout - 34 23 23 21 a1 19 pa13 (swdio) i/o ft (5) ir_out, swdio - 35 - - - - - pf6 i/o ftf - i2c1_scl - 36----- pf7 i/oftf - i2c1_sda - 37 24 24 22 a2 20 pa14 (swclk) i/o ft (5) usart1_tx, swclk - 38 25 25 23 - - pa15 i/o ft (6) spi1_nss, i2s1_ws, tim2_ch_etr, eventout, usart1_rx - 39 26 26 24 - - pb3 i/o ft (6) spi1_sck, i2s1_ck, tim2_ch2, eventout - 40 27 27 25 - - pb4 i/o ft (6) spi1_miso, i2s1_mck, tim3_ch1, eventout - table 11. pin definitions (continued) pin number pin name (function upon reset) pin type i/o structure notes pin functions lqfp48 lqfp32 ufqfpn32 ufqfpn28 wlcsp25 tssop20 alternate functions additional functions pinouts and pin description stm32f031x4 stm32f031x6 30/106 docid025743 rev 4 41 28 28 26 c2 - pb5 i/o ft - spi1_mosi, i2s1_sd, i2c1_smba, tim16_bkin, tim3_ch2 - 42 29 29 27 b2 - pb6 i/o ftf - i2c1_scl, usart1_tx, tim16_ch1n - 43 30 30 28 a3 - pb7 i/o ftf - i2c1_sda, usart1_rx, tim17_ch1n - 44 31 31 1 a4 1 boot0 i b - boot memory selection 45 - 32 - - - pb8 i/o ftf (4) i2c1_scl, tim16_ch1 - 46----- pb9 i/oftf - i2c1_sda, ir_out, tim17_ch1, eventout - 47 32 0 - e1 - vss s - - ground 48 1 1 - - - vdd s - - digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as curr ent sources (e.g. to drive an led). 2. after the first rtc domain power-up, pc13, pc14 and pc15 oper ate as gpios. their function then depends on the content of the rtc registers which are not reset by the system rese t. for details on how to manage these gpios, refer to the rtc domain and rtc register descriptions in the reference manual. 3. vssa pin is not in package pinout. vssa pad of the die is connected to vss pin. 4. on the lqfp32 package, pb2 and pb8 should be treated as unc onnected pins (even when they are not available on the package, they are not forced to a defined level by hardware). 5. after reset, these pins are configured as swdio and swclk alternate functions, and the internal pull-up on the swdio pin and the internal pull-down on the swclk pin are activated. 6. on the wlcsp25 package, pb3, pb4 and pa15 must be set to defined levels by software, as their corresponding pads on the silicon die are left unconnected. apply same recommendations as for unconnected pins. table 11. pin definitions (continued) pin number pin name (function upon reset) pin type i/o structure notes pin functions lqfp48 lqfp32 ufqfpn32 ufqfpn28 wlcsp25 tssop20 alternate functions additional functions stm32f031x4 stm32f031x6 pinouts and pin description docid025743 rev 4 31/106 table 12. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 af7 pa0 - usart1_cts tim2_ch1_ etr -- - -- pa1 eventout usart1_rts tim2_ch2 - - - - - pa2 - usart1_tx tim2_ch3 - - - - - pa3 - usart1_rx tim2_ch4 - - - - - pa4 spi1_nss, i2s1_ws usart1_ck - - tim14_ch1 - - - pa5 spi1_sck, i2s1_ck - tim2_ch1_ etr -- - -- pa6 spi1_miso, i2s1_mck tim3_ch1 tim1_bkin - - tim16_ch1 eventout - pa7 spi1_mosi, i2s1_sd tim3_ch2 tim1_ch1n - tim14_ch1 tim17_ch1 eventout - pa8 mco usart1_ck tim1_ch1 eventout - - - - pa9 - usart1_tx tim1_ch2 - i2c1_scl - - - pa10 tim17_bkin usart1_rx tim1_ch3 - i2c1_sda - - - pa11 eventout usart1_cts tim1_ch4 - - - - - pa12 eventout usart1_rts tim1_etr - - - - - pa13 swdio ir_out - - - - - - pa14 swclk usart1_tx - - - - - - pa15 spi1_nss, i2s1_ws usart1_rx tim2_ch1_ etr eventout - - - - pinouts and pin description stm32f031x4 stm32f031x6 32/106 docid025743 rev 4 table 13. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 pb0 eventout tim3_ch3 tim1_ch2n - pb1 tim14_ch1 tim3_ch4 tim1_ch3n - pb2---- pb3 spi1_sck, i2s1_c k eventout tim2_ch2 - pb4 spi1_miso, i2 s1_mck tim3_ch1 eventout - pb5 spi1_mosi, i2s1_sd tim3_ch2 tim16_bkin i2c1_smba pb6 usart1_tx i2c1_scl tim16_ch1n - pb7 usart1_rx i2c1_sda tim17_ch1n - pb8 - i2c1_scl tim16_ch1 - pb9 ir_out i2c1_sda tim17_ch1 eventout pb10 - i2c1_scl tim2_ch3 - pb11 eventout i2c1_sda tim2_ch4 - pb12 spi1_nss eventout tim1_bkin - pb13 spi1_sck - tim1_ch1n - pb14 spi1_miso - tim1_ch2n - pb15 spi1_mosi - tim1_ch3n - docid025743 rev 4 33/106 stm32f031x4 stm32f031x6 memory mapping 35 5 memory mapping to the difference of stm32f031x6 memory map in figure 9 , the two bottom code memory spaces of stm32f031x4 end at 0x0000 3fff and 0x0800 3fff, respectively. figure 9. stm32f031x6 memory map 0 6 9 $ + % [ ) ) ) ) ) ) ) ) 3 h u l s k h u d o v 6 5 $ 0 ) o d v k p h p r u \ 5 h v h u y h g 6 \ v w h p p h p r u \ 2 s w l r q % \ w h v [ ( ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q [ [ ( [ & [ $ [ [ [ [ [ [ [ [ ) ) ) ( & [ ) ) ) ) [ ) ) ) ) ) ) ) [ 5 h v h u y h g & 2 ' ( $ 3 % $ 3 % 5 h v h u y h g [ [ [ [ 5 h v h u y h g [ $ + % [ 5 h v h u y h g [ ) ) [ ) ) & r u w h [ 0 l q w h u q d o s h u l s k h u d o v 5 h v h u y h g [ ) ) ) ) & 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g memory mapping stm32f031x4 stm32f031x6 34/106 docid025743 rev 4 table 14. stm32f031x4/x6 peripheral register boundary addresses bus boundary address size peripheral 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1kb gpiof 0x4800 0c00 - 0x4800 13ff 2kb reserved 0x4800 0800 - 0x4800 0bff 1kb gpioc 0x4800 0400 - 0x4800 07ff 1kb gpiob 0x4800 0000 - 0x4800 03ff 1kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 3400 - 0x4002 3fff 3 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash memory interface 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0400 - 0x4002 0fff 3 kb reserved 0x4002 0000 - 0x4002 03ff 1 kb dma 0x4001 8000 - 0x4001 ffff 32 kb reserved apb 0x4001 5c00 - 0x4001 7fff 9kb reserved 0x4001 5800 - 0x4001 5bff 1kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3kb reserved 0x4001 4800 - 0x4001 4bff 1kb tim17 0x4001 4400 - 0x4001 47ff 1kb tim16 0x4001 3c00 - 0x4001 43ff 2kb reserved 0x4001 3800 - 0x4001 3bff 1kb usart1 0x4001 3400 - 0x4001 37ff 1kb reserved 0x4001 3000 - 0x4001 33ff 1kb spi1/i2s1 0x4001 2c00 - 0x4001 2fff 1kb tim1 0x4001 2800 - 0x4001 2bff 1kb reserved 0x4001 2400 - 0x4001 27ff 1kb adc 0x4001 0800 - 0x4001 23ff 7kb reserved 0x4001 0400 - 0x4001 07ff 1kb exti 0x4001 0000 - 0x4001 03ff 1kb syscfg 0x4000 8000 - 0x4000 ffff 32 kb reserved docid025743 rev 4 35/106 stm32f031x4 stm32f031x6 memory mapping 35 apb 0x4000 7400 - 0x4000 7fff 3kb reserved 0x4000 7000 - 0x4000 73ff 1kb pwr 0x4000 5800 - 0x4000 6fff 6kb reserved 0x4000 5400 - 0x4000 57ff 1kb i2c1 0x4000 3400 - 0x4000 53ff 8kb reserved 0x4000 3000 - 0x4000 33ff 1kb iwdg 0x4000 2c00 - 0x4000 2fff 1kb wwdg 0x4000 2800 - 0x4000 2bff 1kb rtc 0x4000 2400 - 0x4000 27ff 1kb reserved 0x4000 2000 - 0x4000 23ff 1kb tim14 0x4000 0800 - 0x4000 1fff 6kb reserved 0x4000 0400 - 0x4000 07ff 1kb tim3 0x4000 0000 - 0x4000 03ff 1kb tim2 table 14. stm32f031x4/x6 peripheral register boundary addresses (continued) bus boundary address size peripheral electrical characteristics stm32f031x4 stm32f031x6 36/106 docid025743 rev 4 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 10. pin loading conditions figure 11. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid025743 rev 4 37/106 stm32f031x4 stm32f031x6 electrical characteristics 80 6.1.6 power supply scheme figure 12. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 9 ' ' / h y h o v k l i w h u , 2 o r j l f . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v / 6 ( 5 7 & : d n h x s o r j l f , 1 2 8 7 5 h j x o d w r u * 3 , 2 v [ q ) [ ? ) [ 9 6 6 [ 9 ' ' 9 & 2 5 ( 3 r z h u v z l w f k 9 ' ' , 2 $ ' & $ q d o r j 5 & v 3 / / ? 9 5 ( ) 9 5 ( ) 9 ' ' $ q ) ? ) 9 ' ' $ 9 6 6 $ 9 9 % $ 7 0 6 y 9 electrical characteristics stm32f031x4 stm32f031x6 38/106 docid025743 rev 4 6.1.7 current consumption measurement figure 13. current consum ption measurement scheme 0 6 9 9 % $ 7 9 ' ' 9 ' ' $ , ' ' , ' ' $ , ' ' b 9 % $ 7 docid025743 rev 4 39/106 stm32f031x4 stm32f031x6 electrical characteristics 80 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 15: voltage characteristics , table 16: current characteristics and table 17: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 15. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v dd ?v ss external main supply voltage -0.3 4.0 v v dda ?v ss external analog supply voltage -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda -0.4v v bat ?v ss external backup supply voltage -0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 16: current characteristics for the maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v ddiox + 4.0 (3) 3. valid only if the internal pull-up/pul l-down resistors are disabled. if inter nal pull-up or pull-down resistor is enabled, the maximum limit is 4 v. v input voltage on tta pins v ss ? 0.3 4.0 v boot0 0 9.0 v input voltage on any other pin v ss ? 0.3 4.0 v | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics - electrical characteristics stm32f031x4 stm32f031x6 40/106 docid025743 rev 4 table 16. current characteristics symbol ratings max. unit i vdd total current into sum of all vdd power lines (source) (1) 120 ma i vss total current out of sum of all vss ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd power pin (source) (1) 100 i vss(pin) maximum current out of each vss ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 i io(pin) total output current sunk by su m of all i/os and control pins (2) 80 total output current sourced by su m of all i/os and control pins (2) -80 i inj(pin) (3) injected current on b, ft and ftf pins -5/+0 (4) injected current on tc and rst pin 5 injected current on tta pins (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and ground (vss, vssa) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two c onsecutive power supply pins referr ing to high pin count qfp packages. 3. a positive injection is induced by v in > v ddiox while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 15: voltage characteristics for the maximum allowed input voltage values. 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. on these i/os, a positive injection is induced by v in > v dda . negative injection disturbs the analog performance of the device. see note (2) below table 52: adc accuracy . 6. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 17. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c docid025743 rev 4 41/106 stm32f031x4 stm32f031x6 electrical characteristics 80 6.3 operating conditions 6.3.1 general operating conditions table 18. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 48 mhz f pclk internal apb clock frequency - 0 48 v dd standard operating voltage - 2.0 3.6 v v dda analog operating voltage (adc not used) must have a potential equal to or higher than v dd v dd 3.6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage - 1.65 3.6 v v in i/o input voltage tc and rst i/o ?0.3 v ddiox +0.3 v tta i/o ?0.3 v dda +0.3 (1) ft and ftf i/o ?0.3 5.5 (1) boot0 0 5.5 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) lqfp48 - 364 mw ufqfpn32 - 526 lqfp32 - 357 ufqfpn28 - 169 wlcsp25 - 267 tssop20 - 182 t a ambient temperature for the suffix 6 version maximum power dissipation ?40 85 c low power dissipation (3) ?40 105 ambient temperature for the suffix 7 version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range suffix 6 version ?40 105 c suffix 7 version ?40 125 1. for operation with a voltage higher than v ddiox + 0.3 v, the internal pull-up resistor must be disabled. 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . see section 7.7: thermal characteristics . 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.7: thermal characteristics ). electrical characteristics stm32f031x4 stm32f031x6 42/106 docid025743 rev 4 6.3.2 operating conditions at power-up / power-down the parameters given in table 19 are derived from tests performed under the ambient temperature condition summarized in table 18 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 20 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . table 19. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 20 t vdda v dda rise time rate - 0 v dda fall time rate 20 table 20. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the opti on bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.80 1.88 1.96 (3) 3. data based on characterization results, not tested in production. v rising edge 1.84 (3) 1.92 2.00 v v pdrhyst pdr hysteresis - - 40 - mv t rsttempo (4) 4. guaranteed by design, not tested in production. reset temporization - 1.50 2.50 4.50 ms table 21. programmable voltage detector characteristics symbol parameter conditions min typ max unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 v falling edge 2.09 2.18 2.27 v v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 v falling edge 2.18 2.28 2.38 v v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 v falling edge 2.28 2.38 2.48 v docid025743 rev 4 43/106 stm32f031x4 stm32f031x6 electrical characteristics 80 6.3.4 embedded reference voltage the parameters given in table 22 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 13: current consumption measurement scheme . v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 v falling edge 2.37 2.48 2.59 v v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 v falling edge 2.47 2.58 2.69 v v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 v falling edge 2.56 2.68 2.8 v v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 v falling edge 2.66 2.78 2.9 v v pvdhyst (1) pvd hysteresis - 100 - mv i dd(pvd) pvd current consumption - 0.15 0.26 (1) a 1. guaranteed by design, not tested in production. table 21. programmable voltage detector characteristics (continued) symbol parameter conditions min typ max unit table 22. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v t start adc_in17 buffer startup time ---10 (1) s t s_vrefint adc sampling time when reading the internal reference voltage - 4 (1) 1. guaranteed by design, not tested in production. -- s v refint internal reference voltage spread over the temperature range v dda = 3 v - - 10 (1) mv t coeff temperature coefficient - - 100 (1) - 100 (1) ppm/c electrical characteristics stm32f031x4 stm32f031x6 44/106 docid025743 rev 4 all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled f pclk = f hclk the parameters given in table 23 table 23 to table 27 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . table 23. typical and maximum current consumption from v dd at 3.6 v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, code executing from flash memory hse bypass, pll on 48 mhz 18.4 20.0 20.1 20.4 11.4 12.5 12.5 12.6 ma 32 mhz 12.4 13.2 13.2 13.8 7.9 8.3 8.5 8.6 24 mhz 9.9 10.7 10.7 11.0 6.2 6.8 7.0 7.0 hse bypass, pll off 8 mhz 3.3 3.6 3.8 3.9 2.2 2.6 2.6 2.6 1 mhz 0.8 1.1 1.1 1.1 0.7 0.9 0.9 0.9 hsi clock, pll on 48 mhz 18.9 20.9 21.1 21.5 11.7 12.3 12.9 13.1 32 mhz 12.8 13.7 14.2 14.8 8.0 8.7 9.1 9.1 24 mhz 9.7 10.4 11.2 11.3 6.1 6.5 6.7 6.9 hsi clock, pll off 8 mhz 3.5 4.0 4.0 4.1 2.4 2.6 2.7 2.7 supply current in run mode, code executing from ram hse bypass, pll on 48 mhz 17.3 19.7 (2) 19.8 20.0 (2) 10.3 11.2 (2) 11.3 11.7 (2) 32 mhz 11.2 12.5 12.7 12.7 6.7 7.3 7.6 7.6 24 mhz 8.9 10.0 10.1 10.2 5.1 5.5 5.8 5.9 hse bypass, pll off 8 mhz 2.8 3.1 3.3 3.4 1.7 2.0 2.1 2.1 1 mhz 0.3 0.6 0.6 1.3 0.2 0.5 0.8 0.9 hsi clock, pll on 48 mhz 17.4 19.7 20.0 20.2 10.4 11.2 11.3 11.8 32 mhz 11.8 12.8 13.1 13.3 6.8 7.4 7.7 7.9 24 mhz 9.0 10.0 10.1 10.2 5.2 5.7 6.0 6.0 hsi clock, pll off 8 mhz 3.0 3.2 3.5 3.6 1.8 2.0 2.2 2.2 docid025743 rev 4 45/106 stm32f031x4 stm32f031x6 electrical characteristics 80 i dd supply current in sleep mode hse bypass, pll on 48 mhz 10.7 11.7 (2) 11.9 12.5 (2) 2.4 2.6 (2) 2.7 2.9 (2) ma 32 mhz 7.1 7.8 8.1 8.2 1.6 1.7 1.9 1.9 24 mhz 5.5 6.3 6.4 6.4 1.3 1.4 1.5 1.5 hse bypass, pll off 8 mhz 1.8 2.0 2.0 2.1 0.4 0.4 0.5 0.5 1 mhz 0.2 0.5 0.5 0.5 0.1 0.1 0.1 0.1 hsi clock, pll on 48 mhz 10.8 11.9 12.1 12.6 2.4 2.7 2.7 2.9 32 mhz 7.3 8.0 8.4 8.5 1.7 1.9 1.9 2.0 24 mhz 5.5 6.2 6.5 6.5 1.3 1.5 1.5 1.6 hsi clock, pll off 8 mhz 1.9 2.2 2.3 2.4 0.5 0.5 0.5 0.6 1. data based on characterization results, not te sted in production unless otherwise specified. 2. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). table 23. typical and maximum current consumption from v dd at 3.6 v (continued) symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c table 24. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run or sleep mode, code executing from flash memory or ram hse bypass, pll on 48 mhz 150 170 (3) 178 182 (3) 164 183 (3) 195 198 (3) a 32 mhz 104 121 126 128 113 129 135 138 24 mhz 82 96 100 103 88 102 106 108 hse bypass, pll off 8 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 1 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 hsi clock, pll on 48 mhz 220 240 248 252 244 263 275 278 32 mhz 174 191 196 198 193 209 215 218 24 mhz 152 167 173 174 168 183 190 192 hsi clock, pll off 8 mhz 72 79 82 83 83.5 91 94 95 1. current consumption from the v dda supply is independent of whether the digita l peripherals are enabled or disabled, being in run or sleep mode or executing from flash memory or ram. furthermore, when the pll is off, i dda is independent of clock frequencies. 2. data based on characterization results, not te sted in production unless otherwise specified. 3. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). electrical characteristics stm32f031x4 stm32f031x6 46/106 docid025743 rev 4 table 25. typical and maximum current consumption in stop and standby modes sym- bol para- meter conditions typ @v dd (v dd = v dda )max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 15 15.1 15.3 15.5 15.7 16 18 (2) 38 55 (2) a regulator in low- power mode, all oscillators off 3.2 3.3 3.4 3.5 3.7 4 5.5 (2) 22 41 (2) supply current in standby mode lsi on and iwdg on 0.8 1.0 1.1 1.2 1.4 1.5 - - - lsi off and iwdg off 0.7 0.8 0.9 1.0 1.1 1.3 2 (2) 2.5 3 (2) i dda supply current in stop mode v dda monitoring on regulator in run mode, all oscillators off 1.9 2 2.2 2.3 2.5 2.6 3.5 (2) 3.5 4.5 (2) regulator in low- power mode, all oscillators off 1.9 2 2.2 2.3 2.5 2.6 3.5 (2) 3.5 4.5 (2) supply current in standby mode lsi on and iwdg on 2.3 2.5 2.7 2.9 3.1 3.3 - - - lsi off and iwdg off 1.8 1.9 2 2.2 2.3 2.5 3.5 (2) 3.5 4.5 (2) supply current in stop mode v dda monitoring off regulator in run mode, all oscillators off 1.1 1.2 1.2 1.2 1.3 1.4 - - - regulator in low- power mode, all oscillators off 1.1 1.2 1.2 1.2 1.3 1.4 - - - supply current in standby mode lsi on and iwdg on 1.5 1.6 1.7 1.8 1.9 2.0 - - - lsi off and iwdg off 1 1.0 1.1 1.1 1.2 1.2 - - - 1. data based on characterization results, not te sted in production unless otherwise specified. 2. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ) . docid025743 rev 4 47/106 stm32f031x4 stm32f031x6 electrical characteristics 80 typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins are in analog input configuration ? the flash memory access time is adjusted to f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled, f pclk = f hclk ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively table 26. typical and maximum current consumption from the v bat supply symbol parameter conditions typ @ v bat max (1) unit 1.65 v 1.8 v 2.4 v 2.7 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd _ vbat rtc domain supply current lse & rtc on; ?xtal mode?: lower driving capability; lsedrv[1:0] = '00' 0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.3 1.7 a lse & rtc on; ?xtal mode? higher driving capability; lsedrv[1:0] = '11' 0.8 0.8 0.9 1.0 1.1 1.2 1.3 1.6 2.1 1. data based on characterization results, not tested in production. electrical characteristics stm32f031x4 stm32f031x6 48/106 docid025743 rev 4 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 46: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt table 27. typical current consumption, code executing from flash memory, running from hse 8 mhz crystal symbol parameter f hclk typical run mode typical sleep mode unit peripheral s enabled peripheral s disabled peripheral s enabled peripheral s disabled i dd current from v dd supply 48mhz 20.2 12.3 11.1 2.9 ma 36 mhz 15.3 9.5 8.4 2.4 32 mhz 13.6 8.6 7.5 2.2 24 mhz 10.5 6.7 5.9 1.8 16 mhz 7.2 4.7 4.1 1.4 8 mhz 3.8 2.7 2.3 0.9 4 mhz 2.4 1.8 1.7 0.9 2 mhz 1.6 1.3 1.2 0.8 1 mhz 1.2 1.1 1.0 0.8 500 khz 1.0 1.0 0.9 0.8 i dda current from v dda supply 48mhz 155 ua 36 mhz 117 32 mhz 105 24 mhz 83 16 mhz 60 8 mhz 2.2 4 mhz 2.2 2 mhz 2.2 1 mhz 2.2 500 khz 2.2 docid025743 rev 4 49/106 stm32f031x4 stm32f031x6 electrical characteristics 80 trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 29: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v ddiox f sw c = electrical characteristics stm32f031x4 stm32f031x6 50/106 docid025743 rev 4 table 28. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v ddiox = 3.3 v c =c int 4 mhz 0.07 ma 8 mhz 0.15 16 mhz 0.31 24 mhz 0.53 48 mhz 0.92 v ddiox = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v ddiox = 3.3 v c ext = 10 pf c = c int + c ext + c s 4 mhz 0.32 8 mhz 0.64 16 mhz 1.25 24 mhz 2.23 48 mhz 4.442 v ddiox = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v ddiox = 3.3 v c ext = 33 pf c = c int + c ext + c s 4 mhz 0.64 8 mhz 1.25 16 mhz 3.24 24 mhz 5.02 v ddiox = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67 v ddiox = 2.4 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.66 8 mhz 1.43 16 mhz 2.45 24 mhz 4.97 docid025743 rev 4 51/106 stm32f031x4 stm32f031x6 electrical characteristics 80 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 29 . the mcu is placed under the following conditions: ? all i/o pins are in analog mode ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature and supply voltage conditions summarized in table 15: voltage characteristics ? the power consumption of the digital part of the on-chip peripherals is given in table 29 . the power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. table 29. peripheral current consumption peripheral typical consumption at 25 c unit ahb busmatrix (1) 3.8 a/mhz dma1 6.3 sram 0.7 flash memory interface 15.2 crc 1.61 gpioa 9.4 gpiob 11.6 gpioc 1.9 gpiof 0.8 all ahb peripherals 47.5 electrical characteristics stm32f031x4 stm32f031x6 52/106 docid025743 rev 4 apb apb-bridge (2) 2.6 a/mhz syscfg 1.7 adc (3) 4.2 tim1 17.1 spi1 9.6 usart1 17.4 tim16 8.2 tim17 8.0 dbg (mcu debug support) 0.5 tim2 17.4 tim3 12.8 tim14 6.0 wwdg 1.5 i2c1 5.1 pwr 1.2 all apb peripherals 110.9 1. the busmatrix automatically is active when at least one master is on (cpu or dma1). 2. the apbx bridge is automatically active w hen at least one peripheral is on on the same bus. 3. the power consumption of the analog part (i dda ) of peripherals such as adc is not included. refer to the tables of characteristics in the subsequent sections. table 29. peripheral current consumption (continued) peripheral typical consumption at 25 c unit docid025743 rev 4 53/106 stm32f031x4 stm32f031x6 electrical characteristics 80 6.3.6 wakeup time from low-power mode the wakeup times given in table 30 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction, in the case of a wfi (wai t for interruption) inst ruction, 16 cpu cycles must be added to the following timings due to the interrupt latency in the cortex m0 architecture. the sysclk clock source setti ng is kept unchanged afte r wakeup from sleep mode. during wakeup from stop or standby mode, sysclk takes the default setting: hsi 8 mhz. the wakeup source from sleep and stop mode is an exti line configured in event mode. the wakeup source from standby mode is the wkup1 pin (pa0). all timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions .. 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 14: high-speed external clock source ac timing diagram . table 30. low-power mode wakeup timings symbol parameter conditions typ @v dd = v dda max unit = 2.0 v = 2.4 v = 2.7 v = 3 v = 3.3 v t wustop wakeup from stop mode regulator in run mode 3.23.12.92.92.85 s regulator in low power mode 7.05.85.24.94.69 t wustandby wakeup from standby mode - 60.4 55.6 53.5 52 51 - t wusleep wakeup from sleep mode - 4 sysclk cycles - table 31. high-speed external user clock characteristics symbol parameter (1) min typ max unit f hse_ext user external clock source frequency - 8 32 mhz v hseh osc_in input pin high level voltage 0.7 v ddiox -v ddiox v v hsel osc_in input pin low level voltage v ss - 0.3 v ddiox t w(hseh) t w(hsel) osc_in high or low time 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 electrical characteristics stm32f031x4 stm32f031x6 54/106 docid025743 rev 4 figure 14. high-speed external clock source ac timing diagram low-speed external user clock generated from an external source in bypass mode the lse oscillator is switch ed off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 15 . figure 15. low-speed external clock source ac timing diagram 1. guaranteed by design, not tested in production. table 32. low-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage v ss - 0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / docid025743 rev 4 55/106 stm32f031x4 stm32f031x6 electrical characteristics 80 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 33 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 16 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . table 33. hse oscilla tor characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit f osc_in oscillator frequency - 4 8 32 mhz r f feedback resistor - - 200 - k i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time -8.5 ma v dd = 3.3 v, rm = 30 , cl = 10 pf@8 mhz -0.4- v dd = 3.3 v, rm = 45 , cl = 10 pf@8 mhz -0.5- v dd = 3.3 v, rm = 30 , cl = 5 pf@32 mhz -0.8- v dd = 3.3 v, rm = 30 , cl = 10 pf@32 mhz -1- v dd = 3.3 v, rm = 30 , cl = 20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms electrical characteristics stm32f031x4 stm32f031x6 56/106 docid025743 rev 4 figure 16. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information gi ven in this paragraph are based on design simulation results obtained with typical external components specified in table 34 . in the application, the resonator and the load capa citors have to be placed as cl ose as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time . refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 5 ) % l d v f r q w u r o o h g j d l q i + 6 ( 5 ( ; 7 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / table 34. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.50.9 a lsedrv[1:0]= 01 medium low driving capability --1 lsedrv[1:0] = 10 medium high driving capability --1.3 lsedrv[1:0]=11 higher driving capability --1.6 docid025743 rev 4 57/106 stm32f031x4 stm32f031x6 electrical characteristics 80 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 17. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 6.3.8 internal clock source characteristics the parameters given in table 35 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . the provided curves are characterization results, not tested in production. g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]= 01 medium low driving capability 8- - lsedrv[1:0] = 10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v ddiox is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is en abled (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer table 34. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics stm32f031x4 stm32f031x6 58/106 docid025743 rev 4 high-speed internal (hsi) rc oscillator figure 18. hsi oscillator accuracy characterization results for soldered parts table 35. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = -40 to 105c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 8 - mhz trim hsi user trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle - 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator t a = -40 to 105c -2.8 (3) 3. data based on characterization results, not tested in production. -3.8 (3) % t a = -10 to 85c -1.9 (3) -2.3 (3) t a = 0 to 85c -1.9 (3) -2 (3) t a = 0 to 70c -1.3 (3) -2 (3) t a = 0 to 55c -1 (3) -2 (3) t a = 25c (4) 4. factory calibrated, parts not soldered. -1 - 1 t su(hsi) hsi oscillator startup time - 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - - 80 100 (2) a 0 6 9 5 < ? $ > " . " 9 . * / docid025743 rev 4 59/106 stm32f031x4 stm32f031x6 electrical characteristics 80 high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) figure 19. hsi14 oscillator accuracy characterization results table 36. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - - 14 - mhz trim hsi14 user-trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle - 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 105 c ?4.2 (3) 3. data based on characterization results, not tested in production. -5.1 (3) % t a = ?10 to 85 c ?3.2 (3) -3.1 (3) % t a = 0 to 70 c ?2.5 (3) -2.3 (3) % t a = 25 c ?1 - 1 % t su(hsi14) hsi14 oscillator startup time - 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption --100150 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! electrical characteristics stm32f031x4 stm32f031x6 60/106 docid025743 rev 4 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. table 37. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 38. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier factors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) 8.0 24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -48mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps table 39. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +105 c 40 53.5 60 s t erase page (1 kb) erase time t a = ?40 to +105 c 20 - 40 ms t me mass erase time t a = ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma docid025743 rev 4 61/106 stm32f031x4 stm32f031x6 electrical characteristics 80 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 41 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. table 40. flash memory endurance and data retention symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. unit n end endurance t a = ?40 to +105 c 10 kcycle t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 year 1 kcycle (2) at t a = 105 c 10 10 kcycle (2) at t a = 55 c 20 table 41. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp48, t a = +25 c, f hclk = 48 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp48, t a = +25c, f hclk = 48 mhz, conforming to iec 61000-4-4 4b electrical characteristics stm32f031x4 stm32f031x6 62/106 docid025743 rev 4 software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (for example control registers) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 42. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd = 3.6 v, t a = 25 c, lqfp48 package compliant with iec 61967-2 0.1 to 30 mhz -11 dbv 30 to 130 mhz 21 130 mhz to 1 ghz 21 emi level 4 - docid025743 rev 4 63/106 stm32f031x4 stm32f031x6 electrical characteristics 80 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to gi ve an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator freque ncy deviation). the characterization results are given in table 45 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. table 43. esd absolute maximum ratings symbol ratings conditions packages class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 all 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 all c3 250 v 1. data based on characterization results, not tested in production. table 44. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a electrical characteristics stm32f031x4 stm32f031x6 64/106 docid025743 rev 4 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 46 are derived from tests performed under the conditions summarized in table 18: general operating conditions . all i/os are designed as cmos- and ttl-compliant (except boot0). table 45. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 ?0 na ma injected current on all ft and ftf pins ?5 na injected current on all tta, tc and reset pins ?5 +5 table 46. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v ddiox +0.07 (1) v ft and ftf i/o - - 0.475 v ddiox ?0.2 (1) boot0 - - 0.3 v ddiox ?0.3 (1) all i/os except boot0 pin --0.3 v ddiox v ih high level input voltage tc and tta i/o 0.445 v ddiox +0.398 (1) -- v ft and ftf i/o 0.5 v ddiox +0.2 (1) -- boot0 0.2 v ddiox +0.95 (1) -- all i/os except boot0 pin 0.7 v ddiox -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (2) tc, ft and ftf i/o tta in digital mode v ss v in v ddiox -- 0.1 a tta in digital mode v ddiox v in v dda --1 tta in analog mode v ss v in v dda -- 0.2 ft and ftf i/o v ddiox v in 5 v --10 docid025743 rev 4 65/106 stm32f031x4 stm32f031x6 electrical characteristics 80 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 20 for standard i/os, and in figure 21 for 5 v tolerant i/os. the following curves are design simulation results, not tested in production. r pu weak pull-up equivalent resistor (3) v in = v ss 25 40 55 k r pd weak pull-down equivalent resistor (3) v in = v ddiox 25 40 55 k c io i/o pin capacitance - - 5 - pf 1. data based on design simulation only. not tested in production. 2. the leakage could be higher than the maximum value, if negative current is injected on adjacent pins. refer to table 45: i/o current injection susceptibility . 3. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). table 46. i/o static characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32f031x4 stm32f031x6 66/106 docid025743 rev 4 figure 20. tc and tta i/o input characteristics figure 21. five volt tolerant (ft and ftf) i/o input characteristics 0 6 y 9 7 ( 6 7 ( ' 5 $ 1 * ( 7 ( 6 7 ( ' 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 9 , / p d [ 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 8 1 ' ( ) , 1 ( ' , 1 3 8 7 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ 9 , 1 9 9 ' ' , 2 [ 9 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w 0 6 y 9 7 ( 6 7 ( ' 5 $ 1 * ( 7 ( 6 7 ( ' 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 9 , / p d [ 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w 8 1 ' ( ) , 1 ( ' , 1 3 8 7 5 $ 1 * ( 9 , + p l q 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ 9 , 1 9 9 ' ' , 2 [ 9 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w docid025743 rev 4 67/106 stm32f031x4 stm32f031x6 electrical characteristics 80 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 15: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximu m consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating i vss (see table 15: voltage characteristics ). output voltage levels unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . all i/os are cmos- and ttl-compliant (ft, tta or tc unless otherwise specified). table 47. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin cmos port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v v oh output high level voltage for an i/o pin v ddiox ?0.4 - v ol output low level voltage for an i/o pin ttl port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v v oh output high level voltage for an i/o pin 2.4 - v ol (3) output low level voltage for an i/o pin |i io | = 20 ma v ddiox 2.7 v -1.3 v v oh (3) output high level voltage for an i/o pin v ddiox ?1.3 - v ol (3) output low level voltage for an i/o pin |i io | = 6 ma -0.4 v v oh (3) output high level voltage for an i/o pin v ddiox ?0.4 - v olfm+ (3) output low level voltage for an ftf i/o pin in fm+ mode |i io | = 20 ma v ddiox 2.7 v -0.4v |i io | = 10 ma - 0.4 v 1. the i io current sourced or sunk by the device must alwa ys respect the absolute maxi mum rating specified in table 15: voltage characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings i io . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. data based on characterization results. not tested in production. electrical characteristics stm32f031x4 stm32f031x6 68/106 docid025743 rev 4 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 22 and table 48 , respectively. unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . table 48. i/o ac characteristics (1)(2) 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the stm32f0xxxx rm0091 reference manual for a description of gpio port configuration register. 2. guaranteed by design, not tested in production. ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (3) 3. the maximum frequency is defined in figure 22 . c l = 50 pf -2mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 01 f max(io)out maximum frequency (3) c l = 50 pf -10mhz t f(io)out output fall time - 25 ns t r(io)out output rise time - 25 11 f max(io)out maximum frequency (3) c l = 30 pf, v ddiox 2.7 v - 50 mhz c l = 50 pf, v ddiox 2.7 v - 30 c l = 50 pf, v ddiox < 2.7 v - 20 t f(io)out output fall time c l = 30 pf, v ddiox 2.7 v - 5 ns c l = 50 pf, v ddiox 2.7 v - 8 c l = 50 pf, v ddiox < 2.7 v - 12 t r(io)out output rise time c l = 30 pf, v ddiox 2.7 v - 5 c l = 50 pf, v ddiox 2.7 v - 8 c l = 50 pf, v ddiox < 2.7 v - 12 fm+ configuration (4) 4. when fm+ configuration is set, the i/o speed contro l is bypassed. refer to the stm32f0xxxx reference manual rm0091 for a detailed descrip tion of fm+ i/o configuration. f max(io)out maximum frequency (3) c l = 50 pf -2mhz t f(io)out output fall time - 12 ns t r(io)out output rise time - 34 t extipw pulse width of external signals detected by the exti controller 10 - ns docid025743 rev 4 69/106 stm32f031x4 stm32f031x6 electrical characteristics 80 figure 22. i/o ac charac teristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . 0 6 9 7 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w w ? z k h q o r d g h g e \ & v h h w k h w d e o h , 2 $ & f k d u d f w h u l v w l f v g h i l q l w l r q u i u , 2 r x w w i , 2 r x w w - 7 d q g l i w k h g x w \ f \ f o h l v table 49. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage - - - 0.3 v dd +0.07 (1) v v ih(nrst) nrst input high level voltage - 0.445 v dd +0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis --200-mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k v f(nrst) nrst input filtered pulse - - - 100 (1) ns v nf(nrst) nrst input not filtered pulse 2.7 < v dd < 3.6 300 (3) -- ns 2.0 < v dd < 3.6 500 (3) -- 1. data based on design simulation only. not tested in production. 2. the pull-up is designed with a true re sistance in series with a switchable pmos . this pmos contribution to the series resistance is minimal (~10% order). 3. data based on design simulation only. not tested in production. electrical characteristics stm32f031x4 stm32f031x6 70/106 docid025743 rev 4 figure 23. recommended nrst pin protection 1. the external capacitor protects the device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 49: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 6.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in table 50 are derived from tests performed under the conditions summarized in table 18: general operating conditions . note: it is recommended to perform a calibration after each power-up. 5 3 8 9 ' ' , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) 0 6 9 table 50. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on - 2.4 - 3.6 v i dda (adc) current consumption of the adc (1) v dda = 3.3 v - 0.9 - ma f adc adc clock frequency - 0.6 - 14 mhz f s (2) sampling rate 12-bit resolution 0.043 - 1 mhz f trig (2) external trigger frequency f adc = 14 mhz, 12-bit resolution --823khz 12-bit resolution - - 17 1/f adc v ain conversion voltage range - 0 - v dda v r ain (2) external input impedance see equation 1 and table 51 for details --50k r adc (2) sampling switch resistance ---1k c adc (2) internal sample and hold capacitor ---8pf t cal (2)(3) calibration time f adc = 14 mhz 5.9 s -831/f adc docid025743 rev 4 71/106 stm32f031x4 stm32f031x6 electrical characteristics 80 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). w latency (2)(4) adc_dr register ready latency adc clock = hsi14 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (2) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.179 - 0.250 s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (2) sampling time f adc = 14 mhz 0.107 - 17.1 s - 1.5 - 239.5 1/f adc t stab (2) stabilization time - 14 1/f adc t conv (2) total conversion time (including sampling time) f adc = 14 mhz, 12-bit resolution 1-18s 12-bit resolution 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. during conversion of the sampled value (12.5 x adc clock period), an additional c onsumption of 100 a on i dda and 60 a on i dd should be taken into account. 2. guaranteed by design, not tested in production. 3. specified value includes only adc timing. it does not include the latency of the register access. 4. this parameter specify latency for transfer of the conversion result to the adc_dr register. eoc flag is set at this time. table 50. adc characteristics (continued) symbol parameter conditions min typ max unit r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < . = () () ( ) (1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 electrical characteristics stm32f031x4 stm32f031x6 72/106 docid025743 rev 4 28.52.0425.2 41.52.9637.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na 1. guaranteed by design, not tested in production. table 51. r ain max for f adc = 14 mhz (continued) t s (cycles) t s (s) r ain max (k ) (1) table 52. adc accuracy (1)(2)(3) symbol parameter test conditions typ max (4) unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k v dda = 3 v to 3.6 v t a = 25 c 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k v dda = 2.7 v to 3.6 v t a = ? 40 to 105 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k v dda = 2.4 v to 3.6 v t a = 25 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any of the standard (non-robust) analog input pins should be avoided as this signific antly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to gr ound) to standard analog pins which may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization re sults, not tested in production. docid025743 rev 4 73/106 stm32f031x4 stm32f031x6 electrical characteristics 80 figure 24. adc accuracy characteristics figure 25. typical connecti on diagram using the adc 1. refer to table 50: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 12: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( 7 7 r w d o 8 q d m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h v ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h 9 ' ' $ 9 6 6 $ ( 2 ( 7 ( / ( * ( ' / 6 % , ' ( $ / 0 6 9 0 6 9 $ , 1 [ ? ? $ & s d u d v l w l f , / 9 7 9 7 e l w f r q y h u w h u & $ ' & 5 $ ' & 9 ' ' $ 6 d p s o h d q g k r o g $ ' & f r q y h u w h u 5 $ , 1 9 $ , 1 electrical characteristics stm32f031x4 stm32f031x6 74/106 docid025743 rev 4 6.3.17 temperature sensor characteristics 6.3.18 v bat monitoring characteristics 6.3.19 timer characteristics the parameters given in the followi ng tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 53. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 30 voltage at 30 c ( 5 c) (2) 1.34 1.43 1.52 v t start (1) adc_in16 buffer startup time - - 10 s t s_temp (1) adc sampling time when reading the temperature 4- -s 1. guaranteed by design, not tested in production. 2. measured at v dda = 3.3 v 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte . refer to table 3: temperature sensor calibration values . table 54. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -2 x 50- k q ratio on v bat measurement - 2 - er (1) error on q ?1 - +1 % t s_vbat (1) adc sampling time when reading the v bat 4- -s 1. guaranteed by design, not tested in production. table 55. timx characteristics symbol parameter conditions min typ max unit t res(tim) timer resolution time --1- t timxclk f timxclk = 48 mhz - 20.8 - ns f ext timer external clock frequency on ch1 to ch4 -- f timxclk /2 -mhz f timxclk = 48 mhz - 24 - mhz t max_count 16-bit timer maximum period -- 2 16 - t timxclk f timxclk = 48 mhz - 1365 - s 32-bit counter maximum period -- 2 32 - t timxclk f timxclk = 48 mhz - 89.48 - s docid025743 rev 4 75/106 stm32f031x4 stm32f031x6 electrical characteristics 80 6.3.20 communication interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i 2 c timings requirements are guaranteed by design when the i2cx peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i 2 c i/os characteristics. all i 2 c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 56. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 kh z clock but the microcontroller inte rnal rc frequency can vary from 30 to 60 khz. moreover, given an ex act rc oscillator frequency, the ex act timings still depend on the phasing of the apb interface clock versus the lsi clock so t hat there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 table 57. wwdg min/max timeout value at 48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 electrical characteristics stm32f031x4 stm32f031x6 76/106 docid025743 rev 4 spi/i 2 s characteristics unless otherwise specified, the parameters given in table 59 for spi or in table 60 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 18: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (n ss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 58. i 2 c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns table 59. spi characteristics (1) symbol parameter con ditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) nss setup time slave mode 4tpclk - ns t h(nss) nss hold time slave mode 2tpclk + 10 - t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) t su(si) data input setup time master mode 4 - slave mode 5 - t h(mi) data input hold time master mode 4 - t h(si) slave mode 5 - t a(so) (2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (3) data output disable time slave mode 0 18 t v(so) data output valid time slave mode (after enable edge) - 22.5 t v(mo) data output valid time master mode (after enable edge) - 6 t h(so) data output hold time slave mode (after enable edge) 11.5 - t h(mo) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization results, not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and th e max time is for the maximum time to put the data in hi-z docid025743 rev 4 77/106 stm32f031x4 stm32f031x6 electrical characteristics 80 figure 26. spi timing diagram - slave mode and cpha = 0 figure 27. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 electrical characteristics stm32f031x4 stm32f031x6 78/106 docid025743 rev 4 figure 28. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 table 60. i 2 s characteristics (1) symbol parameter con ditions min max unit f ck 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.597 1.601 mhz slave mode 0 6.5 t r(ck) i 2 s clock rise time capacitive load c l = 15 pf -10 ns t f(ck) i 2 s clock fall time - 12 t w(ckh) i 2 s clock high time master f pclk = 16 mhz, audio frequency = 48 khz 306 - t w(ckl) i 2 s clock low time 312 - t v(ws) ws valid time master mode 2 - t h(ws) ws hold time master mode 2 - t su(ws) ws setup time slave mode 7 - t h(ws) ws hold time slave mode 0 - ducy(sck) i 2 s slave input clock duty cycle slave mode 25 75 % docid025743 rev 4 79/106 stm32f031x4 stm32f031x6 electrical characteristics 80 figure 29. i 2 s slave timing diagram (philips protocol) 1. measurement points are done at cmos levels: 0.3 v ddiox and 0.7 v ddiox . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. t su(sd_mr) data input setup time master receiver 6 - ns t su(sd_sr) slave receiver 2 - t h(sd_mr) (2) data input hold time master receiver 4 - t h(sd_sr) (2) slave receiver 0.5 - t v(sd_mt) (2) data output valid time master transmitter - 4 t v(sd_st) (2) slave transmitter - 20 t h(sd_mt) data output hold time master transmitter 0 - t h(sd_st) slave transmitter 13 - 1. data based on design simulation and/or char acterization results, not tested in production. 2. depends on f pclk . for example, if f pclk = 8 mhz, then t pclk = 1/f plclk = 125 ns. table 60. i 2 s characteristics (1) (continued) symbol parameter con ditions min max unit 0 6 y 9 & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % u h f h l y h / 6 % w u d q v p l w electrical characteristics stm32f031x4 stm32f031x6 80/106 docid025743 rev 4 figure 30. i 2 s master timing diagram (philips protocol) 1. data based on characterization results, not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. 0 6 y 9 & . r x w s x w & 3 2 / & 3 2 / w f & . : 6 r x w s x w 6 ' u h f h l y h 6 ' w u d q v p l w w z & . + w z & . / w v x 6 ' b 0 5 w y 6 ' b 0 7 w k 6 ' b 0 7 w k : 6 w k 6 ' b 0 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w w i & . w u & . w y : 6 / 6 % u h f h l y h / 6 % w u d q v p l w docid025743 rev 4 81/106 stm32f031x4 stm32f031x6 package information 102 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp48 package information lqfp48 is a 48-pin, 7 x 7 mm low-profile quad flat package. figure 31. lqfp48 package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + package information stm32f031x4 stm32f031x6 82/106 docid025743 rev 4 figure 32. recommended footprint for lqfp48 package 1. dimensions are expr essed in millimeters. table 61. lqfp48 package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 a i d docid025743 rev 4 83/106 stm32f031x4 stm32f031x6 package information 102 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 33. lqfp48 package marking example 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 4 5 . ' $ 5 package information stm32f031x4 stm32f031x6 84/106 docid025743 rev 4 7.2 lqfp32 package information lqfp32 is a 32-pin, 7 x 7 mm low-profile quad flat package. figure 34. lqfp32 package outline 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e docid025743 rev 4 85/106 stm32f031x4 stm32f031x6 package information 102 figure 35. recommended footprint for lqfp32 package 1. dimensions are expr essed in millimeters. table 62. lqfp32 package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.100 - - 0.0039 6 ? & 0 ? 6 package information stm32f031x4 stm32f031x6 86/106 docid025743 rev 4 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 36. lqfp32 package marking example 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 7.3 ufqfpn32 package information ufqfpn32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 4 5 . ' , 5 docid025743 rev 4 87/106 stm32f031x4 stm32f031x6 package information 102 figure 37. ufqfpn32 package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of t he ufqfpn package. this pad is used for the device ground and must be connected. it is referred to as pin 0 in table: pin definitions . ! " ? - % ? 6 3 , 1 , g h q w l i l h u 6 ( $ 7 , 1 * 3 / $ 1 ( & & g g g $ $ $ h e ' e ( / h ( ( ' / ' package information stm32f031x4 stm32f031x6 88/106 docid025743 rev 4 figure 38. recommended footprint for ufqfpn32 package 1. dimensions are expr essed in millimeters. table 63. ufqfpn32 package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d1 3.400 3.500 3.600 0.1339 0.1378 0.1417 d2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e1 3.400 3.500 3.600 0.1339 0.1378 0.1417 e2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 $ % b ) 3 b 9 docid025743 rev 4 89/106 stm32f031x4 stm32f031x6 package information 102 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 39. ufqfpn32 package marking example 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r ' , 0 6 9 package information stm32f031x4 stm32f031x6 90/106 docid025743 rev 4 7.4 ufqfpn28 package information ufqfpn28 is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. figure 40. ufqfpn28 package outline 1. drawing is not to scale. table 64. ufqfpn28 package mechanical data (1) symbol millimeters inches min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 - 0.000 0.050 - 0.0000 0.0020 d 3.900 4.000 4.100 0.1535 0.1575 0.1614 d1 2.900 3.000 3.100 0.1142 0.1181 0.1220 e 3.900 4.000 4.100 0.1535 0.1575 0.1614 e1 2.900 3.000 3.100 0.1142 0.1181 0.1220 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 l1 0.250 0.350 0.450 0.0098 0.0138 0.0177 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ! " ? - % ? 6 ' ( ' ( ' h w d l o = ' h w d l o < ' docid025743 rev 4 91/106 stm32f031x4 stm32f031x6 package information 102 figure 41. recommended footprint for ufqfpn28 package 1. dimensions are expr essed in millimeters. 1. values in inches are converted from mm and rounded to 4 decimal digits. $ % b ) 3 b 9 package information stm32f031x4 stm32f031x6 92/106 docid025743 rev 4 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 42. ufqfpn28 package marking example 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q ' r w 5 h y l v l r q f r g h ' d w h f r g h : 8 8 ( s l q l g h q w l i l h u docid025743 rev 4 93/106 stm32f031x4 stm32f031x6 package information 102 7.5 wlcsp25 pac kage information wlcsp25 is a 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale package. figure 43. wlcsp25 package outline 1. drawing is not to scale. table 65. wlcsp25 package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) - 0.025 - - 0.0010 - b (3) (4) 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 2.388 2.423 2.458 0.0940 0.0954 0.0968 e 2.29 2.325 2.36 0.0902 0.0915 0.0929 e - 0.400 - - 0.0157 - e1 - 1.600 - - 0.0630 - e2 - 1.600 - - 0.0630 - f - 0.4115 - - 0.0162 - g - 0.3625 - - 0.0143 - : / & 6 3 b $ 1 b 0 ( b 9 $ r u l h q w d w l r q u h i h u h q f h : d i h u e d f n v l g h ' h w d l o $ u r w d w h g ? 6 h d w l q j s o d q h $ % x p s e 6 l g h y l h z $ $ ' h w d l o $ h ) * h h $ e d o o o r f d w l r q h % x p s v l g h h h h = ( $ $ = ; < = f f f g g g ? e e d o o v = d d d [ e e e = package information stm32f031x4 stm32f031x6 94/106 docid025743 rev 4 figure 44. recommended footprint for wlcsp25 package aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. back side coating. 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 4. primary datum z and seating plane are defi ned by the spherical crowns of the bump. table 66. wlcsp25 recommended pcb design rules dimension recommended values pitch 0.4 mm dpad 0.225 mm dsm 0.290 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.250 mm stencil thickness 0.100 mm table 65. wlcsp25 package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max : / & 6 3 b $ 1 b ) 3 b 9 ' s d g ' v p docid025743 rev 4 95/106 stm32f031x4 stm32f031x6 package information 102 device marking the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 45. wlcsp25 package marking example 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 5 h y l v l r q f r g h : 8 8 ' 3 ' d w h f r g h 3 u r g x f w l g h q w l i l f d w l r q ' r w package information stm32f031x4 stm32f031x6 96/106 docid025743 rev 4 7.6 tssop20 package information tssop20 is a 20-lead thin shrink small-outline, 6.5 x 4.4 mm, 0.65 mm pitch, package. figure 46.tssop20 package outline 1. drawing is not to scale. table 67. tssop20 package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 d (2) 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 (3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - z z d z s? ? > ? l > ^ d / e ' w > e ' h ' w > e x?? uu w / e / e d / & / d / k e docid025743 rev 4 97/106 stm32f031x4 stm32f031x6 package information 102 figure 47. recommended footprint for tssop20 package 1. dimensions are expr essed in millimeters. k 0 - 8 0 - 8 aaa - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. 2. dimension ?d? does not include mold fl ash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 3. dimension ?e1? does not include interlead flash or pr otrusions. interlead flash or protrusions shall not exceed 0.25mm per side. table 67. tssop20 package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 9 ! ? & 0 ? 6 package information stm32f031x4 stm32f031x6 98/106 docid025743 rev 4 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 48. tssop20 package marking example 1. parts marked as "es", "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r ' ' 1 0 6 9 docid025743 rev 4 99/106 stm32f031x4 stm32f031x6 package information 102 7.7 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 18: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v ddiox ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.7.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org table 68. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp48 - 7 7 mm 55 c/w thermal resistance junction-ambient ufqfpn32 - 5 5 mm 38 thermal resistance junction-ambient lqfp32 - 7 7 mm 56 thermal resistance junction-ambient ufqfpn28 - 4 4 mm 118 thermal resistance junction-ambient wlcsp25 - 2.13 x 2.07 mm 74 thermal resistance junction-ambient tssop20 - 6.5 x 4.4 mm 110 package information stm32f031x4 stm32f031x6 100/106 docid025743 rev 4 7.7.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a spec ific maximum junction temperature. as applications do not commonly use the stm 32f031x4/x6 at maximum dissipation, it is useful to calculate the exact power consumpt ion and junction temperature to determine which temperature range will be best suit ed to the application. the following examples show how to calculat e the temperature range needed for a given application. example 1: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 80 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in table 68 t jmax is calculated as follows: ? for lqfp48, 55 c/w t jmax = 80 c + (55c/w 447 mw) = 80 c + 24.585 c = 104.585 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c) see table 18: general operating conditions . in this case, parts must be ordered at leas t with the temperature range suffix 6 (see section 8: part numbering ). note: with this given p dmax we can find the tamax allowed for a giv en device temperature range (order code suffix 6 or 7). suffix 6: t amax = t jmax - (55c/w 447 mw) = 105-24.585 = 80.415 c suffix 7: t amax = t jmax - (55c/w 447 mw) = 125-24.585 = 100.415 c example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. docid025743 rev 4 101/106 stm32f031x4 stm32f031x6 package information 102 assuming the following ap plication conditions: maximum ambient temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in table 68 t jmax is calculated as follows: ? for lqfp48, 55 c/w t jmax = 100 c + (55 c/w 134 mw) = 100 c + 7.37 c = 107.37 c this is above the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 7 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts. part numbering stm32f031x4 stm32f031x6 102/106 docid025743 rev 4 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please cont act your nearest st sales office. table 69. ordering information scheme example :stm32f031 g 6 t6x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 031 = stm32f031xx pin count f = 20 pins e = 25 pins g = 28 pins k = 32 pins c = 48 pins user code memory size 4 = 16 kbyte 6 = 32 kbyte package p = tssop u = ufqfpn t = lqfp y = wlcsp temperature range 6 = ?40 c to +85 c 7 = ?40 c to +105 c options xxx = code id of programmed parts (includes packing type) tr = tape and reel packing blank = tray packing docid025743 rev 4 103/106 stm32f031x4 stm32f031x6 revision history 105 9 revision history table 70. document revision history date revision changes 13-jan-2014 1 initial release. 11-jul-2014 2 changed the document status to datasheet - production data. updated the following: ? table: stm32f031x4/6 family device features and peripheral counts, ? figure: clock tree , ? figure: power supply scheme , ? table: peripheral cu rrent consumption . replaced table typical current consumption in run mode, code with data processing running from flash and table typical current consumption in sleep mode, code running from flash or ram with table: typical current consumption, code executing from flash, running from hse 8 mhz crystal. added the lqfp32 package: updates in section: description, section: pinouts and pin description and section: package information. 28-aug-2015 3 updated: ? figure 9: stm32f031x6 memory map ? af1 alternate functions for pa0, pa1, pa2, pa3 and pa4 in table 12: alternate functions selected through gpioa_afr registers for port a ? the footnote for v in max value in table 15: voltage characteristics ? the footnote for max v in in table 18: general operating conditions ? table 22: embedded internal reference voltage with the addition of t start parameter ? table 50: adc characteristics ? table 53: ts characteristics : removed the min. value for t start parameter ? the typical value for r parameter in table 54: vbat monitoring characteristics ? the structure of section 7: package information . added: ? figure 33: lqfp48 marking example (package top view), figure 36: lqfp32 marking example (package top view), figure 39: ufqfpn32 marking example (package top view), figure 42: ufqfpn28 marking example (package top view), figure 48: tssop20 marking example (package top view) revision history stm32f031x4 stm32f031x6 104/106 docid025743 rev 4 28-aug-2015 3 (continued) added wlcsp25 package, updates in the following: ? table 1: device summary , ? section 2: description , ? table 2: stm32f031x4/x6 family device features and peripheral counts , ? section 4: pinouts and pin description : addition of figure 7: wlcsp25 25-ball package ballout (bump side) and update of table 11: pin definitions , ? table 18: general operating conditions , ? section 7: package information with the addition of section 7.5: wlcsp25 package information , ? table 68: package thermal characteristics . 16-dec-2015 4 cover page: ? number of timers added in the title ? table 1: device summary - stm32f031x4 added section 2: description : ? figure 1: block diagram updated section 3: functional overview : ? figure 2: clock tree updated ? section 3.5.4: low-power modes - added explicit inf. on peripherals configur able to operate with hsi ? section 3.10.2: internal voltage reference (vrefint) - removed information on comparators ? section 3.11.2: general-purpo se timers (tim2, 3, 14, 16, 17) - number of gen-purpose timers corrected ? section table 7.: stm32f031x4/x6 i2c implementation - added 20ma output drive current section 4: pinouts and pin descriptions : ? package pinout figures updated (look and feel) ? figure 7: wlcsp25 package pinout - now presented in top view ? table 11: pin definitions - notes 3 and 6 added section 5: memory mapping : ? added information on memory mapping difference of stm32f031x4 from stm32f031x6 section 6: electrical characteristics : ? table 22: embedded internal reference voltage : removed -40-to-85 conditi on and associated note for v refint ? table 25 and table 26 values rounded to 1 decimal ? table 46: i/o static characteristics - removed note ? table 50: adc characteristics - updated some parameter values, test conditions and added footnotes (3) and (4) table 70. document revision history (continued) date revision changes docid025743 rev 4 105/106 stm32f031x4 stm32f031x6 revision history 105 16-dec-2015 4 (continued) ? section 6.3.16: 12-bit adc characteristics - changed introductory sentence ? table 60: i2s characteristics : table reorganized, t v(sd_st) max value updated section 7: package information : ? figure 41: recommended footprint for ufqfpn28 package updated section 8: part numbering : ? added tray packing to options table 70. document revision history (continued) date revision changes stm32f031x4 stm32f031x6 106/106 docid025743 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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