( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 1 features ? frequency r ange 10mhz to 220mhz ? zero input - output delay. ? low output to output skew ? optional drive strength: standard (8ma) pl 123e - 09 high (12ma) pl 123e - 09 h ? 2.5v or 3.3v , 10% operation. ? available in 16 - pin sop or tssop packages description the pl 123e - 09 ( - 09h for high drive) is a high pe r fo r- mance, low skew, low jitter zero delay buffer d e signed to distribute high speed clocks . it has two low - skew output banks , of 4 outputs each , that a re sy n chronized with the input. control of the two banks o f outputs is achieved by using the s1 and s2 inputs as shown in the selector definition table on page 2. the synchronization is esta b lished via clkout feed back to the input of the pll. since the skew between the input and ou t put is less than ? 100 ps, the device acts as a zero delay buffer. the input output propag a- tion delay can be advanced or delayed by a d justing the load on the clkout pin. these parts are not intended for 5v input - tolerant a p- plica tions. block diagram pll ref clkout clka 1 clka 2 clka 3 clka 4 selector inputs mux clkb 1 clkb 2 clkb 3 clkb 4 s 1 s 2 1 ref clka 1 clka 2 vdd clkout clka 4 clka 3 vdd gnd clkb 4 clkb 3 s 1 10 11 12 13 14 15 16 9 8 7 6 5 4 3 2 s 2 clkb 2 clkb 1 gnd b a n k b b a n k a
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 2 pin descriptions name package t ype type description tssop - 16l sop - 16l ref [1 ] 1 1 i input reference frequency. clk a 1 [2 ] 2 2 o buffered clock output, bank a clk a 2 [2 ] 3 3 o buffered clock output, bank a vdd 4,13 4,13 p vdd c onnection gnd 5,12 5,12 p gnd c onnection clk b1 [2 ] 6 6 o buffered clock output, bank b clk b2 [2 ] 7 7 o buffered clock output, bank b s2 [3 ] 8 8 i selector i nput s1 [3 ] 9 9 i selector i nput clk b3 [2 ] 10 10 o buffered clock output, bank b clk b4 [2 ] 11 11 o buffered clock output, bank b clk a 3 [2 ] 14 14 o buffered clock output, bank a clk a 4 [2 ] 15 15 o buffered clock output, bank a clkout [2 ] 16 16 o buffered clock output. internal feedback on this pin. notes: 1: weak pull - down. 2: weak pull - down on all outputs. 3: weak pull - up on s1 and s2 selector definition s2 s1 clock a 1 C a 4 (bank a ) clock b1 C b4 (bank b ) clkou t output source pll shutdown 0 0 three - state three - state driven pll n 0 1 driven three - state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n input / output skew co ntrol the pl 123e - 09 will achieve zero delay from input to output when all the outputs are loaded equally . adjus t- ments to the input/output delay can be made by adding additional loading to the clkout pin. please contact micrel for more information.
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 3 layout recommendations the following guidelines are to assist you with a pe r formance optimized pcb design: signal integrity and termination consider a tions - keep traces short! - trace = inductor. with a capacitive load this equals ringing! - long trace = t ransmission line. without proper term i- nation this will cause reflections ( looks like rin g ing ). - design long traces as striplines or m i crostrips with defined impedance. - match trace at one side to avoid reflections boun c ing back and forth. decoupl ing and power supply co n siderations - place decoupling capacitors as close as possible to the vdd pin(s) to limit noise from the power supply - addition of a ferrite bead in series with vdd can help prevent noise from other board sources - value of decoup ling capacitor is frequency depen d- ant. typical values to use are 0.1 ? f for designs using frequencies < 50mhz and 0.01 ? f for designs u s ing frequencies > 50mhz. t y p i c a l c m o s t e r m i n a t i o n p l a c e s e r i e s r e s i s t o r a s c l o s e a s p o s s i b l e t o c m o s o u t p u t c m o s o u t p u t b u f f e r ( t y p i c a l b u f f e r i m p e d a n c e 2 0 ? ? ? t o c m o s i n p u t 5 0 ? l i n e c o n n e c t a 3 3 ? ? s e r i e s r e s i s t o r a t e a c h o f t h e o u t p u t c l o c k s t o e n h a n c e t h e s t a b i l i t y o f t h e o u t p u t s i g n a l
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 4 absolute m axim um conditions supply voltage to ground potenti al ...... C 0.5v to 4.6v dc input voltage ............................ v ss C 0.5v to 4.6v storage temperature .......................... C 65c to 150c junction temperature ................................ ..... 150c static discharge voltage (per mil - std - 883, method 3015) .. > 2000v operating conditions description param e ter min max unit supply v oltage v dd 2.25 3.63 v load capacitance, <100 mhz, 3.3v c l [ 4 ] C 30 pf load capacitance, <100 mhz, 2.5v with high drive C 30 pf load capacitance, <133.3 mhz, 3.3v C 22 pf load capacitance, <133.3 mhz, 2.5v with high drive C 22 pf load capacitance, < 133.3 mhz, 2.5v with standard drive C 15 pf load capacitance, >133.3 mhz, 3.3v C 15 pf load capacitance, >133.3 mhz, 2.5v with high drive C 15 pf input capacitance [ 5 ] c in C 5 pf closed - loop bandwidth (typical), 3.3v bw 1 mhz closed - loop bandwidth ( typical), 2.5v 0.5 mhz output impedance (typical), 3.3v high d rive r out 23 ? output impedance (typical), 3.3v standard d rive 33 ? output impedance (typical), 2.5v high d rive 26 ? output impedance (typical), 2.5v standard d rive 39 ? power - up time for all v dd s to reach minimum specified vol t age (power ramps must be monotoni c) t pu 0.01 2 50 ms notes: 4. applies to test circuit #1. 5. applies to both ref clock and internal feedback path on clkout. 6. theta ja, eia jedec 51 test board conditions, 2s2p; theta jc mil - spec 883e method 1012.1.
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 5 3.3v dc electrical specifications descri ption parameter test conditions min max unit supply voltage v dd 2.97 3.6 3 v input low voltage v il C 0.8 v input high voltage v ih 2.5 v dd + 0.3 v input leakage current i il 0 < v in < v il C 10 a input high current i ih v in = v dd C 100 a output low voltage v ol i ol = 8 ma ( s tandard d rive) i ol = 12 m a (high d rive) C C 0.4 0.4 v v output high voltage v oh i oh = C 8 ma (standard drive) i oh = C 12 ma (high d rive) 2.4 2.4 C C v v supply current i dd unloaded outputs, 66 - mhz ref C 45 ma 2.5v dc electrical specifications description param e ter test conditions min max unit supply voltage v dd 2. 25 2.7 5 v input low voltage v il C 0.7 v input high voltage v ih 1.7 v dd + 0.3 v input leakage current i il 0 ( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 6 3.3v and 2.5v ac electrical specifications descri p tion parameter test conditions min typ max unit maximum fr e quency [ 7 ] (i n put/output) 1/t 1 3.3v high d rive 10 C 220 mhz 3.3v standard d rive 10 C 167 mhz 2.5v high d rive 10 C 200 mhz 2.5v s tandard d rive 10 C 134 mhz input duty cycle (pll mode only) t idc <133.3 mhz 25 C 75 % >133.3 mhz 40 C 60 % output duty c y cle [ 8 ] t 2 t 1 <133.3 mhz 47 C 53 % >133.3 mhz 45 C 55 % rise, fall time (3.3v) [8 ] t 3 ,t 4 standard d rive, cl = 30 pf, <100 mhz C 1.6 C ns standard d rive, cl = 22 pf, <133.3 mhz C 1.6 C ns standard d rive, cl = 15 pf, <167 mhz C 0.6 C ns high d rive, cl = 30 pf, <100 mhz C 1.2 C ns high d rive, cl = 22 pf, <133.3 mhz C 1.2 C ns high d rive, cl = 15 pf, >133.3 mhz C 0.5 C ns rise, fall time (2.5v) [8 ] t 3 , t 4 standard d rive, cl = 15 pf, <133.33 mhz C 1.5 C ns high d rive, cl = 30 pf, <100 mhz C 2.1 C ns high d rive, cl = 22 pf, <133.3 mhz C 1.3 C ns high d rive, cl = 15 pf, >133.3 mhz C 1.2 C ns output to output skew [8 ] t 5 all outputs equally loaded C C 100 ps delay, ref rising edge to clkout rising edge [8 ] t 6 pll enabled @ 3.3v C 100 C 100 ps pll enabled @2.5v C 200 C 200 ps part to part skew [8 ] t 7 measured at v dd /2. any output to any output, 3.3v supply C C 150 ps measured at v dd /2. any output to any output, 2.5v supply C C 300 ps pll lock time [8 ] t lock stable power supply, valid clocks pr e- sented on ref and clkout pins C C 1.0 ms cycle - to - c ycle jitter, peak [8 , 9 ] t jcc 3.3v, >66 mhz, <15 pf C C 55 ps 3.3 v, >66 mhz, <30 pf, standard. d rive C C 125 ps 3.3v, >66 mhz, <30 pf, h igh d rive C C 100 ps 2.5v, >66 mhz, <15 pf, standard. d rive C C 95 ps 2.5v, >66 mhz, <15 pf, h igh d rive C C 65 ps 2.5v, >66 mhz, <30 pf, h igh d rive C C 145 ps
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 7 3.3v and 2. 5v ac electrical specifications (continued) descri p tion parameter test conditions min typ max unit period ji t ter, peak [8 ,9 ] t per 3.3v, 66 C 100 mhz, <15 pf C C 75 ps 3.3v, >100 mhz, <15 pf C C 45 ps 3.3v, >66 mhz, <30 pf, standard d rive C C 100 ps 3.3v, >66 mhz, <30 pf, h igh d rive C C 70 ps 2.5v, >66 mhz, <15 pf, standard. d rive C C 60 ps 2.5v, 66 C 100 mhz, <15 pf, h igh d rive C C 60 ps 2.5v, >100 mhz, <15 pf, h igh d rive C C 45 ps notes: 7 . for the given maximum loading conditions. see c l in operating conditions table. 8 . parameter is guaranteed by design and characterization. not 100% tested in production. 9 . typical j itter is measured at 3.3v or 2.5v, 29 c, with all outputs driven into the maximum spec i fied load.
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 8 switching wavefo rms vdd/2 v dd /2 t 2 t 1 t 3 t 4 vdd/2 input t 6 clkout vdd/2 vdd/2 output t 5 output vdd/2 vdd/2 any output, part 1 or 2 1 t 7 vdd/2 duty cycle ti m ing all outputs rise/fall time output - output skew input - output propagation delay device - device skew 0v 3.3v (2.5v) 2.0v(1.8v) output 0.8v(0.6v) any output, part 1 or 2 1 0.8v(0.6v) 2 .0v(1.8v)
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 9 test circuits package drawings ( green package com pliant) vdd vdd gnd gnd outputs c l oad clk 0.1 ? f 0.1 ? f test circuit #1 c l a 16 pin narrow sop , tssop ( mm ) sop tssop symbol min . max . min . max . a 1 . 35 1 . 75 - 1 . 20 a 1 0 . 10 0 . 25 0 . 05 0 . 15 b 0 . 33 0 . 51 0 . 19 0 . 30 c 0 . 19 0 . 25 0 . 09 0 . 20 d 9 . 80 10 . 00 4 . 90 5 . 10 e 3 . 80 4 . 00 4 . 30 4 . 50 h 5 . 80 6 . 20 6 . 40 bsc l 0 . 40 1 . 27 0 . 45 0 . 75 e 1 . 27 bsc 0 . 65 bsc e h d a 1 e b
( preliminary ) pl 123e - 09 low skew zero delay buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 12 / 13 /11 page 10 ordering inform ation micrel inc., reserves the right to make changes in its products or specifications, o r both at any time without notice. the information furnished by micrel is believed to be accurate and reliable. however, micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : micrels products are not authorized for use as critical components in life support devices or systems without the express written approval of the president o f micrel inc. for part ordering, please contact our sales depa rtment: 2 1 80 fortune drive , san jose, ca 95131 , usa tel: (408) 944 - 0800 fax: (408) 474 - 1 000 part number the order number for this device is a combination of the following: device number, package type and operating temperature range part/order nu m ber marking package option pl123e - 09 o c p123e09 oc lllll 16 - pin tssop tube pl123e - 09 o c - r 16 - pin tssop (tape and reel) pl123e - 09hoc p123e09h oc lllll 16 - pin tssop tube pl123e - 09hoc - r 16 - pin tssop (tape and reel) pl123e - 09 s c p123e09 sc lllll 16 - pin sop tube pl123e - 09 s c - r 16 - pin sop (tape and reel) pl123e - 09hsc p123e09h sc lllll 16 - pin sop tube pl123e - 09hsc - r 16 - pin sop (tape and reel) pl123e - 09 o i p123e09 oi lllll 16 - pin tssop tube pl123e - 09 o i - r 16 - pin tssop (tape and r eel) pl123e - 09hoi p123e09h oi lllll 16 - pin tssop tube pl123e - 09hoi - r 16 - pin tssop (tape and reel) pl123e - 09 s i p123e09 si lllll 16 - pin sop tube pl123e - 09 s i - r 16 - pin sop (tape and reel) pl123e - 09hsi p123e09h si lllll 16 - pin sop tube pl123e - 09hsi - r 1 6 - pin sop (tape and reel) *note: lll ll designates lot number p l 1 2 3 e - 0 9 ( h ) x x - x p a r t n u m b e r h = h i g h d r i v e n o n e = s t a n d a r d d r i v e p a c k a g e t y p e o = t s s o p s = s o p n o n e = t u b e s r = t a p e & r e e l t e m p e r a t u r e r a n g e c = c o m m e r c i a l ( 0 c t o 7 0 c ) i = i n d u s t r i a l ( - 4 0 c t o 8 5 c )
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