107 tm march 1997 hd-6402/883 cmos universal asynchronous receiver transmitter (uart) features ? this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. ? 8.0mhz operating frequency (hd-6402/883b) ? 2.0mhz operating frequency (hd-6402/883r) ? low power cmos design ? programmable word length, stop bits and parity ? automatic data formatting and status generation ? compatible with industry standard uarts ? single +5v power supply ? cmos/ttl compatible inputs description the hd-6402/883 is a cmos uart for interfacing comput- ers or microprocessors to an asynchronous serial data chan- nel. the receiver converts serial start, data, parity and stop bits. the transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. the data word length can be 5, 6, 7 or 8 bits. parity may be odd or even. parity checking and generation can be inhibited. the stop bits may be one or two or one and one-half when trans- mitting 5-bit code. the hd-6402/883 can be used in a wide range of applica- tions including modems, printers, peripherals and remote data acquisition systems. utilizing the intersil advanced scaled saji iv cmos process permits operation clock fre- quencies up to 8.0mhz (500k baud). power requirements, by comparison, are reduced from 300mw to 10mw. status logic increases flexibility and simplifies the user interface. pinout hd-6402/883 (cerdip) top view ordering information package temperature range 2mhz = 125k baud 8mhz = 500k baud pkg. no. cerdip -55 o c to +125 o c hd1-6402r/883 hd1-6402b/883 f40.6 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 vcc nc gnd rrd rbr8 rbr7 rbr6 rbr5 rbr4 rbr3 rbr2 rbr1 pe fe oe sfd rrc drr dr rri 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 trc epe cls1 cls2 sbs pi crl tbr8 tbr7 tbr6 tbr5 tbr4 tbr3 tbr2 tbr1 tro tre tbrl tbre mr fn2953.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
108 control definition control word character format cls 2 cls 1 pi epe sbs start bit data bits parity bit stop bits 0000015odd1 0000115odd1.5 0001015 even 1 0001115 even 1.5 001x015none1 001x115none1.5 0100016odd1 0100116odd2 0101016 even 1 0101116 even 2 011x016none1 011x116none2 1000017odd1 1000117odd2 1001017 even 1 1001117 even 2 101x017none1 101x117none2 1100018odd1 1100118odd2 1101018 even 1 1101118 even 2 111x018none1 111x118none2 hd-6402/883
109 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage applied. . . . . gnd -0.5v to v cc +0.5v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . +300 o c esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 typical derating factor . . . . . . . . . . . 1ma/mhz increase in iccop thermal resistance ja jc cerdip package . . . . . . . . . . . . . . . . 50 o c/w 12 o c/w gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range . . . . . . . . . . . . . . . .-55 o c to +125 o c table 1. hd-6402/883 d.c. electrical performance specifications device guaranteed and 100% tested d.c. parameter symbol conditions group a subgroups temperature limits units min max logical ??1?? input voltage vih vcc = 5.5v 1, 2, 3 -55 o c t a +125 o c2.3 - v logical ??0?? input voltage vil vcc = 4.5v 1, 2, 3 -55 o c t a +125 o c- 0.8 v input leakage current iid vin = gnd or vcc, vcc = 5.5v 1, 2, 3 -55 o c t a +125 o c-1.0 1.0 a logical ??1?? output voltage voh ioh = -2.5ma, vcc = 4.5v (note 1) 1, 2, 3 -55 o c t a +125 o c3.0 - v logical ??1?? output voltage voh ioh = -100 a vcc = 4.5v (note 1) 1, 2, 3 -55 o c t a +125 o cvcc -0.4 -v logical ??0?? output voltage vol iol = +2.5ma, vcc = 4.5v (note 1) 1, 2, 3 -55 o c t a +125 o c- 0.4 v output leakage current io vo = gnd or vcc, vcc = 5.5v 1, 2, 3 -55 o c t a +125 o c-1.0 1.0 a standby supply current iccsb vin = gnd or vcc; vcc = 5.5v, output open 1, 2, 3 -55 o c t a +125 o c- 100 a table 2. hd-6402/883 a.c. electrical performance specifications device guaranteed and 100% tested a.c. parameter symbol (note 1) conditions group a subgroups temperature limits hd-6402/883r limits hd-6402/883b units min max min max clock frequency (1) fclock vcc = 4.5v cl = 50pf 9, 10, 11 -55 o c t a +125 o c - 2.0 - 8.0 mhz pulse widths, crl, drr , tbrl (2) tpw 9, 10, 11 -55 o c t a +125 o c150 - 75 - ns pulse width mr (3) tmr 9, 10, 11 -55 o c t a +125 o c 150 - 150 - ns input data setup time (4) tset 9, 10, 11 -55 o c t a +125 o c50 - 20 - ns input data hold time (5) thold 9, 10, 11 -55 o c t a +125 o c60 - 20 - ns output enable time (6) ten 9, 10, 11 -55 o c t a +125 o c - 160 - 35 ns note: 1. interchanging of force and sense conditions is permitted. 2. tested with input levels of vih = 2.76v and vil = 0.4v. rise and fall times are driven at 1ns/v. hd-6402/883
110 table 3. hd-6402/883 electrical performance specifications a.c. parameter symbol conditions notes temperature limits units min max input capacitance cin f = 1mhz all measurements are referenced to device gnd 1t a = +25 o c-25.0pf output capacitance co 1 t a = +25 o c-25.0pf operating supply current iccop vcc = 5.5v, clock freq. = 2mhz, vin = vcc or gnd, outputs open 1-55 o c t a +125 o c- 2.0 ma note: 1. the parameters listed in table 3 are controlled via design or process parameters and are not directly tested. these parameter s are char- acterized upon initial design and after major process and/or design changes. table 4. applicable subgroups conformance groups method subgroups initial test 100%/5004 - interim test 100%/5004 1, 7, 9 pda 100% 1 final test 100% 2, 3, 8a, 8b, 10, 11 group a - 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group c and d samples/5005 1, 7, 9 hd-6402/883
111 burn-in circuits hd-6402/883 cerdip notes: 1. vcc = 5.5v 0.5v 2. f0 = 100khz 10% 3. r1 = 47k ? , 1/4w 10% 4. c = 0.01 f minimum 5. one socket per board should not be loaded, but rather have pin 24 go the ?c? of the 4011. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 1 2 3 4 5 6 7 14 13 12 11 10 9 8 4011 quad nand gate vcc r1 r1 vcc dip hd-6402/883 detail detail a b b a a a a a a a a a a a a a a b a r1 r1 r1 vcc f0 gnd gnd gnd c r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 gnd f0 vcc vcc vcc vcc gnd gnd vcc gnd vcc gnd vcc gnd vcc gnd (note 5) note: one per board vcc c c (note 5) f0 hd-6402/883
112 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com die characteristics die dimensions: 126.4 mils x 134.3 mils x 19 mils metallization: type: si-al thickness: 10k ? - 12k ? glassivation: type: sio 2 thickness: 7k ? - 9k ? worst case current density: 1.42 x 10 5 a/cm 2 metallization mask layout hd-6402/883 rbr7 rbr6 rbr5 rbr4 rbr3 rbr2 rbr1 pe fe oe sfd pi crl tbr8 tbr7 tbr6 tbr5 tbr4 tbr3 tbr2 tbr ro rbr8 rrd gnd nc vcc trc epe cls1 cls2 sbs rrc drr dr rri mr tbre tbrl tre hd-6402/883
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