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mb95810k series new 8fx 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04694 rev. *a revised march 29, 2016 the mb95810k series is a series of general-purpose, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers of these series cont ain a variety of peripheral resources. features f 2 mc-8fx cpu core ? instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test bran ch instructions ? bit manipulation instructions, etc. clock ? selectable main clock source ? main oscillation clock (up to 16.25 mhz, maximum ma- chine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (4 mhz ? 2%) ? main cr pll clock - the main cr pll clock frequency becomes 8 mhz ? 2% when the pll multiplication rate is 2. - the main cr pll clock frequency becomes 10 mhz ? 2% when the pll multiplication rate is 2.5. - the main cr pll clock frequency becomes 12 mhz ? 2% when the pll multiplication rate is 3. - the main cr pll clock frequency becomes 16 mhz ? 2% when the pll multiplication rate is 4. ? selectable subclock source ? suboscillation clock (32.768 khz) ? external clock (32.768 khz) ? sub-cr clock (typ: 100 khz, min: 50 khz, max: 150 khz) timer ? 8/16-bit composite timer ? 2 channels ? 8/16-bit ppg ? 2 channels ? 16-bit ppg timer ? 2 channels ? 16-bit reload timer ? 1 channel ? time-base timer ? 1 channel ? watch prescaler ? 1 channel uart/sio ? 1 channel ? full duplex double buffer ? capable of clock asynchronous (uart) serial data transfer and clock synchronous (sio) serial data transfer i 2 c bus interface ? 1 channel ? built-in wake-up function lin-uart ? full duplex double buffer ? capable of clock asynchronous serial data transfer and clock synchronous serial data transfer external interrupt ? 12 channels ? interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ? can be used to wake up the device from different low power consumption (standby) modes 8/10-bit a/d converter ? 12 channels ? 8-bit or 10-bit resolution can be selected. low power consumption (standby) modes ? there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode ? in standby mode, two further options can be selected: normal standby mode and deep standby mode. i/o port (no. of i/o ports: 58) ? general-purpose i/o ports (cmos i/o): 54 ? general-purpose i/o ports (n-ch open drain): 4 on-chip debug ? 1-wire serial control ? serial writing supported (asynchronous mode) hardware/software watchdog timer ? built-in hardware watchdog timer ? built-in software watchdog timer power-on reset ? a power-on reset is generated when the power is switched on. low-voltage detection (lvd) reset circuit ? the lvd function is enabled by default. for det ails, see ?18.2 recommended operating conditions? in ?electrical characteristics?. ? the lvd function can be controlled through software. ? the lvd reset circuit control register (lvdcc) enables or disables the lvd reset. ? the lvd reset circuit has an internal low-voltage detector. the combination of detection voltage and release voltage can be selected from four options. comparator ? 2 channels ? built-in dedicated bgr ? the comparator reference volt age can be selected between the bgr voltage and the comparator pin. clock supervisor counter ? built-in clock su pervisor counter dual operation flash memory ? the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simul- taneously. flash memory security function ? protects the content of the flash memory.
mb95810k series document number: 002-04694 rev. *a page 2 of 121 contents features............................................................................. 1 1. product line-up ............................................................ 3 2. packages and corresponding products.................... 5 3. differences among pr oducts and notes on product selection ............................................................. 5 4. pin assignment ............................................................ 6 5. pin functions................................................................ 7 6. i/o circuit type ........................................................... 11 7. handling precaution s............ .............. .............. ......... 13 7.1 precautions for product design........................... 13 7.2 precautions for package mounting ..................... 14 7.3 precautions for use environment........................ 16 8. notes on device handling......................................... 16 9. pin connection ........................................................... 17 10. block diagram .......................................................... 19 11. cpu core................................................................... 20 12. memory space .......................................................... 21 12.1 i/o area (addresses: 0x 0000 to 0x007f)........... 21 12.2 extended i/o area (addresses: 0x0f80 to 0x0fff ) ................................ 21 12.3 data area...................... ..................................... 21 12.4 program area ............... ..................................... 21 12.5 memory space map........................................... 22 13. areas for specific applicat ions ...... .............. ......... 23 14. i/o map....................................................................... 24 15. i/o ports..................................................................... 30 15.1 port 0................................................................. 31 15.2 port 1................................................................. 34 15.3 port 2................................................................. 39 15.4 port 3................................................................. 42 15.5 port 4................................................................. 48 15.6 port 5................................................................. 51 15.7 port 6................................................................. 55 15.8 port 7................................................................. 60 15.9 port 8................................................................. 63 15.10 port e .............................................................. 66 15.11 port f............................................................... 69 15.12 port g .............................................................. 72 16. interrupt source table ............................................. 74 17. pin states in each mode .......................................... 75 18. electrical characteristics... ...................................... 78 18.1 absolute maximum rating s............................... 78 18.2 recommended operating conditions ............... 80 18.3 dc characteristics ......... ................................... 81 18.4 ac characteristics.......... ................................... 84 18.5 a/d converter............. .................................... 104 18.6 flash memory program/erase characteristics 108 19. sample characteristics...... .................................... 109 20. ordering information.............................................. 116 21. package dimension. .............. .............. .............. ..... 117 22. major changes in this edition .............................. 119 document history page .............. ................................. 120 sales, solutions, and legal information .................... 121
mb95810k series document number: 002-04694 rev. *a page 3 of 121 1. product line-up part number parameter mb95f814k mb95f816k mb95f818k type flash memory product clock supervisor counter it supervises the main clock osc illation and the subclock oscillation. flash memory capacity 20 kbyte 36 kbyte 60 kbyte ram capacity 512 bytes 1 kbyte 2 kbyte power-on reset yes low-voltage detection reset controlled through software reset input selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o port : 58 ?cmos i/o :54 ? n-ch open drain : 4 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be us ed as the source clock of the software watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? both clock synchronous serial data transfer and cl ock asynchronous serial data transfer are enabled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 12 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? it has the following functions: interval timer func tion, pwc function, pwm fu nction and input capture function. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? it can output square wave. external interrupt 12 channels ? interrupt by edge detection (the rising edge, falling edge, a nd both edges can be selected.) ? it can be used to wake up the device from different standby modes.
mb95810k series document number: 002-04694 rev. *a page 4 of 121 on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode). uart/sio 1 channel ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data leng th (5/6/7/8 bits), an in ternal baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-first data transfer are available to use. ? both clock asynchronous (uart) serial data transfe r and clock synchronous (sio) serial data transfer are enabled. i 2 c bus interface 1 channel ? master/slave transmission and receiving ? it has the following functions: bus error function, arbitration function, transmission direction detection function, wake-up function, and functions of generating and dete cting repeated start conditions. 8/16-bit ppg 2 channels ? each channel can be used as an ?8-bit timer ? 2 channels? or a ?16-bit timer ? 1 channel?. ? the counter operating clock can be selected from eight clock sources. 16-bit ppg timer 2 channels ? pwm mode and one-shot mode are available to use. ? the counter operating clock can be selected from eight clock sources. ? it supports external trigger start. 16-bit reload timer 1 channel ? two clock modes and two counter operating modes are available to use. ? it can output square wave. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? two counter operating modes: reload mode and one-shot mode watch counter ? count clock: it can be selected from eight clock sources from the watch prescaler. ? the counter value can be selected from 0 to 63. (the watch counter can count for one minute when the clock source of one second is selected and 60 is selected as the counter value.) watch prescaler eight different time intervals can be selected. comparator 2 channels the reference voltage of each channel can be select ed between the bgr voltage and the comparator pin. flash memory ? it supports automatic programming (embedded al gorithm), and program/erase/erase-suspend/erase- resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory part number parameter mb95f814k mb95f816k mb95f818k number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
mb95810k series document number: 002-04694 rev. *a page 5 of 121 2. packages and corresponding products ? : available 3. differences am ong products and notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash program/erase. for details of current consumption, see ?electrical characteristics?. ? package for details of information on each package, see ?package s and corresponding products ? and ?package dimension?. ? operating voltage the operating voltage varies, depending on whet her the on-chip debug function is used or not. for details of operating voltage, see ?electrical characteristics?. ? on-chip debug function the on-chip debug function requires that v cc , v ss and one serial wire be connected to an evaluation tool. for details of the connection method, refer to ?chapter 25 example of serial programming conn ection? in ?new 8fx mb95810k series hardware manual?. standby mode there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode in standby mode, two further options can be sele cted: normal standby mode and deep standby mode package fpt-64p-m38 fpt-64p-m39 part number package mb95f814k mb95f816k mb95f818k fpt-64p-m38 ??? fpt-64p-m39 ??? part number parameter mb95f814k mb95f816k mb95f818k
mb95810k series document number: 002-04694 rev. *a page 6 of 121 4. pin assignment *: trg0 and adtg can be mapp ed to either p13 or p83 by using the sysc register. avr pe3/int13 pe2/int12 pe1/int11 pe0/int10 p83/trg0*/adtg* p82 p81 p80 p71/ti0 p70/to0 (top view) lqfp64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avcc pf0/x0 pf1/x1 vss p72 c pg2/x1a pg1/x0a pf2/rst p00/int00 p01/int01 p02/int02 vcc p04/int04 p05/int05 p06/int06 p07/int07 p10/ui0 p11/uo0 p12/dbg p03/int03 p64/ec1 p63/to11 p62/to10 p61/ppg11 p60/ppg10 p53/trg1 p52/ppg1 p51/sda0 48 47 46 45 44 43 42 41 40 39 38 33 34 35 36 37 p24/ec0 p23/to01 p22/to00 p21/ppg01 p20/ppg00 p14/ppg0 p13/uck0/trg0*/adtg* p50/scl0 p30/an00/cmp0_n p31/an01/cmp0_p p32/an02/cmp0_o p33/an03/cmp1_n p34/an04/cmp1_p p35/an05/cmp1_o p36/an06 p37/an07 avss p40/an08 p41/an09 p42/an10 p43/an11 p67/sin p66/sot p65/sck (fpt-64p-m38) (fpt-64p-m39)
mb95810k series document number: 002-04694 rev. *a page 7 of 121 5. pin functions pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3 1av cc ? analog power supply pin for 8/10-bit a/d converter ???? 2avr? reference input pin for 8/10-bit a/d converter ???? 3 pe3 f general-purpose i/o port hysteresis cmos ? ? int13 external interrupt input pin 4 pe2 f general-purpose i/o port hysteresis cmos ? ? int12 external interrupt input pin 5 pe1 f general-purpose i/o port hysteresis cmos ? ? int11 external interrupt input pin 6 pe0 f general-purpose i/o port hysteresis cmos ? ? int10 external interrupt input pin 7 p83 f general-purpose i/o port hysteresis cmos ? ? trg0* 4 16-bit ppg timer ch. 0 trigger input pin adtg* 4 8/10-bit a/d converter trigger input pin 8 p82 f general-purpose i/o port hysteresis cmos ? ? 9 p81 f general-purpose i/o port hysteresis cmos ? ? 10 p80 f general-purpose i/o port hysteresis cmos ? ? 11 p71 f general-purpose i/o port hysteresis cmos ? ? ti0 16-bit reload timer ch. 0 input pin 12 p70 f general-purpose i/o port hysteresis cmos ? ? to0 16-bit reload timer ch. 0 output pin 13 p72 f general-purpose i/o port hysteresis cmos ? ? 14 pf0 b general-purpose i/o port hysteresis cmos ?? x0 main clock input oscillation pin 15 pf1 b general-purpose i/o port hysteresis cmos ?? x1 main clock i/o oscillation pin 16 v ss ? power supply pin (gnd) ? ? ? ? 17 v cc ? power supply pin ? ? ? ? 18 c ? decoupling capacitor connection pin ? ? ? ? 19 pg2 c general-purpose i/o port hysteresis cmos ? ? x1a subclock i/o oscillation pin 20 pg1 c general-purpose i/o port hysteresis cmos ? ? x0a subclock input oscillation pin 21 pf2 a general-purpose i/o port hysteresis cmos ? ? rst reset pin
mb95810k series document number: 002-04694 rev. *a page 8 of 121 22 p00 d general-purpose i/o port hysteresis cmos ? ? int00 external interrupt input pin 23 p01 d general-purpose i/o port hysteresis cmos ? ? int01 external interrupt input pin 24 p02 d general-purpose i/o port hysteresis cmos ? ? int02 external interrupt input pin 25 p03 d general-purpose i/o port hysteresis cmos ? ? int03 external interrupt input pin 26 p04 d general-purpose i/o port hysteresis cmos ? ? int04 external interrupt input pin 27 p05 d general-purpose i/o port hysteresis cmos ? ? int05 external interrupt input pin 28 p06 d general-purpose i/o port hysteresis cmos ? ? int06 external interrupt input pin 29 p07 d general-purpose i/o port hysteresis cmos ? ? int07 external interrupt input pin 30 p10 i general-purpose i/o port cmos cmos ? ? ui0 uart/sio ch. 0 data input pin 31 p11 f general-purpose i/o port hysteresis cmos ? ? uo0 uart/sio ch. 0 data output pin 32 p12 g general-purpose i/o port hysteresis cmos ? ? dbg dbg input pin 33 p13 f general-purpose i/o port hysteresis cmos ? ? uck0 uart/sio ch. 0 clock i/o pin trg0* 4 16-bit ppg timer ch. 0 trigger input pin adtg* 4 8/10-bit a/d converter trigger input pin 34 p14 f general-purpose i/o port hysteresis cmos ? ? ppg0 16-bit ppg timer ch. 0 output pin 35 p20 f general-purpose i/o port hysteresis cmos ? ? ppg00 8/16-bit ppg ch. 0 output pin 36 p21 f general-purpose i/o port hysteresis cmos ? ? ppg01 8/16-bit ppg ch. 0 output pin 37 p22 f general-purpose i/o port hysteresis cmos ? ? to00 8/16-bit composite timer ch. 0 output pin 38 p23 f general-purpose i/o port hysteresis cmos ? ? to01 8/16-bit composite timer ch. 0 output pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95810k series document number: 002-04694 rev. *a page 9 of 121 39 p24 f general-purpose i/o port hysteresis cmos ? ? ec0 8/16-bit composite timer ch. 0 clock input pin 40 p50 h general-purpose i/o port cmos cmos ? ? scl i 2 c bus interface ch. 0 clock i/o pin 41 p51 h general-purpose i/o port cmos cmos ? ? sda i 2 c bus interface ch. 0 data i/o pin 42 p52 f general-purpose i/o port hysteresis cmos ? ? ppg1 16-bit ppg timer ch. 1 output pin 43 p53 f general-purpose i/o port hysteresis cmos ? ? trg1 16-bit ppg timer ch. 1 trigger input pin 44 p60 f general-purpose i/o port hysteresis cmos ? ? ppg10 8/16-bit ppg ch. 1 output pin 45 p61 f general-purpose i/o port hysteresis cmos ? ? ppg11 8/16-bit ppg ch. 1 output pin 46 p62 f general-purpose i/o port hysteresis cmos ? ? to10 8/16-bit composite timer ch. 1 output pin 47 p63 f general-purpose i/o port hysteresis cmos ? ? to11 8/16-bit composite timer ch. 1 output pin 48 p64 f general-purpose i/o port hysteresis cmos ? ? ec1 8/16-bit composite timer ch. 1 clock input pin 49 p65 f general-purpose i/o port hysteresis cmos ? ? sck lin-uart clock i/o pin 50 p66 f general-purpose i/o port hysteresis cmos ? ? sot lin-uart data output pin 51 p67 i general-purpose i/o port cmos cmos ? ? sin lin-uart data input pin 52 p43 e general-purpose i/o port hysteresis/ analog cmos ? ? an11 8/10-bit a/d converter analog input pin 53 p42 e general-purpose i/o port hysteresis/ analog cmos ? ? an10 8/10-bit a/d converter analog input pin 54 p41 e general-purpose i/o port hysteresis/ analog cmos ? ? an09 8/10-bit a/d converter analog input pin 55 p40 e general-purpose i/o port hysteresis/ analog cmos ? ? an08 8/10-bit a/d converter analog input pin pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95810k series document number: 002-04694 rev. *a page 10 of 121 ( ? : available) *1: for the i/o circuit types, see ?i/o circuit type?. *2: n-ch open drain *3: pull-up *4: trg0 and adtg can be mapped to either p13 or p83 by using the sysc register. 56 p37 e general-purpose i/o port hysteresis/ analog cmos ? ? an07 8/10-bit a/d converter analog input pin 57 p36 e general-purpose i/o port hysteresis/ analog cmos ? ? an06 8/10-bit a/d converter analog input pin 58 p35 e general-purpose i/o port hysteresis/ analog cmos ? ? an05 8/10-bit a/d converter analog input pin cmp1_o comparator ch. 1 digital output pin 59 p34 e general-purpose i/o port hysteresis/ analog cmos ? ? an04 8/10-bit a/d converter analog input pin cmp1_p comparator ch. 1 non-inverting analog input (positive input) pin 60 p33 e general-purpose i/o port hysteresis/ analog cmos ? ? an03 8/10-bit a/d converter analog input pin cmp1_n comparator ch. 1 inverting analog input (negative input) pin 61 p32 e general-purpose i/o port hysteresis/ analog cmos ? ? an02 8/10-bit a/d converter analog input pin cmp0_o comparator ch. 0 digital output pin 62 p31 e general-purpose i/o port hysteresis/ analog cmos ? ? an01 8/10-bit a/d converter analog input pin cmp0_p comparator ch. 0 non-inverting analog input (positive input) pin 63 p30 e general-purpose i/o port hysteresis/ analog cmos ? ? an00 8/10-bit a/d converter analog input pin cmp0_n comparator ch. 0 inverting analog input (negative input) pin 64 av ss ? 8/10-bit a/d converter power supply pin (gnd) ???? pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3
mb95810k series document number: 002-04694 rev. *a page 11 of 121 6. i/o circuit type type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx. 5 m ? ? cmos output ? hysteresis input ? pull-up control n-ch reset output / digital output reset input / hysteresis input standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
mb95810k series document number: 002-04694 rev. *a page 12 of 121 type circuit remarks d ? cmos output ? hysteresis input ? pull-up control ? high current output e ? cmos output ? hysteresis input ? pull-up control ? analog input f ? cmos output ? hysteresis input ? pull-up control g ? n-ch open drain output ? hysteresis input h ? n-ch open drain output ?cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch standby control hysteresis input digital output n-ch digital output standby control cmos input
mb95810k series document number: 002-04694 rev. *a page 13 of 121 7. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failu re is greatly affected by the conditions in which they are used (circuit conditions, enviro nmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability fr om your cypress semiconductor devices. 7.1 precautions for product design this section describes precautions when designing electronic equipment usin g semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (v oltage, current, temperature, etc.) in excess of certain established limits, called abso lute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warran ted when operated within these ranges. always use semiconductor devices wit hin the recommended operating conditio ns. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating condit ions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative before- hand. ? processing and protection of pins these precautions must be followed when handling the pi ns which connect semiconductor devices to power supply and input/output functions. (1) preventing over-voltage and over-current conditions exposure to voltage or current levels in excess of maxi mum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over-current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present fo r extended periods of ti me can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. i ? cmos output ?cmos input ? pull-up control type circuit remarks n-ch p-ch p-ch r pull-up control digital output digital output standby control cmos input
mb95810k series document number: 002-04694 rev. *a page 14 of 121 ? latch-up semiconductor devices are cons tructed by the formation of p-type and n-ty pe areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junc tions (called thyristor struct ures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch-up. caution: the occurrence of latch-up not only causes lo ss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power-on sequence. ? observance of safety regulations and standards most countries in the world have established standards an d regulations regarding safety, protection from electromag- netic interference, etc. customers are requested to obse rve applicable regulations an d standards in the design of products. ? fail-safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by in corporating safety design measures into your facility and equipment su ch as redundancy, fire protection, and prevention of over-current le vels and other abnormal operating conditions. ? precautions related to usage of devices cypress semiconductor devices are intended for use in sta ndard applications (computers, office automation and other office equipment, industrial, communications, and measur ement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy co ntrols, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to co nsult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 7.2 precautions for package mounting package mounting may be either lead insertion type or surf ace mount type. in either case, for heat resistance during soldering, you should only mount under cypress?s recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed ci rcuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally in volves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applyi ng liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting.
mb95810k series document number: 002-04694 rev. *a page 15 of 121 ? surface mount type surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open conn ections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting tec hniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for ea ch product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. ? lead-free packaging caution: when ball grid ar ray (bga) packages with sn-ag-cu balls are mounted using sn-pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natu ral environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and ca using packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, cypress packages se miconductor devices in highly moisture -resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum lami nate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de-moistu rized by baking (heat drying). follow the cypress recom- mended conditions for baking. condition: 125c/24 h ? static electricity because semiconductor devic es are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humid ity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ? ). wearing of conductive clothing and shoes, use of conduc tive floor mats and other me asures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti-static measures. (5) avoid the use of styrofoam or ot her highly static-prone materials for storage of completed board assemblies.
mb95810k series document number: 002-04694 rev. *a page 16 of 121 7.3 precautions for use environment reliability of semiconductor devices depends on ambien t temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in de vices as well as printed circuit boards. if high humidity levels are anticipated, consider anti-humidity processing. (2) discharge of static electricity when high-voltage charges exis t close to semiconductor devices, discha rges can cause abnormal operation. in such cases, use anti-static measures or processing to prevent discharges. (3) corrosive gase s, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions th at will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are fl ammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in ot her special environmental conditions should consult with sales repres entatives. 8. notes on device handling ? preventing latch-ups when using the device, ensure that the voltage app lied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pi n, or if a voltage out of the rating range of power sup- ply voltage mentioned in ?18.1 absolute maximum ratings? of ?electrical ch aracteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. ? stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctuat es rapidly even though the fl uctuation is within the guar- anteed operating range of the v cc power supply voltage. as a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscilla tion stabilization wait time is required for power-on reset, wake-u p from sub- clock mode or stop mode.
mb95810k series document number: 002-04694 rev. *a page 17 of 121 9. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a component ma y be permanently damaged due to malfunctions or latch- ups. always pull up or pull down an unused input pin through a resistor of at least 2 k ? . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused outp ut pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, preven t malfunctions of strobe signals due to an increase in the ground level, and conform to the total out put current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addit ion, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a cera mic capacitor of approximately 0.1 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. ?dbg pin connect the dbg pin to an external pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not st ay at ?l? level until the reset output is released. the dbg pin becomes a communication pin in debug mode. si nce the actual pull-up resi stance depends on the tool used and the interconnection length, refer to the t ool document when selecting a pull-up resistor. ?rst pin connect the rst pin to an external pull-up resistor of 2 k ? or above. to prevent the device from unintentionally entering the rese t mode due to noise, minimize the interconnection length between a pull-up resistor and the rst pin and that between a pull-up resistor and the v cc pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after po wer-on. in addition, the reset output of the pf2/rst pin can be enabled by the rstoe bit in the sysc register, and the rese t input function and th e general purpose i/o function can be selected by th e rsten bit in the sysc register. ? analog power supply always set the same potential to the av cc pin and the v cc pin. when v cc is larger than av cc , the current may flow through the an00 to an11 pins. ? treatment of power supply pins on the 8/10-bit a/d converter ensure that av cc is equal to v cc and av ss equal to v ss even when the 8/10-bit a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. therefore, connect a ceramic capacitor of 0.1 f (ap- prox.) as a bypass capacitor between the av cc pin and the av ss pin in the vicinity of this device. ?c pin use a ceramic capacitor or a capacitor with equivalent fr equency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, mini mize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board.
mb95810k series document number: 002-04694 rev. *a page 18 of 121 ? note on serial communication in serial communication, reception of wrong data may occur due to noise or other causes. therefore, design a printed circuit board to prevent noise from occurring. taking acco unt of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. if an error is de tected, retransmit the data. c cs dbg rst ? dbg/rst /c pins connection diagram
mb95810k series document number: 002-04694 rev. *a page 19 of 121 10. block diagram reset with lvd dual operation flash with security function (60/36/20 kbyte) f 2 mc-8fx cpu ram (2048/1024/512 bytes) oscillator circuit cr oscillator clock control watch prescaler watch counter on-chip debug wild register external interrupt ch. 0 to ch. 7 interrupt controller internal bus 8/16-bit composite timer ch. 0 8/16-bit composite timer ch. 1 uart/sio i 2 c bus interface ch. 0 16-bit ppg timer ch. 0 8/16-bit ppg ch. 1 port port pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 p00 *3 /int00 to p07 *3 /int07 c lin-uart p10/ui0 p11/uo0 p13/uck0 (p13/trg0 or p83/trg0) p14/ppg0 8/16-bit ppg ch. 0 p20/ppg00 p21/ppg01 p60/ppg10 p61/ppg11 8/10-bit a/d converter (p13/adtg or p83/adtg) p40/an08 to p43/an11 (p30/an00 to p37/an07) avr p50 *1 /scl p51 *1 /sda p12 *1 /dbg p22/to00 p23/to01 p24/ec0 p62/to10 p63/to11 p64/ec1 comparator ch. 0 (p30/cmp0_n) (p31/cmp0_p) (p32/cmp0_o) comparator ch. 1 (p33/cmp1_n) (p34/cmp1_p) (p35/cmp1_o) p65/sck p66/sot p67/sin 16-bit reload timer ch. 0 p70/to0 p71/ti0 external interrupt ch. 8 to ch. 11 pe0/int10 to pe3/int13 p80 to p82 16-bit ppg timer ch. 1 p52/ppg1 p53/trg1 vcc vss avcc avss *1: p12, p50, p51 and pf2 are n-ch open drain pins. *2: software select *3: p00 to p07 are high-current pins. note: pins in parentheses indicate that those pins are shared among different peripheral functions.
mb95810k series document number: 002-04694 rev. *a page 20 of 121 11. cpu core ? memory space the memory space of the mb95810k series is 64 kbyte in size, and consists of an i/o area, an extended i/o area, a data area, and a program area. the memory space includes areas intended for specific purposes such as general- purpose registers and a vector table. the memory maps of the mb95810k series are shown below. ? memory maps mb95f816k mb95f818k mb95f814k i/o area access prohibited ram 512 bytes registers access prohibited extended i/o area access prohibited flash memory 16 kbyte flash memory 4 kbyte 0x0000 0x0080 0x0090 0x0100 0x0200 0x0290 0x0f80 0x1000 0x2000 0xc000 0xffff i/o area access prohibited 0x0000 0x0080 0x0090 i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 0x0490 registers 0x0100 0x0200 access prohibited extended i/o area flash memory 4 kbyte 0x0f80 0x1000 0x2000 extended i/o area 0x0f80 0x1000 access prohibited ram 1 kbyte access prohibited flash memory 32 kbyte 0x8000 0xffff ram 2 kbyte flash memory 60 kbyte 0x0890 0xffff
mb95810k series document number: 002-04694 rev. *a page 21 of 121 12. memory space the memory space of the mb95810k series is 64 kbyte in size, and consists of an i/o area, an extended i/o area, a data area, and a program area. the memory space includes areas for specific applications such as general-pur- pose registers and a vector table. 12.1 i/o area (addresses: 0x0000 to 0x007f) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the i/o area forms part of the memory space, it can be accessed in the same way as the memory. it can also be accessed at high-speed by using direct addressing instructions. 12.2 extended i/o area (addresses: 0x0f80 to 0x0fff) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the extended i/o area forms part of the memory space, it can be accessed in the same way as the memory. 12.3 data area ? static ram is incorporated in the data area as the internal data area. ? the internal ram size varies according to product. ? the ram area from 0x0090 to 0x00ff can be accessed at high-speed by using dire ct addressing instructions. ? in mb95f818k, the area from 0x0090 to 0x047f is an ex tended direct addressing area. it can be accessed at high- speed by direct addressing instruct ions with a direct bank pointer set. ? in mb95f816k, the area from 0x0090 to 0x047f is an ex tended direct addressing area. it can be accessed at high- speed by direct addressing instruct ions with a direct bank pointer set. ? in mb95f814k, the area from 0x0090 to 0x028f is an ex tended direct addressing area. it can be accessed at high- speed by direct addressing instruct ions with a direct bank pointer set. ? the area from 0x0100 to 0x01ff can be used as a general-purpose register area. 12.4 program area ? the flash memory is incorporated in the program area as the internal program area. ? the flash memory size varies according to product. ? the area from 0xffc0 to 0xffff is used as the vector table. ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register.
mb95810k series document number: 002-04694 rev. *a page 22 of 121 12.5 memory space map direct addressing area extended direct addressing area i/o area access prohibited 0x0000 0x0080 0x0090 registers (general-purpose register area) 0x0100 0x0200 0x047f vector table area extended i/o area 0x0f80 0x0fff 0x1000 access prohibited program area data area 0x088f 0x0890 0xffff 0xffc0
mb95810k series document number: 002-04694 rev. *a page 23 of 121 13. areas for spec ific applications the general-purpose register area and vector tabl e area are used for the specific applications. ? general-purpose register area (addresses: 0x0100 to 0x01ff) ? this area contains the auxiliary registers used fo r 8-bit arithmetic opera tions, transfer, etc. ? as this area forms part of the ram area, it can also be used as conventional ram. ? when the area is used as general-pur pose registers, general-purpose regist er addressing enables high-speed ac- cess with short instructions. ? non-volatile register data area (addresses: 0xffbb to 0xffbf) ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register. for details, refer to ?chapter 27 non-volatile register (nvr) interface? in ?new 8fx mb95810k series hardware manual?. ? vector table area (addresses: 0xffc0 to 0xffff) ? this area is used as the vector table for vector call instructions (callv), interrupts, and resets. ? the top of the flash memory area is allocated to the vect or table area. the start address of a service routine is set to an address in the vector table in the form of data. ?interrupt source table? lists the vect or table addresses corresponding to vector call instructions, interrupts, and re- sets. for details, refer to ?chapter 4 reset?, ?chapt er 5 interrupts? and ?a.2 special instruction special in- struction callv #vct? in ?appendix? in ?new 8fx mb 95810k series ha rdware manual?. ? direct bank pointer and access area *1: due to the memory size limit, the available access area is up to ?0x028f? in mb95f814k. *2: due to the memory size limit, the available a ccess area is up to ?0x047f? in mb95f816k/f818k. direct bank pointer (dp[2:0]) operand-specified dir access area 0bxxx (it does not affect mapping.) 0x0000 to 0x007f 0x0000 to 0x007f 0b000 (initial value) 0x0090 to 0x00ff 0x0090 to 0x00ff 0b001 0x0080 to 0x00ff 0x0100 to 0x017f 0b010 0x0180 to 0x01ff 0b011 0x0200 to 0x027f 0b100 0x0280 to 0x02ff* 1 0b101 0x0300 to 0x037f 0b110 0x0380 to 0x03ff 0b111 0x0400 to 0x047f* 2
mb95810k series document number: 002-04694 rev. *a page 24 of 121 14. i/o map address register abbreviation register name r/w initial value 0x0000 pdr0 port 0 data register r/w 0b00000000 0x0001 ddr0 port 0 directio n register r/w 0b00000000 0x0002 pdr1 port 1 data register r/w 0b00000000 0x0003 ddr1 port 1 directio n register r/w 0b00000000 0x0004 ? (disabled) ? ? 0x0005 watr oscillation stabilization wait time setting register r/w 0b11111111 0x0006 pllc pll control register r/w 0b000x0000 0x0007 sycc system clock cont rol register r/w 0bxxx11011 0x0008 stbc standby control register r/w 0b00000000 0x0009 rsrr reset source register r/w 0b000xxxxx 0x000a tbtc time-base timer control register r/w 0b00000000 0x000b wpcr watch prescaler control register r/w 0b00000000 0x000c wdtc watchdog timer control register r/w 0b00xx0000 0x000d sycc2 system clock control register 2 r/w 0bxxxx0011 0x000e pdr2 port 2 data register r/w 0b00000000 0x000f ddr2 port 2 direction register r/w 0b00000000 0x0010 pdr3 port 3 data register r/w 0b00000000 0x0011 ddr3 port 3 directio n register r/w 0b00000000 0x0012 pdr4 port 4 data register r/w 0b00000000 0x0013 ddr4 port 4 directio n register r/w 0b00000000 0x0014 pdr5 port 5 data register r/w 0b00000000 0x0015 ddr5 port 5 directio n register r/w 0b00000000 0x0016 pdr6 port 6 data register r/w 0b00000000 0x0017 ddr6 port 6 directio n register r/w 0b00000000 0x0018 pdr7 port 7 data register r/w 0b00000000 0x0019 ddr7 port 7 directio n register r/w 0b00000000 0x001a pdr8 port 8 data register r/w 0b00000000 0x001b ddr8 port 8 directio n register r/w 0b00000000 0x001c stbc2 standby control register 2 r/w 0b00000000 0x001d to 0x0024 ? (disabled) ? ? 0x0025 pul8 port 8 pull-up register r/w 0b00000000 0x0026 pdre port e data register r/w 0b00000000 0x0027 ddre port e direction register r/w 0b00000000 0x0028 pdrf port f data register r/w 0b00000000
mb95810k series document number: 002-04694 rev. *a page 25 of 121 0x0029 ddrf port f direction register r/w 0b00000000 0x002a pdrg port g data register r/w 0b00000000 0x002b ddrg port g direction register r/w 0b00000000 0x002c pul0 port 0 pull-up register r/w 0b00000000 0x002d pul1 port 1 pull-up register r/w 0b00000000 0x002e pul2 port 2 pull-up register r/w 0b00000000 0x002f pul3 port 3 pull-up register r/w 0b00000000 0x0030 pul4 port 4 pull-up register r/w 0b00000000 0x0031 pul5 port 5 pull-up register r/w 0b00000000 0x0032 pul7 port 7 pull-up register r/w 0b00000000 0x0033 pul6 port 6 pull-up register r/w 0b00000000 0x0034 pule port e pull-up register r/w 0b00000000 0x0035 pulg port g pull-up register r/w 0b00000000 0x0036 t01cr1 8/16-bit composite timer 01 status control register 1 r/w 0b00000000 0x0037 t00cr1 8/16-bit composite timer 00 status control register 1 r/w 0b00000000 0x0038 t11cr1 8/16-bit composite timer 11 status control register 1 r/w 0b00000000 0x0039 t10cr1 8/16-bit composite timer 10 status control register 1 r/w 0b00000000 0x003a pc01 8/16-bit ppg timer 01 control register r/w 0b00000000 0x003b pc00 8/16-bit ppg timer 00 control register r/w 0b00000000 0x003c pc11 8/16-bit ppg timer 11 control register r/w 0b00000000 0x003d pc10 8/16-bit ppg timer 10 control register r/w 0b00000000 0x003e tmcsrh0 16-bit reload timer control st atus register (upper) ch. 0 r/w 0b00000000 0x003f tmcsrl0 16-bit reload timer control st atus register (lower) ch. 0 r/w 0b00000000 0x0040, 0x0041 ? (disabled) ? ? 0x0042 pcnth0 16-bit ppg status control register (upper) ch. 0 r/w 0b00000000 0x0043 pcntl0 16-bit ppg status contro l register (lower) ch. 0 r/w 0b00000000 0x0044 pcnth1 16-bit ppg status control register (upper) ch. 1 r/w 0b00000000 0x0045 pcntl1 16-bit ppg status contro l register (lower) ch. 1 r/w 0b00000000 0x0046, 0x0047 ? (disabled) ? ? 0x0048 eic00 external interrupt circuit control register ch. 0/ch. 1 r/w 0b00000000 0x0049 eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 0b00000000 0x004a eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 0b00000000 0x004b eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 0b00000000 0x004c eic01 external interrupt circuit control register ch. 10/ch. 11 r/w 0b00000000 0x004d eic11 external interrupt circuit control register ch. 12/ch. 13 r/w 0b00000000 0x004e lvdr lvd reset voltage selection id register r/w 0b00000000 address register abbreviation register name r/w initial value
mb95810k series document number: 002-04694 rev. *a page 26 of 121 0x004f lvdcc lvd reset circuit control register r/w 0b00000001 0x0050 scr lin-uart serial co ntrol register r/w 0b00000000 0x0051 smr lin-uart serial mode register r/w 0b00000000 0x0052 ssr lin-uart serial status register r/w 0b00001000 0x0053 rdr lin-uart receive data register r/w 0b00000000 tdr lin-uart transmit data register 0x0054 escr lin-uart extended status control register r/w 0b00000100 0x0055 eccr lin-uart extended communica tion control register r/w 0b000000xx 0x0056 smc10 uart/sio serial mode control register 1 ch. 0 r/w 0b00000000 0x0057 smc20 uart/sio serial mode control register 2 ch. 0 r/w 0b00100000 0x0058 ssr0 uart/sio serial status and data register ch. 0 r/w 0b00000001 0x0059 tdr0 uart/sio serial output data register ch. 0 r/w 0b00000000 0x005a rdr0 uart/sio serial input data register ch. 0 r 0b00000000 0x005b cmr0 comparator control register ch. 0 r/w 0b11000101 0x005c cmr1 comparator control register ch. 1 r/w 0b11000101 0x005d to 0x005f ? (disabled) ? ? 0x0060 ibcr00 i 2 c bus control register 0 ch. 0 r/w 0b00000000 0x0061 ibcr10 i 2 c bus control register 1 ch. 0 r/w 0b00000000 0x0062 ibsr0 i 2 c bus status register ch. 0 r/w 0b00000000 0x0063 iddr0 i 2 c data register ch. 0 r/w 0b00000000 0x0064 iaar0 i 2 c address register ch. 0 r/w 0b00000000 0x0065 iccr0 i 2 c clock control register ch. 0 r/w 0b00000000 0x0066 to 0x006b ? (disabled) ? ? 0x006c adc1 8/10-bit a/d converter control register 1 r/w 0b00000000 0x006d adc2 8/10-bit a/d converter control register 2 r/w 0b00000000 0x006e addh 8/10-bit a/d converter data register (upper) r/w 0b00000000 0x006f addl 8/10-bit a/d converter data register (lower) r/w 0b00000000 0x0070 wcsr watch counter control register r/w 0b00000000 0x0071 fsr2 flash memory stat us register 2 r/w 0b00000000 0x0072 fsr flash memory status register r/w 0b000x0000 0x0073 swre0 flash memory sector wr ite control register 0 r/w 0b00000000 0x0074 fsr3 flash memory st atus register 3 r 0b000xxxxx 0x0075 fsr4 flash memory stat us register 4 r/w 0b00000000 0x0076 wren wild register address compare enable register r/w 0b00000000 address register abbreviation register name r/w initial value
mb95810k series document number: 002-04694 rev. *a page 27 of 121 0x0077 wror wild register data test setting register r/w 0b00000000 0x0078 ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0x0079 ilr0 interrupt level setting register 0 r/w 0b11111111 0x007a ilr1 interrupt level setting register 1 r/w 0b11111111 0x007b ilr2 interrupt level setting register 2 r/w 0b11111111 0x007c ilr3 interrupt level setting register 3 r/w 0b11111111 0x007d ilr4 interrupt level setting register 4 r/w 0b11111111 0x007e ilr5 interrupt level setting register 5 r/w 0b11111111 0x007f ? (disabled) ? ? 0x0f80 wrarh0 wild register address sett ing register (upper) ch. 0 r/w 0b00000000 0x0f81 wrarl0 wild register address setting register (lower) ch. 0 r/w 0b00000000 0x0f82 wrdr0 wild register data setting register ch. 0 r/w 0b00000000 0x0f83 wrarh1 wild register address sett ing register (upper) ch. 1 r/w 0b00000000 0x0f84 wrarl1 wild register address setting register (lower) ch. 1 r/w 0b00000000 0x0f85 wrdr1 wild register data setting register ch. 1 r/w 0b00000000 0x0f86 wrarh2 wild register address sett ing register (upper) ch. 2 r/w 0b00000000 0x0f87 wrarl2 wild register address setting register (lower) ch. 2 r/w 0b00000000 0x0f88 wrdr2 wild register data setting register ch. 2 r/w 0b00000000 0x0f89 to 0x0f91 ? (disabled) ? ? 0x0f92 t01cr0 8/16-bit composite timer 01 status control register 0 r/w 0b00000000 0x0f93 t00cr0 8/16-bit composite timer 00 status control register 0 r/w 0b00000000 0x0f94 t01dr 8/16-bit composite timer 01 data register r/w 0b00000000 0x0f95 t00dr 8/16-bit composite timer 00 data register r/w 0b00000000 0x0f96 tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 0b00000000 0x0f97 t11cr0 8/16-bit composite timer 11 status control register 0 r/w 0b00000000 0x0f98 t10cr0 8/16-bit composite timer 10 status control register 0 r/w 0b00000000 0x0f99 t11dr 8/16-bit composite timer 11 data register r/w 0b00000000 0x0f9a t10dr 8/16-bit composite time r 10 data register r/w 0b00000000 0x0f9b tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 0b00000000 0x0f9c pps01 8/16-bit ppg01 cycle se tting buffer register r/w 0b11111111 0x0f9d pps00 8/16-bit ppg00 cycle se tting buffer register r/w 0b11111111 0x0f9e pds01 8/16-bit ppg01 duty setting buffer register r/w 0b11111111 0x0f9f pds00 8/16-bit ppg00 duty setting buffer register r/w 0b11111111 address register abbreviation register name r/w initial value
mb95810k series document number: 002-04694 rev. *a page 28 of 121 0x0fa0 pps11 8/16-bit ppg11 cycle sett ing buffer register r/w 0b11111111 0x0fa1 pps10 8/16-bit ppg10 cycle se tting buffer register r/w 0b11111111 0x0fa2 pds11 8/16-bit ppg11 duty setting buffer register r/w 0b11111111 0x0fa3 pds10 8/16-bit ppg10 duty setting buffer register r/w 0b11111111 0x0fa4 ppgs 8/16-bit ppg start register r/w 0b00000000 0x0fa5 revc 8/16-bit ppg output inversion register r/w 0b00000000 0x0fa6 tmrh0 16-bit reload timer timer register (upper) ch. 0 r/w 0b00000000 tmrlrh0 16-bit reload timer reload register (upper) ch. 0 0x0fa7 tmrl0 16-bit reload timer timer register (lower) ch. 0 r/w 0b00000000 tmrlrl0 16-bit reload timer reload register (lower) ch. 0 0x0fa8, 0x0fa9 ? (disabled) ? ? 0x0faa pdcrh0 16-bit ppg downcounter register (upper) ch. 0 r 0b00000000 0x0fab pdcrl0 16-bit ppg downcounter register (lower) ch. 0 r 0b00000000 0x0fac pcsrh0 16-bit ppg cycle setting buffer register (upper) ch. 0 r/w 0b11111111 0x0fad pcsrl0 16-bit ppg cycle setting buffer register (lower) ch. 0 r/w 0b11111111 0x0fae pduth0 16-bit ppg duty setting buffer register (upper) ch. 0 r/w 0b11111111 0x0faf pdutl0 16-bit ppg duty setting buffer register (lower) ch. 0 r/w 0b11111111 0x0fb0 pdcrh1 16-bit ppg downcounter register (upper) ch. 1 r 0b00000000 0x0fb1 pdcrl1 16-bit ppg downcounter register (lower) ch. 1 r 0b00000000 0x0fb2 pcsrh1 16-bit ppg cycle setting buffer register (upper) ch. 1 r/w 0b11111111 0x0fb3 pcsrl1 16-bit ppg cycle setting buffer register (lower) ch. 1 r/w 0b11111111 0x0fb4 pduth1 16-bit ppg duty setting buffer register (upper) ch. 1 r/w 0b11111111 0x0fb5 pdutl1 16-bit ppg duty setting buffer register (lower) ch. 1 r/w 0b11111111 0x0fb6 to 0x0fbb ? (disabled) ? ? 0x0fbc bgr1 lin-uart baud rate generator register 1 r/w 0b00000000 0x0fbd bgr0 lin-uart baud rate generator register 0 r/w 0b00000000 0x0fbe pssr0 uart/sio dedicated baud rate generator prescaler select register ch. 0 r/w 0b00000000 0x0fbf brsr0 uart/sio dedicated baud rate generator baud rate setting register ch. 0 r/w 0b00000000 0x0fc0, 0x0fc1 ? (disabled) ? ? 0x0fc2 aidrh a/d input disable register (upper) r/w 0b00000000 0x0fc3 aidrl a/d input disable register (lower) r/w 0b00000000 0x0fc4 lvdpw lvd reset circuit password register r/w 0b00000000 address register abbreviation register name r/w initial value
mb95810k series document number: 002-04694 rev. *a page 29 of 121 ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. 0x0fc5 to 0x0fe2 ? (disabled) ? ? 0x0fe3 wcdr watch counter data register r/w 0b00111111 0x0fe4 crth main cr clock trimmi ng register (u pper) r/w 0b000xxxxx 0x0fe5 crtl main cr clock trimmi ng register (lower) r/w 0b000xxxxx 0x0fe6 ? (disabled) ? ? 0x0fe7 crtda main cr clock temperature dependent adjustment register r/w 0b000xxxxx 0x0fe8 sysc system configurat ion register r/w 0b11000011 0x0fe9 cmcr clock monitoring control register r/w 0b00000000 0x0fea cmdr clock monitoring data register r 0b00000000 0x0feb wdth watchdog timer selecti on id register (upper) r 0bxxxxxxxx 0x0fec wdtl watchdog timer selecti on id register (lower) r 0bxxxxxxxx 0x0fed, 0x0fee ? (disabled) ? ? 0x0fef wicr interrupt pin selection circuit control register r/w 0b01000000 0x0ff0 to 0x0fff ? (disabled) ? ? r/w : readable/writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. address register abbreviation register name r/w initial value
mb95810k series document number: 002-04694 rev. *a page 30 of 121 15. i/o ports ? list of port registers register name read/write initial value port 0 data register pdr0 r, rm/w 0b00000000 port 0 direction register ddr0 r/w 0b00000000 port 1 data register pdr1 r, rm/w 0b00000000 port 1 direction register ddr1 r/w 0b00000000 port 2 data register pdr2 r, rm/w 0b00000000 port 2 direction register ddr2 r/w 0b00000000 port 3 data register pdr3 r, rm/w 0b00000000 port 3 direction register ddr3 r/w 0b00000000 port 4 data register pdr4 r, rm/w 0b00000000 port 4 direction register ddr4 r/w 0b00000000 port 5 data register pdr5 r, rm/w 0b00000000 port 5 direction register ddr5 r/w 0b00000000 port 6 data register pdr6 r, rm/w 0b00000000 port 6 direction register ddr6 r/w 0b00000000 port 7 data register pdr7 r, rm/w 0b00000000 port 7 direction register ddr7 r/w 0b00000000 port 8 data register pdr8 r, rm/w 0b00000000 port 8 direction register ddr8 r/w 0b00000000 port e data register pdre r, rm/w 0b00000000 port e direction register ddre r/w 0b00000000 port f data register pdrf r, rm/w 0b00000000 port f direction r egister ddrf r/w 0b00000000 port g data register pdrg r, rm/w 0b00000000 port g direction register ddrg r/w 0b00000000 port 0 pull-up register pul0 r/w 0b00000000 port 1 pull-up register pul1 r/w 0b00000000 port 2 pull-up register pul2 r/w 0b00000000 port 3 pull-up register pul3 r/w 0b00000000 port 4 pull-up register pul4 r/w 0b00000000 port 5 pull-up register pul5 r/w 0b00000000 port 6 pull-up register pul6 r/w 0b00000000 port 7 pull-up register pul7 r/w 0b00000000 port 8 pull-up register pul8 r/w 0b00000000 port e pull-up register pule r/w 0b00000000 port g pull-up register pulg r/w 0b00000000
mb95810k series document number: 002-04694 rev. *a page 31 of 121 r/w : readable/writable (the read value is the same as the write value.) r, rm/w : readable/writable (the read value is different fr om the write value. the write value is read by the read- modify-write (rmw) type of instruction.) 15.1 port 0 port 0 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.1.1 port 0 configuration port 0 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 0 data register (pdr0) ? port 0 direction register (ddr0) ? port 0 pull-up register (pul0) 15.1.2 block diagrams of port 0 ? p00/int00 pin this pin has the following peripheral function: ? external interrupt input pin (int00) ? p01/int01 pin this pin has the following peripheral function: ? external interrupt input pin (int01) ? p02/int02 pin this pin has the following peripheral function: external interrupt input pin (int02) ? p03/int03 pin this pin has the following peripheral function: ? external interrupt input pin (int03) ? p04/int04 pin this pin has the following peripheral function: ? external interrupt input pin (int04) ? p05/int05 pin this pin has the following peripheral function: ? external interrupt input pin (int05) ? p06/int06 pin this pin has the following peripheral function: ? external interrupt input pin (int06) ? p07/int07 pin this pin has the following peripheral function: a/d input disable register (upper) aidrh r/w 0b00000000 a/d input disable register (lower) aidrl r/w 0b00000000 register name read/write initial value
mb95810k series document number: 002-04694 rev. *a page 32 of 121 ? external interrupt input pin (int07) ? block diagram of p00/int00, p01/int01, p02/int02, p03/ int03, p04/int04, p05/int05, p06/int06 and p07/int07 15.1.3 port 0 registers ? port 0 register functions ? correspondence between registers and pins for port 0 register abbreviation data read read by read-modify-write (rmw) instruction write pdr0 0 pin state is ?l? level. pdr0 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr0 value is ?1?. as output port, outputs ?h? level. ddr0 0 port input enabled 1 port output enabled pul0 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name p07 p06 p05 p04 p03 p02 p01 p00 pdr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr0 pul0 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write ddr0 pul0 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int00 to int07) hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 33 of 121 15.1.4 port 0 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 0 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr0 register to external pins. ? if data is written to the pdr0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr0 register returns the pdr0 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr0 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr0 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr0 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr0 register, th e pdr0 register va lue is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr0 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr0 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr0 register, the pdr0 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr0 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr0 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input is enabled for the external interrupt (int00 to int07), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an external interrupt input pin ? set the bit in the ddr0 register correspondin g to the external inte rrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt ci rcuit. when using a pin for a function other than the interrupt, disable the external interrupt fu nction corresponding to that pin. ? operation of the pull-up register setting the bit in the pul0 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul0 register.
mb95810k series document number: 002-04694 rev. *a page 34 of 121 15.2 port 1 port 1 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.2.1 port 1 configuration port 1 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 1 data register (pdr1) ? port 1 direction register (ddr1) ? port 1 pull-up register (pul1) 15.2.2 block diagrams of port 1 ? p10/ui0 pin this pin has the following peripheral function: ? uart/sio ch. 0 data input pin (ui0) ? block diagram of p10/ui0 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable cmos pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 35 of 121 ? p11/uo0 pin this pin has the following peripheral function: ? uart/sio ch. 0 data output pin (uo0) ? block diagram of p11/uo0 ? p12/dbg pin this pin has the following peripheral function: ? dbg input pin (dbg) ? block diagram of p12/dbg pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 stop mode, watch mode (spl = 1) od hysteresis internal bus
mb95810k series document number: 002-04694 rev. *a page 36 of 121 ? p13/uck0/trg0/adtg* pin this pin has the following peripheral functions: ? uart/sio ch. 0 clock i/o pin (uck0) ? 16-bit ppg timer ch. 0 trigger input pin (trg0) ? 8/10-bit a/d converter trigger input pin (adtg) *: trg0 and adtg can be mapp ed to either p13 or p83 by using the sysc register. ? block diagram of p13/uck0/trg0/adtg pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 37 of 121 ? p14/ppg0 pin this pin has the following peripheral function: ? 16-bit ppg timer ch. 0 output pin (ppg0) ? block diagram of p14/ppg0 15.2.3 port 1 registers ? port 1 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 1 *: though p12 has no pull-up function, bi t2 in the pul1 register can still be a ccessed. the operation of p12 is not af- fected by the setting of bit2 in the pul1 register. register abbreviation data read read by read-modify-write (rmw) instruction write pdr1 0 pin state is ?l? level. pdr1 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr1 value is ?1?. as output port, outputs ?h? level.* ddr1 0 port input enabled 1 port output enabled pul1 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name - - - p14 p13 p12 p11 p10 pdr1 - - - bit4 bit3 bit2* bit1 bit0 ddr1 pul1 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 38 of 121 15.2.4 port 1 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 1 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr1 register to external pins. ? if data is written to the pdr1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr1 register returns the pdr1 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr1 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr1 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr1 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr1 register, th e pdr1 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr1 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr1 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr1 register, the pdr1 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr1 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr1 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr1 register, the pdr1 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr1 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr1 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input of p10/ui0 and p13/uck0/trg 0/adtg is enabled by the external interrupt control register ch. 0 (eic00) of the external interrupt circuit an d the interrupt pin selection circuit control register (wicr) of the interrupt pin selection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul1 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul1 register.
mb95810k series document number: 002-04694 rev. *a page 39 of 121 15.3 port 2 port 2 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.3.1 port 2 configuration port 2 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 2 data register (pdr2) ? port 2 direction register (ddr2) ? port 2 pull-up register (pul2) 15.3.2 block diagrams of port 2 ? p20/ppg00 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 0 output pin (ppg00) ? p21/ppg01 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 0 output pin (ppg01) ? p22/to00 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 0 output pin (to00) ? p23/to01 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 0 output pin (to01) ? block diagram of p20/ppg00, p21/ppg01, p22/to00 and p23/to01 pdr2 pin pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write pul2 read pul2 write ddr2 pul2 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 40 of 121 ? p24/ec0 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 0 clock input pin (ec0) ? block diagram of p24/ec0 15.3.3 port 2 registers ? port 2 register functions ? correspondence between registers and pins for port 2 register abbreviation data read read by read-modify-write (rmw) instruction write pdr2 0 pin state is ?l? level. pdr2 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr2 value is ?1?. as output port, outputs ?h? level. ddr2 0 port input enabled 1 port output enabled pul2 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name - - - p24 p23 p22 p21 p20 pdr2 - - - bit4 bit3 bit2 bit1 bit0 ddr2 pul2 pdr2 pin pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write pul2 read pul2 write ddr2 pul2 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 41 of 121 15.3.4 port 2 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 2 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr2 register to external pins. ? if data is written to the pdr2 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr2 register returns the pdr2 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr2 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr2 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr2 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr2 register, th e pdr2 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr2 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr2 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr2 register, the pdr2 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr2 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr2 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr2 register, the pdr2 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr2 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr2 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input of p24/ec0 is enabled by the external interrupt control register ch. 0 (eic00) of the external interrupt circuit and the interrupt pin selection circuit control regi ster (wicr) of the interrupt pin selection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul2 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul2 register.
mb95810k series document number: 002-04694 rev. *a page 42 of 121 15.4 port 3 port 3 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.4.1 port 3 configuration port 3 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 3 data register (pdr3) ? port 3 direction register (ddr3) ? port 3 pull-up register (pul3) ? a/d input disable register (lower) (aidrl) 15.4.2 block diagrams of port 3 ? p30/an00/cmp0_n pin this pin has the following peripheral functions: ? 8/10-bit a/d converter analog input pin (an00) ? comparator ch. 0 inverting analog input (negative input) pin (cmp0_n) ? p31/an01/cmp0_p pin this pin has the following peripheral functions: ? 8/10-bit a/d converter analog input pin (an01) ? comparator ch. 0 non-inverting analog input (positive input) pin (cmp0_p) ? p33/an03/cmp1_n pin this pin has the following peripheral functions: ? 8/10-bit a/d converter analog input pin (an03) ? comparator ch. 1 inverting analog input (negative input) pin (cmp1_n) ? p34/an04/cmp1_p pin this pin has the following peripheral functions: ? 8/10-bit a/d converter analog input pin (an04) ? comparator ch. 1 non-inverting analog input (positive input) pin (cmp1_p)
mb95810k series document number: 002-04694 rev. *a page 43 of 121 ? block diagram of p30/an00/cmp0_n, p31/an01 /cmp0_p, p33/an03/cmp1_n and p34/an04/cmp1_p pdr3 pin pdr3 read pdr3 write executing bit manipulation instruction internal bus ddr3 read ddr3 write pul3 read pul3 write aidrl read aidrl write ddr3 pul3 aidrl 0 1 stop mode, watch mode (spl = 1) comparator analog input comparator analog input disable a/d analog input hysteresis pull-up
mb95810k series document number: 002-04694 rev. *a page 44 of 121 ? p32/an02/cmp0_o pin this pin has the following peripheral functions: ? 8/10-bit a/d converter analog input pin (an02) ? comparator ch. 0 digital output pin (cmp0_o) ? p35/an05/cmp1_o pin this pin has the following peripheral functions: ? 8/10-bit a/d converter analog input pin (an05) ? comparator ch. 1 digital output pin (cmp1_o) ? block diagram of p32/an02/cmp0_o and p35/an05/cmp1_o pdr3 pin pdr3 read pdr3 write executing bit manipulation instruction ddr3 read ddr3 write pul3 read pul3 write aidrl read aidrl write ddr3 pul3 aidrl 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output a/d analog input hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 45 of 121 ? p36/an06 pin this pin has the following peripheral function: ? 8/10-bit a/d converter analog input pin (an06) ? p37/an07 pin this pin has the following peripheral function: ? 8/10-bit a/d converter analog input pin (an07) ? block diagram of p36/an06 and p37/an07 pdr3 pin pdr3 read pdr3 write executing bit manipulation instruction ddr3 read ddr3 write pul3 read pul3 write aidrl read aidrl write ddr3 pul3 aidrl 0 1 stop mode, watch mode (spl = 1) a/d analog input hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 46 of 121 15.4.3 port 3 registers ? port 3 register functions ? correspondence between registers and pins for port 3 register abbreviation data read read by read-modify-write (rmw) instruction write pdr3 0 pin state is ?l? level. pdr3 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr3 value is ?1?. as output port, outputs ?h? level. ddr3 0 port input enabled 1 port output enabled pul3 0 pull-up disabled 1 pull-up enabled aidrl 0 analog input enabled 1 port input enabled correspondence between related register bits and pins pin name p37 p36 p35 p34 p33 p32 p31 p30 pdr3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr3 pul3 aidrl
mb95810k series document number: 002-04694 rev. *a page 47 of 121 15.4.4 port 3 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 3 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr3 register to external pins. ? if data is written to the pdr3 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr3 register returns the pdr3 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr3 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when using a pin shared with the analog input function as an input port, set the corresponding bit in the a/d input disable register (lower) (aidrl) to ?1?. ? if data is written to the pdr3 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr3 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr3 register, th e pdr3 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr3 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr3 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr3 register, the pdr3 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr3 regi ster corresponding to the input pin of a peripheral function to ?0?. ? when using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the aidrl register corresponding to that pin to ?1?. ? reading the pdr3 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr3 register, the pdr3 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr3 r egister are initialized to ?0 ? and port input is enabled . as for a pin shared with the analog input function, its port input is disabled beca use the aidrl register is initialized to ?0?. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr3 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an analog input pin ? set the bit in the ddr3 register bit corr esponding to the analog in put pin to ?0? and the bit corresponding to that pin in the aidrl register to ?0?. ? for a pin shared with other peripheral functions, disable th e output of such peripheral f unctions. in addition, set the corresponding bit in the pul3 register to ?0?.
mb95810k series document number: 002-04694 rev. *a page 48 of 121 ? operation of the pull-up register setting the bit in the pul3 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul3 register. ? operation as a comparator input pin (only for p31 and p34) ? set the bit in the aidrl register corresponding to the comparator input pin to ?0?. ? regardless of the value of t he pdr3 register and that of the ddr3 regist er, if the comparator analog input enable bit in the comparator control register ch. 0/ch. 1 (cmr0/cm r1:vcid) is set to ?0?, the comparator input function is enabled. ? to disable the comparator input function, set the vcid bit to ?1?. ? for details of the comparator, refer to ?chapter 28 comparator? in ?new 8fx mb95810k series hardware manual?. ? operation as a comparator input pin (only for p30 and p33) ? set the bit in the aidrl register corresponding to the comparator input pin to ?0?. ? regardless of the value of t he pdr3 register and that of the ddr3 regist er, if the comparator analog input enable bit (vcid) and the negative analog input voltage source se lect bit (bgrs) in the comparator control register ch. 0/ch. 1 (cmr0/cmr1) are both set to ?0?, the comparator input function is enabled. ? to disable the comparator input function, set the vcid bit or the bgrs bit to ?1?. ? for details of the comparator, refer to ?chapter 28 comparator? in ?new 8fx mb95810k series hardware manual?. 15.5 port 4 port 4 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.5.1 port 4 configuration port 4 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 4 data register (pdr4) ? port 4 direction register (ddr4) ? port 4 pull-up register (pul4) ? a/d input disable re gister (upper) (aidrh) 15.5.2 block diagrams of port 4 ? p40/an08 pin this pin has the following peripheral function: ? 8/10-bit a/d converter analog input pin (an08) ? p41/an09 pin this pin has the following peripheral function: ? 8/10-bit a/d converter analog input pin (an09) ? p42/an10 pin this pin has the following peripheral function: ? 8/10-bit a/d converter analog input pin (an10) ? p43/an11 pin this pin has the following peripheral function: ? 8/10-bit a/d converter analog input pin (an11)
mb95810k series document number: 002-04694 rev. *a page 49 of 121 ? block diagram of p40/an08, p41/an09, p42/an10 and p43/an11 15.5.3 port 4 registers ? port 4 register functions register abbreviation data read read by read-modify-write (rmw) instruction write pdr4 0 pin state is ?l? level. pdr4 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr4 value is ?1?. as output port, outputs ?h? level. ddr4 0 port input enabled 1 port output enabled pul4 0 pull-up disabled 1 pull-up enabled aidrh 0 analog input enabled 1 port input enabled pdr4 pin pdr4 read pdr4 write executing bit manipulation instruction ddr4 read ddr4 write pul4 read pul4 write aidrh read aidrh write ddr4 pul4 aidrh 0 1 stop mode, watch mode (spl = 1) a/d analog input hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 50 of 121 ? correspondence between registers and pins for port 4 15.5.4 port 4 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 4 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr4 register to external pins. ? if data is written to the pdr4 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr4 register returns the pdr4 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr4 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when using a pin shared with the analog input function as an input port, set the corresponding bit in the a/d input disable register (upper) (aidrh) to ?1?. ? if data is written to the pdr4 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr4 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr4 register, th e pdr4 register va lue is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr4 regi ster corresponding to the input pin of a peripheral function to ?0?. ? when using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the aidrh register corresponding to that pin to ?1?. ? reading the pdr4 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr4 register, the pdr4 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr4 r egister are initialized to ?0 ? and port input is enabled . as for a pin shared with the analog input function, its port input is disabled beca use the aidrh register is initialized to ?0?. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr4 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an analog input pin ? set the bit in the ddr4 register bit corr esponding to the analog in put pin to ?0? and the bit corresponding to that pin correspondence between related register bits and pins pin name----p43p42p41p40 pdr4 ----bit3bit2bit1bit0 ddr4 pul4 aidrh
mb95810k series document number: 002-04694 rev. *a page 51 of 121 in the aidrh register to ?0?. ? for a pin shared with other peripheral functions, disable th e output of such peripheral f unctions. in addition, set the corresponding bit in the pul4 register to ?0?. ? operation of the pull-up register setting the bit in the pul4 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul4 register. 15.6 port 5 port 5 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.6.1 port 5 configuration port 5 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 5 data register (pdr5) ? port 5 direction register (ddr5) ? port 5 pull-up register (pul5) 15.6.2 block diagrams of port 5 ?p50/scl pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 clock i/o pin (scl) ? p51/sda pin this pin has the following peripheral function: ?i 2 c bus interface ch. 0 data i/o pin (sda) ? block diagram of p50/scl and p51/sda pdr5 pdr5 read pdr5 write executing bit manipulation instruction ddr5 read ddr5 write ddr5 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function input enable peripheral function output pin od internal bus cmos
mb95810k series document number: 002-04694 rev. *a page 52 of 121 ? p52/ppg1 pin this pin has the following peripheral function: ? 16-bit ppg timer ch. 1 output pin (ppg1) ? block diagram of p52/ppg1 ? p53/trg1 pin this pin has the following peripheral function: ? 16-bit ppg timer ch. 1 trigger input pin (trg1) pdr5 pin pdr5 read pdr5 write executing bit manipulation instruction ddr5 read ddr5 write pul5 read pul5 write ddr5 pul5 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 53 of 121 ? block diagram of p53/trg1 15.6.3 port 5 registers ? port 5 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 5 *: though p50 and p51 have no pull-up function, bit0 and bit1 in the pul5 re gister can still be ac cessed. the operation of p50 and p51 is not affected by the setti ngs of bit0 and bit1 in the pul5 register. register abbreviation data read read by read-modify-write (rmw) instruction write pdr5 0 pin state is ?l? level. pdr5 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr5 value is ?1?. as output port, outputs ?h? level.* ddr5 0 port input enabled 1 port output enabled pul5 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name----p53p52p51p50 pdr5 ----bit3bit2bit1*bit0* ddr5 pul5 pdr5 pin pdr5 read pdr5 write executing bit manipulation instruction ddr5 read ddr5 write pul5 read pul5 write ddr5 pul5 0 1 stop mode, watch mode (spl = 1) peripheral function input hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 54 of 121 15.6.4 port 5 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 5 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr5 register to external pins. ? if data is written to the pdr5 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr5 register returns the pdr5 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr5 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr5 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr5 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr5 register, th e pdr5 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr5 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr5 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr5 register, the pdr5 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr5 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr5 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr5 register, the pdr5 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr5 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr5 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul5 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul5 register.
mb95810k series document number: 002-04694 rev. *a page 55 of 121 15.7 port 6 port 6 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.7.1 port 6 configuration port 6 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 6 data register (pdr6) ? port 6 direction register (ddr6) ? port 6 pull-up register (pul6) 15.7.2 block diagrams of port 6 ? p60/ppg10 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 1 output pin (ppg10) ? p61/ppg11 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 1 output pin (ppg11) ? p62/to10 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 1 output pin (to10) ? p63/to11 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 1 output pin (to11) ? p66/sot pin this pin has the following peripheral function: ? lin-uart data output pin (sot)
mb95810k series document number: 002-04694 rev. *a page 56 of 121 ? block diagram of p60/ppg10, p61/ppg11, p62/to10, p63/to11 and p66/sot ? p64/ec1 pin this pin has the following peripheral function: ? 8/16-bit composite timer ch. 1 clock input pin (ec1) ? block diagram of p64/ec1 pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write pul6 read pul6 write ddr6 pul6 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write pul6 read pul6 write ddr6 pul6 0 1 stop mode, watch mode (spl = 1) peripheral function input hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 57 of 121 ? p65/sck pin this pin has the following peripheral function: ? lin-uart clock i/o pin (sck) ? block diagram of p65/sck pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write pul6 read pul6 write ddr6 pul6 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 58 of 121 ? p67/sin pin this pin has the following peripheral function: ? lin-uart data input pin (sin) ? block diagram of p67/sin 15.7.3 port 6 registers ? port 6 register functions ? correspondence between registers and pins for port 6 register abbreviation data read read by read-modify-write (rmw) instruction write pdr6 0 pin state is ?l? level. pdr6 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr6 value is ?1?. as output port, outputs ?h? level. ddr6 0 port input enabled 1 port output enabled pul6 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name p67 p66 p65 p64 p63 p62 p61 p60 pdr6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr6 pul6 pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write pul6 read pul6 write ddr6 pul6 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable cmos pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 59 of 121 15.7.4 port 6 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 6 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr6 register to external pins. ? if data is written to the pdr6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr6 register returns the pdr6 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr6 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr6 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr6 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr6 register, th e pdr6 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr6 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr6 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr6 register, the pdr6 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr6 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr6 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr6 register, the pdr6 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr6 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr6 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input of p65/sck and p67/sin is enabl ed by the external interrupt control register ch. 0 (eic00) of the external interrupt circuit and the interrupt pin select ion circuit control register (wicr) of the interrupt pin se- lection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul6 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul6 register.
mb95810k series document number: 002-04694 rev. *a page 60 of 121 15.8 port 7 port 7 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.8.1 port 7 configuration port 7 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 7 data register (pdr7) ? port 7 direction register (ddr7) ? port 7 pull-up register (pul7) 15.8.2 block diagrams of port 7 ? p70/to0 pin this pin has the following peripheral function: ? 16-bit reload timer ch. 0 output pin (to0) ? block diagram of p70/to0 pdr7 pin pdr7 read pdr7 write executing bit manipulation instruction ddr7 read ddr7 write pul7 read pul7 write ddr7 pul7 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 61 of 121 ? p71/ti0 pin this pin has the following peripheral function: ? 16-bit reload timer ch. 0 input pin (ti0) ? block diagram of p71/ti0 ?p72 pin ? block diagram of p72 pdr7 pin pdr7 read pdr7 write executing bit manipulation instruction ddr7 read ddr7 write pul7 read pul7 write ddr7 pul7 0 1 stop mode, watch mode (spl = 1) peripheral function input hysteresis pull-up internal bus pdr7 pin pdr7 read pdr7 write executing bit manipulation instruction ddr7 read ddr7 write pul7 read pul7 write ddr7 pul7 0 1 stop mode, watch mode (spl = 1) hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 62 of 121 15.8.3 port 7 registers ? port 7 register functions ? correspondence between registers and pins for port 7 15.8.4 port 7 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 7 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr7 register to external pins. ? if data is written to the pdr7 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr7 register returns the pdr7 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr7 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr7 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr7 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr7 register, th e pdr7 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr7 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr7 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr7 register, the pdr7 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr7 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr7 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its register abbreviation data read read by read-modify-write (rmw) instruction write pdr7 0 pin state is ?l? level. pdr7 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr7 value is ?1?. as output port, outputs ?h? level. ddr7 0 port input enabled 1 port output enabled pul7 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name-----p72p71p70 pdr7 -----bit2bit1bit0 ddr7 pul7
mb95810k series document number: 002-04694 rev. *a page 63 of 121 input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr7 register, the pdr7 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr7 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr7 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul7 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul7 register. 15.9 port 8 port 8 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.9.1 port 8 configuration port 8 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 8 data register (pdr8) ? port 8 direction register (ddr8) ? port 8 pull-up register (pul8) 15.9.2 block diagrams of port 8 ?p80 pin ?p81 pin ?p82 pin
mb95810k series document number: 002-04694 rev. *a page 64 of 121 ? block diagram of p80, p81 and p82 ? p83/trg0/adtg* pin this pin has the following peripheral function: ? 16-bit ppg timer ch. 0 trigger input pin (trg0) ? 8/10-bit a/d converter trigger input pin (adtg) *: trg0 and adtg can be mapp ed to either p13 or p83 by using the sysc register. ? block diagram of p83/trg0/adtg pdr8 pin pdr8 read pdr8 write executing bit manipulation instruction ddr8 read ddr8 write pul8 read pul8 write ddr8 pul8 0 1 stop mode, watch mode (spl = 1) hysteresis pull-up internal bus pdr8 pin pdr8 read pdr8 write executing bit manipulation instruction ddr8 read ddr8 write pul8 read pul8 write ddr8 pul8 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 65 of 121 15.9.3 port 8 registers ? port 8 register functions ? correspondence between registers and pins for port 8 15.9.4 port 8 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 8 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr8 register to external pins. ? if data is written to the pdr8 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr8 register returns the pdr8 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr8 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr8 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr8 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr8 register, th e pdr8 register va lue is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr8 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr8 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr8 register, the pdr8 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr8 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode register abbreviation data read read by read-modify-write (rmw) instruction write pdr8 0 pin state is ?l? level. pdr8 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr8 value is ?1?. as output port, outputs ?h? level. ddr8 0 port input enabled 1 port output enabled pul8 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name----p83p82p81p80 pdr8 ----bit3bit2bit1bit0 ddr8 pul8
mb95810k series document number: 002-04694 rev. *a page 66 of 121 ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr8 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input of p83/trg0 /adtg is enabled by the external interrupt control register ch. 0 (eic00) of the external interrupt circuit and the interrupt pin selection circuit control register (wicr) of the interrupt pin selec- tion circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul8 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul8 register. 15.10 port e port e is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.10.1 port e configuration port e is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port e data register (pdre) ? port e direction register (ddre) ? port e pull-up register (pule) 15.10.2 block diagrams of port e ? pe0/int10 pin this pin has the following peripheral function: ? external interrupt input pin (int10) ? pe1/int11 pin this pin has the following peripheral function: ? external interrupt input pin (int11) ? pe2/int12 pin this pin has the following peripheral function: external interrupt input pin (int12) ? pe3/int13 pin this pin has the following peripheral function: ? external interrupt input pin (int13)
mb95810k series document number: 002-04694 rev. *a page 67 of 121 ? block diagram of pe0/int10, pe1 /int11, pe2/int12 and pe3/int13 15.10.3 port e registers ? port e register functions ? correspondence between registers and pins for port e register abbreviation data read read by read-modify-write (rmw) instruction write pdre 0 pin state is ?l? level. pdre value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdre value is ?1?. as output port, outputs ?h? level. ddre 0 port input enabled 1 port output enabled pule 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name----pe3pe2pe1pe0 pdre ----bit3bit2bit1bit0 ddre pule pdre pin pdre read pdre write executing bit manipulation instruction ddre read ddre write pule read pule write ddre pule 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int10 to int13) hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 68 of 121 15.10.4 port e operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr e register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdre register to external pins. ? if data is written to the pdre register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdre register returns the pdre register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddre register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdre register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdre register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdre register, th e pdre register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddre regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdre register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. however, if the re ad-modify-write (rmw) type of instruction is used to read the pdre register, the pdre register value is returned. ? operation at reset if the cpu is reset, all bits in the ddre register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to en ter the high impedance state regardless of the ddre reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input is enabled for the external interrupt (int10 to int13), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an external interrupt input pin ? set the bit in the ddre register corresponding to the external interrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt ci rcuit. when using a pin for a function other than the interrupt, disable the external interrupt fu nction corresponding to that pin. ? operation of the pull-up register setting the bit in the pule register to ?1? makes the pull-up resistor be internally connec ted to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardless of the value of the pule register.
mb95810k series document number: 002-04694 rev. *a page 69 of 121 15.11 port f port f is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.11.1 port f configuration port f is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port f data register (pdrf) ? port f direction register (ddrf) 15.11.2 block diagrams of port f ?pf0/x0 pin this pin has the following peripheral function: ? main clock input oscillation pin (x0) ?pf1/x1 pin this pin has the following peripheral function: ? main clock i/o oscillation pin (x1) ? block diagram of pf0/x0 and pf1/x1 ?pf2/rst pin this pin has the following peripheral function: ? reset pin (rst ) pdrf pin pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 stop mode, watch mode (spl = 1) internal bus hysteresis
mb95810k series document number: 002-04694 rev. *a page 70 of 121 ? block diagram of pf2/rst 15.11.3 port f registers ? port f register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port f *: when the external rese t is selected (sysc:rsten = 1), the port function cannot be used. register abbreviation data read read by read-modify-write (rmw) instruction write pdrf 0 pin state is ?l? level. pdrf value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrf value is ?1?. as output port, outputs ?h? level.* ddrf 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name-----pf2pf1pf0 pdrf -----bit2*bit1bit0 ddrf pdrf pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 1 0 stop mode, watch mode (spl = 1) reset input reset input enable reset output enable reset output pin od internal bus hysteresis
mb95810k series document number: 002-04694 rev. *a page 71 of 121 15.11.4 port f operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr f register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrf register to external pins. ? if data is written to the pdrf register, the value is stored in the output latch and is outpu t to the pin set as an output port as it is. ? reading the pdrf register returns the pdrf register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddrf register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrf register , the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrf register returns the pin value. howeve r, if the read-modify-write (rmw) type of instruction is used to read the pdrf register, t he pdrf register value is returned. ? operation at reset if the cpu is reset, all bits in the ddrf register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddrf reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained.
mb95810k series document number: 002-04694 rev. *a page 72 of 121 15.12 port g port g is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95810k series hardware manual?. 15.12.1 port g configuration port g is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port g data register (pdrg) ? port g direction register (ddrg) ? port g pull-up register (pulg) 15.12.2 block diagram of port g ? pg1/x0a pin this pin has the following peripheral function: ? subclock input oscillation pin (x0a) ? pg2/x1a pin this pin has the following peripheral function: ? subclock i/o oscillation pin (x1a) ? block diagram of pg1/x0a and pg2/x1a pdrg pin pdrg read pdrg write executing bit manipulation instruction ddrg read ddrg write pulg read pulg write ddrg pulg 0 1 stop mode, watch mode (spl = 1) hysteresis pull-up internal bus
mb95810k series document number: 002-04694 rev. *a page 73 of 121 15.12.3 port g registers ? port g register functions ? correspondence between registers and pins for port g 15.12.4 port g operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr g register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrg regi ster to external pins. ? if data is written to the pdrg register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrg register returns the pdrg register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddrg register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrg register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrg register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdrg register, th e pdrg register va lue is returned. ? operation at reset if the cpu is reset, all bits in the ddrg register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is comp ulsorily made to enter th e high impedance state regardless of the ddrg reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pulg register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pulg register. register abbreviation data read read by read-modify-write (rmw) instruction write pdrg 0 pin state is ?l? level. pdrg value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrg value is ?1?. as output port, outputs ?h? level. ddrg 0 port input enabled 1 port output enabled pulg 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name-----pg2pg1- pdrg -----bit2bit1- ddrg pulg
mb95810k series document number: 002-04694 rev. *a page 74 of 121 16. interrupt source table interrupt source interrupt request number vector table address interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower register bit external interrupt ch. 0 irq00 0xfffa 0xfffb ilr0 l00 [1:0] high low external interrupt ch. 4 external interrupt ch. 1 irq01 0xfff8 0xfff9 ilr0 l01 [1:0] external interrupt ch. 5 external interrupt ch. 2 irq02 0xfff6 0xfff7 ilr0 l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 0xfff4 0xfff5 ilr0 l03 [1:0] external interrupt ch. 7 comparator ch. 1 uart/sio ch. 0 irq04 0xfff2 0xfff3 ilr1 l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 0xfff0 0xfff1 ilr1 l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 0xffee 0xffef ilr1 l06 [1:0] lin-uart (reception) irq07 0xffec 0xffed ilr1 l07 [1:0] lin-uart (transmission) irq08 0xffea 0xffeb ilr2 l08 [1:0] 8/16-bit ppg ch. 1 (lower) irq09 0xffe8 0xffe9 ilr2 l09 [1:0] 8/16-bit ppg ch. 1 (upper) irq10 0xffe6 0xffe7 ilr2 l10 [1:0] 16-bit reload timer ch. 0 irq11 0xffe4 0xffe5 ilr2 l11 [1:0] 8/16-bit ppg ch. 0 (upper) irq12 0xffe2 0xffe3 ilr3 l12 [1:0] 8/16-bit ppg ch. 0 (lower) irq13 0xffe0 0xffe1 ilr3 l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 0xffde 0xffdf ilr3 l14 [1:0] 16-bit ppg timer ch. 0 irq15 0xffdc 0xffdd ilr3 l15 [1:0] i 2 c bus interface ch. 0 irq16 0xffda 0xffdb ilr4 l16 [1:0] 16-bit ppg timer ch. 1 irq17 0xffd8 0xffd9 ilr4 l17 [1:0] 8/10-bit a/d converter irq18 0xffd6 0xffd7 ilr4 l18 [1:0] time-base timer irq19 0xffd4 0xffd5 ilr4 l19 [1:0] watch prescaler irq20 0xffd2 0xffd3 ilr5 l20 [1:0] watch counter external interrupt ch. 10 irq21 0xffd0 0xffd1 ilr5 l21 [1:0] external interrupt ch. 11 external interrupt ch. 12 external interrupt ch. 13 comparator ch. 0 8/16-bit composite timer ch. 1 (lower) irq22 0xffce 0xffcf ilr5 l22 [1:0] flash memory irq23 0xffcc 0xffcd ilr5 l23 [1:0]
mb95810k series document number: 002-04694 rev. *a page 75 of 121 17. pin states in each mode pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 pf0/x0 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1 * 2 -hi-z - input blocked* 1 * 2 - previous state kept - input blocked* 1 * 2 -hi-z - input blocked* 1 * 2 -hi-z - input enabled* 3 (however, it does not function.) pf1/x1 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1 * 2 -hi-z - input blocked* 1 * 2 - previous state kept - input blocked* 1 * 2 -hi-z - input blocked* 1 * 2 -hi-z - input enabled* 3 (however, it does not function.) pf2/rst reset input* 4 reset input* 4 reset input reset input reset input reset input reset input* 4 i/o port i/o port - previous state kept - input blocked* 1 * 2 -hi-z - input blocked* 1 * 2 - previous state kept - input blocked* 1 * 2 -hi-z - input blocked* 1 * 2 -hi-z - input enabled* 3 (however, it does not function.) pg1/x0a oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1 * 2 -hi-z* 5 - input blocked* 1 * 2 - previous state kept - input blocked* 1 * 2 -hi-z* 5 - input blocked* 1 * 2 -hi-z - input enabled* 3 (however, it does not function.) pg2/x1a oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1 * 2 -hi-z* 5 - input blocked* 1 * 2 - previous state kept - input blocked* 1 * 2 -hi-z* 5 - input blocked* 1 * 2 -hi-z - input enabled* 3 (however, it does not function.) p00/int00 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 * 6 -hi-z* 5 - input blocked* 2 * 6 - previous state kept - input blocked* 2 * 6 -hi-z* 5 - input blocked* 2 * 6 -hi-z - input enabled* 3 (however, it does not function.) p01/int01 p02/int02 p03/int03 p04/int04 p05/int05 p06/int06 p07/int07 p10/ui0 p11/uo0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.)
mb95810k series document number: 002-04694 rev. *a page 76 of 121 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p12/dbg i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p13/uck0/ trg0/adtg i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 -hi-z - input enabled* 3 (however, it does not function.) p14/ppg0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p20/ppg00 p21/ppg01 p22/to00 p23/to01 p24/ec0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 -hi-z - input enabled* 3 (however, it does not function.) p32/an02/ cmp0_o i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept* 8 - input blocked* 2 -hi-z* 5 - input blocked* 2 - previous state kept* 8 - input blocked* 2 -hi-z* 5 - input blocked* 2 -hi-z - input blocked* 2 p35/an05/ cmp1_o p30/an00/ cmp0_n i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 2, * 7 -hi-z* 5 - input blocked* 2, * 7 - previous state kept - input blocked* 2, * 7 -hi-z* 5 - input blocked* 2, * 7 -hi-z - input blocked* 2 p31/an01/ cmp0_p p33/an03/ cmp1_n p34/an04/ cmp1_p p36/an06 i/o port/ analog input i/o port/ analog input - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 -hi-z - input blocked* 2 p37/an07 p40/an08 p41/an09 p42/an10 p43/an11 p50/scl i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2, * 9 -hi-z - input blocked* 2, * 9 - previous state kept - input blocked* 2, * 9 -hi-z - input blocked* 2, * 9 -hi-z - input enabled* 3 (however, it does not function.) p51/sda
mb95810k series document number: 002-04694 rev. *a page 77 of 121 spl: pin state setting bit in the standby control register (stbc:spl) hi-z: high impedance *1: the pin stays at the state shown when co nfigured as a general-purpose i/o port. *2: ?input blocked? means direct input ga te operation from the pin is disabled. *3: ?input enabled? means that the input function is enabled . while the input function is enabled, a pull-up or pull-down operation has to be performed in order to prevent leaks due to external input. if a pin is used as an output port, its pin state is the same as that of other ports. *4: the pf2/rst pin stays at the state shown w hen configured as a reset pin. *5: the pull-up control sett ing is still effective. *6: though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *7: though input is blocked, an analog signal can also be in put to generate a comparator interrupt when the comparator interrupt is enabled. *8: the output function of the co mparator is still in operati on in stop mode and watch mode. *9: the i 2 c bus interface can wake up the mcu in stop mode or watch mode when its mcu standby mode wakeup func- tion is enabled. for details of the mcu standb y mode wakeup function, refer to ?chapter 24 i 2 c bus interface? in ?new 8fx mb95810k series hardware manual?. pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p52/ppg1 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p53/trg1 p60/ppg10 p61/ppg11 p62/to10 p63/to11 p64/ec1 p66/sot p65/sck i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 -hi-z - input enabled* 3 (however, it does not function.) p67/sin p70/to0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p71/ti0 p72 i/o port i/o port - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 5 - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p80 p81 p82 p83/trg0/ adtg i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 - previous state kept - input blocked* 2, * 6 -hi-z* 5 - input blocked* 2, * 6 -hi-z - input enabled* 3 (however, it does not function.) pe0/int10 pe1/int11 pe2/int12 pe3/int13
mb95810k series document number: 002-04694 rev. *a page 78 of 121 18. electrical characteristics 18.1 absolute maximum ratings *1: these parameters are based on the condition that v ss is 0.0 v. *2: apply equal potential to av cc and v cc . avr must not exceed av cc . *3: v 1 and v 0 must not exceed v cc ? 0.3 v. v 1 must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *4: specific pins: p00 to p07, p10, p11, p13, p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p60 to p67, p70 to p72, p80 to p83, pe0 to pe3, pf0, pf1, pg1, pg2 ? use under recommended operating conditions. ? use with dc voltage (current). parameter symbol rating unit remarks min max power supply voltage* 1 av cc , v cc v ss ?? 0.3 v ss ? 6v *2 avr v ss ?? 0.3 v ss ? 6v input voltage* 1 v i v ss ?? 0.3 v ss ? 6v*3 output voltage* 1 v o v ss ?? 0.3 v ss ? 6v*3 maximum clamp current i clamp ? 2 ? 2 ma applicable to specific pins* 4 total maximum clamp current ? |i clamp | ? 20 ma applicable to specific pins* 4 ?l? level maximum output current i ol ?15ma ?l? level average current i olav1 ? 4 ma other than p00 to p07 average output current = operating current ? operating ratio (1 pin) i olav2 12 p00 to p07 average output current = operating current ? operating ratio (1 pin) ?l? level total maximum output current ? i ol ? 100 ma ?l? level total average output current ? i olav ?37ma total average output current = operating current ? operating ratio (total number of pins) ?h? level maximum output current i oh ? ? 15 ma ?h? level average current i ohav1 ? ? 4 ma other than p00 to p07 average output current = operating current ? operating ratio (1 pin) i ohav2 ? 8 p00 to p07 average output current = operating current ? operating ratio (1 pin) ?h? level total maximum output current ? i oh ? ? 100 ma ?h? level total average output current ? i ohav ? ? 47 ma total average output current = operating current ? operating ratio (total number of pins) power consumption p d ? 320 mw operating temperature t a ? 40 ? 85 ? c storage temperature t stg ? 55 ? 150 ? c
mb95810k series document number: 002-04694 rev. *a page 79 of 121 ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontro ller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a valu e at which the current to be input to the microcontroller pin when the hv (high voltage) signal is in put is below the standard value, irrespecti ve of whether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcon troller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, si nce power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: warning: semiconductor devices may be permanently da maged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolu te maximum ratings. do not exceed any of these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor ? input/output equivalent circuit
mb95810k series document number: 002-04694 rev. *a page 80 of 121 18.2 recommended operating conditions (v ss = 0.0 v) *: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distan ce between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be und er their recommended op erating condition. operation under any conditio ns other than these conditions may adve rsely affect reliab ility of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. parameter symbol value unit remarks min max power supply voltage av cc , v cc 2.88 5.5 v a/d converter reference input voltage avr av cc ?? 0.1 av cc v decoupling capacitor c s 0.022 1 f * operating temperature t a ? 40 ? 85 ? c other than on-chip debug mode ? 5 ? 35 on-chip debug mode c cs dbg * rst ? dbg / rst / c pins connection diagram *: connect the dbg pin to an exte rnal pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not stay at ?l? level until the rese t output is released. the dbg pin becomes a com- munication pin in debug mode. since the actual pull- up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
mb95810k series document number: 002-04694 rev. *a page 81 of 121 18.3 dc characteristics (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85 c) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ihi p10, p50, p51, p67 ? 0.7 v cc ?v cc ? 0.3 v cmos input level v ihs other than p10, p50, p51, p67, pf2 ? 0.8 v cc ?v cc ? 0.3 v hysteresis input v ihm pf2 ? 0.8 v cc ?v cc ? 0.3 v hysteresis input ?l? level input voltage v ili p10, p50, p51, p67 ?v ss ?? 0.3 ? 0.3 v cc v cmos input level v ils other than p10, p50, p51, p67, pf2 ?v ss ?? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ?? 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d p12, p50, p51, pf2 ?v ss ?? 0.3 ? v ss ? 5.5 v ?h? level output voltage v oh1 output pins other than p00 to p07, p12, pf2 i oh = ? 4 ma v cc ?? 0.5 ? ? v v oh2 p00 to p07 i oh = ? 8 ma v cc ?? 0.5 ? ? v ?l? level output voltage v ol1 output pins other than p00 to p07 i ol = 4 ma ? ? 0.4 v v ol2 p00 to p07 i ol = 12 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc ? 5? ? 5a when the internal pull-up resistor is disabled internal pull-up resistor r pull other than p12, p50, p51, pf0 to pf2 v i = 0 v 25 50 100 k ? when the internal pull-up resistor is enabled input capacitance c in other than av cc , av ss , avr, v cc and v ss f = 1 mhz ? 5 15 pf
mb95810k series document number: 002-04694 rev. *a page 82 of 121 (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85 c) parameter symbol pin name condition value unit remarks min typ* 1 max* 2 power supply current* 3 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?4.85.8ma except during flash memory programming and erasing ? 10.1 13.8 ma during flash memory programming and erasing i ccs f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?1.9 3ma i ccl f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = ? 25 c ? 65.9 145 a i ccls f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = ? 25 c ?11.216 a in deep standby mode i cct f cl = 32 khz watch mode main stop mode t a = ? 25 c ?8.613 a in deep standby mode i ccmpll v cc f mcrpll = 16 mhz f mp = 16 mhz main cr pll clock mode (multiplied by 4) t a = ? 25 c ?5.16.8ma i ccmcr f crh = 4 mhz f mp = 4 mhz main cr clock mode ?1.44.6ma i ccscr sub-cr clock mode (divided by 2) t a = ? 25 c ? 63.1 230 a i ccts v cc (external clock operation) f ch = 32 mhz time-base timer mode t a = ? 25 c ?360455a in deep standby mode i cch substop mode t a = ? 25 c ?8.813a in deep standby mode
mb95810k series document number: 002-04694 rev. *a page 83 of 121 (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85 c) *1: v cc = 5.0 v, t a = ? 25 c *2: v cc = 5.5 v, t a = ? 85 c (unless otherwise specified) *3: ? the power supply current is determined by the external clock. when the low-voltage detection reset circuit is se- lected, the power supply current is the sum of adding th e current consumption of the low-voltage detection reset circuit (i lvd ) to one of the values from i cc to i cch . in addition, when both the low-voltage detection reset circuit and a cr oscillator are selected, the power su pply current is the sum of adding up the current consumption of the low- voltage detection reset circuit (i lvd ), the current consumption of the cr oscillators (i crh or i crl ) and one of the val- ues from i cc to i cch . in on-chip debug mode, the main cr oscillator (i crh ) and the low-voltage detection reset circuit are always in operation, and current consumption therefore increases accordingly. ? see ?4. ac characteristics clock timing? for f ch , f cl , f crh and f mcrpll . ? see ?4. ac characteristics so urce clock/machin e clock? for f mp and f mpl . ? the power supply current value in standby mode is meas ured in deep standby mode. the current consumption in normal standby mode is higher than that in deep standby mode. the power supply current value in normal standby mode can be found by adding the current consumption difference between normal st andby mode and deep standby mode (i nstby ) to the power supply current value in deep standby mode. for details of normal standby mode and deep standby mode, refer to ?chapter 3 clock controller? in ?new 8fx mb95810k series hardware manual?. parameter symbol pin name condition value unit remarks min typ* 1 max* 2 power supply current* 3 i v v cc current consumption of the comparator ? 60 160 a i lvd current consumption of the low-voltage detection reset circuit ?4 7a with the lvd reset already enabled by the lvd reset circuit control register (lvdcc) i crh current consumption of the main cr oscillator ? 240 320 a i crl current consumption of the sub-cr oscillator oscillating at 100 khz ?720a i nstby current consumption difference between normal standby mode and deep standby mode t a = ? 25 c ?2230a i a av cc v cc = 5.5 v f ch = 16 mhz current consumption of the a/d converter ?23.1ma i ah f crh = 4 mhz f mp = 4 mhz current consumption with the a/d converter halted t a = ? 25 c ?1 5a
mb95810k series document number: 002-04694 rev. *a page 84 of 121 18.4 ac characteristics 18.4.1 clock timing (v cc = 2.88 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1: open 1 ? 12 mhz when the main external clock is used x0, x1 * 1 ? 32.5 mhz f crh ?? 3.92 4 4.08 mhz operating conditions ? the main cr clock is used. ?0 ? c ?? t a ??? 70 ? c 3.8 4 4.2 mhz operating conditions ? the main cr clock is used. ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c f mcrpll ?? 7.84 8 8.16 mhz operating conditions ? pll multiplication rate: 2 ?0 ? c ?? t a ??? 70 ? c 7.6 8 8.4 mhz operating conditions ? pll multiplication rate: 2 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 9.8 10 10.2 mhz operating conditions ? pll multiplicat ion rate: 2.5 ?0 ? c ?? t a ??? 70 ? c 9.5 10 10.5 mhz operating conditions ? pll multiplicat ion rate: 2.5 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 11.76 12 12.24 mhz operating conditions ? pll multiplication rate: 3 ?0 ? c ?? t a ??? 70 ? c 11.4 12 12.6 mhz operating conditions ? pll multiplication rate: 3 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 15.68 16 16.32 mhz operating conditions ? pll multiplication rate: 4 ?0 ? c ?? t a ??? 70 ? c 15.2 16 16.8 mhz operating conditions ? pll multiplication rate: 4 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c f cl x0a, x1a ? ? 32.768 ? khz when the suboscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 150 khz when the sub-cr clock is used
mb95810k series document number: 002-04694 rev. *a page 85 of 121 (v cc = 2.88 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: the external clock signal is input to x0 and the inverted external clock signal to x1. parameter symbol pin name condition value unit remarks min typ max clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1: open 83.4 ? 1000 ns when an external clock is used x0, x1 * 30.8 ? 1000 ns t lcyl x0a, x1a ?? 30.5 ? s when the subclock is used input clock pulse width t wh1 , t wl1 x0 x1: open 33.4 ?? ns when an external clock is used, the duty ratio should range between 40% and 60%. x0, x1 * 12.4 ?? ns t wh2 , t wl2 x0a ? ?15.2 ? s input clock rising time and falling time t cr , t cf x0, x0a x1: open ? ? 5ns when an external clock is used x0, x1, x0a, x1a *??5ns cr oscillation start time t crhwk ????50s when the main cr clock is used t crlwk ????30s when the sub-cr clock is used pll oscillation start time t mcrpllwk ????100s when the main cr pll clock is used x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf ? input waveform generated when an external clock (main clock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0 x1 x0 x1 f ch f ch when an external clock is used (x1 is open) x0 x1 open f ch ? figure of main clock inpu t port external connection
mb95810k series document number: 002-04694 rev. *a page 86 of 121 x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf ? input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0a x1a x0a x1a open f cl f cl ? figure of subclock input port external connection t crhwk 1/f crh main cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr clock) is used t crlwk 1/f crl sub-cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (sub-cr clock) is used
mb95810k series document number: 002-04694 rev. *a page 87 of 121 t mcrpllwk 1/f mcrpll main cr pll clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr pll clock) is used
mb95810k series document number: 002-04694 rev. *a page 88 of 121 18.4.2 source clock/machine clock (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: this is the clock before it is divided according to the di vision ratio set by the machine cl ock division ratio select bits (sycc:div[1:0]). this source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (sycc:div[1:0]). in addit ion, a source clock can be selected from the follow- ing. ? main clock divided by 2 ? main cr clock ? pll multiplication of main cr clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontrolle r. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 62.5 ? 1000 ns when the main cr clock is used min: f crh = 4 mhz, multiplied by 4 max: f crh = 4 mhz, divided by 4 ?61?s when the suboscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used ? 4 12.5 mhz when the main cr clock is used f spl ? 16.384 ? khz when the subo scillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 250 ? 4000 ns when the main cr clock is used min: f sp = 4 mhz, no division max: f sp = 4 mhz, divided by 16 61 ? 976.5 s when the suboscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.25 ? 16 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the s uboscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
mb95810k series document number: 002-04694 rev. *a page 89 of 121 f ch (main oscillation clock) divided by 2 divided by 2 divided by 2 f mcrpll (main cr pll clock) f crh (main cr clock) f cl (suboscillation clock) f crl (sub-cr clock) sclk (source clock) mclk (machine clock) machine clock divide ratio select bits (sycc:div[1:0]) clock mode select bits (sycc:scs[2:0]) division circuit 1 1/4 1/8 1/16 ? schematic diagram of the clock generation block operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.7 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) ? operating voltage - operating frequency (t a = ? 40 c to ? 85 c)
mb95810k series document number: 002-04694 rev. *a page 90 of 121 18.4.3 external reset (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?source clock/machine clock? for t mclk . 18.4.4 power-on reset (v ss = 0.0 v, t a = ? 40 c to ? 85 c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * ? ns parameter symbol condition value unit remarks min max power supply rising time t r ?? 50 ms power supply cutoff time t off ? 1 ? ms wait time until power-on 0.2 v cc rst 0.2 v cc t rstl 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode set the slope of rising to a value below 30 mv/ms.
mb95810k series document number: 002-04694 rev. *a page 91 of 121 18.4.5 peripheral input timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?source clock/machine clock? for t mclk . 18.4.6 lin-uart timing sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is disabled* 2 . (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0, trg1 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t slovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivshi sck, sin t mclk * 3 ? 80 ? ns sck ? ? valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf ? 1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 ? 10 ? ns sck ? ? sot delay time t slove sck, sot ? 2 t mclk * 3 ? 60 ns valid sin ? sck ? t ivshe sck, sin 30 ? ns sck ? ? valid sin hold time t shixe sck, sin t mclk * 3 ? 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns int00 to int07, int10 to int13, ec0, ec1, ti0, trg0, trg1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95810k series document number: 002-04694 rev. *a page 92 of 121 0.2 v cc 0.2 v cc 0.8 v cc t slovi t ivshi t shixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slove t ivshe t shixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t slsh t shsl t r 0.8 v cc t f ? external shift clock mode
mb95810k series document number: 002-04694 rev. *a page 93 of 121 sampling is executed at the falling edge of the sampling clock* 1 , and serial clock delay is disabled* 2 . (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t shovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivsli sck, sin t mclk * 3 ? 80 ? ns sck ?? valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf ? 1 ttl 3 t mclk * 3 ?? t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 ? 10 ? ns sck ? ? sot delay time t shove sck, sot ? 2 t mclk * 3 ? 60 ns valid sin ? sck ? t ivsle sck, sin 30 ? ns sck ?? valid sin hold time t slixe sck, sin t mclk * 3 ? 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns 0.2 v cc 0.8 v cc 0.8 v cc t shovi t ivsli t slixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode
mb95810k series document number: 002-04694 rev. *a page 94 of 121 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shove t ivsle t slixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t shsl t slsh t f 0.8 v cc t r ? external shift clock mode
mb95810k series document number: 002-04694 rev. *a page 95 of 121 sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is enabled* 2 . (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ??? sot delay time t shovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivsli sck, sin t mclk * 3 ? 80 ? ns sck ?? valid sin hold time t slixi sck, sin 0 ? ns sot ? sck ? delay time t sovli sck, sot 3t mclk * 3 ?? 70 ? ns 0.8 v cc 0.2 v cc 0.2 v cc t shovi t sovli t ivsli t slixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc
mb95810k series document number: 002-04694 rev. *a page 96 of 121 sampling is executed at the falling edge of the sampling clock* 1 , and serial clock delay is enabled* 2 . (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t slovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivshi sck, sin t mclk * 3 ? 80 ? ns sck ? ? valid sin hold time t shixi sck, sin 0 ? ns sot ? sck ? delay time t sovhi sck, sot 3t mclk * 3 ?? 70 ? ns 0.2 v cc 0.8 v cc 0.8 v cc t slovi t sovhi t ivshi t shixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc
mb95810k series document number: 002-04694 rev. *a page 97 of 121 18.4.7 low-voltage detection (v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: after the lvd reset is enabled by the lvd reset circuit cont rol register (lvdcc), the rel ease voltage and the detection voltage can be selected by using the lvd reset voltage select ion id register (lvdr) in t he low-voltage detection reset circuit. for details of the lvdcc register and th e lvdr register, refer to ?chapter 17 low-voltage detection reset circuit? in ?new 8fx mb95810k series hardware manual?. parameter symbol value unit remarks min typ max release voltage* v dl ? 2.52 2.7 2.88 v at power supply rise 2.61 2.8 2.99 2.89 3.1 3.31 3.08 3.3 3.52 detection voltage* v dl ? 2.43 2.6 2.77 v at power supply fall 2.52 2.7 2.88 2.80 3 3.20 2.99 3.2 3.41 hysteresis width v hys ??100mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 650 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 650 ? ? s slope of power supply that the reset release signal generates within the rating (v dl- ) reset release delay time t d1 ??30s reset detection delay time t d2 ??30s lvd reset threshold voltage transition stabilization time t stb 10 ? ? s
mb95810k series document number: 002-04694 rev. *a page 98 of 121 v hys t d2 t d1 t r t f v cc v on v off v dl+ v dl- time time internal reset signal
mb95810k series document number: 002-04694 rev. *a page 99 of 121 18.4.8 i 2 c bus interface timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: the maximum t hd;dat in the standard-mode is applicab le only when the time during which the device is holding the scl signal at ?l? (t low ) does not extend. *3: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, provided that the condition of t su;dat ? 250 ns is fulfilled. parameter symbol pin name condition value unit standard- mode fast-mode min max min max scl clock frequency f scl scl r = 1.7 k ? , c = 50 pf* 1 01000400khz (repeated) start condition hold time sda ??? scl ? t hd;sta scl, sda 4.0 ? 0.6 ? s scl clock ?l? width t low scl 4.7 ? 1.3 ? s scl clock ?h? width t high scl 4.0 ? 0.6 ? s (repeated) start condition setup time scl ??? sda ? t su;sta scl, sda 4.7 ? 0.6 ? s data hold time scl ??? sda ?? t hd;dat scl, sda 0 3.45 *2 00.9 *3 s data setup time sda ???? scl ? t su;dat scl, sda 0.25 ? 0.1 ? s stop condition setup time scl ? ? sda ? t su;sto scl, sda 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl, sda 4.7 ? 1.3 ? s sda scl t wakeup t hd;sta t su;dat f scl t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
mb95810k series document number: 002-04694 rev. *a page 100 of 121 (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter symbol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k ? , c = 50 pf* 1 (2 ? nm/2)t mclk ? 20 ? ns master mode scl clock ?h? width t high scl (nm/2)t mclk ? 20 (nm/2)t mclk ? 20 ns master mode start condition hold time t hd;sta scl, sda0 (-1 ? nm/2)t mclk ? 20 (-1 ? nm)t mclk ? 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl, sda (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode start condition setup time t su;sta scl, sda (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode bus free time between stop condition and start condition t buf scl, sda (2 nm ? 4) t mclk ? 20 ? ns data hold time t hd;dat scl, sda 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl, sda (-2 ? nm/2) t mclk ? 20 (-1 ? nm/2) t mclk ? 20 ns master mode it is assumed that ?l? of scl is not extended. the minimum value is applied to the first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl (nm/2) t mclk ? 20 (1 ? nm/2) t mclk ? 20 ns the minimum value is applied to the interrupt at the ninth scl ? . the maximum value is applied to the interrupt at the eighth scl ? . scl clock ?l? width t low scl 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl 4 t mclk ? 20 ? ns at reception
mb95810k series document number: 002-04694 rev. *a page 101 of 121 (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda0 lines. *2: ? see ?source clock/machine clock? for t mclk . ? m represents the cs[4:3] bits in the i 2 c clock control register (iccr0). ? n represents the cs[2:0] bits in the i 2 c clock control register (iccr0). ? the actual timing of the i 2 c bus interface is determined by the val ues of m and n set by the machine clock (t mclk ) and the cs[4:0] bits in the iccr0 register. ? standard-mode: m and n can be set to values in the following range: 0.9 mhz ? t mclk (machine clock) ? 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 mhz < t mclk ? 1 mhz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 mhz < t mclk ? 2 mhz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 mhz < t mclk ? 4 mhz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 mhz < t mclk ? 10 mhz (m, n) = (8, 22) : 0.9 mhz < t mclk ? 16.25 mhz ? fast-mode: m and n can be set to values in the following range: 3.3 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 mhz < t mclk ? 4 mhz (m, n) = (1, 22), (5, 4) : 3.3 mhz < t mclk ? 8 mhz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 mhz < t mclk ? 10 mhz (m, n) = (5, 8) : 3.3 mhz < t mclk ? 16.25 mhz parameter symbol pin name condition value* 2 unit remarks min max start condition detection t hd;sta scl, sda r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns no start condition is detected when 1 t mclk is used at reception. stop condition detection t su;sto scl, sda 2 t mclk ? 20 ? ns no stop condition is detected when 1 t mclk is used at reception. restart condition detection condition t su;sta scl, sda 2 t mclk ? 20 ? ns no restart condition is detected when 1 t mclk is used at reception. bus free time t buf scl, sda 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl, sda 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl, sda t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl, sda 0 ? ns at reception data setup time t su;dat scl, sda t mclk ? 20 ? ns at reception sda ? ? scl ? (with wakeup function in use) t wakeup scl, sda oscillation stabilization wait time ? 2 t mclk ? 20 ?ns
mb95810k series document number: 002-04694 rev. *a page 102 of 121 18.4.9 uart/sio, serial i/o timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck0 internal clock operation 4 t mclk *? ns uck ??? uo time t slov uck0, uo0 ? 190 ? 190 ns valid ui ? uck ? t ivsh uck0, ui0 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, ui0 2 t mclk *? ns serial clock ?h? pulse width t shsl uck0 external clock operation 4 t mclk *? ns serial clock ?l? pulse width t slsh uck0 4 t mclk *? ns uck ??? uo time t slov uck0, uo0 ? 190 ns valid ui ? uck ? t ivsh uck0, ui0 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, ui0 2 t mclk *? ns 0.2 v cc 0.2 v cc 0.8 v cc t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0 uo0 ui0 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode
mb95810k series document number: 002-04694 rev. *a page 103 of 121 18.4.10 comparator timing (v cc = 2.88 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) 18.4.11 bgr for comparator (v cc = 2.88 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter pin name value unit remarks min typ max voltage range cmp0_p, cmp0_n, cmp1_p, cmp1_n 0?v cc ? 1.3 v offset voltage cmp0_p, cmp0_n, cmp1_p, cmp1_n ? 15 ? ? 15 mv delay time cmp0_o, cmp1_o ? 650 1200 ns overdrive 5 mv ? 140 420 ns overdrive 50 mv power down delay cmp0_o, cmp1_o ? ? 1200 ns power down recovery pd: 1 ? 0 power up stabilization wait time cmp0_o, cmp1_o ? ? 1200 ns output stabilization time at power up parameter symbol value unit remarks min typ max power up stabilization wait time ? ? ? 150 s load: 10 pf output voltage vbgr 1.1495 1.21 1.2705 v t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0 uo0 ui0 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slsh t shsl ? external shift clock mode
mb95810k series document number: 002-04694 rev. *a page 104 of 121 18.5 a/d converter 18.5.1 a/d converter electrical characteristics (av cc = v cc = 2.7 v to 5.5 v, av ss = v ss = 0.0 v, t a = ? 40 c to ? 85 c) 18.5.2 notes on using a/d converter ? external impedance of analog input and its sampling time the a/d converter of has a sample and hold circuit. if the ex ternal impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the intern al sample and hold circuit is insufficient, adversely af- fecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, considering the rela- tionship between the external impedance and minimum samp ling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. in addi- tion, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. parameter symbol value unit remarks min typ max resolution ? ??10bit to t a l e r r o r ? 3? ? 3lsb linearity error ? 2.5 ? ? 2.5 lsb differential linearity error ? 1.9 ? ? 1.9 lsb zero transition voltage v 0t av ss ?? 7.2 lsb av ss ? 0.5 lsb av ss ? 8.2 lsb v full-scale transition voltage v fst avr ?? 6.2 lsb avr ?? 1.5 lsb avr ? 9.2 lsb v compare time ? 3 ? 10 s 2.7 v ? av cc ? 5.5 v sampling time ? 0.941 ? ? s 2.7 v ? av cc ? 5.5 v, with external impedance ? 3.3 k ? and external capacitance = 10 pf analog input current i ain ? 0.3 ? ? 0.3 a analog input voltage v ain av ss ?avrv reference voltage ? av cc ?? 0.1 ? av cc v voltage applied to the avr pin note: the values are reference values. 4.5 v av cc 5.5 v 2.7 v av cc < 4.5 v 1.45 k (max) 2.7 k (max) 14.89 pf (max) v cc r c 14.89 pf (max) comparator analog input during sampling: on r c ? analog input equivalent circuit
mb95810k series document number: 002-04694 rev. *a page 105 of 121 ? a/d conversion error as |avr ? av ss | decreases, the a/d conversion error increases proportionately. [external impedance = 0 k to 100 k ] external impedance [k ] minimum sampling time [ s] 02468101214161820 100 80 60 40 20 0 [external impedance = 0 k to 20 k ] external impedance [k ] minimum sampling time [ s] 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 20 15 10 5 0 note: external capacitance = 10 pf ? relationship between external impedance and minimum sampling time
mb95810k series document number: 002-04694 rev. *a page 106 of 121 18.5.3 definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?0000000000? ? ? ?0000000001?) of a device to the full-scale transition point (?1111111111? ? ? ?1111111110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a th eoretical value. the error ca n be caused by a zero tran- sition error, a full-scale transition errors, a linearity error, a quantum error, or noise. v fst ideal i/o characteristics 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff digital output digital output 2 lsb v 0t 1 lsb 0.5 lsb total error analog input analog input 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn {1 lsb (n ? 1) + 0.5 lsb} v nt total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb lsb = avr ? av ss 1024 v 1 lsb = avr av ss avr av ss
mb95810k series document number: 002-04694 rev. *a page 107 of 121 zero transition error linearity error full-scale transition error 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff digital output differential linearity error of digital output n v (n + 1)t ? v nt 1 lsb ? 1 = linearity error of digital output n v nt ? {1 lsb n + v 0t } 1 lsb = digital output analog input 0x001 0x002 0x3fc 0x3fd 0x003 0x3fe 0x3ff 0x004 actual conversion characteristic actual conversion characteristic v 0t (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) avr av ss avr av ss avr av ss avr av ss analog input digital output analog input ideal characteristic {1 lsb n + v 0t } actual conversion characteristic ideal characteristic actual conversion characteristic v 0t (measurement value) v fst (measurement value) v nt differential linearity error 0x(n ? 2) 0x(n ? 1) 0xn 0x(n + 1) digital output analog input actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n + 1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn v 0t (ideal value) = avr + 0.5 lsb [v] v fst (ideal value) = av ss ? 2 lsb [v] ideal characteristic
mb95810k series document number: 002-04694 rev. *a page 108 of 121 18.6 flash memory program/erase characteristics *1: v cc = 5.5 v, t a = ? 25 c, 0 cycle *2: v cc = 2.4 v, t a = ? 85 c, 100000 cycles *3: these values were converted from the result of a techno logy reliability assessment. (t hese values were converted from the result of a high temperature accelerated test us ing the arrhenius equation with the average temperature being ? 85 c.) parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.3* 1 1.6* 2 s the time of writing ?0x00? prior to erasure is excluded. sector erase time (32 kbyte sector) ?0.6* 1 3.1* 2 s the time of writing ?0x00? prior to erasure is excluded. byte writing time ? 17 272 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 2.4 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = ? 85 c number of program/erase cycles: 1000 or below 10* 3 ?? average t a = ? 85 c number of program/erase cycles: 1001 to 10000 inclusive 5* 3 ?? average t a = ? 85 c number of program/erase cycles: 10001 or above
mb95810k series document number: 002-04694 rev. *a page 109 of 121 19. sample characteristics ? power supply current temp erature characteristics 0 5 15 10 20 ? 50 0 + 50 + 100 + 150 i cc [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc ? t a v cc ? 5.5 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the ex ternal clock operating 0 5 15 10 20 234567 i cc [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating 0 2 6 4 8 10 234567 i ccs [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 2 6 4 10 8 ? 50 0 + 50 + 100 + 150 i ccs [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 20 60 40 100 80 234567 i ccl [ a] v cc [v] 0 25 60 40 100 80 ? 50 0 + 50 + 100 + 150 i ccl [ a] t a [ c] i ccs ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccs ? t a v cc ? 5.5 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccl ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) subclock mode with the external clock operating i ccl ? t a v cc ? 5.5 v, f mpl ? 16 khz (divided by 2) subclock mode with the external clock operating
mb95810k series document number: 002-04694 rev. *a page 110 of 121 0 30 20 10 60 50 40 80 70 ? 50 0 + 50 + 100 + 150 i cct [ a] t a [ c] i cct ? t a v cc ? 5.5 v, f mpl ? 16 khz (divided by 2) watch mode with the external clock operating 0 30 20 10 60 50 40 80 70 ? 50 0 + 50 + 100 + 150 i ccls [ a] t a [ c] i ccls ? t a v cc ? 5.5 v, f mpl ? 16 khz (divided by 2) subsleep mode with the external clock operating 0 10 40 30 20 80 70 60 50 234567 i ccls [ a] v cc [v] 0 10 40 30 20 80 70 60 50 234567 i cct [ a] v cc [v] 0.0 1.2 1.0 0.8 0.6 0.4 0.2 1.4 234567 i ccts [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0.0 0.2 1.0 0.8 0.6 0.4 1.4 1.2 ? 50 0 + 50 + 100 + 150 i ccts [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i ccls ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) subsleep mode with the external clock operating i cct ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) watch mode with the external clock operating i ccts ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i ccts ? t a v cc ? 5.5 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating
mb95810k series document number: 002-04694 rev. *a page 111 of 121 0 5 15 10 20 ? 50 0 + 50 + 100 + 150 i cch [ a] t a [ c] i cch ? t a v cc ? 5.5 v, f mpl ? (stop) substop mode with the external clock stopping 0 5 15 10 20 2 1 34567 i cch [ a] v cc [v] 0 5 15 10 20 234567 i ccmcr [ma] v cc [v] 0 5 15 10 20 ? 50 0 + 50 + 100 + 150 i ccmcr [ma] t a [ c] 0 2 6 4 10 8 2 1 34567 i ccmpll [ma] v cc [v] 0 2 8 6 4 10 ? 50 0 + 50 + 100 + 150 i ccmpll [ma] t a [ c] i cch ? v cc t a ? ? 25 ? c, f mpl ? (stop) substop mode with the external clock stopping i ccmcr ? v cc t a ? ? 25 ? c, f mp ? 4 mhz (no division) main cr clock mode i ccmcr ? t a v cc ? 5.5 v, f mp ? 4 mhz (no division) main cr clock mode i ccmpll ? v cc t a ? ? 25 ? c, f mp ? 16 mhz (pll multiplication rate: 4) main cr pll clock mode i ccmpll ? t a v cc ? 5.5 v, f mp ? 16 mhz (pll mult iplication rate: 4) main cr pll clock mode
mb95810k series document number: 002-04694 rev. *a page 112 of 121 0 50 150 100 200 ? 50 0 + 50 + 100 + 150 i ccscr [ a] t a [ c] i ccscr ? t a v cc ? 5.5 v, f mpl ? 50 khz (divided by 2) sub-cr clock mode 0 50 150 100 200 234567 i ccscr [ a] v cc [v] i ccscr ? v cc t a ? ? 25 ? c, f mpl ? 50 khz (divided by 2) sub-cr clock mode
mb95810k series document number: 002-04694 rev. *a page 113 of 121 ? input voltage characteristics 0 1 2 4 5 234567 v ihi /v ili [v] v cc [v] 3 v ihi v ili 0 1 2 4 5 234567 v ihs /v ils [v] v cc [v] 3 v ihs v ils v ihi ? v cc and v ili ? v cc t a ? ? 25 ? c v ihs ? v cc and v ils ? v cc t a ? ? 25 ? c 0 1 2 4 5 234567 v ihm /v ilm [v] v cc [v] 3 v ihm v ilm v ihm ? v cc and v ilm ? v cc t a ? ? 25 ? c
mb95810k series document number: 002-04694 rev. *a page 114 of 121 ? output voltage characteristics 0.0 0.2 0.4 0.8 1.4 2.0 1.8 1.6 1.2 1.0 0 ? 2 ? 1 ? 3 ? 5 ? 7 ? 9 ? 4 ? 6 ? 8 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 v cc ? v oh2 [v] i oh [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh2 ) ? i oh t a ? ? 25 ? c v ol1 ? i ol t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.4 2.0 1.8 1.6 1.2 1.0 0 ? 2 ? 1 ? 3 ? 5 ? 7 ? 9 ? 4 ? 6 ? 8 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 v cc ? v oh1 [v] i oh [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh1 ) ? i oh t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.0 02 13579 4 6 8 101112131415 v ol2 [v] i ol [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol2 ? i ol t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.4 2.0 1.8 1.6 1.2 1.0 02 13579 4 6 8 101112131415 v ol1 [v] i ol [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v
mb95810k series document number: 002-04694 rev. *a page 115 of 121 ? pull-up characteristics 0 50 100 150 200 23456 r pull [k ] v cc [v] r pull ? v cc t a ? ? 25 ? c
mb95810k series document number: 002-04694 rev. *a page 116 of 121 20. ordering information part number package mb95f814kpmc1-g-sne2 mb95f816kpmc1-g-sne2 mb95f818kpmc1-g-sne2 64-pin plastic lqfp (fpt-64p-m38) mb95f814kpmc-g-sne2 mb95f816kpmc-g-sne2 mb95f818kpmc-g-sne2 MB95F818KPMC-G-UNE2 64-pin plastic lqfp (fpt-64p-m39)
mb95810k series document number: 002-04694 rev. *a page 117 of 121 21. package dimension 64-pin plastic lqfp lead pitch 0.50 mm package width package length 10.00 mm 10.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.32 g 64-pin plastic lqfp (fpt-64p-m38) (fpt-64p-m38) "a" 0.08(.003) (.006 .002) 0.145 0.055 0.08(.003) m (.009 .002) 0.22 0.05 0.50(.020) 12.00 0.20(.472 .008)sq *10.00 0.10(.394 .004)sq index 49 64 33 48 17 32 16 1 2010 fujitsu semiconductor limited f64038s-c-1-2 (stand off) details of "a" part (.004 .004) 0.10 0.10 (.024 .006) 0.60 0.15 (.020 .008) 0.25(.010) c 0.50 0.20 (mounting height) .059 ? .004 +.008 ? 0.10 +0.20 1.50 0~8 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mb95810k series document number: 002-04694 rev. *a page 118 of 121 64-pin plastic lqfp lead pitch 0.65 mm package width package length 12.00 mm 12.00 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.47 g 64-pin plastic lqfp (fpt-64p-m39) (fpt-64p-m39) "a" 0.10(.004) (.006 .002) 0.145 0.055 0.13(.005) m (.013 .002) 0.32 0.05 0.65(.026) 14.00 0.20(.551 .008)sq 12.00 0.10(.472 .004)sq index 49 64 33 48 17 32 16 1 2010-2011 fujitsu semiconductor limited hmbf64-39sc-2-2 details of "a" part (.004 .004) 0.10 0.10 (.024 .006) 0.60 0.15 0.25(.010)bsc c .059 ? .004 +.008 ? 0.10 +0.20 1.50 0~8? (.020 .008) 0.50 0.20 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness.
mb95810k series document number: 002-04694 rev. *a page 119 of 121 22. major changes in this edition spansion publication number: ds702-00015-2v0-e note: please see ?document history ? about later revised information. page section details 18 pin connection ?dbg pin revised details of ?? dbg pin?. ?rst pin revised details of ?? rst pin?. 19 ? c pin corrected the following statement. the bypass capacitor for the v cc pin must have a capacitance larger than c s . ? the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . 79 i/o ports 11. port f (4) port f operations ? operation as an input port added the following statement. for a pin shared with other peripheral functions, disable the output of such peripheral functions. 82 12. port g (4) port g operations ? operation as an input port added the following statement. for a pin shared with other peripheral functions, disable the output of such peripheral functions. 89 electrical ch aracteristics 2. recommended operating conditions corrected the following statem ent in the remark of the parameter ?decoupling capacitor?. the bypass capacitor for the v cc pin must have a capacitance larger than c s . ? the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . revised the remark in ?? dbg/rst /c pins connection diagram?. 90 3. dc characteristics revised the remark of the parameter ?input leak current (hi-z output leak current)?. when pull-up resistance is disabled ? when the internal pull-up resistor is disabled renamed the parameter ?pull-up resistance? to ?internal pull-up resistor?. revised the remark of the parameter ?internal pull-up resistor?. when pull-up resistance is enabled ? when the internal pull-up resistor is enabled 95 4. ac characteristics (1) clock timing corrected the pin names of the parameter ?input clock rising time and falling time?. x0 ? x0, x0a x0, x1 ? x0, x1, x0a, x1a
mb95810k series document number: 002-04694 rev. *a page 120 of 121 document history page document title: mb95810k series, new 8fx 8-bit microcontrollers document number: 002-04694 revision ecn orig. of change submission date description of change ** - akih 05/27/2013 migrated to cypress and assigned document number 002-08453. no change to document contents or format. *a 5193921 akih 03/29/2016 updated to cypress template added MB95F818KPMC-G-UNE2 in "ordering information".
document number: 002-04694 rev. *a revised march 29, 2016 page 121 of 121 mb95810k series ? cypress semiconductor corporation 2012-2016. this document is the property of cypress semiconductor corporation and its subsi diaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the r ight to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not lim ited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any informati on provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as crit ical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support de vices or systems, other medical devices or systems (including r esuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or syste m, or to affect its safety or effectiv eness. cypress is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or relate d to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from and against all claims, costs, da mages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypr ess trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support

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