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? 2009-2015 microchip technology inc. ds00001870b-page 1 highlights single-chip ethernet physical layer transceiver (phy) compliant wi th ieee 802.3ab (1000base-t), ieee 802.3u (fast ethernet ), and iso 802-3/ieee 802.3 (10base-t) hp auto-mdix support in accordance with ieee 802.3ab specification at 10/100/1000 mbps oper- ation small footprint 72-pin qfn lead-free rohs com- pliant package with gmii (10 x 10 x 0.9mm height) flexible configurations for led status indicators implements reduced power operating modes target applications set-top boxes networked printers and servers test instrumentation lan on motherboard embedded telecom applications video record/playback systems cable modems/routers dsl modems/routers digital video recorders ip and video phones wireless access points digital televisions digital media adaptors/servers gaming consoles poe applications key benefits high-performance 10/100/1000 ethernet trans- ceiver - compliant with ieee 802.3ab (1000base-t) - compliant with i eee 802.3/802.3u (fast ethernet) - compliant with is o 802-3/ieee 802.3 (10base-t) - 10base-t, 100base-tx and 1000base-t support - loop-back modes - auto-negotiation (next page support) - automatic polarity detection and correction - link status change wake-up detection - vendor specific register functions - supports gmii interface - controlled impedance outputs - four status led outputs and configurable led modes with support for tricolor operation - compliant with ieee 802.3-2005 standards - gmii pins tolerant to 3.6v - integrated dsp implements adaptive equal- izer, echo cancellers, and crosstalk cancel- lers - efficient digital baseline wander correction power and i/os - configurable led outputs - various low power modes - variable voltage i/o supply (2.5v/3.3v) miscellaneous features - ieee 1149.1 (jtag) boundary scan - multiple clock options - 25mhz crystal or 25mhz single-ended clock packaging - 72-pin qfn (10x10 mm) rohs compliant package with gmii environmental - commercial temperature range (0c to +70c) - industrial temperature range (-40c to +85c) lan8810/lan8810i gmii 10/100/1000 ethernet transceiver with hp auto-mdix support downloaded from: http:///
lan8810/lan8810i ds00001870b-page 2 ? 2009-2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 3 lan8810/lan8810i table of contents 1.0 introduction ..................................................................................................................................................................................... 4 2.0 pin description and configuration .................................................................................................................................................. 5 3.0 functional description .................................................................................................... .............................................................. 13 4.0 register descriptions .................................................................................................................................................................... 34 5.0 operational charac teristics ............................................................................................... ............................................................ 60 6.0 package outline ............................................................................................................................................................................ 76 appendix a: data sheet revision history ........................................................................................................................................... 78 the microchip web site ........................................................................................................ .............................................................. 80 customer change notification service ............................................................................................................................................... 80 customer support ............................................................................................................................................................................... 80 product identification system ................................................................................................. ............................................................ 81 downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 4 lan8810/lan8810i 1.0 introduction the lan8810/lan8810i is a low-power 10base-t/100base- tx/1000base-t gigabit ethernet physical layer (phy) transceiver with variable i/o volta ge that is fully compliant with t he ieee 802.3 and 802 .3ab standards. the lan8810/lan8810i can be configured to communicat e with an ethernet mac via the standard mii(ieee 802.3u)/ gmii(ieee 802.3z) interfaces. it contains a full-duplex tran sceiver for 1000mbps operation on four pairs of category 5 or better balanced twisted pair cable. per ieee 802.3-2005 st andards, all digital interface pins are tolerant to 3.6v. the lan8810/lan8810i is configurable via hardware and software, supporting both ieee 802.3-2005 compliant and vendor-specific register functions via smi. the lan8 810/lan8810i implements auto-negotiation to automatically determine the best possible speed and duplex mode of operat ion. hp auto-mdix support al lows the use of direct con- nect or cross-over cables. an internal block diagram of the lan8810/lan8810i is shown in figure 1-1 . a typical system-level diagram is shown in figure 1-2 . figure 1-1: internal block diagram figure 1-2: system level block diagram lan8810/lan8810i gmii 3 2 1 active hybrid 0 10/100/1000 ethernet 3 2 1 analog rx 0 3 2 1 analog tx 0 3 2 1 dsp 0 3 2 1 spectral shaper 0 digital tx scrambler trellis 4dpam-5 encoders digital rx descrambler viterbi decoder 4dpam-5 decoders 32 1 0 32 1 0 32 1 0 32 1 0 physical coding sublayer tap controller leds pll leds jtag 32 1 0 3210 lan8810/ lan8810i 10/100/1000 ethernet mac led status gmii crystal mdi ethernet magnetics jtag ethernet downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 5 lan8810/lan8810i 2.0 pin description and configuration figure 2-1: 72-qfn pin assignments (top view) vss note: exposed pad (vss) on bottom of package must be connected to ground lan8810/lan8810i 72 pin qfn (top view) tr0n txd1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 70 69 68 67 66 65 64 63 62 61 60 59 58 57 tr0p vdd12a tr1n tr1p vdd12a vdd12bias vdd12pll tr2n tr2p vdd12a tr3n tr3p txd2 vddvario vdd12core txd3 txd4 txd5 txd6 txd7 nc vdd12core vddvario rxclk col 56 55 nreset hpd vdd12a 72 71 irq tdi 19 20 crs rxer 35 36 txentxd0 downloaded from: http:///
lan8810/lan8810i ds00001870b-page 6 ? 2009-2015 microchip technology inc. table 2-1: gmii interface pins num pins name symbols buffer type description 1 transmit data 0 txd0 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 1 txd1 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 2 txd2 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 3 txd3 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 4 txd4 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 5 txd5 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 6 txd6 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 7 txd7 vis (pd) the mac transmits data to the phy using this signal. 1 transmit error txer vis (pd) indicates a transmit error condition. note: this input is ignored during 10base-t operation. 1 transmit enable txen vis (pd) indicates the presence of valid data on txd[7:0] 1 transmit clock txclk vo8 used to latch data from the mac into the phy. mii (100base-tx): 25mhz mii (10base-t): 2.5mhz note: for 1000base-t operat ion, gtxclk is used as the transmit clock. txclk is not used in 1000base-t mode. 1 gmii transmit clock gtxclk vis (pd) 125mhz clock used to latch data from the mac into the phy in 1000base-t mode. 1 receive data 0 rxd0 vo6 the phy transfers data to the mac using this signal. 1 receive data 1 rxd1 vo6 the phy transfers data to the mac using this signal. 1 receive data 2 rxd2 vo6 the phy transfers data to the mac using this signal. 1 receive data 3 rxd3 vo6 the phy transfers data to the mac using this signal. 1 receive data 4 rxd4 vo6 the phy transfers data to the mac using this signal. 1 receive data 5 rxd5 vo6 the phy transfers data to the mac using this signal. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 7 lan8810/lan8810i note 2-1 configuration strap values are latched on hardware reset. configuration straps are identified by an underlined symbol name. signals that function as configuration st raps must be augmented with an external resistor when connected to a load. refer to section 3.8, "configuration," on page 23 for additional information. 1 receive data 6 rxd6 vo6 the phy transfers data to the mac using this signal. 1 receive data 7 rxd7 vo6 the phy transfers data to the mac using this signal. 1 receive data valid rxdv vo6 indicates that recovered and decoded data is being presented on the receive data pins. 1 receive error rxer vo6 asserted to indicate an error has been detected in the frame presently being transferred from the phy. 1 receive clock rxclk vo6 used to transfer data to the mac. gmii (1000base-t): 125mhz mii (100base-tx): 25mhz mii (10base-t): 2.5mhz 1 collision detect col vo6 asserted to indicate detection of a collision condition. (used in half-duplex mode only) 1 carrier sense crs vo6 indicates detection of carrier. (used in half-duplex mode only) table 2-2: serial management interface (smi) pins num pins name symbols buffer type description 1 smi clock mdc vis (pd) serial management interface clock. 1 smi data input/ output mdio vis/vo8 (pu) serial management interface data input/output. table 2-1: gmii interface pins (continued) num pins name symbols buffer type description downloaded from: http:///
lan8810/lan8810i ds00001870b-page 8 ? 2009-2015 microchip technology inc. note 2-2 configuration strap values are latched on hardware reset. configuration straps are identified by an underlined symbol name. signals that function as configuration st raps must be augmented with an external resistor when connected to a load. refer to section 3.8, "configuration," on page 23 for additional information. table 2-3: led & configuration pins num pins name symbols buffer type description 1 10base-t link led indicator 10_led vo8 10base-t led link indication. refer to section 3.9.1, "leds," on page 27 for additional information. 1 100base-tx link led indicator 100_led vo8 100base-tx led link indication. refer to section 3.9.1, "leds," on page 27 for additional information. hardware power down (hpd) mode configuration strap hpd_mode vis (pd) this configuration strap is used to select the hardware power down (hpd) mode. when pulled- up, the pll is not disabled when hpd is asserted. when pulled-down, the pll is disabled when hpd is asserted. refer to section 3.7.3, "hardware power-down," on page 23 for additional information. see note 2-2 for more informati on on configuration straps. 1 1000base-t link led indicator 1000_led vo8 1000base-t led link indication. refer to section 3.9.1, "leds," on page 26 for additional information. 1 link activity led indicator act_led vo8 link activity led indication. refer to section 3.9.1, "leds," on page 26 for additional information. 1 configuration input 0 config0 vis (pd) this pin sets the phya dd[1:0] bits of the 10/100 special modes register on reset or power-up. it must be connected to vss, 100_led, 1000_led, or vddvario. refer to section 3.8.1.2, "config[3:0] configuration pins," on page 24 for additional information. 1 configuration input 1 config1 vis (pd) this pin sets the pause bit of the auto negotiation advertisement register and phyadd [2] bit of the 10/100 special modes register on reset or power- up. it must be connected to vss, 100_led, 1000_led, or vddvario. refer to section 3.8.1.2, "config[ 3:0] configuration pins," on page 24 for additional information. 1 configuration input 2 config2 vis (pd) this pin sets the mod[1:0] bits of the extended mode control/status register on reset or power- up. it must be connected to vss, 100_led, 1000_led, or vddvario. refer to section 3.8.1.2, "config[ 3:0] configuration pins," on page 24 for additional information. 1 configuration input 3 config3 vis (pd) this pin sets the mod[3] bit of the extended mode control/status register on reset or power-up. it must be connected to 1000_led or vddvario. refer to section 3.8.1.2, "config[3:0] configuration pins," on page 24 for additional information. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 9 lan8810/lan8810i table 2-4: ethernet pins num pins name symbol buffer type description 1 ethernet tx/ rx positive channel 0 tr0p aio transmit/receive positive channel 0. 1 ethernet tx/ rx negative channel 0 tr0n aio transmit/receive negative channel 0. 1 ethernet tx/ rx positive channel 1 tr1p aio transmit/receive positive channel 1. 1 ethernet tx/ rx negative channel 1 tr1n aio transmit/receive negative channel 1. 1 ethernet tx/ rx positive channel 2 tr2p aio transmit/receive positive channel 2. 1 ethernet tx/ rx negative channel 2 tr2n aio transmit/receive negative channel 2. 1 ethernet tx/ rx positive channel 3 tr3p aio transmit/receive positive channel 3. 1 ethernet tx/ rx negative channel 3 tr3n aio transmit/receive negative channel 3. 1 external phy bias resistor ethrbias ai used for the internal bias circuits. connect to an external 8.06k 1.0% resistor to ground. table 2-5: jtag pins num pins name symbol buffer type description 1 jtag test data out tdo vo8 jtag (ieee 1149.1) data output. 1 jtag test data input tdi vis (pu) jtag (ieee 1149.1) data input. note: when not used, tie this pin to vddvario. 1 jtag test clock tck vis (pd) jtag (ieee 1149.1) test clock. note: when not used, tie this pin to vss. 1 jtag test mode select tms vis (pu) jtag (ieee 1149.1) te st mode select. note: when not used, tie this pin to vddvario. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 10 ? 2009-2015 microchip technology inc. note 2-3 exposed pad on package bottom ( figure 2-1 ). table 2-6: miscellaneous pins num pins name symbol buffer type description 1 crystal input xi iclk external 25 mhz crystal input. note: this pin can also be driven by a 25 mhz single-ended clock oscillator. when this method is used, xo should be left unconnected. refer to section 5.6, "clock circuit," on page 75 for additional information. 1 crystal output xo oclk external 25 mhz crystal output. 1 system reset nreset vis (pu) this active-low pin allows external hardware to reset the device. 1 interrupt request irq vo8 programmable interrupt request. note: when used, this pin requires an external 4.7k pull-up resistor. 1 hardware power down hpd vis (pd) when asserted, this pin places the device into hardware power down (hpd) mode. refer to section 3.7.3, "hardware power-down," on page 23 for additional information. 1 no connect nc - this pin must be left floating for normal device operation. table 2-7: power pins num pins name symbol buffer type description 6 +3.3v/+2.5v i/o power supply input vddvario p +2.5v/+3.3v variable i/o power. refer to section 3.10, "application diagrams," on page 31 and the lan8810/lan8810i reference schematics for connection information. 6 digital core +1.2v power supply input vdd12core p refer to section 3.10, "application diagrams," on page 31 and the lan8810/lan8810i reference schematics for connection information. 4 ethernet +1.2v port power supply input for channels 0-3 vdd12a p refer to section 3.10, "application diagrams," on page 31 and the lan8810/lan8810i reference schematics for connection information. 1 ethernet +1.2v bias power supply input vdd12bias p refer to section 3.10, "application diagrams," on page 31 and the lan8810/lan8810i reference schematics for connection information. 1 ethernet pll +1.2v power supply input vdd12pll p refer to section 3.10, "application diagrams," on page 31 and the lan8810/lan8810i reference schematics for connection information. note 2-3 ground vss p common ground downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 11 lan8810/lan8810i table 2-8: 72-qfn pin assignments pin num pin name pin num pin name pin num pin name pin num pin name 1 tck 19 rxer 37 txer 55 nreset 2 tms 20 crs 38 txclk 56 hpd 3 tdo 21 col 39 gtxclk 57 tr0n 4 xi 22 rxclk 40 vdd12core 58 tr0p 5 xo 23 vddvario 41 vddvario 59 vdd12a 6 vddvario 24 vdd12core 42 act_led 60 tr1n 7 vdd12core 25 nc 43 1000_led 61 tr1p 8 rxd0 26 txd7 44 100_led/ hpd_mode 62 vdd12a 9 rxd1 27 txd6 45 10_led 63 vdd12bias 10 rxd2 28 txd5 46 config3 64 vdd12pll 11 rxd3 29 txd4 47 config2 65 tr2n 12 rxd4 30 txd3 48 vdd12core 66 tr2p 13 rxd5 31 vdd12core 49 vddvario 67 vdd12a 14 vddvario 32 vddvario 50 config1 68 tr3n 15 vdd12core 33 txd2 51 config0 69 tr3p 16 rxd6 34 txd1 52 mdc 70 vdd12a 17 rxd7 35 txd0 53 mdio 71 irq 18 rxdv 36 txen 54 ethrbias 72 tdi exposed pad must be connected to vss downloaded from: http:///
lan8810/lan8810i ds00001870b-page 12 ? 2009-2015 microchip technology inc. 2.1 buffer types note 1: the digital signals are not 5v tolerant. refer to section 5.1, "absolute maximum ratings*," on page 60 for additional buffer information. 2: sink and source capabilities are dependant on the vddvario voltage. refer to section 5.1, "absolute max- imum ratings*," on page 60 for additional information. table 2-9: buffer types buffer type description vis variable voltage schmitt-triggered input vo6 variable voltage output with 6ma sink and 6ma source vo8 variable voltage output with 8ma sink and 8ma source pu 50ua (typical) internal pull-up. unless otherwis e noted in the pin description, internal pull- ups are always enabled. note: internal pull-up resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an ex ternal resistor must be added. pd 50ua (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. note: internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals ex ternal to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 13 lan8810/lan8810i 3.0 functional description this chapter provides functional descr iptions of the various device features . these features have been categorized into the following sections: auto-negotiation hp auto-mdix rgmii interface serial management interface (smi) interrupt management resets power-down modes configuration miscellaneous functions application diagrams 3.1 auto-negotiation the purpose of the auto-n egotiation function is to automatically configure the phy to the optimum link parameters based on the capabilities of its link partner. auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically sele cting the highest performance mode of ope ration supported by both sides. auto- negotiation is fully defined in clause 28 and clause 40 of the ieee 802.3 specification. once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the integrated serial management interface (smi) . the results of the negotiation process are reflected in the speed indica- tion field of the phy special control / status register as well as the auto negotiation link partner ability register . the advertised capabilities of the phy are stored in auto negotiation advertisement register . the defaults advertised by the device are determined as described in section 3.8.1.2.2, "configuring the mode of operation (config[3:2])," on page 26 . the auto-negotiation protocol is a purely physical layer acti vity and proceeds independently of the mac controller. when enabled, auto-negotiation is started by the occurrence of one of the following events: hardware reset software reset power-down reset link status down setting the restart auto-negotiate bit of the basic control register on detection of one of these events, the device begins auto-nego tiation by transmitting bursts of fast link pulses (flp). the data transmitted by an flp burst is known as a link c ode word. this exchange of information allows link partners to determine the highest common ability (hcd). once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any dif- ference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if all of the re quired flp bursts are not received. writing the 100base-tx full duplex , 100base-tx , 10base-t full duplex , and 10base-t bits of the auto negotiation advertisement register allows software control of the advert ised capabilities. however, writing the auto negotiation advertisement register does not automatically re-s tart auto-negotiation. the restart auto-negotiate bit of the basic control register must be set before the new abilities will be advertised. auto-negotiation can also be disabled via soft- ware by clearing the auto-negotiation enable bit of the basic control register . auto-negotiation also resolves the master/slave clocking relationship between two phys for a 1000base-t link. refer to section 3.1.4, "master/slave," on page 14 for additional information. 3.1.1 restarting auto-negotiation auto-negotiation can be restarted at any time by using the restart auto-negotiate bit of the basic contro l register . auto-negotiation will also re-start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation resumes in an attempt to determine the new link configuration. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 14 ? 2009-2015 microchip technology inc. if the management entity restarts auto-negotiation by writing to the restart auto-negotiate bit, the device will respond by stopping all transmission/receiving operations. auto-ne gotiation will restart after approximately 1200 ms. the link partner will have also dropped the li nk and will resume auto-negotiation. 3.1.2 disabling auto-negotiation auto-negotiation can be disabled via software by clearing the auto-negotiation enable bit of the basic control register . the device will then force its speed of operation to reflect the information in the speed select[1] , speed select[0] , and duplex mode bits of the basic control register . these bits are ignored when auto-negotiation is enabled. 3.1.3 parallel detection if the lan8810/lan8810i is connected to a device lacking t he ability to auto-negotiate (i.e., no flps are detected), it is able to determine the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case, the link is presumed to be half-duplex per the ieee standard. this ability is know n as parallel detection. this feature ensures inter operability with legacy link partners. the ethernet mac has access to information regarding parallel detect via the auto negotiation expansion register . if a link is formed via parallel detection, the link partner auto-negotiation able bit of the auto negotiation expansion reg- ister is cleared to indicate that the link partner is not capa ble of auto-negotiation. if a fault occurs during parallel detec- tion, the parallel detection fault bit of this register is set. the auto negotiation link partner ability register is updated with informatio n from the link partner which is coded in the received flps. if the link partner is not auto-negotiation capable, then the auto negotiation link partner ability register is updated after completion of parallel detection to reflect the speed capability of the link partner. parallel detect cannot be used to establish gigabit ethernet links because echo cancellation and signal recovery on a gigabit ethernet link requires resolution of the master/slave clock relationship, which requires the exchange of flps. 3.1.4 master/slave in 1000base-t, one of the two link partne r devices must be configured as mast er and the other as slave. the master device transmits data using the local clock, while the slav e device uses the clock reco vered from incoming data. the master and slave assignments are set usin g the configuration pins as described in section 3.8.1.2.2, "configuring the mode of operation (config[3:2])," on page 26 or by using the master/slave manual config enable and master/ slave manual config value bits of the master/slave control register . if both the link partner and the local device are manually given the same master/slave assignment, an error will be indicated in the master/slave configuration fault bit of the master/slave status register . depending on the link partner configuratio n, the manual master/slave mode can be resolved to sixteen possible out- comes, as shown in table 3-1 . table 3-1: master/slave r esolution for 1000base-t lan8810/lan8810i advertisement link partner advertisement lan8810/lan8810i result link partner result single-port single-port m/s resolved by r andom seed m/s resolved by random seed single-port multi-port slave master single-port manual master slave master single-port manual slave master slave multi-port single-port master slave multi-port multi-port m/s resolved by r andom seed m/s resolved by random seed multi-port manual master slave master multi-port manual slave master slave manual master single-port master slave downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 15 lan8810/lan8810i 3.1.5 manual operation the device supports a manual (forced) operation for test purpo ses. in manual operation, the user sets the link speed (10mbps or 100mbps) and the duplex state (full or half). auto-negotiation must be disabled in order to manually co nfigure the speed and the duplex. this may be accomplished using the configuration pins, as described in section 3.8.1.2.2, "conf iguring the mode of oper ation (config[3:2])," on page 26 , or by using the basic control register register as described in section 3.1.2, "disabling auto-negotiation," on page 14 . for 10base-t and 100base-tx, the link stat e of the device is determined by the speed select[1] , speed select[0] , and duplex mode bits of the basic control register . manual operation at a link speed of 1000mbps is not supported. 3.1.6 half vs. full-duplex half-duplex operation relies on the csma /cd (carrier sense multiple access / collision detect) protocol to handle net- work traffic and collisions. in this mode, the internal carri er sense signal, crs, responds to both transmit and receive activity. if data is received while the phy is transmitting, a collision results. in full-duplex mode, the phy is able to transmit and receiv e data simultaneously and collision detection is disabled. in this mode, the internal crs responds only to receive activity. in 10base-t and 100base-t mode, crs is redefined to respond only to received activity . in 1000base-t, crs is disabled. table 3-2 describes the behavior of the internal crs bit under all receive/transmit conditions. manual master multi-port master slave manual master manual master no link no link manual master manual slave master slave manual slave single-port slave master manual slave multi-port slave master manual slave manual master slave master manual slave manual slave no link no link table 3-2: crs behavior mode speed duplex activity crs behavior ( note 3-1 ) manual 10 mbps half-duplex transmitting active manual 10 mbps half-duplex receiving active manual 10 mbps full-duplex transmitting low manual 10 mbps full-duplex receiving active manual 100 mbps half-duplex transmitting active manual 100 mbps half-duplex receiving active manual 100 mbps full-duplex transmitting low manual 100 mbps full-duplex receiving active auto-negotiation 10 mbps half-duplex transmitting active auto-negotiation 10 mbps half-duplex receiving active table 3-1: master/slave resoluti on for 1000base-t (continued) downloaded from: http:///
lan8810/lan8810i ds00001870b-page 16 ? 2009-2015 microchip technology inc. note 3-1 the internal crs signal operates in two modes: active and low. when in active mode, the internal crs will transition high and low upon line activity, where a high value indicates a carrier has been detected. in low mode, the internal crs stays low and does not indicate carrier detection. 3.2 hp auto-mdix hp auto-mdix facilitates the use of cat-5 (100base-t) medi a utp interconnect cable without consideration of inter- face wiring scheme. if a user plugs in either a direct c onnect lan cable, or a cross-ov er patch cable, as shown in figure 3-1 , the auto-mdix phy is capable of configuring the t wisted pair pins for correct transceiver operation. the internal logic of the device detects the tx and rx pins of the connecting device. it can automatically re-assign chan- nel 0 and 1 if required to establish a link. in 1000base-t mode, it can re-assign channel 2 and 3. crossover resolution precedes the actual auto-negotiation process that involves exchange of flps to advertise capabilities. automatic mdi/ mdix is described in ieee 802.3ab clause 40, section 40.8.2. since the rx and tx line pairs are interchangeable, spe- cial pcb design considerations are needed to accommoda te the symmetrical magnetics and termination of an auto- mdix design. auto-mdix is enabled by default, and can be disabled by the auto mdix disable bit in the 10/100 mode control/status register . when auto-mdix is disabled, the tx and rx pins can be configured manually by the mdi/mdi-x 0:1 and mdi/ mdi-x 2:3 bits in the extended mode contro l/status register . the device includes an advanced crossover resolution capability called semi crossover. this is an extension to hp auto-mdix that corrects for a cable with only two pairs crossed. if semi crossover is enabled, after the device has attempted to establish a link with all four signal pairs normal or crossed, it will attempt to establish a link with pairs 2/3 switched and 0/1 straight, and then wi th pairs 0/1 switched and pairs 2/3 straight. the semi crossover is enabled by default, and can be disabled by the semi crossover enable bit in the 10/100 mode control/status register . after resolution of crossed pairs is complete, using either hp auto-mdix or the semi crossover function, the mdi/mdi- x status is reported through the xover resolution 0:1 and xover resolution 2:3 bits of the user status 2 register . auto-negotiation 10 mbps full-duplex transmitting low auto-negotiation 10 mbps full-duplex receiving active auto-negotiation 100 mbps half-duplex transmitting active auto-negotiation 100 mbps half-duplex receiving active auto-negotiation 100 mbps full-duplex transmitting low auto-negotiation 100 mbps full-duplex receiving active table 3-2: crs behavior (continued) mode speed duplex activity crs behavior ( note 3-1 ) downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 17 lan8810/lan8810i 3.2.1 required ethernet magnetics the magnetics selected for use with the device should be an auto-mdix style magnetic available from several vendors. refer to application note 8.13 "suggested magnetics" for th e latest qualified and suggested magnetics. vendors and part numbers are provided in this application note. figure 3-1: cable connection types: st raight-through, cr ossover, semi crossover 12 3 4 5 6 7 8 tr0p 12 3 4 5 6 7 8 tr0p direct connect cable rj-45 8-pin straight-through 12 3 4 5 6 7 8 12 3 4 5 6 7 8 crossover cable rj-45 8-pin crossover tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0n tr1p tr2p tr2n tr1n tr3p tr3n tr0p tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0p tr0n tr1p tr2p tr2n tr1n tr3p tr3n 12 3 4 5 6 7 8 12 3 4 5 6 7 8 0/1 straight, 2/3 crossed rj-45 8-pin semi crossover tr0p tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0p tr0n tr1p tr2p tr2n tr1n tr3p tr3n 12 3 4 5 6 7 8 12 3 4 5 6 7 8 0/1 crossed, 2/3 straight rj-45 8-pin semi crossover tr0p tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0p tr0n tr1p tr2p tr2n tr1n tr3p tr3n downloaded from: http:///
lan8810/lan8810i ds00001870b-page 18 ? 2009-2015 microchip technology inc. 3.3 gmii interface the device communicates with an external mac using the gigabit media independent inte rface (gmii). the gmii is compliant with the ieee 802.3 standar d, and provides support for 1000base-t, 100base-tx, or 10base-t operation. for 1000base-t, the mac generated 125m hz gtxclk transmit clock is used to synchronize the txd, txen and txer signals. for 100base-t x and 10base-t operatio n, the device generated txclk transmit clock is used to syn- chronize the txd, txen and txer signals. txclk is 25mhz or 2.5mhz for 100base-tx and 10base-t operation, respectively. txer and txen are both driven by the mac and indicate a transmit error and valid transmit data, respec- tively. on the receiver side, the device generated rxclk is used to synchronize the rxd, rxdv, rxer, col and crs signals for all modes of operation. the gmii provides backwards co mpatibility with the legacy mii. table 3-3, "gmii/mii signal mapping" describes which pins are used in each mode. timing information for the gmii/m ii interface is provided in section 5.5, "ac specif ications," on page 65 . for additional information on the gmii/m ii interface, refe r to the ieee 802. 3 specification. 3.3.1 mii isolate mode the device may be configured to electrica lly isolate the gmii pins by setting the isolate bit of the basic control register . in this mode, all mac data interface output pins are high and all mac data interface input pins are ignored. in this mode, the smi interface is k ept active, allowing the mac to access the sm i registers and generate interrupts. all mdi operations are halted while in isolate mode. table 3-3: gmii/mii signal mapping gmii mode (ieee 802.3 clause 35) mii mode (ieee 802.3 clause 22) txd[3:0] txd[3:0] txd[7:4] txen txen txer txer txclk (10/100mbps operation) txclk gtxclk (1000mbps operation) col col crs crs rxd[3:0] rxd[3:0] rxd[7:4] rxdv rxdv rxer rxer rxclk rxclk downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 19 lan8810/lan8810i 3.4 serial management interface (smi) the serial management interface is used to control the device and obtain its status . this interface supports the standard phy registers required by clause 22 of the 802.3 standard, as well as vendor-specific re gisters allowed by the spec- ification. non-supported regist ers (such as 11 to 14) will be read as hexadecimal ffff. device registers are detailed in section 4.0, "register descriptions," on page 34 . at the system level, smi provides 2 si gnals: mdio and mdc. the mdc signal is an aperiodic clock provided by the station management controller (smc). mdio is a bi-directional data smi input/output signal that receives serial data (commands) from the controller smc a nd sends serial data (status) to the smc. the minimum time between edges of the mdc is 160 ns. there is no maximu m time between edges. the minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. these modest timing requirements allow this interface to be easily driven by the i/o port of a microcontroller. the data on the mdio line is latched on the rising edge of the mdc. the frame structure and timing of the data is shown in figure 1-1 and figure 1-2 . the timing relationships of the mdio signals are further described in section 5.5.6, "smi timing," on page 73 . figure 3-2: mdio timing and frame structure - read cycle figure 3-3: mdio timing and frame structure - write cycle mdc mdio read cycle ... 32 1's 0 1 1 0 a4a3a2a1a0r4r3r2r1r0 d1 ... d15 d14 d0 preamble start of frame op code phy address register address turn around data data from phy data to phy mdc mdio ... 32 1's 0 1 1 0 a4a3a2a1a0r4r3r2r1r0 write cycle d15 d14 d1 d0 ... data preamble start of frame op code phy address register address turn around data to phy downloaded from: http:///
lan8810/lan8810i ds00001870b-page 20 ? 2009-2015 microchip technology inc. 3.5 interrupt management the device supports multiple interrupt capabilities which are not a part of the ieee 802.3 s pecification. an active low asynchronous interrupt signal may be generated on the irq pin when selected events are detected, as configured by the interrupt mask register . to set an interrupt, the corresponding mask bit in the interrupt mask register must be set (see table 3-3 ). when the associated event occurs, the irq pin will be asserted. when t he corresponding event to deassert irq is true, the irq pin will be deasserted. all interrupts are masked following a reset. note 3-2 the energyon bit of the 10/100 mode control/status register (17.1) defaults to 1 after a hardware reset. if no energy is detected before 256ms, the energyon bit will be cleared. when energyon is 0 and energy is detected, due to the establishment of a valid link or the phy auto- negotiation moving past th e ability detect state, the energyon bit will be set and the int7 bit of the interrupt source flags register will assert. if energyon is set and the energy is removed, the int7 bit will assert. the energyon bit will clear 256ms after the interrupt. if the phy is in manual mode, int7 will be asserted 256ms after the link is broken. if the phy is auto-negotiating, int7 will be asserted 256ms after the phy returns to the abilit y detect state (maximum of 1.5s after the link note: table 3-3 utilizes register index and bit number referencing in lieu of individual names. for example, 30.10 is used to reference bit 10 (transmitter elastic buffer overflow interrupt enable) of the interrupt mask register (register index 30). table 3-4: interrupt management table mask interrupt source flag interrupt source event to assert irq event to deassert irq 30.15:11 29.15:11 reserved -na- -na- -na- -na- 30.10 29.10 transmitter elastic buffer overflow -na- -na- ( note 3-3 ) transmitter elastic buffer overflow overflow condition resolved 30.9 29.9 transmitter elastic buffer underflow -na- -na- ( note 3-3 ) transmitter elastic buffer underflow underflow condition resolved 30.8 29.8 idle error count overflow 10.7:0 idle error count idle error count overflow reading register 10 30.7 29.7 energyon 17.1 energyon rising 17.1 ( note 3-2 ) falling 17.1 or reading register 29 30.6 29.6 auto-negotiation complete 1.5 auto-negotiate complete rising 1.5 falling 1.5 or reading register 29 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status falling 1.2 reading register 1 or reading register 29 30.3 29.3 reserved -na- -na- -na- -na- 30.2 29.2 parallel detection fault 6.4 parallel detection fault rising 6.4 falling 6.4 or reading register 6, or reading register 29 or re-autonegotiate or link down 30.1 29.1 auto-negotiation page received 6.1 page received rising 6.1 falling of 6.1 or reading register 6, or reading register 29 re-auto-negotiate, or link down. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 21 lan8810/lan8810i is broken). to prevent an unexpected asserti on of irq, the energyon interrupt mask ( int7_en ) should always be cleared as part of the energyon interrupt service routine. note 3-3 the transmitter fifo depth can be adjusted via the transmitter fifo depth field of the extended mode control/status register (19.10:9). 3.6 resets the device provides the following chip-level reset sources: hardware reset (nreset) software reset power-down reset 3.6.1 hardware reset (nreset) a hardware reset will occur when the sy stem reset nreset input pin is driven lo w. anytime nreset is asserted, it must be held low for the minimum time specified in section 5.5.4, "reset timing," on page 68 to ensure proper reset to the phy. following a hardware reset, the device resets the device registers and relatches the configuration straps and con- fig[3:0] pins. on first power-up of the device, the sequence below must be also be followed to ensure the device exits reset in the correct operational state: 1. perform a hardware reset on power-up as per section 5.5.3, "power-on hard ware reset timing," on page 67 . 2. wait a minimum of 250ms 3. write smi register 0 ( basic control register ) = 0x4040 4. wait a minimum of 1 second 5. assert the nreset input pin (nreset = 0) 6. wait a minimum of 50ms 7. deassert the nreset input pin (nreset = 1) after completing this sequence, the lan8810/lan8810i will be in the default states and re ady for any initialization or configuration and allow operation. 3.6.2 software reset a software reset is initiated by writing a 1 to the phy soft reset (reset) bit of the basic control register . this self- clearing bit will return to 0 after approximately 256 ? s, at which time the phy reset is complete. this reset initializes the logic within the phy, with the exception of register bits marked as nasr (not af fected by software reset). following a software reset, the device configuration is reload ed from the register bit values, and not from the configura- tion straps and config[3:0] pins. the devi ce does not relatch the hardware configuration settings. for example, if the device is powered up and a configuration st rap is changed from its initial power up state, a software reset will not load the new strap setting. note: system implementers should conne ct the nreset input pin to an output pin from the respective mac or microcontroller, so that the required power-up s equence can be performed without causing a full system reset event. note: a hardware reset (nreset assertion) is required fo llowing power-up. refer to section 5.5.3, "power-on hardware reset timing," on page 67 for additional information. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 22 ? 2009-2015 microchip technology inc. 3.6.3 power-down reset a power-down reset is automatically activated when the device comes out of the power-down mode. during power- down, the registers are not rese t. configuration straps and config[3:0] pins are not latched as a result of a power- down reset. the power-down reset is internally extended by 256 ? s after exiting the power-down mode to allow the plls to stabilize before the logic is released from reset. refer to section 3.7, "power-down modes," on page 23 for details on the various power-down modes. 3.7 power-down modes the device supports 3 power-down modes: general power-down energy detect power-down hardware power-down 3.7.1 general power-down this power-down mode is controlled by the power down bit of the basic control register . in this mode, the entire device is powered-down except for the serial management interface. the device remains in the general power-down mode while power down is set. when power down is cleared, the device powers up and is automatically reset (via a power- down reset ). for maximum power savings, auto-negotiation sh ould be disabled before enabling the general power- down mode. 3.7.2 energy detect power-down this power-down mode is controlled by the edpwrdown bit of the 10/100 mode control/status register . in this mode, when no energy is present on the line, nothing is transmi tted and the device is powered-down except for the manage- ment interface, the squelch circuit and the energyon logic. the energyon bit in the 10/100 mode control/status register is asserted when there is valid energy from the line (100base-tx, 10base-t, or auto-negotiation signals) and the phy powers-up. it au tomatically resets itself into the previous state prior to power-down, and stays in active mode as long as energy exists on the line. if the engergyon interrupt is enabled ( int7_en of the interrupt mask register ), irq is asserted. 3.7.3 hardware power-down this power-down mode is controlled by the hpd pin. in th is mode, the entire device is powered-down except for the serial management interface. the hpd_mode configuration strap selects whethe r the pll will be shut down when in hardware power-down mode. to exit t he hardware power-down mode, the hpd pin must be deasserted, followed by the deassertion of the power down bit in the basic contro l register . if the hardware power-down mode is set to shut down the pll, a software reset must also be issued. note 1: the device will wake-up in the hardware power-down mo de if the hpd pin is asserted during hardware reset. 2: for additional information on the hpd_mode configuration strap, refer to section 3.8.1.1, "configuration straps," on page 24 . 3.8 configuration the device mode of operation may be controlled by hardware and software (register-selectable) configuration options. the initial configuration may be se lected in hardware as described in section 3.8.1 . in addition, register-selectable soft- ware configuration options may be us ed to further define the functionalit y of the transceiver as described in section 3.8.2 . the device supports both ieee 802.3-2005 complia nt and vendor-specific register functions. 3.8.1 hardware configuration hardware configuration is controlled via multiple configur ation straps and the config[3:0 ] configuration pins. these items are detailed in the following sub-sections. note: the first and possibly second packet to activate energyon may be lost. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 23 lan8810/lan8810i 3.8.1.1 configuration straps configuration straps are multi-functi on pins that are driven as output s during normal operation. during a hardware reset (nreset) , these outputs are tri-stated. the high or low state of the signal is latched following de-assertion of the reset and is used to determine the default configuration of a pa rticular feature. table 3-4 details the configuration straps. configuration straps are also listed as part of section 2.0, "pin description and configuration," on page 5 with underlined names. configuration straps include internal resistors in order to pr event the signal from floating w hen unconnected. if a partic- ular configuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the internal resistor can also be overridden by the addition of an external resistor. note 1: the system designer must gua rantee that conf iguration straps meet the ti ming requirements specified in section 5.5.3, "power-on hard ware reset timing," on page 67 . if configuration straps are not at the correct voltage level prior to being latched, the dev ice may capture incorrect strap values. 2: configuration straps must never be driven as inputs. if required, configuration straps can be augmented, or overridden with external resistors. 3.8.1.2 config[3:0] configuration pins the device provides 4 dedicated configuration pins, config[3:0], which are used to select the default smi address and mode of operation. the config[3:0] confi guration pins differ from configuration straps in that they are single-purpose pins and have different latch timing requirements. the high or low states of the config[3:0 ] pins are latched following deassertion of a hardware reset (nreset) . refer to section 5.5.3, "power-on hard ware reset timing," on page 67 for additional config[3:0] timing information. each config[3:0] configuration pin can be connected in on e of four ways. the configur ation pin value (cpv) repre- sented by each connection option is shown in table 3-5 . using the cpv nomenclature for each config[3:0] pin, section 3.8.1.2.1 describes how to configure the smi address and section 3.8.1.2.2 describes how to configure the initial mode of operation. table 3-5: configuration straps configuration strap description logic 0 (pd) logic 1 (pu) hpd_mode selects the hardware power-down (hpd) mode hpd with pll disabled (default) hpd with pll enabled table 3-6: hardware connection determines configuration pin value (cpv) config[x] connects to: value gnd cpv(0) 100_led cpv(1) 1000_led cpv(2) vdd cpv(3) note: the hpd pin is also a dedicated conf iguration pin. hpd forces the entir e device to power down except for the management interface. the hardware power-down mode is described in section 3.7.3, "hardware power-down," on page 23 . downloaded from: http:///
lan8810/lan8810i ds00001870b-page 24 ? 2009-2015 microchip technology inc. 3.8.1.2.1 configuring the smi address (config[1:0]) the smi address may be configured via hardware to any value between 0 and 7. if an addre ss greater than 7 is required, the user can configure the phy address using software configuration via the phyadd[4:0] field of the 10/100 special modes register (after smi communication at an address is established). the config1 pin is used to configure bo th the smi address and the value of the pause operation (pause) bit in the auto negotiation advertisement register . the user must first determine the de sired pause value. the configuration pin values for config1 and conf ig0 should then be selected using ta b l e 3 - 6 (pause=0) or ta b l e 3 - 7 (pause=1), respectively. 3.8.1.2.2 configuring the mode of operation (config[3:2]) this section describes the initial mode s of operation that are available using the config[3:2] configuration pins. the user may configure additional modes using software configuration when the config[3:2] options do not include the desired mode. the config3 pin is used to configure the values of the mod field (19.15:11) the configur ation pin values for config3 and config2 should be selected using ta b l e 3 - 8 . these tables also detail how the mod field of the extended mode control/status register will be configured. table 3-7: smi address configuration with pause=0 phyadd[2:0] config1 config0 000 cpv(0) cpv(0) 001 cpv(0) cpv(1) 010 cpv(0) cpv(2) 011 cpv(0) cpv(3) 100 cpv(1) cpv(0) 101 cpv(1) cpv(1) 110 cpv(1) cpv(2) 111 cpv(1) cpv(3) table 3-8: smi address configuration with pause=1 phyadd[2:0] config1 config0 000 cpv(2) cpv(0) 001 cpv(2) cpv(1) 010 cpv(2) cpv(2) 011 cpv(2) cpv(3) 100 cpv(3) cpv(0) 101 cpv(3) cpv(1) 110 cpv(3) cpv(2) 111 cpv(3) cpv(3) downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 25 lan8810/lan8810i section 3.8.1.2.3 describes how the mod field controls other configuration bits in the device. when a soft reset is issued via the phy soft reset (reset) bit of the basic control register , configuration is controlled by the register bit values and the config[3:0] pins have no affect. likewise, changing the mod field of the extended mode control/status reg- ister bits does not change the configuration of the device in this case. 3.8.1.2.3 configuration bits impa cted by the mode of operation immediately after a reset, the mod field of the extended mode control/status register will be set dependent on the configuration pin values of the config3 and config2 pins, as described in section 3.8.1.2.2 . ta b l e 3 - 9 details how the mod field effects other device configuration register bits. note: table 3-8 utilizes register index and bit number referencing in lieu of individual names. table 3-9: configuring th e mode of operation mode definitions config3 config2 reg 19 [15:11] 10base-t half duplex. auto-negot iation disabled. cpv(2) cpv(0) 00000 10base-t full duplex. auto-negotiation disabled. cpv(2) cpv(1) 00001 100base-tx half duplex. au to-negotiation disabled. crs is active during transmit & receive. cpv(2) cpv(2) 00010 100base-tx full duplex. au to-negotiation disabled. crs is active during receive. cpv(2) cpv(3) 00011 all mode capable (10/100/1000). auto-negotiation enabled. auto master/slave resolution single port. cpv(3) cpv(0) 00111 10base-t/100base-tx capable. auto-ne gotiation enabled. cpv(3) cpv(1) 00100 all mode capable (10/100/1000). auto-negotiation enabled. manual master/slave resolution slave port. cpv(3) cpv(2) 01001 all mode capable (10/100/1000). auto-negotiation enabled. manual master/slave resolution master port. cpv(3) cpv(3) 01010 note: table 3-9 utilizes register index and bit number referencing in lieu of individual names downloaded from: http:///
lan8810/lan8810i ds00001870b-page 26 ? 2009-2015 microchip technology inc. 3.8.2 software configuration the serial management interface (smi) allows for the configur ation and control of multiple transceivers. several 16-bit status and control registers are accessible through the management interface pins mdc and mdio for 10/100/ 1000mbps operation. the device implements all the required mii registers and optional registers as described in section 4.0, "register descriptions" . configuring the smi address is described in section 3.8.1.2.1 . refer to section 3.4, "serial management interface (smi)," on page 20 for additional information on the smi. 3.9 miscellaneous functions 3.9.1 leds the device provides the following led signals to enable visual indication of status: 1000_led 100_led 10_led act_led in all modes, the full duplex led (act_led) is driven imm ediately after auto-negotiation has resolved the duplex state and before the link is established. the speed leds ( 1000_led, 100_led, 10_led) are driven after a link is estab- lished. three led modes of operation are available: led mode 1 ( table 3-11 ) led mode 2 ( table 3-12 ) led mode 3 (default mode - table 3-13 ) table 3-10: register bits impacted by the mode of operation (mod) reg 19 [15:11] mode definitions reg 0 [13,12,8,6] reg 4 [8,7,6,5] reg 9 [12,11,10,9,8] 00000 10base-t half duplex. auto-negotiation disabled. 0000 xxxx xxx00 00001 10base-t full duplex. auto-negotiation disabled. 0010 xxxx xxx00 00010 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 1000 xxxx xxx00 00011 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 1010 xxxx xxx00 00100 10base-t/100base-tx capable. auto-negotiation enabled. 11x0 1111 xxx00 00101 reserved --- 00110 reserved --- 00111 all capable. auto-negotiation enabled. auto master/slave re solution single port. 01x1 1111 00011 01000 reserved --- 01001 all capable. auto-negotiation enabled. manual master/slave resolution slave port. 01x1 1111 10011 01010 all capable. auto-negotiation enabled. manual master/slave resolution master port. 01x1 1111 11111 01011 - 11111 reserved --- downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 27 lan8810/lan8810i the led mode is configured via the led_mode[1:0] field of the extended mode control/status register . the func- tional operation of the leds in each mode is described in table 3-11 , ta b l e 3 - 1 2 and table 3-13 . note 1: led mode 3 is the default mode of operation an d requires four leds for full operation. 2: led modes 1 and 2 require two dual led packages (t wo leds in each package). led mode 2 provides collision detection, while led mode 1 does not. note 3-4 switching at 50% duty cycle creates a third color (e.g., if color1 is orange and color2 is green, color 3 will be yellow (orange + green)). note 3-5 activity will cause duplex led color to blink. note 3-6 switching at 50% duty cycle creates a third color (e.g., if color1 is orange and color2 is green, color 3 will be yellow (orange + green)) note 3-7 activity will cause duplex led color to blink. table 3-11: led mode 1 operation - led_mode[1:0]=01b led status description 100_led on color1 100base-t link 1000_led on color2 1000base-t link 100_led & 1000_led on color3 note 3-4 10base-t link act_led on color1 note 3-5 link operates at full duplex 10_led on color2 transmit/receive activity 10_led & act_ led off half duplex, no activity on color1 full duplex, no activity off/color2 half duplex, transmit/receive activity color1/color2 full duplex, transmit/receive activity table 3-12: led mode 2 oper ation - led_mode[1:0]=10b led status description 1000_led on color1 1000base-t link 100_led on color2 100base-t link 100_led & 1000_led on color3 note 3-4 10base-t link act_led on color1 note 3-7 link operates at full duplex 10_led on color2 transmit/receive activity 10_led & act_led on color3 note 3-4 collision off half duplex, no activity on color1 full duplex, no activity off/color2 half duplex, transmit/receive activity color1/color2 full duplex, transmit/receive activity downloaded from: http:///
lan8810/lan8810i ds00001870b-page 28 ? 2009-2015 microchip technology inc. 3.9.2 variable voltage i/o the devices digital i/o pins are variable voltage, allowing them to take advantage of low power savings from shrinking technologies. these pins can operate at +2.5v or 3.3v. the applied i/o voltage must maintain its value within the toler- ances specified in section 5.0, "operational characteristics," on page 60 . varying the voltage up or down after the trans- ceiver has completely powered-on can cause er rors in the transceiver operation. refer to section 5.0, "operational characteristics," on page 60 for additional information. 3.9.3 isolate mode the device data paths may be electrically isol ated from the gmii interface by setting the isolate bit of the basic control register to 1. in isolation mode, the tr ansceiver does not respond to the txd, txen and txer inputs, but does respond to management transactions. isolation provides a means for multiple transceivers to be connected to the same gmii interface without contention. by default, the transceiver is not isolated (on power-up, isolate =0). 3.9.4 carrier sense the carrier sense signal is output on crs. carrier sense ope ration is defined in the ieee 802.3u standard. the phy asserts carrier sense based only on receive activity whenever the phy is either in repeat er mode or full-duplex mode. otherwise, the phy asserts carrier sense based on either transmit or receive activity. the carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. it activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. carrier sense terminates if a span of 10 con- secutive ones is detected before a /j/k / start-of stream delimiter pair. if an ssd pair is detected, carrier sense is asserted until either /t/r/ endCof-stream delimiter pair or a pair of idle symbols is detected. carrier is negated after the /t/ symbol or the first idle. if /t/ is not followed by /r/, then carrier is maintained. carrier is treated similarly for i dle followed by some non-idle symbol. 3.9.5 collision detect a collision is the occurrence of simultaneous transmit and rece ive operations. the col output is asserted to indicate that a collision has been detected. col remains active for the duration of the collision. col is changed asynchronously to both rxclk and txclk. a collision can only occur in hal f-duplex mode. the col output becomes inactive during full duplex mode. col may be tested by setting the collision test bit of the basic control register . this enables the collision test. col will be asserted within 512 bit times of txen rising a nd will be de-asserted within 4 bit times of txen falling. in 10base-t mode, col pulses for approxim ately 10 bit times (1us), 2us after ea ch transmitted packet (de-assertion of txen). this serves as the signal quality error (sqe ) signal and indicates that the transmission was successful. table 3-13: led mode 3 operation - led_mode[1:0]=11b led status description 1000_led on 1000base-t link blinking transmit/receive activity 100_led on 100base-t link blinking transmit/receive activity 10_led on 10base-t link blinking transmit/receive activity act_led on link operates at full duplex off link operates at half duplex downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 29 lan8810/lan8810i 3.9.6 link integrity this section details the establishment, maintenance and re moval of links between the device and a link partner in 1000base-t, 100base-tx and 10base-t modes. link status is reported in the link status bit of the basic status reg- ister . the link status is also used to drive the device leds as described in section 3.9.1, "leds," on page 27 . 3.9.6.1 establishing and maintaining a link once a link state is determined via auto-negotiation, parallel detection, or forced operation, the device and the link part- ner establish a link. the completion of the auto-negotiation process is reported via the auto-negotiate complete bit of the basic status reg- ister and issues an interrupt as described in section 3.5, "interrupt management," on page 21 . the speed of the link is reported in the speed indication field of the phy special control / status register . the speed is also reported on the led pins for any link. failure to complete the auto-negotiation process is reported through the following status bits: parallel detection fault reported in the auto negotiation expansion register while operating in 10base-t or 100base-tx modes. master/slave configuration fault reported in the master/slave status register while operating in 1000base-t mode. a fault occurs if the master/slave conf iguration conditions do not allow master/slave resolution, as defined in the master/ slave manual config enable and master/slave manual config value bits in the master/slave control register of the local and remote link partners. 3.9.6.2 1000base-t for 1000base-t links, the device and its link partner enter a training phase after completion of the auto-negotiation process. the links exchange idle symbols and use the informati on obtained from receiving this signal to set their adap- tive filter coefficients. these coefficients are used in the receiver to equalize the incoming signal, as well as eliminate signal impairments such as echo and cross-talk. each side indicates completion of th e training phase to its link partner by changing the encoding of the idle-symbols it transmits. the link is established after both sides indicate completion of the training phase. each side continues to send idle sym- bols whenever it has no data to transmit. the link is maintai ned as long as valid idle, data, or carrier extension symbols are received. status of both local and remote receivers is reported in the local receiver status and remote receiver status bits of the master/slave status register . the device also provides an ad vanced auto link breaker feature (only for 1000base-t links). usin g this feature, the link can be taken down if the bit error rate (ber) exceeds the threshold defined in link break threshold field of the link control register . the error counting occurs during the idle time fo r a period commensurate with the specified ber. the auto link breaker feature is enabled via the link break enable bit of the link control register . 3.9.6.3 100base-tx for 100base-tx links, the device and its link partner begin transmitting id le symbols after comple tion of the auto-nego- tiation process. each side continues s ending idle symbols whenever it has no data to transmit. the link is maintained as long as valid idle symbols or data are received. 3.9.6.4 10base-t for 10base-t links, the device and its link partner begin exc hanging normal link pulses (nlps) after completion of the auto-negotiation process. the device transmits an nlp every 16ms and expects to receive an nlp every 8 to 24ms. a link is maintained as long as nlps are received. 3.9.6.5 taking down a link the device takes down an established link when the requ ired conditions are no longer met. when a link is down, data transmission stops. for 10base-t links, the link is taken down after nlps are no long er received. for 100base-tx and 1000base-t links, the link is taken down after valid id le codes are no longer received. after a link is down, the device does the following: if auto-negotiation is enabled, the device re-enter s the auto-negotiation phase a nd begins transmitting flps downloaded from: http:///
lan8810/lan8810i ds00001870b-page 30 ? 2009-2015 microchip technology inc. if auto-negotiation is not enabled, the device transm its nlps in 10base-t mode, and mlt-3s in 100base-tx mode. 3.9.7 speed optimizer the speed optimize function is designed to resolve the i ssue of using auto-negotiation to establish a link on impaired cable plants. examples of impaired cable plants for 1000base-t (gigabit) connections include: channel 2 twisted pair cable plant is broken channel 3 twisted pair cable plant is broken channel 2 and 3 twisted pair cable plants are broken cable plant is too long examples of impaired cable plants for 100base-tx connections include: cable plant is too long using wrong cable plant (such as cat-3) the speed optimize function requires the mac to suppor t 1000/100/10 mbps speeds, 1000/100 mbps speeds, 1000/ 10 mbps or 100/10 mbps speeds. if a link fails to establish after the link partners go through auto-negotiation several times at the hcd (highest common denominator), the device advertises the next highest-allowable speed (as set in the auto negotiation advertisement register ) and restarts auto-negotiation with the new speed. when 1000base-t is advertised, the speed optimize f unction can change its advertised speed from 1000base-t to 100base-tx and from 100base-tx to 10base-t. when 100base- tx is advertised, the speed optimize function can change its advertised speed from 100base-tx to 10base-t. if a previous link has used the speed optimize function to establish a link, when the link goes down, the device begins advertising with all capable speeds. the speed optimize function resets itself to advertise hcd/ all speed capabilities after any of the following occurrences: hardware reset software reset while link partners exchange link pulses through the speed optimize process, the device does not receive link pulses for a period of few seconds after an established link goes down the speed optimize function is enabled via speed optimize enable bit in the 10/100 mode control/status register . when a link (with a speed slower than hcd) is being established through the speed optimize process, it is reported via the speed optimize status bit in the user status 2 register . 3.9.8 loopback operation the local loopback mode is enabled by setting the loopback bit of the basic control register . in this mode, the scram- bled transmit data (output of the scrambler) is looped into the receive logic (input of the de scrambler). this mode is use- ful as a board diagnostic and serves as a quick functional verification of the device. the col signal will be inactive in this mode, unless the collision test bit of the basic control register is set. 3.9.9 ieee 1149.1 (jtag) boundary scan the device includes an integrated jtag boundary-scan test por t for board-level testing. the interface consists of four pins (tdo, tdi, tck and tms) and includes a state machine, data register array, and an instruction register. the jtag pins are described in ta b l e 2 - 5 , " j ta g p i n s " . the jtag interface conforms to the ieee stan dard 1149.1 - 1990 stan- dard test access port (tap) and boundary-scan architecture . all input and output data is synchronous to the tck test clock input. tap input signals tms and tdi are clocked into the test logic on the rising edge of tck, while the output signal tdo is clocked on the falling edge. the jtag logic is reset via a hardware reset or when the tms and tdi pins are high for five tck periods. note: during transmission in local loopback mode, nothing is transmitted to the line and the transmitters are pow- ered down. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 31 lan8810/lan8810i the implemented ieee 1149.1 instructions and their op codes are shown in ta b l e 3 - 11 . 3.9.10 advanced features the device implements several advanced features to enhance manageability of t he ethernet link. th ese features are detailed in the following sub-sections. 3.9.10.1 crossover indicators the device reports crossed channels in the xover resolution 0:1 and xover resolution 2:3 fields of the user status 2 register . this feature is useful for trouble-s hooting problems during network installation. 3.9.10.2 polarity inversion indicators the device automatically detects and corrects inverted signal polarity. this is reported in the polarity inversion bits ( polarity_inv_3 , polarity_inv_2 , polarity_inv_1 and polarity_inv_0 ) of the user status 1 register . the polarity inversion bit for channel 1 ( polarity_inv_1 ) is valid after auto-negotiation is complete as indicated by the auto-negotiate complete bit of the basic status register . the polarity inversion bits for channels 0, 2 and 3 ( polarity_inv_0 , polarity_inv_2 , polarity_inv_3 ) are valid only after the link is up as indicated by the link status bit of the basic status register . 3.9.10.3 receive error-free packets counter the quality of a link can be monitored by using the receive error-free packets counter. the device counts the number of good packets received and reports a 48 -bit value across 3 advanced registers: receive error-free packets counter low register , receive error-free packets counter mid register , and receive error-free packets counter high reg- ister . the receive error-free packets counter low register latches the two other relat ed counter registers and must always be read first. the receive error-free packets counter high register register must be read last, and will auto- matically clear the counter. 3.9.10.4 crc error counter this 48-bit counter counts the number of crc errors detected . its value can be read acro ss 3 advanced registers: crc error counter low register , crc error counter mid register , and crc error counter high register . the crc error counter low register latches the two other related counter registers and must always be read first. the crc error counter high register must be read last, and will automatically clear the counter. 3.9.10.5 receive error during data counter this 16-bit counter counts the number of errors that occurred while data was being received. the value is read from the receive error during data counter register . table 3-14: ieee 1149.1 op codes instruction op code comment bypass 111 mandatory instruction sample/preload 010 mandatory instruction extest 000 mandatory instruction clamp 011 optional instruction highz 100 optional instruction idcode 001 optional instruction note: all digital i/o pins support ieee 1149.1 operation. analog pins and the xo pin do not support ieee 1149.1 operation. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 32 ? 2009-2015 microchip technology inc. 3.9.10.6 receive error during idle counter this 16-bit counter counts the number of errors that occurred during idle. the value is read from the receive error during idle counter register register. 3.9.10.7 transmitted packets counter this 48-bit counter counts the number of packets that were transmitted. its value can be read across 3 advanced reg- isters: transmit packet counter low register , transmit packet counter mid register , and transmit packet counter high register . the transmit packet counter low register latches the two other relate d counter registers and must always be read first. the transmit packet counter high register must be read last, and it will automatically clear the counter. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 33 lan8810/lan8810i 3.10 application diagrams this section provides typical appl ication diagrams for the following: simplified application diagram power supply & twisted pair interface diagram 3.10.1 simplified application diagram figure 3-4: simplified application diagram 8 lan8810/ lan8810i txd[7:0] txclk txen txer tr0p tr0n magnetics rj45 tr1p tr1n tr2p tr2n tr3p tr3n 8 rxd[7:0] rxclk rxdv 25mhz config[3:0] 4 interface mdio mdc nreset rxer gtxclk irq col crs xi xo jtag (optional) tdi tms tck tdo hpd gmii 10_led 100_led 1000_led act_led downloaded from: http:///
lan8810/lan8810i ds00001870b-page 34 ? 2009-2015 microchip technology inc. 3.10.2 power supply & twisted pair interface diagram figure 3-5: power supply & twisted pair interface diagram lan8810/lan8810i ethrbias vss 8.06k ohm 1% (x4) vdd12a vdd12pll c bypass vdd12bias c bypass vdd12core (x6) c bypass vddvario (x6) c bypass x6x6 power supply 2.5 C 3.3v power supply 1.2v magnetics tr0p tr0n 12 3 4 5 6 7 8 1000 pf 2 kv circuitry within the dotted line is for channel 0. duplicate this circuit for channels 1, 2 and 3. rj45 75 c bypass 49.9 49.9 0.022uf note: 0.022uf capacitor is optional. in an emi constrained environment, populate this capacitor. the component must be placed close to the transformer. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 34 lan8810/lan8810i 4.0 register descriptions this chapter describes the various cont rol and status registers (csrs). all registers follow the ieee 802.3 (clause 22.2.4) management register set. all fu nctionality and bit definitions comply wi th these standards. the ieee 802.3 spec- ified register index (in decimal) is included with each regi ster definition, allowing for a ddressing of these registers via the serial management interface (smi) protocol. the device registers are categorized into following groups: primary phy registers advanced phy registers 4.1 register nomenclature table 4-1 describes the register bit attri butes used throughout this document. many of these register bit notations can be comb ined. some examples of this are shown below: r/w: can be written. will return current setting on a read. r/wac: will return current setting on a read. writing anything clears the bit. table 4-1: register bit types register bit type notation register bit description r read: a register or bit with this attribute can be read. w write: a register or bit with th is attribute can be written. ro read only: read only. writes have no effect. wo write only: if a register or bit is write-on ly, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect. wac write anything to clear: writing anything clears the value. rc read to clear: contents is cleared after the read. writes have no effect. ll latch low: clear on read of register. lh latch high: clear on read of register. sc self-clearing: contents is self-cleared after the bein g set. writes of zero have no effect. contents can be read. ro/lh read only, latch high: this mode is used by the ether net phy registers. bits with this attribute will stay high until the bit is read. af ter it a read, the bit will remain high, but will change to low if the condition th at caused the bit to go high is removed. if the bit has not been read the bit will remain high regardless of if its cause has been removed. nasr not affected by software reset: the state of nasr bits does not change on assertion of a software reset. x either a 1 or 0. reserved reserved field: reserved fields must be written with zeros, unless otherwise indicated, to ensure future compatibility. the value of reserved bits is not guaranteed on a read. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 35 ? 2009-2015 microchip technology inc. 4.2 primary phy registers the primary phy registers are accessed via the smi bus. an index is used to access individual primary registers. pri- mary phy register indexes are shown in table 4-2, "phy control and status registers" . additional read-only advanced registers are indirectly accessible via the advanced register address port and advanced register read data port . sec- tion 4.3, "advanced phy registers," on page 53 provides detailed information regarding the advanced registers. note 1: all unlisted register index values are no t supported and should not be addressed. 2: the nasr (not affected by software reset) designation is only applicable when the phy soft reset (reset) bit of the basic control register is set. table 4-2: phy control and status registers index (in decimal) register name 0 basic control register 1 basic status register 2 phy identifier 1 register 3 phy identifier 2 register 4 auto negotiation advertisement register 5 auto negotiation link partner ability register 6 auto negotiation expansion register 7 auto negotiation next page tx register 8 auto negotiation next page rx register 9 master/slave control register 10 master/slave status register 15 extended status register 16 link control register 17 10/100 mode control/status register 18 10/100 special modes register 19 extended mode control/status register 20 advanced register address port 21 advanced register read data port 27 control / status indications register 29 interrupt source flags register 30 interrupt mask register 31 phy special control / status register downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 36 lan8810/lan8810i 4.2.1 basic control register note 4-1 the default is determined by the config[3:2] pins as described in section 3.8.1.2.3, "configuration bits impacted by the mode of operation," on page 26 index (in decimal): 0 size: 16 bits bits description type default 15 phy soft reset (reset) 1 = phy software reset. this bit is self-clearing. when setting this bit, do not set other bits in this register. the conf iguration is set from the register bit values as described in section 3.6.2, "software reset," on page 22 . note: the phy will be in the normal mode after a phy software reset. r/w sc 0b 14 loopback 0 = normal operation 1 = loopback mode r/w 0b 13 speed select[0] together with speed select[1] , sets speed per the following table: [speed select1][speed select 0] 00 = 10mbps 01 = 100mbps 10 = 1000mbps 11 = reserved note: ignored if the auto-negotiation enable bit of this register is 1. r/w note 4-1 12 auto-negotiation enable 0 = disable auto-negotiate process 1 = enable auto-negotiate process (overrides the speed select[0] , speed select[1] , and duplex mode bits of this register) r/w note 4-1 11 power down 0 = normal operation 1 = general power down mode note: auto-negotiation enable must be cleared before setting this bit. r/w 0b 10 isolate 0 = normal operation 1 = electrical isolation of phy from gmii r/w 0b 9 restart auto-negotiate 0 = normal operation 1 = restart auto-negotiate process note: bit is self-clearing. r/w sc 0b 8 duplex mode 0 = half duplex 1 = full duplex note: ignored if the auto-negotiation enable bit of this register is 1. r/w note 4-1 7 collision test 0 = disable col test 1 = enable col test r/w 0b 6 speed select[1] see description for speed select[0] for details. ro note 4-1 5:0 reserved ro - downloaded from: http:///
lan8810/lan8810i ds00001870b-page 37 ? 2009-2015 microchip technology inc. 4.2.2 basic status register index (in decimal): 1 size: 16 bits bits description type default 15 100base-t4 0 = no t4 ability 1 = t4 able ro 0b 14 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 1b 13 100base-tx half duplex 0 = no tx half duplex ability 1 = tx with half duplex ro 1b 12 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex ro 1b 11 10base-t half duplex 0 = no 10mbps with half duplex ability 1 = 10mbps with half duplex ro 1b 10 100base-t2 full duplex 0 = phy not able to perform full duplex 100base-t2 1 = phy able to perform full duplex 100base-t2 ro 0b 9 100base-t2 half duplex 0 = phy not able to perfo rm half duplex 100base-t2 1 = phy able to perform half duplex 100base-t2 ro 0b 8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 ro 1b 7:6 reserved ro - 5 auto-negotiate complete 0 = auto-negotiate process not completed 1 = auto-negotiate process completed ro 0b 4 remote fault 0 = no remote fault 1 = remote fault condition detected ro/lh 0b 3 auto-negotiate ability 0 = unable to perform auto-negotiation function 1 = able to perform aut o-negotiation function ro 1b 2 link status 0 = link is down 1 = link is up ro/ll 0b 1 jabber detect 0 = no jabber condition detected 1 = jabber condition detected ro/lh 0b 0 extended capabilities 0 = does not support extended capabilities registers 1 = supports extended capabilities registers ro 1b downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 38 lan8810/lan8810i 4.2.3 phy identi fier 1 register 4.2.4 phy identi fier 2 register note 4-2 the default value of this field will vary dependant on the silicon revision number. 4.2.5 auto negotiation advertisement register index (in decimal): 2 size: 16 bits bits description type default 15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui), respectively. oui=00800fh r/w 0007h index (in decimal): 3 size: 16 bits bits description type default 15:10 phy id number assigned to the 19th through 24th bits of the oui. r/w c0h 9:4 model number six-bit manufacturers model number. r/w 0eh 3:0 revision number four-bit manufacturers revision number. r/w note 4-2 index (in decimal): 4 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable note: this device does not support next page ability. r/w 0b 14 reserved ro - 13 remote fault 0 = no remote fault 1 = remote fault detected r/w 0b 12 reserved ro - downloaded from: http:///
lan8810/lan8810i ds00001870b-page 39 ? 2009-2015 microchip technology inc. note 4-3 the default is determined by the config1 pin as described in section 3.8.1.2.1, "configuring the smi address (config[1:0])," on page 25 note 4-4 the default is determined by the config[3:2] pins as described in section 3.8.1.2.3, "configuration bits impacted by the mode of operation," on page 26 . 4.2.6 auto negotiation link partner ability register 11 asymmetric pause 0 = asymmetrical pause direct ion is not supported by mac 1 = asymmetrical pause direction is supported by mac r/w 0b 10 pause operation (pause) 0 = pause operation is not supported by mac 1 = pause operation is supported by mac r/w note 4-3 9 reserved ro - 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex r/w note 4-4 7 100base-tx 0 = no tx ability 1 = tx able r/w note 4-4 6 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex r/w note 4-4 5 10base-t 0 = no 10mbps ability 1 = 10mbps able r/w note 4-4 4:0 selector field 00001 = ieee 802.3 r/w 00001b index (in decimal): 5 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received 1 = link code word received from partner ro 0b 13 remote fault 0 = no remote fault 1 = remote fault detected ro 0b 12:11 reserved ro - 10 pause operation (pause) 0 = pause operation is not supported by remote mac 1 = pause operation is supported by remote mac ro 0b bits description type default downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 40 lan8810/lan8810i 4.2.7 auto negotiation expansion register 9 100base-t4 0 = no t4 ability 1 = t4 able note: this phy does not support t4 ability. ro 0b 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 0b 7 100base-tx 0 = no tx ability 1 = tx able ro 0b 6 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex ro 0b 5 10base-t 0 = no 10mbps ability 1 = 10mbps able ro 0b 4:0 selector field 00001 = i eee 802.3 ro 00001b index (in decimal): 6 size: 16 bits bits description type default 15:5 reserved ro - 4 parallel detection fault 0 = no fault detected by parallel detection logic 1 = fault detected by parallel detection logic ro/lh 0b 3 link partner next page able 0 = link partner does not have next page ability 1 = link partner has next page ability ro 0b 2 next page able 0 = local device does not have next page ability 1 = local device has next page ability ro 0b 1 page received 0 = new page not yet received 1 = new page received ro/lh 0b 0 link partner auto -negotiation able 0 = link partner does not have auto-negotiation ability 1 = link partner has auto-negotiation ability ro 0b bits description type default downloaded from: http:///
lan8810/lan8810i ds00001870b-page 41 ? 2009-2015 microchip technology inc. 4.2.8 auto negotiation next page tx register 4.2.9 auto negotiation next page rx register index (in decimal): 7 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 message page 0 = unformatted page 1 = message page r/w 1b 12 acknowledge 2 0 = device cannot comply with message 1 = device will comply with message r/w 0b 11 toggle 0 = previous value was high 1 = previous value was low ro 0b 10:0 message code message/unformatted code field rw 00 0000 0001b index (in decimal): 8 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received from partner 1 = link code word received from partner ro 0b 13 message page 0 = unformatted page 1 = message page ro 1b 12 acknowledge 2 0 = device cannot comply with message 1 = device will comply with message ro 0b 11 toggle 0 = previous value was high 1 = previous value was low ro 0b 10:0 message code message/unformatted code field ro 000 0000 0000b downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 42 lan8810/lan8810i 4.2.10 master/slave control register note 4-5 the default is determined by the config[3:2] pins as described in section 3.8.1.2.3, "configuration bits impacted by the mode of operation," on page 26 . index (in decimal): 9 size: 16 bits bits description type default 15:13 test mode 000 = normal mode 001 = test mode 1 - transmit waveform test 010 = test mode 2 - transmit jitter test in master mode 011 = test mode 3 - transmit jitter test in slave mode 100 = test mode 4 - transmitter distortion test 101 = reserved 110 = reserved 111 = reserved note: setting these bits may prevent co rrect link partner connection if both the device phy and link pa rtner phy are set as masters. r/w 000b 12 master/slave manual config enable 0 = disable master-slave manual configuration value 1 = enable master-slave manual configuration value r/w note 4-5 11 master/slave manual config value active only when the master/slave manual config enable bit of this register is 1. 0 = slave 1 = master r/w note 4-5 10 port type active only when the master/slave manual config enable bit of this register is 0. 0 = single port device 1 = multiport device r/w note 4-5 9 1000base-t full duplex 0 = advertise phy is not 100 0base-t full duplex capable 1 = advertise phy is 1000 base-t full duplex capable r/w note 4-5 8 1000base-t half duplex 0 = advertise phy is not 100 0base-t half duplex capable 1 = advertise phy is 1000 base-t half duplex capable r/w note 4-5 7:0 reserved ro - downloaded from: http:///
lan8810/lan8810i ds00001870b-page 43 ? 2009-2015 microchip technology inc. 4.2.11 master/slave status register index (in decimal): 10 size: 16 bits bits description type default 15 master/slave configuration fault 0 = no master-slave configuration fault detected 1 = master-slave configuration fault detected ro/lh 0b 14 master/slave configuration resolution 0 = local phy configuration resolved to slave 1 = local phy configuration resolved to master ro 0b 13 local receiver status 0 = local receiver not ok 1 = local receiver ok ro 0b 12 remote receiver status 0 = remote receiver not ok 1 = remote receiver ok ro 0b 11 lp 1000t fd this bit is valid only when the page received bit of the auto negotiation expansion register is 1. 0 = link partner is not capable of 1000base-t full duplex 1 = link partner is capa ble of 1000base-t full duplex ro 0b 10 lp 1000t hd this bit is valid only when the page received bit of the auto negotiation expansion register is 1. 0 = link partner is not capable of 1000base-t half duplex 1 = link partner is capa ble of 1000base-t half duplex ro 0b 9:8 reserved ro - 7:0 idle error count cumulative count of the errors detected when the receiver is receiving idles. these bits are reset to all zeroes when the error count is read by the management function or upon executio n of a hardware reset, software reset, or logical reset. this field is held at all ones in case of over-flow. this field can be used to trigger an interrupt upon overflow. refer to section 3.5, "interrupt ma nagement," on page 21 for additional information. ro 00h downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 44 lan8810/lan8810i 4.2.12 extended status register 4.2.13 link control register index (in decimal): 15 size: 16 bits bits description type default 15 1000base-x full duplex 0 = phy not able to perfo rm full duplex 1000base-x 1 = phy able to perform full duplex 1000base-x ro 0b 14 1000base-x half duplex 0 = phy not able to perform half duplex 1000base-x 1 = phy able to perform half duplex 1000base-x ro 0b 13 1000base-t full duplex 0 = phy not able to perfo rm full duplex 1000base-t 1 = phy able to perform full duplex 1000base-t ro 1b 12 1000base-t half duplex 0 = phy not able to perform half duplex 1000base-t 1 = phy able to perform half duplex 1000base-t ro 1b 11:0 reserved ro - index (in decimal): 16 size: 16 bits bits description type default 15:10 reserved ro - 9:8 speed optimize control this register sets the number of auto negotiation attempts before the speed optimize mechanism redu ces the advertised speed. 00 = 7 attempts 01 = 5 attempts 10 = 4 attempts 11 = 3 attempts note: refer to section 3.9.5, "speed optimizer," on page 29 for additional information. r/w 00b 7:6 reserved ro - 5:4 link break threshold idle error threshold for failing the link, if link break in enabled. 00 = link break threshold is 10e-8. 01 = link break threshold is 10e-9. 10 = link break threshold is 10e-10. 11 = link break threshold is 10e-11 r/w 10b 3 link break enable 0 = link break is disabled 1 = link break is enabled r/w 0b downloaded from: http:///
lan8810/lan8810i ds00001870b-page 45 ? 2009-2015 microchip technology inc. 4.2.14 10/100 mode control/status register 2 power optimization disable 0 = automatic power optimization is enabled 1 = automatic power optimization is disabled (power consumption is maximum) r/w 0b 1 reserved ro - 0 lrst logic reset. this bit generates a reset that put all the logic into a known state, but does not affect the register sets and 10/100 circuits. this bit is not a self-clearing bit. writing "1" to this bit generates synchronous reset. ro - index (in decimal): 17 size: 16 bits bits description type default 15 edshort energy detect short detection mode 0 = normal detect mode 1 = short detect mode r/w 0b 14 fastrip 10base-t fast mode 0 = normal operation 1 = activates phyt_10 test mode r/w 0b 13 edpwrdown enable the energy detect power-down mode 0 = energy detect power-down is disabled 1 = energy detect power-down is enabled r/w 0b 12 ed power down mode select energy detect power down mode 0 = ed power down mode without nlp transmission 1 = ed power down mode with nlp transmission r/w 0b 11:8 reserved ro - 7 speed optimize enable 0 = disable speed optimize 1 = enable speed optimize note: refer to section 3.9.5, "speed optimizer," on page 29 for additional information. r/w 0b 6 autoneg np enable 0 = next page is disabled in the auto-negotiation process 1 = next page is enabled in the auto-negotiation process r/w 1b 5 auto mdix disable 0 = auto xover is enabled 1 = auto xover is disabled selection is done manually r/w 0b bits description type default downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 46 lan8810/lan8810i 4.2.15 10/100 special modes register 4 auto next page disable setting this bit disables automatic next page exchange in 1000base-t. advertising of next pages then depends on the value of the next page bit of the auto negotiation advertisement register . in this case, if next page is cleared, only the base page is sent. 0 = normal operation 1 = automatic next page is disabled r/w 0b 3:2 reserved ro - 1 energyon this bit indicates whether energy is detec ted on the line. it is reset to 1 by a hardware reset. when a software reset is asserted, this bit is cleared. if this bit was set prior to a software reset, it will cause the int7 bit of the interrupt source flags register to be set. therefore, after a software or hardware reset, the int7 bit should be cleared by writing a 1 to it. refer to section 3.5, "interrupt management," on page 21 for additional energyon information. ro 1b 0 semi crossover enable setting this register enables semi cross over. 0 = disable semi cross over 1 = enable semi cross over note: refer to section 3.2, "hp auto-mdix," on page 16 for additional information. r/w 0b index (in decimal): 18 size: 16 bits bits description type default 15 enable rxdv early assertion setting this bit enables early assert ion of rxdv in 10base-t. rxdv is asserted before the sfd. 0 = disable 1 = enable r/w 0b 14 10bt hd loopback disable setting this bit disables mii loopback in 10base-t half duplex mode. 0 = normal operation 1 = activates phyt_10 test mode r/w nasr 000000b 13:8 reserved ro - 7 crc error counter data source setting this bit changes the data source of the 1000base-t crc error counter. 0 = data source in 1000base-t received data 1 = data source in 1000base-t transmitted data r/w 0b 6 mclk25en enable an 25mhz mac clock output. 0 = 125mhz 1 = 25mhz ro 0b 5 reserved ro - bits description type default downloaded from: http:///
lan8810/lan8810i ds00001870b-page 47 ? 2009-2015 microchip technology inc. note 4-6 the default is determined by the config[1:0] pins as described in section 3.8.1.2. 1, "configuring the smi address (config[1:0])," on page 25 . 4.2.16 extended mode co ntrol/status register 4:0 phyadd[4:0] the phy address is used for the smi address and for the initialization of the cipher (scrambler) key. r/w nasr note 4-6 index (in decimal): 19 size: 16 bits bits description type default 15:11 mod configures mode of operation. refer to section 3.8.1.2.2, "configuring the mode of operation (c onfig[3:2])," on page 26 for details. note: the mod bits should not be modified and must be preserved when writing to this register. r/w nasr note 4-7 10:9 transmitter fifo depth 00 = 4 bytes 01 = 5 bytes 10 = 6 bytes 11 = 7 bytes r/w 00b 8:6 reserved these bits must be written as 000b. ro - 5:4 led_mode[1:0] 00 = reserved 01 = led mode 1 10 = led mode 2 11 = led mode 3 refer to section 3.9.1, "leds," on page 26 for additional information. r/w 11b 3 reserved this bit must be written as 1b r/w 1b 2 mdi/mdi-x 0:1 selects between mdi and mdi-x for channel 0 and channel 1 only if the auto mdix disable bit of the 10/100 mode control/status register is 1. 0 = mdi 1 = mdi-x rw 0b 1 mdi/mdi-x 2:3 selects between mdi and mdi-x for channel 2 and channel 3 only if the auto mdix disable bit of the 10/100 mode control/status register is 1. 0 = mdi 1 = mdi-x rw 0b 0 conditional parallel detect 0 = parallel detect. ( auto negotiation advertisement register is ignored.) 1 = conditional parallel detect only at the speed advertised in the auto negotiation advertisement register . 10base-t half duplex ( 10base-t bit =1) 100base-tx half duplex ( 100base-tx bit =1) rw 0b bits description type default downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 48 lan8810/lan8810i note 4-7 the default mode is determined by the config[3:2] pins as described in section 3.8.1.2.2, "configuring the mode of operat ion (config[3:2])," on page 26 4.2.17 advanced register address port 4.2.18 advanced register read data port index (in decimal): 20 size: 16 bits bits description type default 15 read when this bit is set to 1, the contents of the advanced regi ster selected by the register address field are latched to the advanced register read data port . this bit is self-cleared. sc 0b 14:7 reserved must be written with 00000011b for proper operation. the values of reserved bits are not guaranteed on a read. r/w - 6:0 register address the address of the advanced register being accessed (0-12). ro 0000000b note: refer to section 4.3, "advanced phy registers," on page 53 for additional information on the advanced register set. index (in decimal): 21 size: 16 bits bits description type default 15:0 read data read from the advanced register selected via the advanced register address port . ro 0000h note: refer to section 4.3, "advanced phy registers," on page 53 for additional information on the advanced register set. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 49 ? 2009-2015 microchip technology inc. 4.2.19 control / status indications register 4.2.20 interrupt sour ce flags register index (in decimal): 27 size: 16 bits bits description type default 15:5 reserved ro - 4 xpol polarity state of the 10base-t: 0 = normal polarity 1 = reversed polarity ro 0b 3:0 reserved ro - index (in decimal): 29 size: 16 bits bits description type default 15:11 reserved ro - 10 int10 0 = not source of interrupt 1 = transmitter elastic buffer overflow lh/wc 0b 9 int9 0 = not source of interrupt 1 = transmitter elastic buffer underflow lh/wc 0b 8 int8 0 = not source of interrupt 1 = idle error count overflow lh/wc 0b 7 int7 0 = not source of interrupt 1 = energyon generated this bit is set when there is a 0 to 1 transition of the energyon bit in the 10/100 mode control/ status register . this occurs when transitioning from no energy detected to energy detected, or vice versa. lh/wc 0b 6 int6 0 = not source of interrupt 1 = auto-negotiation complete lh/wc 0b 5 int5 0 = not source of interrupt 1 = remote fault detected lh/wc 0b 4 int4 0 = not source of interrupt 1 = link down (link status negated) lh/wc 0b downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 50 lan8810/lan8810i note: refer to section 3.5, "interrupt management," on page 21 for additional information. 4.2.21 interrupt mask register 3 int3 0 = not source of interrupt 1 = auto-negotiation lp acknowledged lh/wc 0b 2 int2 0 = not source of interrupt 1 = parallel detection fault or master/slave configuration fault lh/wc 0b 1 int1 0 = not source of interrupt 1 = auto-negotiation page received lh/wc 0b 0 reserved ro - index (in decimal): 30 size: 16 bits bits description type default 15:11 reserved ro - 10 int10_en transmitter elastic buffer overflow interrupt enable. 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 9 int9_en transmitter elastic buffer underflow interrupt enable. 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 8 int8_en idle error count overflow interrupt enable. 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 7 int7_en energyon interrupt enable 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 6 int6_en auto-negotiation interrupt enable 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 5 int5_en remote fault detected interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 4 int4_en link down (link status negated) interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b bits description type default downloaded from: http:///
lan8810/lan8810i ds00001870b-page 51 ? 2009-2015 microchip technology inc. 4.2.22 phy special control / status register note 4-8 set according to the results of auto-negotiation. 3 int3_en auto-negotiation lp acknowledge interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 2 int2_en parallel detection fault or master/slave configuration fault interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 1 int1_en auto-negotiation page received interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 0 reserved ro - note: refer to section 3.5, "interrupt management," on page 21 for additional information. index (in decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 auto-negotiation done indication 0 = auto-negotiation is not done or disabled (or not active) 1 = auto-negotiation is done note: this is a duplicate of register 1.5, however reads to register 31 do not clear status bits. ro 0b 11:5 reserved ro - 4:2 speed indication hcdspeed value: [001]=10mbps half-duplex [101]=10mbps full-duplex [010]=100base-tx half-duplex [110]=100base-tx full-duplex ro note 4-9 1:0 reserved ro - bits description type default downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 52 lan8810/lan8810i 4.3 advanced phy registers the advanced phy registers are accessed using the following procedure: 1. write to the advanced register address port with the read bit set high, and the address of the desired advanced register in the register address field. 2. read the contents of the selected register from advanced register read data port . 4.3.1 advanced register mapping note: the advanced registers cannot be wri tten. all advanced registers are comp rised of read-only (ro), or read- to-clear (rc) bits. table 4-3: advanced register mapping registernumber register name u0 user status 1 register u1 user status 2 register u2 receive error-free packets counter high register u3 receive error-free packets counter mid register u4 receive error-free packets counter low register u5 crc error counter high register u6 crc error counter mid register u7u8 receive error during data counter register u9 receive error during idle counter register u10 transmit packet counter high register u11 transmit packet counter mid register u12 transmit packet counter low register downloaded from: http:///
lan8810/lan8810i ds00001870b-page 53 ? 2009-2015 microchip technology inc. 4.3.2 user status 1 register index: u0 size: 16 bits bits description type default 15 pllready 0 = pll is not locked 1 = pll is locked ro 0b 14 polarity_inv_3 this bit indicates reverse polarity on channel 3 when operating in 1000base-t mode. 0 = channel 3 polarity is correct 1 = channel 3 polarity is reversed ro 0b 13 polarity_inv_2 this bit indicates reverse polarity on channel 2 when operating in 1000base-t mode. 0 = channel 2 polarity is correct 1 = channel 2 polarity is reversed ro 0b 12 polarity_inv_1 this bit indicates reverse polarity on channel 1 when operating in 1000base-t mode. 0 = channel 1 polarity is correct 1 = channel 1 polarity is reversed ro 0b 11 polarity_inv_0 this bit indicates reverse polarity on channel 0 when operating in 1000base-t mode. 0 = channel 0 polarity is correct 1 = channel 0 polarity is reversed ro 0b 10:0 reserved ro - downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 54 lan8810/lan8810i 4.3.3 user status 2 register 4.3.4 receive error-free packets counter high register index: u1 size: 16 bits bits description type default 15 xover resolution 0:1 0 = channel 0 and channel 1 resolved as mdi. 1 = channel 0 and channel 1 resolved as mdi-x. ro 0b 14 xover resolution 2:3 0 = channel 2 and channel 3 resolved as mdi. 1 = channel 2 and channel 3 resolved as mdi-x. ro 0b 13 speed optimize status when set, indicates the link was established using the speed optimize mechanism. note: refer to section 3.9.5, "speed optimizer," on page 29 for additional information. ro 0b 12:0 reserved ro - index: u2 size: 16 bits bits description type default 15:0 rcvgpkt[47:32] counts the received error-free packets. contains the 16 upper bits of the 48-bit counter. reading this register resets all bi ts in the receive error-free packets counter. ro/ rc 0000h note: the 48-bit receive error-free packets counter is split across 3 registers. in order to read the counter cor- rectly, the registers must be read in the following order: receive error-free packets counter low register , receive error-free packets counter mid register , receive error-free packets counter high register . after reading the high register, the counter will be automatically cleared. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 55 ? 2009-2015 microchip technology inc. 4.3.5 receive error-free pac kets counter mid register 4.3.6 receive error-free pac kets counter low register index: u3 size: 16 bits bits description type default 15:0 rcvgpkt[31:16] counts the received error-free packets. contains the 16 middle bits of the 48-bit counter. ro 0000h note: the 48-bit receive error-free packets counter is split across 3 registers. in order to read the counter cor- rectly, the registers must be read in the following order: receive error-free packets counter low register , receive error-free packet s counter mid register , receive error-free packets counter high register . after reading the high register, the counter will be automatically cleared. index: u4 size: 16 bits bits description type default 15:0 rcvgpkt[15:0] counts the received error-free packets. contains the 16 low-order bi ts of the 48-bit counter. ro 0000h note: the 48-bit receive error-free packets counter is split across 3 registers. in order to read the counter cor- rectly, the registers must be read in the following order: receive error-free packets counter low register , receive error-free packet s counter mid register , receive error-free packets counter high register . after reading the high register, the counter will be automatically cleared. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 56 lan8810/lan8810i 4.3.7 crc error counter high register 4.3.8 crc error co unter mid register 4.3.9 crc error co unter low register index: u5 size: 16 bits bits description type default 15:0 crcerr[47:32] counts the crc errors, which are gener ated by the crc checker circuit. contains the 16 upper bits of the 48-bit counter. reading this register resets all bits in the crc error counter. ro/ rc 0000h note: the 48-bit crc error counter is split across 3 registers. in order to read the counter correctly, the registers must be read in the following order: , crc error counter mid register , crc error counter high register . after reading the high register, the counter will be automatically cleared. index: u6 size: 16 bits bits description type default 15:0 crcerr[31:16] counts the crc errors, which are gener ated by the crc checker circuit. contains the 16 middle bits of the 48-bit counter. ro 0000h note: the 48-bit crc error counter is split across 3 registers. in order to read the counter correctly, the registers must be read in the following order: , crc error counter mid register , crc error counter high register . after reading the high register, the counter will be automatically cleared. index: u7 size: 16 bits bits description type default 15:0 crcerr[15:0] counts the crc errors, which are gener ated by the crc checker circuit. contains the 16 low-order bi ts of the 48-bit counter. ro 0000h note: the 48-bit crc error counter is split across 3 registers. in order to read the counter correctly, the registers must be read in the following order: , crc error counter mid register , crc error counter high register . after reading the high register, the counter will be automatically cleared. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 57 ? 2009-2015 microchip technology inc. 4.3.10 receive error during data counter register 4.3.11 receive error during idle counter register 4.3.12 transmit packet counter high register 4.3.13 transmit packet counter mid register index: u8 size: 16 bits bits description type default 15:0 rxerind_data[15:0] counts the assertions of rxer (going from low to high) when rxdv is high . ro/ rc 0000h index: u9 size: 16 bits bits description type default 15:0 rxerind_idle[15:0] counts the assertions of rxer (going from low to high) when rxdv is low . ro/ rc 0000h index: u10 size: 16 bits bits description type default 15:0 txpkt[47:32] counts the number of transmitted packets. contains the 16 upper bits of the 48-bit counter. reading this register resets all bits in the trans mit packet counter. ro/ rc 0000h note: the 48-bit transmit packet counter is split across 3 registers. in order to read the counter correctly, the reg- isters must be read in the following order: transmit packet counter low register , transmit packet counter mid register , transmit packet counter high register . after reading the high register, the counter will be automatically cleared. index: u11 size: 16 bits downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 58 lan8810/lan8810i 4.3.14 transmit packet counter low register bits description type default 15:0 txpkt[31:16] counts the number of transmitted packets. contains the 16 middle bits of the 48-bit counter. ro 0000h note: the 48-bit transmit packet counter is split across 3 registers. in order to read the counter correctly, the reg- isters must be read in the following order: transmit packet counter low register , transmit packet counter mid register , transmit packet counter high register . after reading the high register, the counter will be automatically cleared. index: u12 size: 16 bits bits description type default 15:0 txpkt[15:0] counts the number of transmitted packets. contains the 16 low-order bi ts of the 48-bit counter. ro 0000h note: the 48-bit transmit packet counter is split across 3 registers. in order to read the counter correctly, the reg- isters must be read in the following order: transmit packet counter low register , transmit packet counter mid register , transmit packet counter high register . after reading the high register, the counter will be automatically cleared. downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 60 lan8810/lan8810i 5.0 operational characteristics 5.1 absolute maximum ratings* supply voltage (vddvario) ( note 5-1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +3.6v analog supply voltage (vdd12a) ( note 5-1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v to +1.5v digital core supply voltage (vdd12core) ( note 5-1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +1.5v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +3.6v positive voltage on signal pins, with respect to ground ( note 5-2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v negative voltage on signal pins, with respect to ground ( note 5-3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v positive voltage on xi, with re spect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6v positive voltage on xo, with re spect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 5-4 junction to ambient ( ? ja ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..22.5 o c/w junction to top of package ( jt ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..0.1 o c/w storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 latch-up performance per eia/jesd 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..+/-150ma note 5-1 when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. note 5-2 this rating does not apply to the following pins: xi, xo, ethrbias. note 5-3 this rating does not apply to the following pins: ethrbias. note 5-4 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condit ion exceeding those indicated in section 5.2, "operating conditions**" , section 5.4, "dc specifications" , or any other applicable section of this specif ication is not implied. note, device signals are not 5 volt tolerant unless specified otherwise. 5.2 operating conditions** supply voltage (vddvario) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25v to +3.6v supply voltage (vdd12a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14v to +1.26v digital core supply voltage (vdd12core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14v to +1.26v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25v to +3.6v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 5-4 **proper operation of the device is guar anteed only within the ranges specified in this section. after the device has com- pleted power-up, vddvario and the magnetics power supply must maintain their voltage level within +/-10%. varying the voltage greater than +/-10% after the device has completed power-up can cause errors in device operation. downloaded from: http:///
lan8810/lan8810i ds00001870b-page 61 ? 2009-2015 microchip technology inc. 5.3 power consumption this section details the power consumpt ion of the device as measured during various modes of operation. power con- sumption values are provided for both the device-only, and for the device plus ethernet components. power dissipation is impacted by temperature, supply vo ltage, and external source/sink requir ements. all measurements were taken at +25 ? c. note 5-5 when the external magnetics operate at +2.5v, current consumption remains the same. however, ethernet component power consumption will be reduced accordingly. note 5-6 when the external magnetics operate at +2.5v, current consumption remains the same. however, ethernet component power consumption will be reduced accordingly. note 5-7 when the external magnetics operate at +2.5v, current consumption remains the same. however, ethernet component power consumption will be reduced accordingly. table 5-1: power consumption - 1000base-t linked parameter typical unit supply current (vddvario) (@ +3.3v) 36 ma supply current (vdd12core, vdd12bias, vdd12pll, vdd12a) (@ +1.2v) 454 ma external magnetics current (@ +3.3v) 202 ma total power dissipation (device only) ( note 5-5 ) 665 mw total power dissipation (devic e and ethernet components) ( note 5-5 ) 1331 mw table 5-2: power consumption - 100base-tx linked parameter typical unit supply current (vddvario) (@ +3.3v) 24 ma supply current (vdd12core, vdd12bia s, vdd12pll, vdd12a) (@ +1.2v) 82 ma external magnetics current (@ +3.3v) 63 ma total power dissipation (device only) ( note 5-6 ) 177 mw total power dissipation (devic e and ethernet components) ( note 5-6 ) 385 mw table 5-3: power consumption - 10base-t linked parameter typical unit supply current (vddvario) (@ +3.3v) 21 ma supply current (vdd12core, vdd12bia s, vdd12pll, vdd12a) (@ +1.2v) 32 ma external magnetics current (@ +3.3v) 123 ma total power dissipation (device only) ( note 5-7 ) 107 mw total power dissipation (devic e and ethernet components) ( note 5-7 ) 513 mw downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 62 lan8810/lan8810i note 5-8 when the external magnetics operate at +2.5v, current consumption remains the same. however, ethernet component power consumption will be reduced accordingly. note 5-9 when the external magnetics operate at +2.5v, current consumption remains the same. however, ethernet component power consumption will be reduced accordingly. note 5-10 when the external magnetics operate at +2.5v, current consumption remains the same. however, ethernet component power consumption will be reduced accordingly. table 5-4: power consumption - energy detect parameter typical unit supply current (vddvario) (@ +3.3v) 30 ma supply current (vdd12core, vdd12bia s, vdd12pll, vdd12a) (@ +1.2v) 28 ma external magnetics current (@ +3.3v) 21 ma total power dissipation (device only) ( note 5-8 ) 133 mw total power dissipation (devic e and ethernet components) ( note 5-8 ) 203 mw table 5-5: power consumption - h ardware power down (pll enabled) parameter typical unit supply current (vddvario) (@ +3.3v) 0.12 ma supply current (vdd12core, vdd12bias, vdd12pll, vdd12a) (@ +1.2v) 17.29 ma external magnetics current (@ +3.3v) 7.00 ma total power dissipation (device only) ( note 5-9 ) 21.16 mw total power dissipation (devic e and ethernet components) ( note 5-9 ) 44.26 mw table 5-6: power consumption - hardware power down (pll disabled) parameter typical unit supply current (vddvario) (@ +3.3v) 0.12 ma supply current (vdd12core, vdd12bias, vdd12pll, vdd12a) (@ +1.2v) 4.39 ma external magnetics current (@ +3.3v) 0.02 ma total power dissipation (device only) ( note 5-10 ) 5.68 mw total power dissipation (devic e and ethernet components) ( note 5-10 ) 5.73 mw downloaded from: http:///
lan8810/lan8810i ds00001870b-page 63 ? 2009-2015 microchip technology inc. 5.4 dc specifications note 5-11 this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resistors add +/- 50ua per-pin (typical). note 5-12 xi can optionally be driven from a 25mhz single-ended clock oscillator. note 5-13 ieee 802.ab test mode 1 table 5-7: i/o buffer characteristics parameter symbol min 2.5v typ 3.3v typ max units notes vis type input buffer low input level high input level negative-going threshold positive-going threshold schmitttrigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddvario) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 0.640.81 102 -10 1.15 1.29 136 1.411.65 138 3.6 1.761.90 288 10 3 vv v v mv ua pf schmitt trigger schmitt trigger note 5-11 vo6 type buffers low output level high output level v ol v oh vddvario - 0.4 0.4 v v i ol = 6ma i oh = -6ma vo8 type buffers low output level high output level v ol v oh vddvario - 0.4 0.4 v v i ol = 8ma i oh = -8ma iclk type buffer (xi input) low input level high input level v ili v ihi -0.3 1.4 0.53.6 vv note 5-12 table 5-8: 1000base-t transceiver characteristics parameter symbol min typ max units notes peak differential output voltage v op 670 820 mv note 5-7 signal amplitude symmetry v ss 1% note 5-7 signal scaling v sc 2% note 5-8 output droop v od 73.1 % note 5-7 transmission distortion 10 mv note 5-9 downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 64 lan8810/lan8810i note 5-14 from 1/2 of average v op , test mode 1 note 5-15 ieee 802.ab distortion processing note 5-16 measured at line side of transformer, line replaced by 100 ? (+/- 1%) resistor. note 5-17 offset from 16ns pulse width at 50% of pulse peak. note 5-18 measured differentially. note 5-19 min/max voltages guaranteed as measured with 100 ? resistive load. table 5-9: 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 5-10 peak differential output voltage low v ppl -950 - -1050 mvpk note 5-10 signal amplitude symmetry v ss 98 - 102 % note 5-10 signal rise and fall time t rf 3.0 - 5.0 ns note 5-10 rise and fall symmetry t rfs --0 . 5n s note 5-10 duty cycle distortion d cd 35 50 65 % note 5-11 overshoot and undershoot v os --5% jitter 1.4 ns note 5-12 table 5-10: 10base-t tran sceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 5-13 receiver differential squelch threshold v ds 300 420 585 mv downloaded from: http:///
lan8810/lan8810i ds00001870b-page 65 ? 2009-2015 microchip technology inc. 5.5 ac specifications this section details the various ac timing specifications of the device. 5.5.1 equivalent test load output timing specifications assume a 25pf equivalent test load, unless otherwise noted, as illustrated in figure 5-1 . note: the gmii/mii timing adheres to the ieee 802.3 specificat ion. refer to the ieee 802. 3 specification for addi- tional gmii/mii timing information. note: the ethernet tx/rx pin timi ng adheres to the ieee 802. 3 specification. refer to the ieee 802.3 specifi- cation for detailed ethernet timing information. figure 5-1: output equivalent test load 25 pf output downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 66 lan8810/lan8810i 5.5.2 power sequence timing power supplies must adhere to the following rules: all power supplies of the same volt age must be powered up/down together. there is no power-up sequencing requirement, however all power supplies must reach operational levels within the time periods specified in ta b l e 5 - 11 . there is no power-down sequencing or timing requir ement, however the device must not be powered for an extended period of time without all supplies at operational levels. following initial power-on, or if a power supply brownout occurs (i.e., one or more supplies drops below opera- tional limits), a power-on reset must be executed once all power supplies reach operational levels. refer to sec- tion 5.5.3, "power-on hardware reset timing," on page 67 for power-on reset requirements. do not drive input signals without power supplied to the device. note 1: the vddvario power supply c an be run at 2.5v or 3.3v. 2: the magnetics power supply can be run at 2.5v or 3.3v. note: violation of these specific ations may damage the device. figure 5-2: power sequence timing table 5-11: power sequence timing values symbol description min typ max units t pon power supply turn on time 0 25 ms all 3.3v power supply pins all 2.5v power supply pins all 1.2v power supply pins t pon downloaded from: http:///
lan8810/lan8810i ds00001870b-page 67 ? 2009-2015 microchip technology inc. 5.5.3 power-on hardware reset timing figure 5-3 illustrates the nreset, conf iguration strap/pin, and config[3:0] timing requirem ents in relation to power- on. a hardware reset (nreset asserti on) is required following power-up. fo r proper operation, nreset must be asserted for no less than t rstia . the nreset pin can be asserted at any time, but must not be deasserted before t purstd after all external power supplies have reached operational levels . in order for valid configuration strap values to be read at power-up, the t css and t csh timing constraints must be followed. in order for config[3:0] values to be read at power- up, the t cs and t ch timing constraints must be followed. refer to section 3.6.1, "hardware reset (nreset)," on page 22 for additional information. . note 1: device configuration straps are latched as a result of nreset assertion. refer to section 3.8.1.1, "config- uration straps," on page 24 details. configuration straps must only be pulled high or low and must not be driven as inputs. 2: nreset deassertion must be monotonic. figure 5-3: hardware reset timing table 5-12: hardware reset timing values symbol description min typ max units t purstd external power supplies at operational level to nreset deassertion 25 ms t purstv external power supplies at operational level to nreset valid 0n s t rstid nreset input deassertion time 10 ? s t rstia nreset input assertion time 100 ? s t css configuration strap pins set up to nreset deassertion 200 ns t csh configuration strap pins hold after nreset deassertion 10 ns t otaa output tri-state after nreset assertion 50 ns t odad output drive after deassertion 40 800 ns t cs config[3:0] setup to nreset deassertion 0 ns t ch config[3:0] hold after nreset deassertion 1 us t css nreset configuration straps t csh configuration strap pins output drive all external power supplies t purstd v opp t cs config[3:0] t ch t rstia t odad t purstv t otaa t rstid downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 68 lan8810/lan8810i 5.5.4 reset timing figure 5-4 illustrates the nreset pin timing requirements. for pr oper operation, nreset must be asserted for no less than t rstia . in order for valid configurat ion strap values to be read upon a nreset asse rtion, the t css and t csh timing con- straints must be followed. in order for config [3:0] values to be re ad at power-up, the t cs and t ch timing constraints must be followed. refer to section 3.6.1, "hardware reset (nreset)," on page 22 for additional information. 5.5.5 gmii timing (1000base-t) this section specifies the gmii interface tr ansmit and receive timing. please refer to section 3.3, "gmii interface," on page 18 for additional details. note: a hardware reset (nreset assertion) is required fo llowing power-up. refer to section 5.5.3, "power-on hardware reset timing," on page 67 for additional information. figure 5-4: reset timing table 5-13: reset timing values symbol description min typ max units t rstia nreset input assertion time 1 ? s t css configuration strap pins setup to nreset deassertion 200 ns t csh configuration strap pins hold after nreset deassertion 10 ns t otaa output tri-state after nreset assertion 50 ns t odad output drive after deassertion 40 800 ns t cs config[3:0] setup to nreset deassertion 0 ns t ch config[3:0] hold after nreset deassertion 1 us note: device configuration straps are latched as a result of nreset assertion. refer to section 3.8.1.1, "con- figuration straps," on page 24 details. configuration straps must only be pulled high or low and must not be driven as inputs. t css nreset configuration straps t csh configuration strap pins output drive t cs config[3:0] t ch t rstia t odad t otaa downloaded from: http:///
lan8810/lan8810i ds00001870b-page 69 ? 2009-2015 microchip technology inc. note 5-1 min/max limits are non-sustainable long term. note 5-2 t r and t f are measured from v il_ac(max) =0.7v to v ih_ac(min) =1.9v. note: all gmii timing specifications assume a point-to-point test circuit as defined in section 35.4.2.2 of the ieee 802.3-2005 specification. figure 5-5: gmii transmit timing table 5-14: gmii transmit timing values symbol description min max units notes f gtxclk gtxclk frequency 125 - 100ppm 125 + 100ppm mhz t clkp gtxclk period 7.5 8.5 ns note 5-1 t clkh gtxclk high time 2.5 ns t clkl gtxclk low time 2.5 ns t val txd[7:0], txen, txer setup time to rising edge of gtxclk 2.0 ns t hold txd[7:0], txen, txer hold time after rising edge of gtxclk 0.0 ns t r gtxclk rise time 1 ns note 5-2 t f gtxclk fall time 1 ns note 5-2 gtxclk txd[7:0], txen, txer t clkh t clkl t clkp t hold t val t r t f downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 70 lan8810/lan8810i note 5-1 t r and t f are measured from v il_ac(max) =0.7v to v ih_ac(min) =1.9v. note 5-2 5.5.6 mii timing (100base-tx, 10base-t) this section specifies the mii interface tran smit and receive timing. please refer to section 3.3, "gmii interface," on page 18 for additional details. figure 5-6: gmii receive timing table 5-15: gmii receive timing values symbol description min max units notes t clkp rxclk period 7.5 ns t clkh rxclk high time 2.5 ns t clkl rxclk low time 2.5 ns t val rxd[7:0], rxdv, rxer output valid from rising edge of rxclk 5.0 ns t hold rxd[7:0], rxdv, rxer output hold from rising edge of rxclk 0.5 ns t r rxclk rise time 1 ns note 5-1 t f rxclk fall time 1 ns note 5-1 rxclk rxd[7:0], rxer, rxdv t clkh t clkl t clkp t hold t hold t val t val t r t f downloaded from: http:///
lan8810/lan8810i ds00001870b-page 71 ? 2009-2015 microchip technology inc. note 5-3 40ns for 100base-tx operation, 400ns for 10base-t operation. note 5-4 timing was designed for system load between 10 pf and 25 pf. figure 5-7: mii receive timing table 5-16: mii receive timing values symbol description min max units notes t clkp rxclk period note 5-3 ns t clkh rxclk high time t clkp *0.4 t clkp *0.6 ns t clkl rxclk low time t clkp *0.4 t clkp *0.6 ns t val rxd[3:0], rxdv output valid from rising edge of rxclk 28.0 ns note 5-4 t hold rxd[3:0], rxdv output hold from rising edge of rxclk 10.0 ns note 5-4 rxclk rxd[3:0] rxdv t clkh t clkl t clkp t val t hold t val t val t hold downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 72 lan8810/lan8810i note 5-5 40ns for 100base-tx operation, 400ns for 10base-t operation. note 5-6 timing was designed for system load between 10 pf and 25 pf. figure 5-8: mii transmit timing table 5-17: mii transmit timing values symbol description min max units notes t clkp txclk period note 5-5 ns t clkh txclk high time t clkp *0.4 t clkp *0.6 ns t clkl txclk low time t clkp *0.4 t clkp *0.6 ns t su txd[3:0], txen setup time to rising edge of txclk 12.0 ns note 5-6 t hold txd[3:0], txen hold time after rising edge of txclk 0n s note 5-6 txclk t su txd[3:0] txen t clkh t clkl t clkp t hold t su t hold t hold t su t hold downloaded from: http:///
lan8810/lan8810i ds00001870b-page 73 ? 2009-2015 microchip technology inc. 5.5.7 smi timing this section specifies the smi timing of the device. please refer to section 3.4, "serial mana gement interface (smi)," on page 20 for additional details. figure 5-9: smi timing table 5-18: smi timing values symbol description min max units notes t clkp mdc period 400 ns t clkh mdc high time 160 (80%) ns t clkl mdc low time 160 (80%) ns t val mdio (read from phy) output valid from rising edge of mdc 300 ns t ohold mdio (read from phy) output hold from rising edge of mdc 0n s t su mdio (write to phy) se tup time to rising edge of mdc 10 ns t ihold mdio (write to phy) inpu t hold time after rising edge of mdc 10 ns mdc mdio t clkh t clkl t clkp t ohold mdio t su t ihold (data-out) (data-in) t ohold t val downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 74 lan8810/lan8810i 5.5.8 jtag timing this section specifies the jtag timi ng of the device. please refer to section 3.9.7, "ieee 11 49.1 (jtag) boundary scan," on page 30 for additional details. figure 5-10: jtag timing table 5-19: jtag timing values symbol description min max units notes t tckp tck clock period 66.67 ns t tckhl tck clock high/low time t tckp *0.4 t tckp *0.6 ns t su tdi, tms setup to tck rising edge 10 ns t h tdi, tms hold from tck rising edge 10 ns t dov tdo output valid from tck falling edge 16 ns t dohinvld tdo output invalid from tck falling edge 0 ns tck (input) tdi, tms (inputs) t tckhl t tckp t tckhl t su t h t dov tdo (output) t dohinvld downloaded from: http:///
lan8810/lan8810i ds00001870b-page 75 ? 2009-2015 microchip technology inc. 5.6 clock circuit the device can accept either a 25mhz crystal (preferred) or a 25 mhz single-ended clock oscillator (+/- 50ppm) input. if the single-ended clock oscillator method is implemented, xo should be left unconnected and xi should be driven with a nominal 0v-vddvario clock signal. the input clock duty cycle is 40% minimum, 50% typical and 60% maximum. it is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (xi/xo). see table 5-20 for the recommended crystal specifications. note 5-7 the maximum allowable values for frequency tolerance and frequency stability are application dependant. since any particular application must meet the ieee +/-50 ppm total ppm budget, the combination of these two values must be approximately +/-45 ppm (allowing for aging). note 5-8 frequency deviation over time is also referred to as aging. note 5-9 the total deviation for the tr ansmitter clock frequency is specified by ieee 802.3u as +/- 50 ppm. note 5-10 0 o c for commercial version, -40 o c for industrial version. note 5-11 +70 o c for commercial version, +85 o c for industrial version. note 5-12 this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xo/xi pin and pcb capacitance values are required to accurately calculate the value of the two external load capacitors. these tw o external load capacitors determine the accuracy of the 25.000 mhz frequency. table 5-20: crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - +/-50 ppm note 5-21 frequency stability over temp f temp - - +/-50 ppm note 5-21 frequency deviation over time f age - +/-3 to 5 - ppm note 5-22 total allowable ppm budget - - +/-50 ppm note 5-23 shunt capacitance c o -7 p f load capacitance c l -1 8 p f drive level p w 300 - - uw equivalent series resistance r 1 --5 0 o h m operating temperature range note 5-24 - note 5-25 o c xi pin capacitance - 3 typ - pf note 5-26 xo pin capacitance - 3 typ - pf note 5-26 downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 76 lan8810/lan8810i 6.0 package outline 6.1 72-qfn package note 1: all dimensions are in millim eters unless otherwise noted. 2: dimension b applies to plated terminals and is meas ured between 0.15 and 0.30 mm from the terminal tip. 3: the pin 1 identifier may vary, but is always located within the zone indicated. figure 6-1: 72-qfn package table 6-1: 72-qfn dimensions min nominal max remarks a 0.80 0.85 1.00 overall package height a1 0.00 0.02 0.05 standoff a2 - 0.65 0.80 mold cap thickness d/e 9.90 10.00 10.10 x/y body size d1/e1 9.65 9.75 9.85 x/y mold cap size d2/e2 5.90 6.00 6.10 x/y exposed pad size l 0.30 0.40 0.50 terminal length b 0.18 0.25 0.30 terminal width k 1.50 - - center pad to pin clearance e 0.50 bsc terminal pitch downloaded from: http:///
lan8810/lan8810i ds00001870b-page 77 ? 2009-2015 microchip technology inc. figure 6-2: 72-qfn recommended pcb land pattern downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 78 lan8810/lan8810i appendix a: data sheet revision history table 6-2: revision history revision level & date section/figure/entry correction ds00001870b (10-27-15) table 3-9, "configuring the mode of operation" table 3-9 - in row 6, removed crs is active during transmit & receive. trademark and sales office listings updated. all: (cover, figure 2-1 , table 2-3 , table 2-6 , table 2-8 , table 3-4 , section 4.3.2 , section 5.6 ) removed references to 125mhz single-ended clock support and the ref_sel configuration strap. table 2-3 updated config3 pin description to correct list of connection pins. table 3-10 updated mode definition reg 19[15:11] 00100 entry. section 4.2.10 updated bit 11 description (active only when manual config. enable is 1). section 4.2.16 added note to mod bits: the mod bits should not be modified and must be preserved when writing to this register. updated bits 8:6 description to indicate they must be written with specific values. table 3-9 corrected typos in mode definitions of rows 3 and 4. table 3-10 corrected typos in row 5 (00100) mode definitions, reg 0, and reg 4 columns. section 5.6 updated second sentence to if the single-ended clock oscillator method is implemented, xo should be left unconnected and xi should be driven with a nominal 0v-vddvario clock signal. ds00001870a (12-09-14) section 3.6.1, "hardware reset (nreset)," on page 22 updated section with additional details on power- up sequencing requirements. section 5.5.3, "power-on hardware reset timing," on page 67 updated section with additional details on power- up sequencing requirements. section title and included figures/tables updated. rev. 1.1 (06-03-13) section 4.2.4, "phy identifier 2 register," on page 38 corrected bits 9:4 default values from 0ch to 0eh table 3-11, led mode 1 operation - led_mode[1:0]=01b, on page 27 and table 3-12, led mode 2 operation - led_mode[1:0]=10b, on page 27 updated led function definitions downloaded from: http:///
lan8810/lan8810i ds00001870b-page 79 ? 2009-2015 microchip technology inc. table 2-3, led & configuration pins, on page 7 , table 2-6, miscellaneous pins, on page 9 , table 3-4, configuration straps, on page 24 , section 5.6, "clock circuit," on page 75 updated xi and refclk_sel definitions/info for clarity. figure 2-1: 56-qfn pin assignments (top view) on page 5 , ta b l e 2 - 1 , rgmii interface pins, on page 6 . table 2-6, miscellaneous pins, on page 9 , table 2-8, 72-qfn pin assignments, on page 11 updated pin 25 definition to no connect (nc). section 3.7.1, "general power-down," on page 23 , section 3.7.2, "energy detect power-down," on page 23 , table 3-4, configuration straps, on page 24 , section 3.8.1.2.2, "configuring the mode of operation (config[3:2])," on page 26 , table 3-8, configuring the mode of operation, on page 26 , figure 3-6: simplified application diagram on page 32 , section 4.2.16, "extended mode control/ status register," on page 47 removed references to macclk and updated definition of bit 3 of the extended mode control/ status register. rev. 1.0 (08-02-12) section 5.3, "power consumption," on page 61 updated power numbers with latest lab measurements. all added commercial version. table 5-15, gmii receive timing values, on page 70 removed t val min value and added t val max value of 5.0ns. rev. 1.0 (06-29-11) all initial release table 6-2: revision history (continued) revision level & date section/figure/entry correction downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 80 lan8810/lan8810i the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 81 lan8810/lan8810i product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: lan8810 temperature range: blank = 0 ? c to +70 ? c (extended commercial) i= - 4 0 ? c to +85 ? c (industrial) package: akze = 72-pin qfn tape and reel option: blank = standard packaging (tray) tr = tape and reel (1) examples: a) LAN8810I-AKZE-TR industrial temperature, 72-pin qfn tape & reel b) lan8810-akze extended commercial temperature, 72-pin qfn tray note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sa les office for package availability with the tape and reel option. reel size is 4,000. part no. [x] xxxx package temperature range device [x] (1) tape and reel option - - downloaded from: http:///
? 2009-2015 microchip technology inc. ds00001870b-page 82 lan8810/lan8810i note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with y our specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising fr om this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, i ndemnify and hold harmless microchip from any and all dama ges, claims, suits, or expenses resulting from such use. no licenses are conveyed, implic- itly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of mi crochip technology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code gene ration, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbchec k, varisense, viewspan, wipe rlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microchi p technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., i n other countries. all other trademarks mentioned herein are pr operty of their respective companies. ? 2009-2015, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 9781632778833 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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