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toshiba original cmos 16-bit microcontroller tlcs-900/l1 series TMP91CW40FG semiconductor company
preface thank you very much for making us e of toshiba microcomputer lsis. before use this lsi, refer the section, ?points of note and restrictions?. especially, take care below cautions.
tmp91cw40 2008-09-19 91cw40-1 low voltage/low power consumption cmos 16-bit microcontroller TMP91CW40FG 1. outline and features the tmp91cw40 is a high-speed, high-performance 16-bit microcontroller capable of low-voltage, low-power-consumption operation. this microcontroller comes in a 100-pin flat package and has the following features: (1) toshiba proprietary 16-bit cpu (900/l1 cpu) ? instruction mnemonics are upwardly compatible with the tlcs-90 and tlcs-900. ? 16-mbyte linear address space ? architecture based on general-purp ose registers and register banks ? 16-bit multiply/divide instructions and bit transfer/arithmetic instructions ? micro dma: 4 channels (593 ns/2 bytes at 27 mhz) (2) minimum instruction execution time: 148 ns (at 27 mhz) (3) internal ram: 4 kbytes (4) internal rom: 128 kbytes restrictions on product use 20070701-en general ? the information contained herein is subject to change without notice. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity an d vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshib a products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconduct or devices,? or ?toshiba semiconductor reliability handbook? etc. ? the toshiba products listed in this document are intend ed for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipmen t, industrial robotics, domestic appliances, etc.).these toshiba products are neither intended nor warranted for us age in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instrument s, traffic signal instruments, combus tion control instruments, medical instruments, all types of safety devices, etc.. uninte nded usage of toshiba products listed in his document shall be made at the customer?s own risk. ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. ? the information contained herein is presented only as a gui de for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third partie s which may result from its use. no license is granted by implicat ion or otherwise under any patents or other rights of toshiba or the third parties. ? please contact your sales representative for product- by-product details in this document regarding rohs compatibility. please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of cont rolled substances. toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
tmp91cw40 2008-09-19 91cw40-2 (5) 8-bit timer: 4 channels (6) 16-bit timer: 3 channels (7) divider output (8) general-purpose serial interface: 4 channels ? both uart and synchronous transfer modes are supported. (9) 10-bit ad converter (with sample-and-hold): 4 channels (10) watchdog timer (11) key-on wakeup: 4 channels (12) real-time clock (rtc) ? based on the tc8521a specifications (13) melody/alarm generator (mld) (14) program patch logic: 6 banks (15) lcd driver/controller (voltage reducer type, reference voltage = vcc) ? lcd direct drive possible (8 to 40 segments x 4 commons) ? 1/4 duty, 1/3 duty, 1/2 duty or static drive selectable (16) interrupts: 43 sources ? 9 cpu interrupts: triggered by a software interrupt instruction or undefined instruction ? 27 internal interrupts: 7 priority levels ? 7 external interrupts: 7 priority levels (two interrupts support selection of triggering edge.) (17) input/output ports: 61 pins (18) standby function three halt modes (programmable idle2, idle1, stop) (19) clock control function ? low-frequency clock (fs = 32.768 khz) (20) operating voltage range ? vcc = 2.7 to 3.6 v (fc max = 27 mhz) ? vcc = 2.2 to 3.6 v (fc max = 16 mhz) (vcc 2.7v: lcdd disabled.) (21) package: lqfp100-p-1414-0.50f
tmp91cw40 2008-09-19 91cw40-3 figure 1.1 tmp91cw40 block diagram x1 x2 power supply pins high-frequency oscillator connecting pins input/output ports (segment outputs) dvdd dvss address/data bus system controller standby controller high- frequency low- frequency clock generator tlcs-900/l1 cpu ram 4 kb rom 128 kb interrupt controller ad converter power supply analog reference power supply input/output ports avcc,avss vrefh,vrefl p50 (an0/kwi0) p51 (an1/kwi1) p52 (an2/kwi2) p53 (an3/ adtrg /kwi3) seg7 to seg0 p6 10-bit ad converter p5 p8 asynchronous/ synchronous serial interface sio0 address/data bus common outputs com3 to com0 lcd driver (automatic display) p0 p07 (seg31) to p00 (seg24) pb pb7 (seg39) to pb0 ( seg32 ) lcd power supply circuit lcd driver power supply c0 c1 v1 v2 v3 reset pin reset test pins am1, am0 emu1, emu0 tc5 8-bit timer/counter tc6 tc7 tc8 tc1 16-bit timer/counter watchdog timer p80(tc5out) p81(tc6out) p82(tc7out) p83(tc8out) p60(int0) p61(int1) p62( alarm ) xt1 xt2 low-frequency oscillator connecting pins p2 p27 (seg15) to p20 ( seg8 ) p1 p17 (seg23) to p10 (seg16) tc2 tc3 p7 p70(ecnt1) p71(ecnt2) p72(ecnt3/ dvo / mldalm ) p73(ecin1) p74(ecin2) p75(ecin3) sio1 sio2 sio3 p9 p90(txd0) p91(rxd0) p92(sclk0/ 0cts ) p93(txd1) p94(rxd1) p95(sclk1/ 1cts ) rtc pa pa0(txd2) pa1(rxd2) pa2(sclk2/ 2cts ) pa3(txd3) pa4(rxd3) pa5(sclk3/ 3cts ) input ports nmi mld
tmp91cw40 2008-09-19 91cw40-4 2. pin assignments and pin functions the assignment of input/output pins for the tmp91cw40, their names and functions are follows: 2.1 pin assignments figure 2.1.1 shows the pin assignments of the TMP91CW40FG. p82/tc7ou t TMP91CW40FG lqfp100 top view 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 p82 /tc8out dvcc p62/ alarm p90/txd0 p91/r xd0 p92/ sclk0/ cts0 p93/txd1 p94/rxd1 p95/sclk1/ cts1 dvss pa0 /txd2 pa 1 / r xd 2 pa2/sclk2/ cts2 pa3 /txd3 pa 4 / r xd 3 pa5/ sclk3/ cts3 nmi p60/int0 p61/int1 p70/ecnt1 p72/ecnt3/ dvo / mldalm dvcc seg6 seg7 dvcc dvss p20/seg8 p21/seg9 p22/seg10 p23/seg11 p24/seg12 p25/seg13 p26/seg14 p27/seg15 p11/seg17 p12/seg18 p13/seg19 p14/seg20 p15/seg21 p16/seg22 p17/seg23 p00/seg24 p01/seg25 p02/seg26 p03/seg27 p04/seg28 p0 5/seg29 p06/seg30 p07/seg31 dvcc dvss pb0/seg32 pb1/seg33 pb2/seg34 pb3/seg35 pb4/seg36 pb5/seg37 pb6/seg38 pb7/seg39 p7 5/ec in3 p74/ecni2 p73/ecin1 em u1 emu0 xt2 xt1 am1 x1 dvss x2 vrefl v3 a vss p53/an3/ /kwi 3 p52/an2/kwi2 p51 /an1 /kwi1 p50 /an0 /kwi0 p80/tc5out v2 v1 c0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 p81 /tc6out am 0 seg5 a vcc p71/ecnt2 reset p10/seg16 c1 adtrg vrefh figure 2.1.1 TMP91CW40FG pin assignments (100-pin lqfp, top view)
tmp91cw40 2008-09-19 91cw40-5 2.2 pin names and functions table 2.2.1 to table 2.2.2 list the names and functions of the input and output pins of the tmp91cw40. t able 2.2.1 pin names and functions (1/2) pin name number of pins i/o function p50 to p53 an0 to an3 adtrg kwi0 to kwi3 4 input input input input port 5: input port analog input: input to the ad converter ad trigger: external start request pin for the ad converter (multiplexed with p53) key-on wakeup input (multiplexed with p50 to p53) p60 int0 1 input input port 60: input port interrupt request pin 0: programmable as high-level, low-level, rising-edge or falling-edge sensitive p61 int1 1 i/o input port 61: input/output port interrupt request pin 1: programmable as high-level, low-level, rising-edge or falling-edge sensitive p62 alarm boot 1 output output input port 62: input/output port rtc alarm output pin boot mode control pin for flash memory (spec ifically designed for 91fw40; to be pulled up during the reset period) note: in normal mode, do not input low level on this pin during the reset period. if low level is input, boot mode will be entered. p70 ecnt1 1 i/o input port 70: input/output port 16-bit timer 1 input: count cont rol input for 16-bit timer tc1 p71 ecnt2 1 i/o input port 71: input/output port 16-bit timer 2 input: count cont rol input for 16-bit timer tc2 p72 ecnt3 dvo mldalm 1 i/o input output output port 72: input/output port 16-bit timer 3 input: count cont rol input for 16-bit timer tc3 divider output pin melody/alarm output pin p73 ecin1 1 i/o input port 73: input/output port 16-bit timer 1 input: count input for 16-bit timer tc1 p74 ecin2 1 i/o input port 74: input/output port 16-bit timer 2 input: count input for 16-bit timer tc2 p75 ecin3 1 i/o input port 75: input/output port 16-bit timer 3 input: count input for 16-bit timer tc3 p80 tc5out 1 i/o output port 80: input/output port (large-current port 8-bit timer 5 output: output pin for 8-bit timer tc5 open-drain output mode by programmable p81 tc6out 1 i/o output port 81: input/output port (large-current port) 8-bit timer 6 output: output pin for 8-bit timer tc6 open-drain output mode by programmable p82 tc7out 1 i/o output port 82: input/output port (large-current port) 8-bit timer 7 output: output pin for 8-bit timer tc7 open-drain output mode by programmable p83 tc8out 1 i/o output port 83: input/output port (large-current port) 8-bit timer 8 output: output pin for 8-bit timer tc8 open-drain output mode by programmable p90 txd0 1 i/o output port 90: input/output port serial 0 transmit data open-drain output mode by programmable p91 rxd0 1 i/o input port 91: input/output port serial 0 receive data p92 sclk0 0cts 1 i/o i/o input port 92: input/output port serial 0 clock input/output serial 0 data transmit enable (clear to send)
tmp91cw40 2008-09-19 91cw40-6 table 2.2.2 pin names and functions (2/2) pin name number of pins i/o function p93 txd1 1 i/o output port 93: input/output port serial 1 transmit data open-drain output mode by programmable p94 rxd1 1 i/o input port 94: input/output port serial 1 receive data p95 sclk1 cts1 1 i/o i/o input port 95: input/output port serial 1 clock input/output serial 1 data transmit enable (clear to send) pa0 txd2 1 i/o output port a0: input/output port serial 2 transmit data open-drain output mode by programmable pa1 rxd2 1 i/o input port a1: input/output port serial 2 receive data pa2 sclk2 cts2 1 i/o i/o input port a2: input/output port serial 2 clock input/output serial 2 data transmit enable (clear to send) pa3 txd3 1 i/o output port 3: input/output port serial 3 transmit data open-drain output mode by programmable pa4 rxd3 1 i/o input port a4: input/output port serial 3 receive data pa5 sclk3 cts3 1 i/o i/o input port a5: input/output port serial 3 clock input/output serial 3 data transmit enable (clear to send) seg0 to seg7 8 output segment output p20 to p27 seg8 to seg15 8 i/o output port 2: input/output port segment output p10 to p17 seg16 to seg23 8 i/o output port 1: input/output port segment output p00 to p07 seg24 to seg31 8 i/o output port 0: input/output port segment output pb0 to pb7 seg32 to seg39 8 i/o output port b: input/output port segment output c0,c1 2 lcd drive power supply v1 to v3 3 lcd drive power supply com0 to com3 4 common output nmi 1 input nonmaskable interrupt request pin: causes an nmi interrupt on the falling edge; programmable to be rising-edge s ensitive (schmitt input). am0, am1 2 input operation mode both am0 and am1 should be held at logic 1. emu0 1 output this pin should be left open. emu1 1 output this pin should be left open. reset 1 input reset: initializes the tmp91cw40. (schmitt input, with pull-up resistor) vrefh 1 input input pin for high reference voltage for the ad converter vrefl 1 input input pin for low reference voltage for the ad converter avcc 1 power supply pin for the ad converter avss 1 ground pin for the ad converter (0 v) x1/x2 2 i/o connection pins fo r a high-frequency oscillator xt1/xt2 2 i/o connection pins for a low-frequency oscillator dvcc dvss 4 4 power supply pins (the dvcc pins should be connected to power supply.) ground pins (the dvss pins shoul d be connected to ground (0 v).)
tmp91cw40 2008-09-19 91cw40-7 3. operation this section describes the functions and basic operation of the tmp91cw40. 3.1 cpu the tmp91cw40 contains a high-performance 16-bit cpu (900/l1 cpu). for a detailed description of the cpu, refer to ?tlcs- 900/l1 cpu? in the preceding chapter. functions unique to the tmp91cw40 not cove red in ?tlcs-900/l1 cpu? are described below. 3.1.1 reset operation to reset the tmp91cw40, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then, set the reset input to low level for at least 10 system clocks (1s at 27 mhz). after turning on the power to the tmp91cw40, hold the reset input at low level for at least 10 system clocks with the power supply voltage within the operating voltage range and the internal high-frequency oscillator oscillating stably. reset operation initializes the system clock f sys to fc/2. the cpu performs the following operations as a result of a reset: ? sets the program counter (pc) according to the reset vector stored at addresses ffff00h to ffff02h. pc < 7:0 > value at address ffff00h pc < 15:8 > value at address ffff01h pc < 23:16 > value at address ffff02h ? sets the stack pointer (xsp) to 100h. ? sets the bits of the status register (sr) to 111 (setting the interrupt level mask register to level 7). ? sets the bit of the status register (sr) to 1 (selecting maximum mode). ? clears the bits of the status regi ster (sr) to 000 (selecting register bank 0). after the reset state is released, the cpu starts executing instructions according to the pc. cpu internal registers other than the above are not changed. the internal i/o peripherals, ports and other pi ns are initialized as follows upon a reset: ? all internal i/o registers are initialized. ? all port pins, including those multiplexed with internal i/o functions, are configured either as general-purpose inputs or general-purpose outputs. note: reset operation does not affect the contents of the in ternal ram or the cpu registers other than pc, sr and xsp. figure 3.1.1 shows reset timings of the tmp91cw40.
tmp91cw40 2008-09-19 91cw40-8 f fph sampling indicates high-impedance state. sampling (input mode) rese t p62 p70 to p75 p80 to p83 p90 to p95, pa0 to pa5 pb0 to pb7(seg32 to seg39) p00 to p07(seg24 to seg31) p10 to p17(seg16 to seg23) p20 to p27(seg8 to seg15) seg0 to seg7 (input mode) com0 to com3 (output mode) (input mode) p62 tmp91fw40 only, (pull-up) figure 3.1.1 tmp91cw40 reset timings
tmp91cw40 2008-09-19 91cw40-9 3.2 memory map figure 3.2.1 shows a memory map of the tmp91cw40. figure 3.2.1 memory map 000000h 001000h 16-mbyte area (r) ( ? r) (r + ) (r + r8/16) (r + d8/16) (nnn) direct area ( n ) 64-kbyte area (nn) internal rom ( 128 kb y tes ) internal i/o (4 kbytes) internal ram (4 kbytes) 002000h 010000h fe0000h ( = internal area) ffff00h ffffffh vector table (256 bytes) external memory (access prohibited) 000100h
tmp91cw40 2008-09-19 91cw40-10 3.3 system clock/standby control and noise reduction the tmp91cw40 incorporates clock gear, stan dby control and noise reduction circuits to minimize power consumption and no ise. single-clock mode (x1 and x2 pins only) and dual-clock mode (x1, x2, xt1, and xt2 pins) are supported. figure 3.3.1 shows state transitions in each clock mode. figure 3.3.1 state transitions in each operation mode the clock frequency terms used in this document are defined as follows: fc: clock frequency supplied via the x1 and x2 pins fs: clock frequency supplied via the xt1 and xt2 pins f fph : clock frequency select ed by syscr1 f sys : clock frequency obta ined by dividing f fph by two 1 state: one period of f sys reset (f c /2) reset released instruction interrupt stop mode (whole chip halted) normal mode (f c /2) idle2 mode (i/o active) idle1 mode (only oscillator active) k (a) state transitions in single-clock mode (b) state transitions in dual-clock mode stop mode (whole chip halted) slow mode (fs/2) instruction instruction interrupt instruction interrupt reset (f c /2) reset released normal mode (f c /2) idle2 mode (i/o active) idle1 mode (only oscillator active) instruction interrupt instruction interrupt idle2 mode (i/o active) idle1 mode (only oscillator active) instruction interrupt instruction interrupt interrupt instruction instruction
tmp91cw40 2008-09-19 91cw40-11 3.3.1 system clock block diagram figure 3.3.2 system clock block diagram warm-up (for high- and low-frequency oscillators) syscr0 syscr2 2 4 f fph t0 t f fph f c x1 x2 f sys 2 high-frequency oscillator xt1 xt2 low-frequency oscillator syscr0 syscr0 syscr1 fs fs f sys cpu rom ram interrupt controller wdt i/o ports t0 sio0~sio3 adc prescaler
tmp91cw40 2008-09-19 91cw40-12 3.3.2 sfrs 7 6 5 4 3 2 1 0 bit symbol xen xten rxen rxten rsysck wuef ? ? read/write r/w after reset 1 0 1 0 0 0 0 0 function high- frequency oscillator 0: stop 1: active low- frequency oscillator 0: stop 1: active high- frequency oscillator after release of stop mode 0: stop 1: active low- frequency oscillator after release of stop mode 0: stop 1: active clock selection after release of stop mode 0: high- frequency 1: low- frequency warm-up timer (wup) control 0 write: don?t care 1 write: start wup 0 read: wup finished 1 read: wup counting always write 00. bit symbol sysck ? ? ? read/write r/w after reset 0 0 0 0 function system clock selection 0: high- frequency (fc) 1: low- frequency (fs) always write 000. bit symbol ? wuptm1 wuptm0 haltm1 haltm0 drve read/write r/w r/w r/w r/w r/w r/w after reset 0 1 0 1 1 0 function always write 0. oscillator warm-up time 00: reserved 01: 2 8 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency halt mode selection 00: reserved 01: stop mode 10: idle1 mode 11: idle2 mode 1: pins are driven in stop mode. bit symbol lcdckmod read/write r/w after reset 0 function lcd clock 0: fc 1: fs note: bits 7 to 4 of the syscr1 and bits 7 and 1 of the syscr2 are read as undefined. figure 3.3.3 sfrs for the system clock syscr0 (00e0h) syscr1 (00e1h) syscr3 (00e5h) syscr2 (00e2h)
tmp91cw40 2008-09-19 91cw40-13 7 6 5 4 3 2 1 0 bit symbol protect ? ? ? ? extin drvosch drvoscl read/write r r/w r/w r/w r/w r/w r/w r/w after reset 0 0 1 0 0 0 1 1 function protection flag 0: off 1: on always write 0. always write 1. always write 0. always write 0. 1: external clock used as fc fc oscillator drive capability 1: normal 0: weak fs oscillator drive capability 1: normal 0: weak bit symbol read/write after reset function writing 1fh disables protection. writing a value other than 1fh enables protection. note: in case restarting the oscillator in the stop oscillation state (e.g. restart the oscillator in stop mode), set emccr0, =?1?. figure 3.3.4 noise-related sfrs emccr1 (00e4h) emccr0 (00e3h)
tmp91cw40 2008-09-19 91cw40-14 3.3.3 system clock control unit the system clock control unit generates system clock pulses (f sys ) that are supplied to the cpu core and internal i/o. it accepts either fc or fs clock pulses generated by the high-frequency or low-frequency oscillator, respectively. syscr1 is used to select the high-frequency or low-frequency oscillator. syscr0 and are used to enable and disable the high-frequency and low-frequency oscillators, respectively, so that power consumpt ion can be reduced. a system reset initializes to 1, to 0 and to 0, setting the system clock f sys to fc/2. for example, if a 27 mhz resonator is connected between the x1 and x2 pins, the f sys clock operates at 13.5 mhz. (1) switching between normal mode and slow mode a warm-up timer is provided to ensure stab le oscillation of the resonator connected between the x1 and x2 pins or between the xt1 and xt2 pins before switching the system clock frequency. this warm-up ti me can be selected by syscr2 according to the properties of the resonator to be used. syscr0 is used to start the warm-up timer and to check whether or not the warm-up time has elapsed. for how to program the warm-up timer, refer to examples 1 and 2 on the pages that follow. table 3.3.1 shows the warm-up times for changing the system clock frequency. note 1: if the oscillator to be used has stabl e oscillation, no warm-up time is needed. note 2: since the warm-up timer is operated by an oscilla tion clock, warm-up times may include some errors if there are fluctuations in oscillation frequency. table 3.3.1 warm-up times (for cha nging the system clock frequency) warm-up time setting syscr2 changing to normal mode (fc) changing to slow mode (fs) 01 (2 8 / oscillation frequency) 9.5 [ s] 7.8 [ms] 10 (2 14 /oscillation frequency) 0.607 [ms] 500 [ms] 11 (2 16 /oscillation frequency) 2.427 [ms] 2000 [ms] at fc = 27mhz fs = 32.768khz
tmp91cw40 2008-09-19 91cw40-15 example 1 changing the system clock from high-frequency (fc) to low-frequency (fs) syscr0 equ 00e0h syscr1 equ 00e1h syscr2 equ 00e2h ld (syscr2), x ? 11 ? ?x ? b ; set warm-up time to 2 16 /fs. set 6, (syscr0) ; enable low-frequency oscillator. set 2, (syscr0) ; clear and start warm-up timer. wup: bit 2, (syscr0) ; jr nz, wup ; detect completion of warming up. set 3, (syscr1) ; change f sys from fc to fs. res 7, (syscr0) ; disable high-frequency oscillator. x: don?t care, ? : no change count up fs pulses fc syscr0 x 1, x2 pins x t1, xt2 pins syscr0 w arm-up timer w arm-up complete s yscr1 fs system clock f sys enable low-frequency oscillator clear & start warm-up timer warm-up complete change f sys from fc to fs disable high-frequency oscillator
tmp91cw40 2008-09-19 91cw40-16 example 2 changing the system clock from low-frequency (fs) to high-frequency (fc) syscr0 equ 00e0h syscr1 equ 00e1h syscr2 equ 00e2h ld (syscr2), x ? 10 ? ?x ? b ; set warm-up time to 2 14 /fc. set 7, (syscr0) ; enable high-frequency oscillator. set 2, (syscr0) ; clear and start warm-up timer. wup: bit 2, (syscr0) ; jr nz, wup ; detect completion of warming up. res 3, (syscr1) ; change f sys from fs to fc. res 6, (syscr0) ; disable low-frequency oscillator. x: don?t care, ? : no change count up fc pulses fs syscr0 x1, x2 pin s xt1, xt2 pins syscr0 warm-up timer warm-up co mplete syscr1 system clock f sys enable high-frequency oscillator start & clear warm-up timer warm-up complete change f sys from fs to fc disable low-frequency oscillator fc
tmp91cw40 2008-09-19 91cw40-17 3.3.4 prescaler clock control unit the internal i/o functions (sio0 to sio3) are provided with a clock prescaler. the prescaler clock sources t and t0 are f fph / 2 and f fph / 4, respectively. 3.3.5 noise reduction circuits the tmp91cw40 incorporates circuits providing the following features to reduce electromagnetic interference (emi) and electromagnetic susceptibility (ems): (1) reducing drive capability of the high-frequency oscillator (2) reducing drive capability of the low-frequency oscillator (3) canceling double-drive operation of the high-frequency oscillator (4) preventing software or system lockups using a protection register these features are specified using the emccr0 and emccr1 registers, as described below. (1) reducing drive capability of the high-frequency oscillator purpose: to suppress noise generated by the high-fr equency oscillator and to reduce power consumption of the high-frequency oscillator when an external resonator is connected. block diagram: description: setting the bit of the emccr0 register to 0 reduces the high-frequency oscillator?s drive capability. a system reset initializes the bit to 1, so the high-frequency oscillator st arts oscillating with no rmal drive capability upon power-on. the bit should not be set to 0 when vcc 2.7v. resonator c2 c1 x1 pin emccr0 fc enable oscillation (stop+emccr0) x2 pin
tmp91cw40 2008-09-19 91cw40-18 (2) reducing drive capability of the low-frequency oscillator purpose: to suppress noise generated by the low-frequency oscillator and to reduce power consumption of the low-frequency oscillator when an external resonator is connected. block diagram: description: setting the bit of the emccr0 register to 0 reduces the low-frequency oscillator?s drive capability. a system reset initializes the bit to 1. (3) canceling double-drive operation of the high-frequency oscillator purpose: to prevent malfunction due to noise coming through the x2 pin that is open when an external oscillator is used, with double-drive operation not required. block diagram: description: setting the bit of the emccr0 register to 1 causes the high-frequency oscillator to stop oscillation with the x2 pin driven high. a system reset initializes the bit to 0. note: do not write emccr0 = ?1? when using external resonator. xt1 pin resonator c2 c1 enable oscillation emccr0 fs xt2 pin x1 pin x2 pin enable oscillation (stop+emccr0) emccr0 fc
tmp91cw40 2008-09-19 91cw40-19 (4) preventing software or system lockups using a protection register purpose: to prevent software or system lockups that may occur due to incoming noise. applying protection causes specified sfrs to be write-protected, thus preventing the system recovery routine from becoming unfetchable, for example, if the system clock stops or a memory control register (cs/wait controller) is modified. applicable sfrs 1. clock gear (only emccr1 can be written.) syscr0, syscr1, syscr2, syscr3, emccr0 block diagram: description: writing any code other than 1fh to the emccr1 register enables protection, preventing specified sfrs from being written. writing 1fh to the emccr1 register cancels protection. the state of protection can be determined by reading the bit of the emccr0. a system reset cancels protection. write other than 1fh to emccr1 write 1fh to emccr1 s q r protection flag emccr0 sfr write signal write signal to specified sfrs write signal to other sfrs
tmp91cw40 2008-09-19 91cw40-20 3.3.6 standby control (1) halt mode executing the halt instruction causes the tmp91cw40 to enter one of the halt modes?idle2, idle1 or stop?as specified by the syscr2 bits. the characteristics of idle2, idle1 and stop modes are as follows: a. idle2: the cpu stops. each internal i/o can be selectively enabled and disabled through use of a register bit in an sfr, as shown in table 3.3.2. table 3.3.2 idle2 mode regi ster settings internal i/o sfr sio0 sc0mod1 sio1 sc1mod1 sio2 sc2mod1 sio3 sc3mod1 ad converter admod1 wdt wdmod b. idle1: only the oscillator, rtc(real-time clock) and mld are operational. c. stop: the whole tmp91cw40 stops. table 3.3.3 shows the operation of each circuit block in halt modes. t able 3.3.3 tmp91cw 4 0 circuit blocks in halt modes halt mode idle2 idle1 stop syscr2 11 10 01 cpu off i/o ports holding the states when the halt instruction was executed see table 3.3.6 tc1 to tc3, tc5 to tc8 on sio0 to sio3 off ad converter wdt selectable programmatically on a block-by-block basis rtc, mld lcdd on circuit block interrupt controller on
tmp91cw40 2008-09-19 91cw40-21 (2) wakeup signaling there are two ways to exit a halt mode: an interrupt request or reset signal. availability of wakeup signaling depends on the settings of the interrupt mask level bits, , of the cpu status register (sr) and the current halt mode (see table 3.3.4). ? wak e up via interrupt signaling the operation upon return from a halt mode varies, depending on the interrupt priority level programmed before executing the halt instruction. if the interrupt priority level is greater than or equal to the processor?s interrupt mask level, execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the halt instruction. if the interrupt priority level is less than the processor?s interrupt mask level, the halt mode is not terminated. (nonmaskable interrupts are always serv iced upon return from a halt mode, regardless of the current interrupt mask level.) only int0, int1, kwi0 to kwi3, intrtc and intalm0 to intalm4 interrupts can, however, terminate a halt mode even if the interrupt priority level is less than the processor?s interrupt mask level. in that case, program execution resumes with the instruction immediately following the halt instruction without executing the interrupt service routine. (the interrupt request flag remains set.) ? wakeup via reset signaling reset signaling always brings the tmp91cw40 out of any halt mode. a wakeup from stop mode must allow suffi cient time for the oscillator to restart and stabilize (see table 3.3.5). a rese t does not affect the contents of the internal ram, but initializes everything else, whereas an interrupt preserves all internal states that were in effect before the halt mode was entered.
tmp91cw40 2008-09-19 91cw40-22 table 3.3.4 wakeup signaling sources and wakeup operations interrupt masking unmasked interrupt (request level) (mask level) masked interrupt (request level) < (mask level) halt mode programmable idle2 idle1 stop programmable idle2 idle1 stop interrupts nmi intwd int0,int1, kwi0 to kwi3 note 1) intalm0 to intalm4 intrtc inttmr1 to inttmr3, inttmr5 to inttmr8 intrx0 to intrx3, inttx0 to inttx3 intad ? ? ? ? ? ? ? ? ? ? ? ? ? ? * 1 ? * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? * 1 wakeup signaling sources reset initializes the whole tmp91cw40. ? : execution resumes with the interrupt service routine. ? : execution resumes with the instruction immediately followi ng the halt instruction. (the interrupt is not serviced.) : cannot be used to exit a halt mode. ? : these combinations are not possibl e because nonmaskable interrupts are assi gned the highest priority level (7). * 1: the tmp91cw40 exits the halt mode after the warm-up period timer expires. note 1: if the interrupt request level is greater than the mask le vel, an int0 or int1 interrupt signal which is programmed as level-sensitive must be held high until interrupt processing begi ns. otherwise, the interrupt will not be serviced successfully . example of exiting a halt mode when using an edge-sensitive int0 interrupt to exit idle1 mode address fe8200h ld (p6fc), 01h ; set p60 to int0. fe8203h ld (iimc), 00h ; set int0 interrupt to rising-edge sensitive. fe8206h ld (inte0ad), 06h ; set int0 interrupt priority level to 6. fe8209h ei 5 ; set cpu interrupt priority level to 5. fe820bh ld (syscr2), 28h ; select idle1 mode. fe820eh halt ; stop cpu. int0 int0 interrupt service routine reti fe820fh ld xx, xx
tmp91cw40 2008-09-19 91cw40-23 (3) operation in halt modes a. idle2 mode in idle2 mode, the cpu stops executing instructions and only the internal i/o functions enabled with the idle2 setting bits in respective sfrs are operational. figure 3.3.5 shows example timings for ex it ing id le2 m ode with an interrupt. figure 3.3.5 example timings for exiting a halt mode (idle2 mode) with an interrupt b. idle1 mode in idle1 mode, the system clock stops while only the internal oscillator and time-of-day clock timer are active. interru pt requests are sampled asynchronously with the system clock in a halt state, but the halt mode is exited in synchronization with the system clock. figure 3.3.6 shows example timings for ex it ing i d le1 m ode with an interrupt. figure 3.3.6 example timings for exiting a halt mode (idle1 mode) with an interrupt address address + 2 x1 a0 to a23 wakeup interrupt idle2 mode wakeup interrupt address address + 2 a0 to a23 idle1 mode x1 rd rd
tmp91cw40 2008-09-19 91cw40-24 c. stop mode in stop mode, the whole tmp91cw40 stops, including the internal oscillator. pin states in stop mode depend on the setting of the syscr2 bit, as shown in table 3.3.6. upon det e ction of wakeup signaling, the warm-up period timer should be activated to allow sufficient time for the oscillator to restart and stabilize before exiting stop mode. after that, the system clock output can restart. upon exiting stop mode, the operation resumes according to the settings in the syscr0, and bits. these bits must be set before executing the halt instruction. the warm-up period is chosen through the syscr2 bits, as shown in table 3.3.5. figure 3.3.7 shows example timings for ex iting stop m ode with an interrupt. figure 3.3.7 example timings for exiting a halt mode (stop mode) with an interrupt 3.3.5 example warm-up period settings (when exiting stop mode) fc = 27 mhz, fs = 32.768 khz syscr2 syscr0 01 (2 8 ) 10 (2 14 ) 11 (2 16 ) 0 (fc) 9.5 s 0.607 ms 2.427 ms 1 (fs) 7.8 ms 500 ms 2000 ms wakeup interrupt address a0 to a21 stop mode address + 2 x1 warm-up period rd
tmp91cw40 2008-09-19 91cw40-25 example: entering stop mode while using the low-frequency clock, exiting stop mode with an nmi interrupt, and then resuming operation with the high-frequency clock ?: no change note: when different system clock frequencies are to be us ed before entering and after exiting stop mode as shown above, if a wakeup interrupt is accepted while the halt in struction is being executed (a period of 6 states), stop mode may be exited without the system clock frequency being changed. in a system where interrupts are input during execution of the halt instruction, use the same system clock frequency before entering and after exiting stop mode. address syscr0 equ 00e0h syscr1 equ 00e1h syscr2 equ 00e2h fe8ffdh ld (syscr1), 08h ; f sys =fs/2 fe9000h ld (syscr2), x ? 1001x1b ; warm-up time = 2 14 /fc fe9002h ld (syscr0), 01100000b ; enable high-frequency clock after exiting stop mode fe9005h halt nmi pin input fe9006h ld xx, xx reti warm-up timer clear & start (high-frequency clock) warm-up complete nmi interrupt service routine
tmp91cw40 2008-09-19 91cw40-26 table 3.3.6 tmp91cw40 input buffer state table input buffer state in halt mode (stop) when the cpu is operating in halt mode (idle2/idle1) =1 =0 port name i nput function name during reset when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port p50-52 kwi0-kwi2 *1 kwi3 *1 p53 adtrg off on (by read) off off off *1 p60 int0 input p61 int1 input on on on on on p62 ? ? ? ? ? p70 ecnt1 input p71 ecnt2 input p72 ecnt3 input p73 ecin1 input p74 ecin2 input p75 ecin3 input on on on off p80-83 ? p90 ? ? ? ? ? p91 rxd0 input sclk0 input p92 0cts input on on on off p93 ? ? ? ? ? p94 rxd1 input sclk1 input p95 1cts input on on on off pa0 ? ? ? ? ? pa1 rxd2 input sclk2 input pa2 2cts input on on on off pa3 ? ? ? ? ? pa4 rxd3 input sclk3 input pa5 3cts input p20-27 ? p10-17 ? p00-07 ? pb0-b7 ? on on on off off nmi ? reset ? am0,am1 ? on on x1 ? on on ? on ? off ? off ? on: the buffer is always turned on. a current flows through the input buffer if the input pin is not driven. *1: ain input does not cause a current to flow through the buffer. off: the buffer is always turned off. -: not applicable
tmp91cw40 2008-09-19 91cw40-27 3.4 interrupts interrupt processing is controlled by the cp u interrupt mask register sr and the on-chip interrupt controller. the tmp91cw40 supports the foll owing 43 interrupt sources: ? 9 cpu internal interrupts (software interrupts and interrupts triggered when an undefined instruction is executed) ? 7 external interrupt pins ( nmi , int0, int1, kwi0 to kwi3) ? 27 internal i/o interrupts each interrupt source has a unique interrupt vector number (fixed). each maskable interrupt is assigned one of six priority levels (variable) while nonmaskable interrupts have the highest priority level of 7 (fixed). when an interrupt occurs, the interrupt controll er sends the priority level of that interrupt source to the cpu. if two or more interrupts occur simultaneously, it sends the highest of their priority levels (7 if a nonmaskable interrupt occurs) to the cpu. the cpu compares the sent priority level with the contents of the cpu interrupt mask register . if the sent priority level is hi gher than or equal to the interrupt mask level, the cpu accepts the interrupt. the contents of the bits can be modified using the ei instruction in the format of ei num, where num is the value to be set in . for example, ?ei 3? causes the cpu to accept maskable interrupts having a priority level of 3 or higher, as specified with the interrupt controller, as well as all nonmaskable interrupts. the di instruction, which sets to 7, has the same effect as ?ei 7?. it is used to prevent the cpu from accepting maskable interrupts because maskable interrupts can have priority levels of only up to 6. the ei instruction takes effect immediately after it is executed. in addition to general interrupt servicing, as described above, the tmp91cw40 supports micro dma mode, where the cpu automatically transfers data (1 byte, 2 bytes or 4 bytes). this mode enables faster data transfer to inte rnal/external memory and internal i/o. a micro dma request can be issued either us ing an interrupt source or programmatically with the soft start feature. figure 3.4.1 shows the overall flow of interrupt servicing.
tmp91cw40 2008-09-19 91cw40-28 figure 3.4.1 overall interrupt servicing flow general interrupt servicing interrupt specified by micro dma start vector? yes interrupt servicing push pc push sr sr accepted interrupt level + 1 intnest intnest + 1 end pc (ffff00h + v) interrupt service routine count count ? 1 count = 0 no yes transfer data using micro dma no micro dma mode reti instruction pop sr pop pc intnest intnest ? 1 inttc interrupt occurred clear micro dma start vector register clear interrupt request flip-flop read interrupt vector v clear interrupt request flag micro dma soft start request
tmp91cw40 2008-09-19 91cw40-29 3.4.1 general interrupt servicing the cpu performs the following operations once it accepts an interrupt. these operations are the same as those performed by the tlcs-900/l and tlcs-900/h. (1) reads an interrupt vector from the interrupt controller. if two or more interrupts having the same priority level occur simultaneously, the interrupt controller generates an interrupt vect or according to default priorities (fixed, higher priorities assigned to smaller vector values) and clears the interrupt request. (2) pushes the contents of the program counter (pc) and status register (sr) to the stack area indicated by the xsp. (3) sets the interrupt mask register bits to one level higher than the accepted interrupt level. if the level is 7, however, the cpu sets to 7 without incrementing the value. (4) increments the interrupt nesting counter intnest by one. (5) makes a branch to the address specified with the data stored at address ?ffff00h + interrupt vector? and then starts the interrupt service routine. the above procedure requires 18 states (1.33 s at 27 mhz) in the best case (with 16-bit data bus and 0-wait cycles). upon completion of interrupt servicing, the reti instruction is usually used to return to the main routine. the reti instruction restor es the contents of the pc and sr from the stack and decrements the intnest by one. nonmaskable interrupts cannot be disabled programmatically. maskable interrupts can be disabled or enabled programmatically and a priority level can be specified for each interrupt source. the cpu accepts an interrupt if its priority level is higher than or equal to the value stored in the cpu?s bits. the cpu then sets the bits to the accepted priority level plus one. this enables the cpu to accept any higher-priority interrupt that occurs while servicing the curre nt interrupt, so that interrupts are nested. if another interrupt request is issued while the cpu is performing the above steps, the request is sampled immediately after the first instruction of the current interrupt service routine is executed. the di instruction can be used as the first instruction in an interrupt service routine to prohibit nesting of maskable interrupts. upon a system reset, the bits are in itialized to 7 so that maskable interrupts are disabled. addresses ffff00h to ffffffh (256 bytes) are assigned to the interrupt vector area. table 3.4.1 shows the interrupt vector table.
tmp91cw40 2008-09-19 91cw40-30 table 3.4.1 interrupt vector table default priority type interrupt source vector value vector reference address micro dma start vector 1 reset or swi0 instruction 0000h ffff00h ? 2 swi1 instruction 0004h ffff04h ? 3 intundef: undefined instruction or swi2 instruction 0008h ffff08h ? 4 swi3 instruction 000ch ffff0ch ? 5 swi4 instruction 0010h ffff10h ? 6 swi5 instruction 0014h ffff14h ? 7 swi6 instruction 0018h ffff18h ? 8 swi7 instruction 001ch ffff1ch ? 9 nmi pin 0020h ffff20h ? 10 non- maskable intwd: watchdog timer 0024h ffff24h ? ? (micro dma) ? ? ? 11 int0 pin 0028h ffff28h 0ah 12 int1 pin, kwi0 to kwi3 pins 002ch ffff2ch 0bh 13 intalm0: alm0 (8192 hz) 0030h ffff30h 0ch 14 intalm1: alm1 (512 hz) 0034h ffff34h 0dh 15 intalm2: alm2 (64 hz) 0038h ffff38h 0eh 16 intalm3: alm3 (2 hz) 003ch ffff3ch 0fh 17 intalm4: alm4 (1 hz) 0040h ffff40h 10h 18 inttmr5: 8-bit timer 5 (tc5) 0044h ffff44h 11h 19 inttmr6: 8-bit timer 6 (tc6) 0048h ffff48h 12h 20 inttmr7: 8-bit timer 7 (tc7) 004ch ffff4ch 13h 21 inttmr8: 8-bit timer 8 (tc8) 0050h ffff50h 14h 22 inttmr1: 16-bit timer 1 (tc1) 0054h ffff54h 15h 23 inttmr2: 16-bit timer 2 (tc2) 0058h ffff58h 16h 24 reserved 005ch ffff5ch ? 25 reserved 0060h ffff60h ? 26 reserved 0064h ffff64h ? 27 reserved 0068h ffff68h ? 28 inttmr3: 16-bit timer 3 (tc3) 006ch ffff6ch 1bh 29 reserved 0070h ffff70h ? 30 intrx0: serial receive (channel 0) 0074h ffff74h 1dh 31 inttx0: serial transmit (channel 0) 0078h ffff78h 1eh 32 intrx1: serial receive (channel 1) 007ch ffff7ch 1fh 33 inttx1: serial transmit (channel 1) 0080h ffff80h 20h 34 reserved 0084h ffff84h ? 35 reserved 0088h ffff88h ? 36 intrx2: serial receive (channel 2) 008ch ffff8ch 23h 37 inttx2: serial transmit (channel 2) 0090h ffff90h 24h 38 intrx3: serial receive (channel 3) 0094h ffff94h 25h 39 inttx3: serial transmit (channel 3) 0098h ffff98h 26h 40 intad: ad conversion complete 009ch ffff9ch 27h 41 inttc0: micro dma complete (channel 0) 00a0h ffffa0h 42 inttc1: micro dma complete (channel 1) 00a4h ffffa4h 43 inttc2: micro dma complete (channel 2) 00a8h ffffa8h 44 inttc3: micro dma complete (channel 3) 00ach ffffach 45 maskable intrtc: rtc (alarm interrupt) 00b0h ffffb0h 2ch (reserved) : (reserved) 00b4h : 00fch ffffb4h : fffffch ? : ?
tmp91cw40 2008-09-19 91cw40-31 3.4.2 micro dma in addition to general interrupt servicing, the tmp91cw40 supports a micro dma feature. interrupt requests specified with the micro dma are assigned highest priority levels among maskable interrupts regardless of the priority levels actually set. the micro dma consists of four channels so that continuous transfer can be performed using burst specification, described later. because the micro dma feature is realized in cooperation with the cpu, micro dma requests are ignored and remain pending if the cpu executes the halt instruction and enters a standby state. (1) micro dma operation if an interrupt specified with the micro dma start vector register is requested, the micro dma transfers data to the cpu assu ming the highest priority level for a maskable interrupt regardless of the priority level assigned to the interrupt source. micro dma requests are not, however, accepted when = 7. the micro dma has four channels so that it can be specified for up to four interrupt sources simultaneously. when the cpu accepts a micro dma request, it clears the interrupt request flag assigned to that channel, performs a single data transfer (1 byte, 2 bytes, or 4 bytes) from the source address to de stination address, as specifie d with the control register, and then decrements the transfer counter. if the decremented counter reaches zero, the interrupt controller receives a reques t from the cpu and generates a micro dma transfer complete interrupt (inttcn). then the cpu clears the micro dma start vector register (dmanv) to 0, thus disabl ing subsequent start of the micro dma and terminating micro dma servicing. even if the decremented counter does not reach zero, the cpu terminates micro dma servicing unless burst transfer is specified. in this case, the interrupt controller does no t generate a micro dma transfer complete interrupt (inttcn). when using an interrupt source only to st art the micro dma, set the priority level for that interrupt to 0. if the priority level is set to 1 to 6 and this interrupt request is generated before it is set for micro dm a transfer, the cpu will perform general interrupt servicing. when using an interrupt source for bo th the micro dma and general interrupt servicing, set the priority level for that interrupt to a level less that those of all other interrupt sources. note that only edge-triggered interrupts can be used in such a way. a micro dma transfer complete interrupt is serviced according to its priority level and default priorities, in the same way as other maskable interrupts. if two or more micro dma channels issue requests simultaneously, channels having smaller numbers have higher priorities, regardless of the respective interrupt priority levels. the transfer source and destination addr esses are each spec ified using a 32-bit control register. the micro dma can, howeve r, handle only 16-mbyte space because there are only 24 address output lines. note: if the priority level of micro dma is set higher than that of other interrupts, cpu operates as follows. in case intxxx interrupt is generated first and then intyyy interrupt is generated between checking ?interrupt specified by micro dma start vector? (in the figure 3.4.1) and reading interrupt vector with setting below. the vector shifts to that of inty yy at the time. this is because t he priority level of intyyy is higher than that of intxxx. in the interrupt routine, cpu reads the vector of intyyy because cheking of micro dma has finished. and intyyy is generated regardle ss of transfer counter of micro dma. intxxx: level 1 without micro dma intyyy: level 6 with micro dma
tmp91cw40 2008-09-19 91cw40-32 the micro dma supports three transfer mo des: 1 byte, 2 bytes or 4 bytes. for each transfer mode, the transfer sou rce and destination addresses can be incremented, decremented or fixed after the transfer of a single unit of data. this ability to select various mo des facilitates data transfer from i/o to memory, memory to i/o, and i/o to i/o. for detail s of transfer modes, see ?(4) transfer mode registers?. the transfer counter consists of 16 bits so that up to 65536 micro dma transfers (if the counter defaults to 0000h) can be performed for a single interrupt source. the micro dma supports 19 inte rrupt sources as shown in table 3.4.1 as well as a soft start. figure 3.4.2 shows micro dma cycles for 2-by te transfer in th e t ransfer destination address increment mode (with all address ar eas accessed with a 16 -bit data bus, no wait cycles, and even-numbered source/destination addresses). figure 3.4.2 micro dma cycles 1st to 3rd states: instruction fetch cycles (prefetching next instruction code). if three or more bytes of instructio n code are stored in the instruction queue buffer, these cycles become dummy cycles. 4th to 5th states: micro dma read cycles 6th state: dummy cycle (address bus left in the 5th state). 7th and 8th states: micro dma write cycle note 1: if the source address area uses an 8-bit bus, additional two states are needed. if the source address area uses a 16-bit bus but starts with an odd-numbered address, additional two states are needed. note 2: if the destinatin address area uses an 8-bit bus, additional two states are needed. if the destination address area uses a 16-bit bus but star ts with an odd-numbered address, additional two states are needed. output input source address + 2 address 1 state d0 d15 x1 a 0a23 dm1 dm2 dm3 dm4 dm5 dm6 dm7 dm8 note 1 note 2 rd wr / hwr destination
tmp91cw40 2008-09-19 91cw40-33 (2) soft start in addition to interrupt sources, the micro dma can also be started by software. this soft start feature enables the micro dma to be started upon the detection of a write cycle to the dmar register. writing 1 to each bit in the dmar register starts a micro dma transfer in the corresponding channel. when the transfer is completed, the bit is automatically cleared to 0. only one channel can be starte d at a time. (do not write 1 to more than one bit in the dmar register at the same time.) a dmar register bit must be verified to be 0 before it can be set to 1 again. if read 1, micro dma transfer isn?t started yet. when a burst transfer is specified in the dmab register, the micro dma channel that has been once started continues transf erring data until the micro dma transfer counter reaches zero. if execute soft star t during micro dma transfer by interrupt source, micro dma transfer counter doesn?t change. don?t use read-modify-write instruction to avoid writing to other bits by mistake. symbol name address 7 6 5 4 3 2 1 0 dmar3 dmar2 dmar1 dmar0 r / w 0 0 0 0 dmar dma software request register 89h (read- modify-write instructions are prohibited) 1: dma request (3) transfer control registers the following registers in the cpu are used to control the transfer source and destination addresses. use the ?ldc cr, r? instruction to set data in these registers. channel 0 dmas0 transfer source address register 0; only lower 24 bits are used. dmad0 transfer destination address register 0; only lower 24 bits are used. dmac0 transfer counter register 0; 1 to 65536 dmam0 transfer mode register 0 channel 3 dmas3 transfer source address register 3 dmad3 transfer destination address register 3 dmac3 transfer counter register 3 dmam3 transfer mode register 3 8 bits 16 bits 32 bits
tmp91cw40 2008-09-19 91cw40-34 (4) transfer mode registers: dmam0 to dmam3 (dmam0 to dmam3) 0 0 0 mode 0 0 0 z z 8 states (593 ns) byte/word transfer destination address increment mode ....................... i/o to memory (dmadn + ) (dmasn) dmacn dmacn ? 1 if dmacn = 0 then inttc occurs 12 states (889 ns) 4-byte transfer 0 0 1 z z 8 states (593 ns) byte/word transfer destination address decrement mode ...................... i/o to memory (dmadn ? ) (dmasn) dmacn dmacn ? 1 if dmacn = 0 then inttc occurs 12 states (889 ns) 4-byte transfer 0 1 0 z z 8 states (593 ns) byte/word transfer source address increment mode.............................. memory to i/o (dmadn) (dmasn +) dmacn dmacn ? 1 if dmacn = 0 then inttc occurs 12 states (889 ns) 4-byte transfer 0 1 1 z z 8 states (593 ns) byte/word transfer source address decrement mode ........................... memory to i/o (dmadn) (dmasn ?) dmacn dmacn ?1 if dmacn = 0 then inttc occurs 12 states (889 ns) 4-byte transfer 1 0 0 z z 8 states (593 ns) byte/word transfer fixed address mode ................................................. i/o to i/o (dmadn) (dmasn) dmacn dmacn ? 1 if dmacn = 0 then inttc occurs 12 states (889 ns) 4-byte transfer 1 0 1 0 0 counter mode counting the number of interrupts that have occurred dmasn dmasn + 1 dmacn dmacn ? 1 if dmacn = 0 then inttc occurs 5 states (370 ns) note 1: n: corresponding micro dma channel (0 to 3) dmadn+ /dmasn + : post-increment (incrementing the register value after transfer) dmadn? /dmasn ? : post-decrement (decrementing the register value after transfer) in the table, ?i/o? means a fixed address while ?memory? means an address that can be incrementaed or decremented. note 2: execution time: the time required to complete transfe rring a single unit of data when a 16-bit bus is used for the sour ce and destination address areas and no wait cycles are inserted. clock settings: fc = 27 mhz, cloock gear = x1 (fc) note 3: any code other than those listed above must not be written to transfer mode registers. note: the upper three bits of data written to these registers must always be ?0?. zz: 0 = byte transfer, 1 = word transfer, 2 = 4-byte transfer, 3 = reserved execution time
tmp91cw40 2008-09-19 91cw40-35 3.4.3 interrupt controller figure 3.4.3 shows a block diagram of the in terrupt circuit. the left-hand side of the diagram shows the interrupt controller while the right-hand side shows the cpu?s interrupt request signal circuit and halt wakeup circuit. for each of the 25 interrupt channels there is an interrupt request flag, interrupt priority register and micro dma start vector register. th e interrupt request flag is used to latch an interrupt request issued by peripherals. this flag is cleared in the following cases: ? reset ? the cpu accepts the interrupt and reads the vector for the interrupt. ? an instruction that clears the interrupt is executed. (a dma start vector is written to the intclr register.) ? the cpu accepts a micro dma request for the interrupt. ? micro dma burst transfer for the interrupt completes. priority levels for individual interrupts can be specified using interrupt priority registers (such as inte0ad and inte1alm 0) provided for each interrupt source. six levels of priority (1 to 6) can be set. an interrupt is disabled when its priority level is set to 0 or 7. nonmaskable interrupts ( nmi pin and watchdog timer) have a fixed level of 7. if two or more interrupts having the same priority level occur simutaneously, the cpu accepts interrupts according to default priorities. reading bits 3 and 7 of an interrupt priority register obtains the status of the interrupt request flag, indicating whether an interrupt request is present for the corresponding channel. the interrupt controller determines the interrupt with the highest priority among interrupts occuring simultaneously if any, and sends it priority level and vector address to the cpu. the cpu compares that priority level with the contents of the interrupt mask register, that is, the bits of the status register (sr). the cpu accepts the interrupt if its priority level is higher than the register value. it then sets the bits to the accepted interrupt level plus one, so that only interrupt requests having a priority level higher than or equal to the register value can be accepted while the current interrupt is handled. upon completion of interrupt servicing (with the execution of the reti instruction), the bits are restored to the value before the interrupt occurred which has been saved on the stack. the interrupt controller has registers for storing mirco dma start vectors for four channels. writing a start vector (see table 3.4.1) to these registers enables the micro dma to start when the corresp o nding interrupt occurs. note that the registers for setting micro dma parameters (such as dmas and dmad) must be set beforehand.
tmp91cw40 2008-09-19 91cw40-36 i nterrup t requ est if iff = 7, then 0 micro dma st art vect or register inttc 0 inttc1 inttc 2 inttc 3 intrt c v = a0 h v = a4h v = a8h v = ach v = b0h soft s tart micro dma counter 0 interrupt 6 inttc 0 idle1 mod 30 3 3 3 1 6 1 7 2 2 4 6 34 4-input or i nt0, int1, rtc, kwi0 t o 3, al m0 to alm4 micro dma channel priority encoder priority encoder dma0v dma1v dma2v dm a3v res et i nterrupt requ es t fl ag reset re set priority setting register v = 20 h v = 24h interrupt contro ll er cpu s q r v = 28h v = 2ch v = 38h v = 3ch v = 40 h d q clr a b c dn dn + 1 dn + 2 interrupt request fl ag interrupt accept micro dma accept inte rrup t requ est flip -floprea d dn + 3 a b c interrupt vec tor v read d 2 d3 d4 d 5 d6 d7 selecto r s q r 0 1 2 3 a b d0 d1 interrupt vector v read cpu interrupt ac c e p tance fla g mi cr o d ma r eq uest halt wakeup nmi if intrq2 to 0 iff 2 to 0, then 1. intrq2 to intrq 0 if f2: 0 determine priority level res et ei1 to 7 di interrupt request signal sto p mod e micro dma channel specification reset nm i intw d int0 int1,kwi0 to kwi 3 intalm 0 intalm1 intalm 2 s interrupt vector gen er ator select highe st prio rity le vel (7 = top priority) 1 2 3 4 5 6 7 d5 d4 d3 d2 d1 d0 d q c lr dec oder y1 y2 y3 y4 y5 y6 figure 3.4.3 interrupt co ntroller block diagram
tmp91cw40 2008-09-19 91cw40-37 (1) interrupt priority registers symbol name address 7 6 5 4 3 2 1 0 intad int0 iadc iadm2 iadm1 iadm0 i0c i0m2 i0m1 i0m0 r r/w r r/w inte0ad int0 & intad enable 90h 0 0 0 0 0 0 0 0 intalm0 int1 ia0c ia0m2 ia0m1 ia0m0 i1c i1m2 i1m1 i1m0 r r r r inte1alm0 int1& intalm0 enable 91h 0 0 0 0 0 0 0 0 intalm2 intalm1 ia2c ia2m2 ia2m1 ia2m0 ia1c ia1c ia1m2 ia1m0 r r/w r r/w intealm12 intalm1 & intalm2 enable 92h 0 0 0 0 0 0 0 0 intalm4 intalm3 ia4c ia4m2 ia4m1 ia4m0 ia3c ia3c ia3m2 ia3m0 r r/w r r/w intealm34 intalm3 & intalm4 enable 93h 0 0 0 0 0 0 0 0 inttmr6 (tc6) inttmr5 (tc5) itm6c itm6m2 itm6m1 itm6m0 itm5c itm5m2 itm5m1 itm5m0 r r/w r r/w intetmr56 inttmr5 & inttmr6 enable 94h 0 0 0 0 0 0 0 0 inttmr8 (tc8) inttmr7 (tc7) itm8c itm8m2 itm8m1 itm8m0 itm7c itm7m2 itm7m1 itm7m0 r r/w r r/w intetmr78 inttmr7 & inttmr8 enable 95h 0 0 0 0 0 0 0 0 inttmr2 (tc2) inttmr1 (tc1) itm2c itm2m2 itm2m1 itm2m0 itm1c itm1m2 itm1m1 itm1m0 r r/w r r/w intetmr12 inttmr1 & inttmr2 enable 96h 0 0 0 0 0 0 0 0 ? inttmr3 (tc3) ? ? ? ? itm3c itm3m2 itm3m1 itm3m0 ? ? r r/w intetmr3 inttmr3 enable 99h write ?0?. 0 0 0 0 lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disable interrupt requests. 0 0 1 set interrupt priority level to 1. 0 1 0 set interrupt priority level to 2. 0 1 1 set interrupt priority level to 3. 1 0 0 set interrupt priority level to 4. 1 0 1 set interrupt priority level to 5. 1 1 0 set interrupt priority level to 6. 1 1 1 disable interrupt requests. interrupt request flag
tmp91cw40 2008-09-19 91cw40-38 symbol name address 7 6 5 4 3 2 1 0 inttx0 intrx0 itx0c itx0m2 itx0m1 itx0m0 irx0c irx0m2 irx0m1 irx0m0 r r/w r r/w intes0 interrupt enable serial 0 9ah 0 0 0 0 0 0 0 0 inttx1 intrx1 itx1c itx1m2 itx1m1 itx1m0 irx1c irx1m2 irx1m1 irx1m0 r r/w r r/w intes1 interrupt enable serial 1 9bh 0 0 0 0 0 0 0 0 ? intrtc ? ? ? ? irx2c irx2m2 irx2m1 irx2m0 ? ? r r/w intrtc intrtc enable 9ch write ?0?. 0 0 0 0 inttx2 intrx2 itx2c itx2m2 itx2m1 itx2m0 irx2c irx2m2 irx2m1 irx2m0 r r/w r r/w intes2 interrupt enable serial 2 9dh 0 0 0 0 0 0 0 0 inttx3 intrx3 itx3c itx3m2 itx3m1 itx3m0 irx3c irx3m2 irx3m1 irx3m0 r r/w r r/w intes3 interrupt enable serial 3 9eh 0 0 0 0 0 0 0 0 inttc1 inttc0 itc1c itc1m2 itc1m1 itc1m0 itc0c itc0m2 itc0m1 itc0m0 r r/w r r/w intetc01 inttc0 & inttc1 enable a0h 0 0 0 0 0 0 0 0 inttc3 inttc2 itc3c itc3m2 itc3m1 itc3m0 itc2c itc2m2 itc2m1 itc2m0 r r/w r r/w intetc23 inttc2 & inttc3 enable a1h 0 0 0 0 0 0 0 0 lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disable interrupt requests. 0 0 1 set interrupt priority level to 1. 0 1 0 set interrupt priority level to 2. 0 1 1 set interrupt priority level to 3. 1 0 0 set interrupt priority level to 4. 1 0 1 set interrupt priority level to 5. 1 1 0 set interrupt priority level to 6. 1 1 1 disable interrupt requests. interrupt request flag
tmp91cw40 2008-09-19 91cw40-39 (2) external interrupt control symbol name address 7 6 5 4 3 2 1 0 ? ? ? i1edge i1le i0edge i0le nmiree w 0 0 0 0 0 0 0 0 iimc interrupt input control 8ch (read- modify-write instructions are prohibited) always write ?0?. int1 edge polarity 0: rising 1: falling int1 sensitivity 0: edge 1: level int0 edge polarity 0: rising 1: falling int0 sensitivity 0: edge 1: level 1: also triggered by nmi rising edge int1 sensitivity 0 edge-triggered 1 level-sensitive int0 sensitivity 0 edge-triggered 1 level-sensitive nmi rising edge enable 0 int request occurs at falling edge only 1 int request occurs at rising/falling edge note: when int1 is is set to be level-sensitive, the key-on wakeup function must be disabled. (3) interrupt request flag clear register an interrupt request flag can be cleared by writing a micro dma start vector (see table 3.4.1) to the intclr register. for example , the int0 interrupt flag can be cleared by the following register operation after execution of the di instruction. intclr 0ah clear the int0 interrupt request flag symbol name address 7 6 5 4 3 2 1 0 clrv5 clrv4 clrv3 clrv2 clrv1 clrv0 w 0 0 0 0 0 0 intclr interrupt clear control 88h (read- modify-write instructions are prohibited) w riting a dma start vector clears the corresponding interrupt request flag.
tmp91cw40 2008-09-19 91cw40-40 (4) micro dma start vector registers a micro dma start vector register specifie s which interrupt source is assigned to micro dma processing. the interrupt sour ce having the micro dma start vector specified in this register is assi gned as a micro dma request source. when the micro dma transfer counter reache s zero, the interrupt controller receives a request from the cpu and generates a micro dma transfer complete interrupt for the relevant channel. then, the cpu clears th e micro dma start vector register, thus clearing the micro dma request source for the channel. if it is necessary to continue micro dma processing, the micro dma start vector register must be set again in the service routine for the micro dma transfer complete interrupt. if the same vector is set in two or more micro dma start vector registers at the same time, the channel having the smallest number takes precedence. therefore, if the same vector is set in the micro dma start vector registers of two channels, micro dma transfer is first performed with the smaller-numbered channel until it completes. unless the interrupt controller reloads the mi cro dma start vector for this channel, micro dma transfer is then performed with the larger-numbered channel (micro dma chaining). symbol name address 7 6 5 4 3 2 1 0 dma0v5 dma0v4 dma0v3 dma0v2 dma0v1 dma0v0 r/w 0 0 0 0 0 0 dma0v dma0 start vector 80h dma0 start vector dma1v5 dma1v4 dma1v3 dma1v2 dma1v1 dma1v0 r/w 0 0 0 0 0 0 dma1v dma1 start vector 81h dma1 start vector dma2v5 dma2v4 dma2v3 dma2v2 dma2v1 dma2v0 r/w 0 0 0 0 0 0 dma2v dma2 start vector 82h dma2 start vector dma3v5 dma3v4 dma3v3 dma3v2 dma3v1 dma3v0 r/w 0 0 0 0 0 0 dma3v dma3 start vector 83h dma3 start vector (5) micro dma burst specification the micro dma supports burst specification, with which a single micro dma startup can cause transfer to continue until the transfer counter register reaches zero. burst transfer can be specified by setting the dmab register bit corresponding to each micro dma channel to 1. symbol name address 7 6 5 4 3 2 1 0 dmar3 dmar2 dmar1 dmar0 r/w 0 0 0 0 dmar dma software request register 89h (read- modify-write instructions are prohibited) 1: dma soft request dmab3 dmab2 dmab1 dmab0 r/w 0 0 0 0 dmab dma burst register 8ah 1: dma burst request
tmp91cw40 2008-09-19 91cw40-41 (6) precautions the instruction execution unit and the bus interface unit of this cpu operate independently. therefore, after accepting an interrupt the cpu may fetch an instruction that clears the interrupt request flag for this interrupt (note) immediately before the interrupt is about to be generated. in this case, the cpu may execute this interrupt request clear instruction after accepting the interrupt request but before reading the interrupt vector for this interrupt. if this happens, the cpu reads ?0008h? (interrupt vector cleared) and reads th e interrupt vector from address ffff08h. to avoid the above situation, make sure to execute the di instruction before an instruction for clearing an interrupt requ est flag. after the clear instruction is executed, at least one instruction must be inserted before the ei instruction is executed to re-enable interrupts.(e.g., ?nop? 1 times) if the ei instruction immediately follows the clear instruction, interrupts ma y be enabled before the interrupt flag is cleared. when the pop sr instruction is used to modify the interrupt mask level ( bits of the status register sr), the di instruction must be executed to disable interrupts before executing the pop sr instruction. in addition, note the following two exceptional circuits which demand special attention: when int0 or int1 is used as a level-sensitive interrupt pin (rather than edge-triggered), the interrupt reques t flip-flop is disabled so that a peripheral interrupt request directly passes through the s input of the flip-flop to appear at the q output. changing the mode (edge to level) causes the previous in terrupt request flag to be cleared automatically. when int0 or int1 is set as a level-sensitive interrupt if int0 is driven from low to high causing the cpu to start an interrupt response sequence, int0 must be held high until the interrupt response sequence is comple ted. when level-sensitive int0 is used to exit halt mode, int0 must also be held high once it is driven from low to high until halt mode is exited. (ensure that it is not temporarily driven low due to noise during that period.) when int0 is changed from level- sensitive to edge-triggered, any interrupt request flag accepted in le vel-sensitive mode is not cleared. use the following sequence to clear the interrupt request flag: di ld (iimc), 00h ; change from level to edge. ld (intclr), 0ah ; clear int0 interrupt request flag. nop ; wait ei instruction. ei intrx clearing the interrupt request flip-flop requires a system reset or reading the serial channel receive buffer. it cannot be cleared by an instruction. note: the following instructions or pin state transition are equivalent to an instruction that clears an interrupt request flag: int0/int1: instruction that changes the pin mode to level-sensitive after an interrupt is generated in edge-triggered mode. change in the pin input level (from high to low) af ter an interrupt request is generated in level-sensitive mode intrx: instruction that reads the receive buffer.
tmp91cw40 2008-09-19 91cw40-42 3.5 i/o ports the tmp91cw40 has a total of 69 i/o port pins. all the port pins except a few share pins with alternate functions. they can be individually programmed as general-purpose i/o or dedicated i/o for the cpu or internal functions. table 3.5.1 shows the functions of the port pins of the tmp91cw40. table 3.5.2 to table 3.5.4 give a summary of regist er sett ings used to co n trol the port pins. table 3.5.1 i/o ports port name pin name number of pins direction direction programmability p-od alternate functions port 5 p50 to p53 4 input (fixed) an0 to an3, adtrg (p53) kwi0 to kwi3 port 6 p60 1 input (fixed) int0 p61 1 input/output bit int1 p62 1 input/output bit alarm port 7 p70 1 input/output bit ecnt1 p71 1 input/output bit ecnt2 p72 1 input/output bit ecnt3, dvo , mldalm p73 1 input/output bit ecin1 p74 1 input/output bit ecin2 p75 1 input/output bit ecin3 port 8 p80 1 input/output bit tc5out p81 1 input/output bit tc6out p82 1 input/output bit tc7out p83 1 input/output bit tc8out port 9 p90 1 input/output bit txd0 p91 1 input/output bit rxd0 p92 1 input/output bit sclk0/ cts0 p93 1 input/output bit txd1 p94 1 input/output bit rxd1 p95 1 input/output bit sclk1/ cts1 port a pa0 1 input/output bit txd2 pa1 1 input/output bit rxd2 pa2 1 input/output bit sclk2/ cts2 pa3 1 input/output bit txd3 pa4 1 input/output bit rxd3 pa5 1 input/output bit sclk3/ cts3 8 output (fixed) seg0 to seg7 port 2 p20 to p27 8 input/output bit seg8 to seg15 port 1 p10 to p17 8 input/output bit seg16 to seg23 port 0 p00 to p07 8 input/output bit seg24 to seg31 port b pb0 to pb7 8 input/output bit seg32 to seg39
tmp91cw40 2008-09-19 91cw40-43 table 3.5.2 i/o port settings (1/3) i/o register settings port pin name direction/function pn pncr pnfc pnfc2 ode input port an0 to an3 inputs note 1) p50 to p53 kwi0 to kwi3 inputs note 2) port 5 p53 adtrg input note 3) n/a n/a n/a n/a input port 0 p60 int0 input n/a 1 input port 0 0 output port 1 0 p61 int1 input 0 1 input port 0 0 output port 1 0 port 6 p62 alarm output 1 1 n/a n/a input port 0 p70 to p75 output port 1 p70 ecnt1 input 0 p71 ecnt2 input 0 n/a n/a ecnt3 input 0 0 0 dvo output 1 1 0 p72 mldalm output 1 1 p73 ecin1 input 0 p74 ecin2 input 0 port 7 p75 ecin3 input 0 n/a n/a n/a input port 0 0 output port (cmos output) 1 0 0 p80 to p83 output port (open-drain output) 1 0 1 tc5out output (cmos output) 1 1 0 p80 tc5out output (open-drain output) 1 1 1 tc6out output (cmos output) 1 1 0 p81 tc6out output (open-drain output) 1 1 1 tc7out output (cmos output) 1 1 0 p82 tc7out output (open-drain output) 1 1 1 tc8out output (cmos output) 1 1 0 port 8 p83 tc8out output (open-drain output) 1 1 n/a 1 x: don?t care note 1: when p50 to p53 are used as input channels for the ad converter, the analog channel to be used is selected by the bits of the admod1 register. note 2: to use p50 to p53 as input ports of key-on wakeup, enable interrupts of kwi0 to kwi3 with kwien register. note 3: when p53 is used as adtrg input, the bit of the admod1 register is used to enable and disable ad conversion start by an external trigger.
tmp91cw40 2008-09-19 91cw40-44 table 3.5.3 i/o port settings (2/3) i/o register settings port pin name direction/function pn pncr pnfc ode input port 0 0 output port (cmos output) 1 0 0 p90, p93 output port (open-drain output) 1 0 1 input port 0 p91, p94 output port 1 n/a input port 0 0 p92, p95 output port 1 0 n/a txd0 output (cmos output) 1 1 0 p90 txd0 output (open-drain output) 1 1 1 p91 rxd0 input 0 n/a sclk0 input 0 0 sclk0 output 1 1 p92 cts0 input 0 0 n/a txd1 output (cmos output) 1 1 0 p93 txd1 output (open-drain output) 1 1 1 p94 rxd1 input 0 n/a sclk1 input 0 0 sclk1 output 1 1 port 9 p95 cts1 input 0 0 n/a input port 0 0 output port (cmos output) 1 0 0 pa0, pa3 output port (open-drain output) 1 0 1 input port 0 pa1, pa4 output port 1 n/a input port 0 0 pa2, pa5 output port 1 0 n/a txd2 output (cmos output) 1 1 0 pa0 txd2 output (open-drain output) 1 1 1 pa1 rxd2 input 0 n/a sclk2 input 0 0 sclk2 output 1 1 pa2 cts2 input 0 0 n/a txd3 output (cmos output) 1 1 0 pa3 txd3 output (open-drain output) 1 1 1 pa4 rxd3 input 0 n/a sclk3 input 0 0 sclk3 output 1 1 port a pa5 cts3 input 0 0 n/a x: don?t care
tmp91cw40 2008-09-19 91cw40-45 table 3.5.4 i/o port settings (3/3) i/o register settings port pin name direction/function pn pncr lcdswn mseg07 input port 0 0 output port 1 0 port 2 p00 to p07 seg8 to seg15 outputs 1 n/a input port 0 0 output port 1 0 port 1 p10 to p17 seg16 to seg23 outputs 1 n/a input port 0 0 output port 1 0 port 0 p20 to p27 seg24 to seg31 outputs 1 n/a input port 0 0 output port 1 0 port b pb0 to pb7 seg32 to seg39 outputs 1 n/a hi-z 0 0 low output (note 4) 0 1 seg seg0 to seg7 seg0 to seg7 outputs n/a n/a 1 0 x: don?t care note 4: do not set the lcdcr2 bit to 1 when the lcdcr bit is 1. upon reset, the port pins are configured as general-purpose input/output ports. pins that can be programmed for either input or output are conf igured as input port pins. to use port pins for alternate functions, appropriate settings must be programmed.
tmp91cw40 2008-09-19 91cw40-46 3.5 3.5.1 port 5 (p50 to p53) port 5 is a 4-bit input-only port that can also be used as analog input pins for the ad converter. p53 can also be used as an ad trigger input pin for the ad converter. figure 3.5.1 port 5 port 5 register 7 6 5 4 3 2 1 0 bit symbol p53 p52 p51 p50 read/write r after reset data from external port key-on wakeup enable register 7 6 5 4 3 2 1 0 bit symbol kwi3en kwi2en kwi1en kwi0en read/write w after reset 0 0 0 0 function kwi interrupt input 0: disable 1: enable figure 3.5.2 port 5 registers note 1: the kwien do not support read-modify-write operation. note 2: the ad converter mode register (admod1) is used to select the ad converter input channel to be used and to enable and disable ad conversion st art by an external trigger. note 3: the key-on wakeup enable register (kwien) is used to enable and disable key-on wakeup. kwien (03a0h) p5 (000dh) kwi0 to kwi3 internal data bus a d read conversion result register ad converter channel selector port 5 read port 5 p50 to p53 (an0 to an3/kwi0 to kwi3/ adtrg ) a dtrg (p53 only)
tmp91cw40 2008-09-19 91cw40-47 3.5.2 port 6 (p60 to p62) the port 6 is compos ed of a 1-bit input port (p60) an d 2-bit input/output ports (p61 and p62) of which inputs and outputs can be specified in units of bits. a reset allows the port 6 to be put in input mode and bits 1 and 2 of the output latch register p6 are set to ?1?. besides the input/output function, the po rt 6 inputs external interrupt and outputs alarm. (1) p60 (int0) p60 can be used either as a general-purpose input port pin or an input pin for external interrupt int0. figure 3.5.3 p60 internal data bus p60 (int0) p6 read function control (bitwise) reset p6fc write level/edge select & rising/falling edge select int0 iimc
tmp91cw40 2008-09-19 91cw40-48 (2) p61 (int1) p61 can be used either as a general-purpose input/output port pin or an input pin for external interrupt int1. figure 3.5.4 p61 internal data bus selector a b s p61 (int1) p6 read direction control (bitwise) p6cr write function control (bitwise) s output latch p6 write reset p6fc write level/edge select & rising/fallig edge select int1 iimc
tmp91cw40 2008-09-19 91cw40-49 (3) p62 ( alarm ) p62 can be used either as a general-purpose input/output port pin or an output pin for the alarm function. figure 3.5.5 p62 p6 write reset p6 read selector a b s selector a b s p62 ( alarm ) 91fw40 p62 ( alarm , boot ) direction control (bitwise) p6cr write function control (bitwise) p6fc write s output latch internal data bus a lram boot reset 91fw40 only 91fw40 only
tmp91cw40 2008-09-19 91cw40-50 port 6 register 7 6 5 4 3 2 1 0 bit symbol p62 p61 p60 read/write r/w r after reset data from external port (output latch register is set to 1.) data from external port port 6 control register 7 6 5 4 3 2 1 0 bit symbol p62c p61c read/write w after reset 0 0 function 0: input 1: output 0: input 1: output port 6 function register 7 6 5 4 3 2 1 0 bit symbol p62f p61f p60f read/write w after reset 0 0 0 function 0: port 1: alarm output 0: port 1: int1 input 0: port 1: int0 input figure 3.5.6 port 6 registers p6fc (0015h) p6 (0012h) note: the p6cr and p6fc do not support read-modify-write operation. p60 int0 input setting p6fc 1 p61 int1 input setting p6fc 1 p6cr 0 p62 alarm output setting p6cr 1 p6fc 1 p6cr (0014h)
tmp91cw40 2008-09-19 91cw40-51 3.5 3.5.3 port 7 (p70 to p75) port 7 is a 6-bit general-purpose i/o port. each bit can be individually programmed for input or output. reset operation initializes all pins to input port pins. in addition to functioning as a general-purpose input/output port, port 7 can also function as input pins for 16-bit timers 1, 2, and 3 (ecin1, ecnt1 , ecin2, ecnt2, ecin3, ecnt3) , a divider output pin ( dvo ), a melody/alarm output pin ( mldalm ). figure 3.5.7 port 7 ecin1 ecnt1 ecin2 ecnt2 ecin3 p7 read internal data bus selector a b s p70 (ecnt1) p71 (ecnt2) p73 (ecin1) p74 (ecin2) p75 (ecin3) direction control (bitwise) r output latch p7cr write p7 write reset p write reset p7 read selector a b s selector a b s p72 (ecnt3, dvo , mldalm ) dvo bit direction (bitwise) p7cr write function control (bitwise) p7fc write s output latch internal data bus ecnt3 function control (bitwise) p7fc2 write selector a b s mldalm
tmp91cw40 2008-09-19 91cw40-52 port 7 register 7 6 5 4 3 2 1 0 bit symbol p75 p74 p73 p72 p71 p70 read/write r/w after reset data from external port (output latch register is reset to 0.) port 7 control register 7 6 5 4 3 2 1 0 bit symbol p75c p74c p73c p72c p71c p70c read/write w after reset 0 0 0 0 0 0 function 0: input 1: output port 7 function register 7 6 5 4 3 2 1 0 bit symbol p72f read/write w after reset 0 function 0: port 1: dvo port 7 function register 2 7 6 5 4 3 2 1 0 bit symbol p72f2 read/write w after reset 0 function 0: port/ dvo 1: mldalm figure 3.5.8 port 7 registers p7 (0013h) p7cr (0016h) port 7 input/output setting 0 input 1 output p7fc2 (002dh) p7fc (0017h) p72 dvo output setting p7fc 1 p7fc2 0 p7cr 1 p72 mldalm output setting p7fc2 1 p7cr 1 note 1: the p7cr, p7fc and p7fc2 do not support read-modify-write operation. note 2: the p70 to p75 (ecnt1 to ecnt3, ecin1 to ecin3) pins do not have a register bit for selecting t he port or timer function. the input to these pins is always directed to 16-bit timers 1 to 3 even when they are used as general -purpose input pins.
tmp91cw40 2008-09-19 91cw40-53 3.5.4 port 8 (p80 to p83) port 8 is a 4-bit general-purpose input/ou tput port. each bit can be individually programmed for input or output. reset operation initializes all pins to input port pins. all bits in the output latch register (p8) are set to 1. in addition to functioning as a general-purpose input/output port , port 8 can also function as output pins for 8-bit timers. this alternate function can be enabled by writin g 1 to respective bits of the port 8 function register (p8fc). upon reset, the p8cr and p8fc registers are all initialized to 0, setting all pins as input port pins. figure 3.5.9 port 8 (p80 to p83) p8 write reset p8 read selector a b s selector a b s p80 (tc5out) p81 (tc6out) p82 (tc7out) p83 (tc8out) tc5out,tc6out tc7out,tc8out direction control (bitwise) p8cr write function control (bitwise) p8fc write s output latch internal data bus configurable as open-drain output ode
tmp91cw40 2008-09-19 91cw40-54 port 8 register 7 6 5 4 3 2 1 0 bit symbol p83 p82 p81 p80 read/write r/w after reset data from external port (output latch register is set to 1.) port 8 control register 7 6 5 4 3 2 1 0 bit symbol p83c p82c p81c p80c read/write w after reset 0 0 0 0 function 0: input 1: output port 8 function register 7 6 5 4 3 2 1 0 bit symbol p83f p82f p81f p80f read/write w w w w after reset 0 0 0 0 function 0: port 1: tc8out 0: port 1: tc7out 0: port 1: tc6out 0: port 1: tc5out open-drain register 7 6 5 4 3 2 1 0 bit symbol odea3 odea0 ode93 ode90 ode83 ode82 ode81 ode80 read/write r/w after reset 0 0 0 0 0 0 0 0 function pa3 open-drain output 0: disable 1: enable pa0 open-drain output 0: disable 1: enable p93 open-drain output 0: disable 1: enable p90 open-drain output 0: disable 1: enable p83 open-drain output 0: disable 1: enable p82 open-drain output 0: disable 1: enable p81 open-drain output 0: disable 1: enable p80 open-drain output 0: disable 1: enable figure 3.5.10 port 8 registers p8fc (001bh) p8 (0018h) p8cr (001ah) note: the p8cr and p8fc do not support read-modify-write operation. port 8 input/output setting 0 input 1 output p80 tc5out output setting p8fc 1 p8cr 1 ode (002fh) 0 disable 1 enable open-drain output setting p81 tc6out output setting p8fc 1 p8cr 1 p82 tc7out output setting p8fc 1 p8cr 1 p83 tc8out output setting p8fc 1 p8cr 1
tmp91cw40 2008-09-19 91cw40-55 3.5.5 port 9 (p90 to p95) port 9 is a 6-bit general-purpose input/ou tput port. each bit can be individually programmed for input or output. reset operatio n initializes all pins as input port pins. all bits in the output latch register (p9) are set to ?1?. in addition to functioning as a general-purpose input/output po rt, port 9 can also function as input/output pins for serial channels 0 and 1. this alternate function can be enabled by writing ?1? to respective bits of the port 9 function register (p9fc). upon reset the p9cr and p9fc registers are all initialized to ?0?, setting all pins as input port pins. (1) p90, p93 (txd0, txd1) p90 and p93 can be used either as general-purpose input/output port pins or txd output pins for serial channels 0 and 1. the output buffer is configurable as an open-drain output using the and bits of the ode register. figure 3.5.11 port 9 (p90, p93) ode configurable as open-drain output selector a b s selector a bs p90 (txd0) p93 (txd1) txd0, txd1 p9 read direction control (bitwise) p9cr write function control (bitwise) p9fc write s output latch p9 write reset internal data bus
tmp91cw40 2008-09-19 91cw40-56 (2) p91, p94 (rxd0, rxd1) p91 and p94 can be used either as input/output port pins or rxd input pins for serial channels 0 and 1. figure 3.5.12 port 9 (p91, p94) (3) p92, p95 ( cts0 /sclk0, cts1 /sclk1) p92 and p95 can be used as general-purpose input/output port pins, cts input pins for serial channels 0 and 1, or sclk input/output pins. figure 3.5.13 port 9 (p92, p95) rxd0, rxd1 selector a bs p9 read p91 (rxd0) p94 (rxd1) direction control (bitwise) p9cr write reset s output latch internal data bus p9 write selector a b s selector a bs p92 (sclk0/ cts0 ) p95 (sclk1/ cts1 ) sclk0, sclk1 output p9 read cts0 , cts1 direction control (bitwise) p9cr write function control (bitwise) p9fc write s output latch p9 write reset sclk0, sclk1 input internal data bus
tmp91cw40 2008-09-19 91cw40-57 port 9 register 7 6 5 4 3 2 1 0 bit symbol p95 p94 p93 p92 p91 p90 read/write r/w after reset data from external port (output latch register is set to 1.) port 9 control register 7 6 5 4 3 2 1 0 bit symbol p95c p94c p93c p92c p91c p90c read/write w after reset 0 0 0 0 0 0 function 0: input 1: output port 9 function register 7 6 5 4 3 2 1 0 bit symbol p95f p93f p92f p90f read/write w w w w after reset 0 0 0 0 function 0: port 1: sclk1 output 0: port 1: txd1 0: port 1: sclk0 output 0: port 1: txd0 open-drain register 7 6 5 4 3 2 1 0 bit symbol odea3 odea0 ode93 ode90 ode83 ode82 ode81 ode80 read/write r/w after reset 0 0 0 0 0 0 0 0 function pa3 open-drain output 0: disable 1: enable pa0 open-drain output 0: disable 1: enable p93 open-drain output 0: disable 1: enable p90 open-drain output 0: disable 1: enable p83 open-drain output 0: disable 1: enable p82 open-drain output 0: disable 1: enable p81 open-drain output 0: disable 1: enable p80 open-drain output 0: disable 1: enable figure 3.5.14 port 9 registers p9fc (001dh) p9cr (001ch) note 1: the p9cr and p9fc do not support read-modify-write operation. note 2: to specify the txd pin as an open-drain output, write 1 to bit 4 (for the txd0 pin) o r bit 5 (for the txd1 pin) of the ode register. the p91/rxd0 and p94/rxd1 pins do not have a register bit for selecting the port or sio function. the input to these pins is always directed to the sio as serial receive data even when they are used as general-purpose input pins. p9 (0019h) port 9 input/output setting 0 input 1 output ode (002fh) p90 txd0 output setting p9fc 1 p9cr 1 p92 sclk0 output setting p9fc 1 p9cr 1 p93 txd1 output setting p9fc 1 p9cr 1 p95 sclk1 output setting p9fc 1 p9cr 1 0 disable 1 enable open-drain output setting
tmp91cw40 2008-09-19 91cw40-58 3.5.6 port a (pa0 to pa5) port a is a 6-bit general-purpose input/ou tput port. each bit can be individually programmed for input or output. reset operatio n initialize all pins as input port pins. all bits in the output latch register (pa) ar e set to 1. in addition to functioning as a general-purpose input/output port, port a ca n also function as input/output pins for serial channels 2 and 3. this alternate function can be enabled by writing 1 in respective bits of the port a function register (pafc). upon reset, the pacr and pafc are all initialized to 0, setting all pins as input port pins. (1) pa0, pa3 (txd2, txd3) pa0 and pa3 can be used either as general-purpose input/output port pins or txd output pins for serial channels 2 and 3. the output buffer is configurable as an open-drain output using the and bits of the ode register. figure 3.5.15 port a (pa0, pa3) ode configurable as open-drain output selector a b s selector a bs pa0 (txd2) pa3 (txd3) txd2, txd3 pa read direction control (bitwise) pacr write function control (bitwise) p a fc write s output latch p a write reset internal data bus
tmp91cw40 2008-09-19 91cw40-59 (2) pa1, pa4 (rxd2, rxd3) pa1 and pa4 can be used either as general-purpose input/output port pins or rxd input pins for serial channels 2 and 3. figure 3.5.16 port a (pa1, pa4) (3) pa2, pa5 ( 2cts /sclk2, 3cts /sclk3) pa2 and pa5 can be used either as general-purpose input/output port pins, cts input pins for serial channels 2 an d 3, or sclk input/output pins. figure 3.5.17 port a (pa2, pa5) rxd2 rxd3 selector a bs pa read pa1 (rxd2) pa4 (rxd3) direction control (bitwise) p a cr write reset s output latch internal data bus p a write selector a b s selector a bs pa2 (sclk2/ 2 cts ) pa5 (sclk3/ 3 cts ) sclk2, sclk3 output pa read 2cts , 3cts direction control (bitwise) p a cr write function control (bitwise) p a fc write s output latch p a write reset sclk2, sclk3 input internal data bus
tmp91cw40 2008-09-19 91cw40-60 port a register 7 6 5 4 3 2 1 0 bit symbol pa5 pa4 pa3 pa2 pa1 pa0 read/write r/w after reset data from external port (output latch register is set to 1.) port a control register 7 6 5 4 3 2 1 0 bit symbol pa5c pa4c pa3c pa2c pa1c pa0c read/write w after reset 0 0 0 0 0 0 function 0: input 1: output port a function register 7 6 5 4 3 2 1 0 bit symbol pa5f pa3f pa2f pa0f read/write w w w w after reset 0 0 0 0 function 0: port 1: sclk3 output 0: port 1: txd3 0: port 1: sclk2 output 0: port 1: txd2 open-drain register 7 6 5 4 3 2 1 0 bit symbol odea3 odea0 ode93 ode90 ode83 ode82 ode81 ode80 read/write r/w after reset 0 0 0 0 0 0 0 0 function pa3 open-drain output 0: disable 1: enable pa0 open-drain output 0: disable 1: enable p93 open-drain output 0: disable 1: enable p90 open-drain output 0: disable 1: enable p83 open-drain output 0: disable 1: enable p82 open-drain output 0: disable 1: enable p81 open-drain output 0: disable 1: enable p80 open-drain output 0: disable 1: enable figure 3.5.18 port a registers pafc (0021h) pa (001eh) pacr (0020h) note 1: the pacr and pafc do not support read-modify-write operation. note 2: to specify the txd pin as an open-drain output, write 1 to bit 6 (for the txd2 pin) or bit 7 (for the txd3 pin). the pa1/rxd2 and pa4/rxd3 pins do not have a register bit for selecting the port or sio function. the input to these pins is always directed to the sio as serial receive data even when the pins are used as general-purpos e input pins. port a input/output setting 0 input 1 output ode (002fh) pa0 txd2 output setting pafc 1 pacr 1 pa2 sclk2 output setting pafc 1 pacr 1 pa3 txd3 output setting pafc 1 pacr 1 pa5 sclk3 output setting pafc 1 pacr 1 0 disable 1 enable open-drain output setting
tmp91cw40 2008-09-19 91cw40-61 3.5.7 port 2 (p20 to p27) port 2 is an 8-bit general-purpose input/ou tput port. each bit can be individually programmed for input or output. reset operation initializes all pins as input port pins. all bits of the output latch register (p2) are set to 1. in addition to functioning as a general-purpose input/output port, port 2 can also function as lcd segment output pins. this alternate function can be enabled by writing 1 to respective bits of the lcd output control 1 register (lcdsw1). upon reset, the p2cr and lcdsw1 registers are all initialized to 0, setting all pins as input port pins. figure 3.5.19 port 2 (p20 to p27) p2 write reset p2 read selector a b s p20 to p27 (seg8 to seg15) direction control (bitwise) p2cr write function control (bitwise) lcdsw1 write output latch internal data bus seg8 to seg15
tmp91cw40 2008-09-19 91cw40-62 port 2 register 7 6 5 4 3 2 1 0 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w after reset data from external port (output latch register is set to 1.) port 2 control register 7 6 5 4 3 2 1 0 bit symbol p27c p26c p25c p24c p23c p22c p21c p20c read/write w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output lcd output control 1 register 7 6 5 4 3 2 1 0 bit symbol seg15c seg14c seg13c seg12c seg11c seg10c seg9c seg8c read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: seg15 0: port 1: seg14 0: port 1: seg13 0: port 1: seg12 0: port 1: seg11 0: port 1: seg10 0: port 1: seg9 0: port 1: seg8 figure 3.5.20 port 2 registers note: the lcd output control register is also provided for seg0 to seg7 which do not support the port function. lcd output control 0 register 7 6 5 4 3 2 1 0 bit symbol seg7c seg6c seg5c seg4c seg3c seg2c seg1c seg0c read/write w after reset 0 0 0 0 0 0 0 0 function 0: hi-z 1: seg7 0: hi-z 1: seg6 0: hi-z 1: seg5 0: hi-z 1: seg4 0: hi-z 1: seg3 0: hi-z 1: seg2 0: hi-z 1: seg1 0: hi-z 1: seg0 lcdsw1 (03d9h) p2 (0006h) p2cr (0008h) ? ) p2cr, lcdsw1 `??? ?? segn output setting example lcdsw1 1 port 2 input/output setting 0 input 1 output (lcdsw1=0) lcdsw0 (03d8h) note: the p2cr and lcdsw1 do not support read-modify-write operation. lcdsw1 1 note: the lcdsw0 do not support read-modify-write operation. segn output setting example lcdsw0 1
tmp91cw40 2008-09-19 91cw40-63 3.5.8 port 1 (p10 to p17) port 1 is an 8-bit general-purpose input/ou tput port. each bit can be individually programmed for input or output. reset operation initializes all pins to input port pins. all bits of the output latch register (p1) are set to 0. in addition to functioning as a general-purpose input/output port, port 1 can also function as lcd segment output pins. this alternate function can be enabled by writ ing 1 to respective bits in the lcd output control 2 register. upon reset, the p1cr and lcdsw2 are all initialized to 0, setting all pins as input port pins. figure 3.5.21 port 1 (p10 to p17) p1 write reset p1 read selector a b s p10 to p17 (seg16 to seg23) direction control (bitwise) p1cr write function control (bitwise) lcdsw2 write output latch internal data bus seg16 to seg23
tmp91cw40 2008-09-19 91cw40-64 port 1 register 7 6 5 4 3 2 1 0 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w after reset data from external port (output latch register is set to 0.) port 1 control register 7 6 5 4 3 2 1 0 bit symbol p17c p16c p15c p14c p13c p12c p11c p10c read/write w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output lcd output control 2 register 7 6 5 4 3 2 1 0 bit symbol seg23c seg22c seg 21c seg20c seg19c seg18c seg17c seg16c read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: seg23 0: port 1: seg22 0: port 1: seg21 0: port 1: seg20 0: port 1: seg19 0: port 1: seg18 0: port 1: seg17 0: port 1: seg16 figure 3.5.22 port 1 registers lcdsw2 (03dah) p1 (0001h) p1cr (0004h) note: the p1cr and ldcsw2 do not support read-modify-write operation. segn output setting example lcdsw2 1 port 1 input/output setting 0 input 1 output ldcsw2=0
tmp91cw40 2008-09-19 91cw40-65 3.5.9 port 0 (p00 to p07) port 0 is an 8-bit general-purpose input/ou tput port. each bit can be individually programmed for input or output. reset operation initializes all pins as input port pins. all bits of the output latch register (p0) are set to 0. in addition to functioning as a general-purpose input/output port, port 0 can also function as lcd segment output pins. this alternate function can be enabled by writing 1 to respective bits of the lcd output control 3 register. upon reset, the p0cr and lcdsw3 registers are all initialized to 0, setting all pins as input port pins. figure 3.5.23 port 0 (p00 to p07) p0 write reset p0 read selector a b s p00 to p07 (seg24 to seg31) direction control (bitwise) p0cr write function control (bitwise) lcdsw3 write output latch internal data bus seg24 to seg31
tmp91cw40 2008-09-19 91cw40-66 port 0 register 7 6 5 4 3 2 1 0 bit symbol p07 p06 p05 p04 p03 p02 p01 p00 read/write r/w after reset data from external pins (output latch register is set to 0.) port 0 control register 7 6 5 4 3 2 1 0 bit symbol p07c p06c p05c p04c p03c p02c p01c p00c read/write w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output lcd output control 3 register 7 6 5 4 3 2 1 0 bit symbol seg31c seg30c seg 29c seg28c seg27c seg26c seg25c seg24c read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: seg31 0: port 1: seg30 0: port 1: seg29 0: port 1: seg28 0: port 1: seg27 0: port 1: seg26 0: port 1: seg25 0: port 1: seg24 figure 3.5.24 port 0 registers lcdsw3 (03dbh) p0 (0000h) p0cr (0002h) note: the p0cr and lcdsw3 do not support read-modify-write operation. segn output setting example lcdsw3 1 port 0 input/output setting 0 input 1 output lcdsw3=0
tmp91cw40 2008-09-19 91cw40-67 3.5.10 port b (pb0 to pb7) port b is an 8-bit general-purpose input/output port. each bit can be individually programmed for input or output. reset operation initializes all pins as input port pins. all bits of the output latch register (pb) are set to 0. in addition to functioning as a general-purpose input/output port, port b can also function as lcd segment output pins. this alternate function can be enabled by writing 1 to respective bits of the lcd output control 4 register (lcdsw4). upon reset, the pbcr and lcdsw4 registers are all initialized to 0, setting all pins as input port pins. figure 3.5.25 port b (pb0 to pb7) pb write reset pb read selector a b s pb0 to pb7 (seg32 to seg39) direction control (bitwise) pbcr write function control (bitwise) lcdsw4 write output latch internal data bus seg32 to seg39
tmp91cw40 2008-09-19 91cw40-68 port b register 7 6 5 4 3 2 1 0 bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 read/write r/w after reset data from external port (output latch is set to 0.) port b control register 7 6 5 4 3 2 1 0 bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c read/write w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output lcd output control 4 register 7 6 5 4 3 2 1 0 bit symbol seg39c seg38c seg 37c seg36c seg35c seg34c seg33c seg32c read/write w after reset 0 0 0 0 0 0 0 0 function 0: port 1: seg39 0: port 1: seg38 0: port 1: seg37 0: port 1: seg36 0: port 1: seg35 0: port 1: seg34 0: port 1: seg33 0: port 1: seg32 figure 3.5.26 port b registers lcdsw4 (03dch) pb (0024h) pbcr (0025h) note: the pbcr and lcdsw4 do not support read-modify-write operation. segn output setting example lcdsw4 1 port b input/output setting 0 input 1 output lcdsw4=0
tmp91cw40 2008-09-19 91cw40-69 3.6 timing generator the timing generator generates va rious system clocks to be supplied to peripheral hardware based on the basic clock (fc or fs). (1) configuration the timing generator consists of two counters, one for the high-frequency clock and one for the low-frequency clock. figure 3.6.1 configuration of the timing generator high-frequency clock ( fc ) counter fc fc/2 fc/3 fc/2 3 fc/2 5 fc/2 7 fc/2 10 fc/2 11 fc/2 12 fc/2 13 fc/2 14 fc/2 23 low-frequency clock (fs) counter fs fs/2 2 fs/2 3 fs/2 4 fs/2 5 fs/2 6 fs/2 15
tmp91cw40 2008-09-19 91cw40-70 3.7 divider output ( dvo ) the timing generator is provided with a divider output feature which enables output of approximately 50% duty pulses. this feature is us eful for driving a piezoe lectric beeper. divider output is implemented on the p72 ( dvo ) pin. note: the divider output frequency (, ) mu st be specified and the timing generator operating status (, ) must be changed while di vider output is disabled (=0). also note that the peripheral circuits using the timing generator (8-bit/16-bit ti mers) must also be stopped before changing the and bits. 7 6 5 4 3 2 1 0 tbtcr (0340 h ) dvoen dvock dvsel D D fsdis fcdis (initial value:0000 **00) dvoen divider output enable/disable 0: disable output 1: enable output dvsel = 0 dvsel = 1 00 01 10 dvock divider output ( dvo pin) frequency [hz] 11 fc/2 13 fc/2 12 fc/2 11 fc/2 10 fs/2 5 fs/2 4 fs/2 3 fs/2 2 r/w fsdis timing generator control for low-frequency clock (fs) 0: operate 1: stop fcdis timing generator control for high-frequency control (fc) 0: operate 1: stop w note 1: fc: high-frequency clock [h z], fs: low-frequency clock [hz], *: undefined value note 2: =0 must not be set in slow and sleep modes. note 3: the tbtcr does not support read-modify-write operation. figure 3.7.1 divider output control register table 3.7.1 divider output frequencies (at fc = 27.0 mhz, fs = 32.768 khz) divider output frequency [hz] dvock dvsel = 0 dvsel = 1 00 01 10 11 3.296 k 6.592 k 13.184 k 26.367 k 1.024 k 2.048 k 4.096 k 8.192 k
tmp91cw40 2008-09-19 91cw40-71 figure 3.7.2 divider output p7 output latch p72 ( dvo , mldalm ) selecto r d q fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 10 or fs/2 2 a b c d s y 2 dvock dvoen tbtcr divider out p ut control re g iste r (a) configuration of the divider output circuit (b) divider output timing chart p72 output latch dvoen dvo pin y a b s p7fc function latch d q p7fc p7fc2 function latch d q y a b s mldalm p7fc2 =0
tmp91cw40 2008-09-19 91cw40-72 3.8 16-bit timer/counter the tmp91cw40 has three channels of 16-bit timers (tc1, tc2 and tc3). each of the three channels operates independently, and is functionally equivalent. in the following sections, any references to tc1 also apply to other channels. 3.8.1 configuration figure 3.8.1 timer/counter 1 (tc1) tc1cr1 fc/2 23 fc/2 13 fc/2 11 fs/2 15 or fc/2 7 fs/2 5 or fc/2 3 fs/2 3 or fc/2 fs or fc 3 tc1ck sgedg comparator 16-bit up-counter h g f e y d c b a s 2 tc1m 2 tc1s 1 tc1c 0944h b y a s ecnt pin ecin pin a b y c s fc/2 12 or fs/2 4 fc/2 13 or fs/2 5 fc/2 14 or fs/2 6 2 wgpsck window pulse generator edge detector 1 tc1m 2 tc1cr2 1 seg 2 sgp 1 sgedg 2 wgpsck 0945h inttmr1 interrupt request clear request treg1al treg1ah 0940h 0941h f/f tc1sr 0946h 1 1 treg1b 0943h seg edge detector 1 10 y 11 00 s p u l se w idth measurement mode f requency measu r ement mode ti mer / even t counter mode timer/event counter mode p u l se w idth measurement mode f requency measurement mode
tmp91cw40 2008-09-19 91cw40-73 3.8.2 control the timer/counter 1 (tc1) is controlled by the timer/counter 1 control registers (tc1cr1/tc1cr2), timer register (treg1a) and internal window gate pulse setting register (treg1b). timer register treg1a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (0941h, 0940h) treg1ah (0941h) treg1al (0940h) read/write (initial value: 0000 0000 0000 0000) internal window gate pulse setting register 7 6 5 4 3 2 1 0 treg1b (0943h) ta tb (initial value: 0000 0000) ta window gate pulse ?h? level period (16 ? ta) 2 13 /fc or (16 ? ta) 2 5 /fs [s] tb window gate pulse ?l? level period (16 ? tb) 2 13 /fc or (16 ? tb) 2 5 /fs [s] r/w note: wgpsck = 01 timer/counter 1 control register 1 7 6 5 4 3 2 1 0 tc1cr1 (0944h) tc1c tc1s tc1ck tc1m (initial value: 1000 0000) note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz], * : don?t care note 2: after the lower byte of the timer register (treg1al) is written, match detection is temporarily disabled until a write to the upper byte (treg1ah) is completed. (it is not possible to modify only the lower byte of the timer register.) also note that match detection is enabled again after one machine cycle has elapsed upon completion of a write to the upper byte. note 3: before changing the operating mode, source clock and edge selection, be sure to stop the timer/counter (=00). tc1cr1 and tc1cr1 must not be changed simultaneously. note 4: the source clock can be set to fc, fc/2 and fs only in the pulse width measurement mode (in normal or idle2 mode). note 5: when a read instruction is executed on the timer register (treg1a), the counter immediate value, not the value written to the treg1a is read out. before reading the treg1a, therefore, make sure that the timer/counter is stopped ; otherwise an undefined value may be read out. note 6: the timer register value should be treg1a 1. note 7: in the timer or pulse width measurement mode, select an internal clock as the source clock (tc1cr1). note 8: in the event counter mode, select an external clock as the source clock (tc1cr1). note 9: since the timer register (treg1a) has different write and read values, read-modify-write instructions must not be used on this register. note 10: in normal mode, changing tc1cr1 and treg1a while selecting fs (tc1cr2=?1?) is prohibited. note 11: in slow mode, do not set tc1cr2=0. note 12: ? ? ?indicates a setting that must not be selected. figure 3.8.2 tc1 timer register/window ga te pulse setting register/control register tc1c 0: clear counter and overflow flag (automatically set to 1 after clearing) tc1s tc1 start control 00: stop and clear counter (and overflow flag) 10: start tc1 * 1: reserved tc1sel=0 tc1sel=1 000 fc (note 4) fs (note 4) 001 fc/2 (note 4) fs/2 3 010 fc/2 3 fs/2 5 011 fc/2 7 fs/2 15 100 fc/2 11 ? 101 fc/2 13 ? 110 fc/2 23 ? [hz] tc1ck tc1 source clock select 111 external clock (ecin1 pin input) tc1m tc1 operating mode select 00: timer/event counter mode 01: reserved 10: pulse width measurement mode 11: frequency measurement mode r/w
tmp91cw40 2008-09-19 91cw40-74 timer/counter 1 control register 2 7 6 5 4 3 2 1 0 tc1cr2 (0945h) seg sgp sgedg wgpsck D tc1sel (initial value: 0000 00*0) note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz], * : don?t care note 2: before setting the tc1cr2, be sure to stop the timer/counter ( = 00). timer/counter 1 status register 7 6 5 4 3 2 1 0 tc1sr (0946h) hecf heovf D D D D D D (initial value: 00** ****) hecf operating status monitor 0: stopped (tb period) or disabled 1: counting (ta period) heovf counter overflow monitor 0: overflow not occurred 1: overflow occurred read only note: can be used only in the frequency measurement mode. figure 3.8.3 tc1 control register/status register tc1 tc2 tc3 treg1al 0940h treg2al 0950h treg3al 0960h treg1ah 0941h treg2ah 0951h treg3ah 0961h treg1b 0943h treg2b 0953h treg3b 0963h tc1cr1 0944h tc2cr1 0954h tc3cr1 0964h tc1cr2 0945h tc2cr2 0955h tc3cr2 0965h tc1sr 0946h tc2sr 0956h tc3sr 0966h note: do not access locations where no registers exist in the 0940h to 096fh area. seg external input clock (ecin1) edge select 0: count at the rising edge 1: count at the rising and falling edges sgp window gate pulse select 00: ecnt1 input 01: internal window gate pulse (treg1b) 10: reserved 11: reserved sgedg window gate pulse interrupt edge select 0: interrupt at the falling edge 1: interrupt at the falling and rising edges tc1sel=0 tc1sel=1 00: fc/2 12 fs/2 4 01: fc/2 13 fs/2 5 10: fc/2 14 fs/2 6 wgpsck window gate pulse source clock select 11: reserved r/w
tmp91cw40 2008-09-19 91cw40-75 source clocks that can be used in each operating mode (normal or idle2 mode) operating mode fc/2 23 fc/2 13 fc/2 11 or fs/2 15 fc/2 7 or fs/2 5 fc/2 3 or fs/2 3 fc/2 fc or fs ecin timer mode yes yes yes yes yes no no ? event counter mode no no no no no no no tc1cr2 = 0 fc/2 4 or fs/2 4 (max) tc1cr2 = 1 fs/2 5 or fs/2 5 (max) pulse width measurement mode yes yes yes yes yes yes yes ? frequency measurement mode no no no no no no no fc = 16 mhz or slower ecin1= fc/2 (max) fc = 16 mhz or faster ecin1= 8 mhz (max) (slow or idle2 mode) operating mode fs/2 15 fs/2 5 fs/2 3 fs ecin timer mode yes yes yes no ? event counter mode no no no no tc1cr2=0 fs/2 4 max) tc1cr2=1 fs/2 5 (max) pulse width measurement mode yes yes yes yes ? frequency measurement mode no no no no ecin1=fs/2 (max)
tmp91cw40 2008-09-19 91cw40-76 3.8.3 functional description the timer/counter 1 has the following four operating modes: (1) timer mode in the timer mode, the counter counts up on the rising edge of the internal clock. when a match between the counter value and the treg1a register value is detected, an inttmr1 interrupt is generated and the counter is cleared. the counter continues counting up after it has been cleared. table 3.8.1 timer/counter 1 s ource clock (internal clock) source clock resolution maximum setting time tc1sel = 0 tc1sel = 1 fc = 27 mhz fs = 32.768 khz fc = 27 mhz fs = 32.768 khz fc/2 23 [hz] fc/2 13 fc/2 11 fc/2 7 fc/2 3 fs/2 15 [hz] fs/2 5 fs/2 3 ? 0.31 s 303.41 s 75.85 s 4.74 s 0.3 s 1s 0.98 ms 244 s ? ? 5.66 h 19.88 s 4.97 s 310.69 ms 19.42 ms 18.2 h 1.07 min 16 s ? ? figure 3.8.4 timer mode timing chart 1 treg1a inttmr1 interrupt command start source clock counter 0 n match detect counter clear 2 3 4 n ? 1 n 0 1 2 3 4 5 6
tmp91cw40 2008-09-19 91cw40-77 programming sequences (be sure to follow these sequences.) ? setting the timer mode with the system clock fc and the counter source clock fc/2 3 ld (tc1cr2),00h : set the bit. ( = 0) ld (tc1cr1),80h : select the timer mode. ldw (treg1a),0100h : set the timer register. (treg1ah=01h, treg1al=00h) ld (tc1cr1),88h : set the source clock to fc/2 3 . ld (tc1cr1),0c8h : start the timer. ? changing the source clock and the timer register contents (after the timer is started) ld (tc1cr1),88h : stop the timer & clear the counter. ldw (treg1a),0080h : set the timer register. (treg1ah=00h, treg1al=80h) ld (tc1cr1),8ch : change the source clock from fc/2 3 to fc/2 7 . ld (tc1cr1),0cch : start the timer. ? changing the source clock to fs/2 3 (after the timer is started) ld (tc1cr1),8ch : stop the timer & clear the counter. ld (tc1cr2),00h : set =0 to select fc (in normal mode only) once. note: in normal mode, do not change the tc1cr1/treg1a with fs selected. ld (tc1cr1),8ch : change the source clock to fs/2 15 . ld (tc1cr2),01h : set =1 to select fs. ld (tc1cr1),0cch : start the timer.
tmp91cw40 2008-09-19 91cw40-78 (2) event counter mode in the event counter mode, the counter counts up on the rising edge of the ecin1 pin input. when a match between the counter value and the treg1a register value is detected, an inttmr1 interrupt is generated and the counter is cleared. then, the counter continues counting up on each rising edge of the ecin1 pin input. the maximum allowed frequency is fc/2 4 [hz] (in normal or idle2 mode) and f/2 4 [hz] (in slow or sleep mode) when tc1cr2=0. both high and low levels require a pulse width of at least two machine cycles. figure 3.8.5 event counter mode timing chart programming sequences (be sure to follow these sequences.) ? setting initial values : set the bit. (=0) ld (tc1cr2),00h =0 to count up on the rising edge of ecin1 ld (tc1cr1),80h : select the event counter mode. ldw (treg1a),0100h : set the timer register. (treg1ah=01h, treg1al=00h) ld (tc1cr1),9ch : set the source clock to the ecin1 pin input. ld (tc1cr1),0dch : start the timer. ? changing the timer register contents (after the timer is started) ld (tc1cr1),9ch : stop the timer & clear the counter. ld (tc1cr1),80h : set the source clock to an internal clock once. ldw (treg1a),0080h : set the timer register. (treg1ah=00h, treg1al=80h) ld (tc1cr1),9ch : change the source clock to the ecin1 pin input. ld (tc1cr1),0dch : start the timer. * before changing the tc1cr2, tc1cr1 and treg1a, be sure to once change the source clock to an internal clock. 1 treg1a inttmr1 interrupt start ecin1 pin input counte r 0 n match detect counter clear 2 n ? 1 1 2 n 0
tmp91cw40 2008-09-19 91cw40-79 (3) pulse width measurement mode in the pulse width measurement mode, the counter counts up on the rising edge of the and pulse of the ecin1 pin input (window pulse) and the internal clock. the internal clock is selected by tc1cr1. an inttmr1 interrupt is generated at the falling edge or at both the rising and falling edges of the window pulse, as programmed in tc1cr2. the counter value (treg1a) should be read in the interrupt service routine while the counter is stopped (i.e., ecin1 pin is at low level). then, the counter should be cleared by using tc1cr. if the counter is not cleared, it resumes counting up from the current value when counting is started again. when the treg1a counts up from ffffh to 0000h , an overflow occurs. whether or not an overflow occurred can be monitored by tc1sr . the overflow flag state is retained until the counter is cleared. note 1: inttmr1 interrupt generation timing when tc1cr2 = 1 (falling and rising edges) in the pulse width measurement mode note 2: in the pulse width measurement mode, the ope ration status monitor (tc1sr) cannot be used. figure 3.8.6 pulse width measurement mode timing chart 2 1 inttmr1 interrupt program internal clock counter 0 read & clear 2 3 n ? 1 ecin1 pin input n ? 2 n 0 1 count start count stop count start interrupt service routine inttmr1 interrupt ecin1 pin input timer start timer start a) when the timer is started with ecin1 pin at low level b) when the timer is started with ecin1 pin at high level timer start when an ecin1 port started a timer at the time of ?1?, the interrupt just after the start does not occur.
tmp91cw40 2008-09-19 91cw40-80 programming sequences (be sure to follow these sequences.) ? setting initial values ld (tc1cr2),00h : set the bit. (=0) ld (tc1cr1),82h : select the pulse width measurement mode. ld (tc1cr1),8ah : set the source clock to fc/2 3. ld (tc1cr1),0cah : start the timer. ? changing the timer register contents (after the timer is started) ld (tc1cr1),8ah : stop the timer & clear the counter. ld (tc1cr1),8eh : change the source clock to fc/2 7 . ld (tc1cr1),0ceh : start the timer.
tmp91cw40 2008-09-19 91cw40-81 (4) frequency measurement mode the frequency measurement mode is used to measure the frequency of the ecin1 pin input pulse. (in this mode, tc1cr1 should be set to external clock.) the counter counts up at the rising edge of the input pulse while the window gate pulse selected by tc1cr2 is at high level. an inttmr1 interrupt is generated at the falling edge or at both the rising and falling edges of the window gate pulse, as programmed in tc1cr2. to use the ecnt1 pin input as the window gate pulse, set tc1cr2 to 00. the counter value (treg1a) should be read out in the interrupt service routine while the counter is stopped (i.e., the window gate pulse is at low level). then, the counter should be cleared by using tc1cr. if the counter is not cleared, it resumes counting up from the current value when counting is started again. the window gate pulse state can be monitored by tc1sr. whether or not an overflow occurred in the binary counter can be monitored by tc1sr. the overflow flag state is retained until the counter is cleared. ? the internal window gate pulse, when selected, is set as explained below. the internal window gate pulse is comprised of a high level period (ta) in which counting is performed and a low level period (tb) in which counting is stopped. the ta and tb periods can be programmed independently in the treg1b register. one cycle of the window gate pulse is defined as ?ta + tb?. note 1: since the internal window gate pulse is gener ated in synchronization with the internal divider, a delay of up to one source clock (wgpsck) period may occur immediately after the timer is started. note 2: the window gate pulse must be programmed while the timer is stopped. table 3.8.2 ta and tb times (tc1cr2 = 10, fs = 32.768 khz) value n time value n time 0 31.25 ms 8 15.63 ms 1 29.30 ms 9 13.67 ms 2 27.34 ms a 11.72 ms 3 25.39 ms b 9.77 ms 4 23.44 ms c 7.81 ms 5 21.48 ms d 5.86 ms 6 19.53 ms e 3.91 ms 7 17.58 ms f 1.95 ms figure 3.8.7 window gate pulse times the ta and tb periods are represented by the following equations: when (tc1cr2 = 10): (16 ? n) 2 14 /fc [s] or (16 ? n) 2 6 /fs [s] table 3.8.2 at the right shows the ta and tb times when fs = 32.768 khz. the ta period is set by the upper 4 bits (bits 7 to 4) of the treg1b and the tb period by the lower 4 bits (bits 3 to 0). ta tb
tmp91cw40 2008-09-19 91cw40-82 figure 3.8.8 frequency meas urement mode timing chart (interrupt at the falling edge of the window gate pulse) figure 3.8.9 frequency meas urement mode timing chart (interrupt at the rising/falling edges of the window gate pulse) figure 3.8.10 frequency m easurement mode timing chart (interrupt at the rising/falling edges of the window gate pulse) counter inttmr1 interrupt ecin1 pin input window gate pulse read 1 6 0 2 3 4 5 0 1 2 3 4 5 clear ta ta tb counter inttmr1 interrupt ecin1 pin input window gate pulse 0 0 1 2 3 4 5 ta ta tb counter start mode setting 1 2 3 4 read clear 5 counter inttmr1 interrupt ecin1 pin input window gate pulse read 1 6 0 2 3 4 5 0 1 2 3 4 5 clear ta ta tb when an ecin1 port started a timer at the time of ?1?, the interrupt just after the start does not occur.
tmp91cw40 2008-09-19 91cw40-83 figure 3.8.11 frequency m easurement mode timing chart (counter overlow) programming sequences (be sure to follow these sequences) ? setting initial values ld (tc1cr2),0a8h : =0 to select fc =1 (count on the rising/falling edges of ecin1) =01 (internal window gate pulse) =0 (interrupt at the falling edge of wgp) =10 (fc/2 14 ) ld (tc1cr1),83h : select the frequency measurement mode. ld (treg1b),11h : =1, =1 ld (tc1cr1),9fh : set the source clock to the ecin1 pin input. ld (tc1cr1),0dfh : start the timer. ? changing the source clock (after the timer is started) ld (tc1cr1),9fh : stop the timer & clear the counter. ld (tc1cr1),83h : set the source clock to internal clock once. ld (tc1cr2),0a9h : set =1 to change to fs. ld (tc1cr1),9fh : set the source clock to the ecin1 pin input. ld (tc1cr1),0dfh : start the timer. * before changing the , and treg1a, be sure to once change the source clock to an internal clock. counter inttmr1 interrupt ecin1 pin input window gate pulse fffe read clea r ffff 1 2 3 fffd 0 4 0 tc1sr
tmp91cw40 2008-09-19 91cw40-84 3.9 8-bit timer/counter the tmp91cw40 has four channe ls of 8-bit timers (tc5,tc6 ? tc7 and tc8). these channels are configured into two modules, each comprising two channels (tc5 and tc6; tc7 and tc8). each module operates independently, and is function ally equivalent. in the following sections, any references to tc5 and tc6 al so apply to tc7 and tc8. 3.9.1 configuration figure 3.9.1 8-bit timer/counters 5 & 6 fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fc/3 fc/2 fc or fs tc6ck tc6cr1 a b c d e f g y s 8-bit up-counter tc6s a b y s timer or ppg mode pwm mode toggle q set clear tc6out pin inttmr6 interrupt request timer mode s a y b pwm or ppg mode decode en pwm or ppg mode 16-bit mode clear tc6m tc6s tff6 16-bit mode ttreg6 pwreg6 tff6 tc5s clear 16-bit mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fc/3 fc/2 fc or fs tc5ck tc5cr1 a b c d e f g y s 8-bit up-counter tc5m tc5s tff5 ttreg5 pwreg5 pwm mode timer mode timer mode pwm mode 16-bit mode 16-bit mode inttmr5 interrupt request toggle q set clear tc5out pin decode en tff5 pwm mode a y b s 16-bit mode overflow overflow note: depending on i/o port settings, control inputs/outputs may not become effective. for details, see the chapter on i/o port s. timer f/f6 timer f/f5 16-bit mode a b y s
tmp91cw40 2008-09-19 91cw40-85 3.9.2 control the timer/counter 5 is controlled by the ti mer/counter 5 control register 1 (tc5cr1), timer/counter 5 control register 2 (tc5cr2) and two 8-bit timer registers (ttreg5 and pwreg5). timer registers 7 6 5 4 3 2 1 0 ttreg5 (0904h) (initial value: 1111 1111) r/w 7 6 5 4 3 2 1 0 pwreg5 (0908h) (initial value: 1111 1111) r/w note 1: do not change the ttreg5 value while the timer is running. note 2: in the 8-bit or 16-bit pwm mode, do not c hange the pwreg5 value while the timer is running. note 3: values that can be set in each timer register are limited depending on the timer?s operating mode. for details, see table 3.9.3 . timer/counter 5 control register 1 7 6 5 4 3 2 1 0 tc5cr1 (0900h) tff5 tc5ck tc5s tc5m (initial value: 0000 0000) tff5 timer f/f5 control 0: clear 1: set tc5sel=0 tc5sel = 1 000 001 010 011 100 101 110 fc/2 11 fc/2 7 fc/2 5 fc/2 3 fc/3 (note 6) fc/2 (note 6) fc (note 6) fs/2 3 ? ? ? ? ? fs (note 6) tc5ck operating clock select [hz] 111 ? tc5s timer start control 0: stop & clear counter 1: start tc5m operating mode select 000: 8-bit timer mode 001: reserved 010: 8-bit pulse width modulation (pwm) output mode 011: 16-bit mode (use tc6cr1 to specify which 16-bit mode to use.) 1 **: reserved r/w note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: do not change the , , and settings while the timer is running. note 3: do not change the , and setti ngs at the same time as stopping the timer ( = 1 0) or starting the timer ( = 0 1). note 4: when the timer/counter 5 is used in 16-bit mode, the operating mode is selected by tc6cr1 and tc5cr1 must be set to 011. note 5: when the timer/counter 5 is used in 16-bit mode, various control settings are made in the tc6cr1 register. tc5cr1 must be set to 0. note 6: in selecting operation clock, fc/3, fc/2, fc and fs are selectable only in 8 or 16 bit pwm modes. see table 3.9.1 and table 3.9.2 for details.
tmp91cw40 2008-09-19 91cw40-86 timer/counter 5 control register 2 7 6 5 4 3 2 1 0 tc5cr2 (0902h) ? ? ? ? ? ? ? tc5sel (initial value: **** ***0) tc5sel timer input clock control 0: fc 1: fs r/w note 1: do not set =0 in slow or sleep mode. note 2: do not change ttreg5 when using for fs in normal mode. note 3: *: undefined value figure 3.9.2 timer registers and cont rol registers for timer/counter 5
tmp91cw40 2008-09-19 91cw40-87 the timer/counter 6 is controlled by the ti mer/counter 6 control register 1 (tc6cr1), timer/counter 6 control register 2 (tc6cr2) , and two 8-bit timer registers (ttreg6 and pwreg6). timer register 7 6 5 4 3 2 1 0 ttreg6 (0905h) (initial value: 1111 1111) r/w 7 6 5 4 3 2 1 0 pwreg6 (0909h) (initial value: 1111 1111) r/w note 1: do not change the ttreg6 value while the timer is running. note 2: in the 8-bit or 16-bit pwm mode, do not c hange the pwreg6 value while the timer is running. note 3: values that can be set in each timer register are limited depending on the timer?s operating mode. for details, see table 3.9.3. timer/count er 6 control register 7 6 5 4 3 2 1 0 tc6cr1 (0911h) tff6 tc6ck tc6s tc6m (initial value: 0000 0000) tff6 timer f/f6 control 0: clear 1: set tc6sel = 0 tc6sel = 1 000 001 010 011 100 101 110 fc/2 11 fc/2 7 fc/2 5 fc/2 3 fc/3 (note 6) fc/2 (note 6) fc (note 6) fs/2 3 ? ? ? ? ? fs (note 6) tc6ck operating clock select [hz] 111 ? tc6s timer start control 0: stop & clear counter 1: start tc6m operating mode select 000: 8-bit timer mode 001: reserved 010: 8-bit pulse width modulation (pwm) output mode 011: reserved 100: 16-bit timer mode 101: reserved 110: 16-bit pulse width modulation (pwm) output mode 111: 16-bit ppg mode r/w note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2 do not change the , , and settings while the timer is running note 3: do not change the , and settings at the same time as stopping the timer (tc6cr1 = 1 0) or starting the timer (tc6cr1 = 0 1). note 4: when the timer/counter 6 is used in 16-bit mode, the operating mode is selected by tc6cr1 and tc5cr1 must be set to 011. note 5: when the timer/counter 6 is used in 16-bit mode, various control settings are made in the tc6cr1 register. tc5cr1 must be set to 0. note 6: selection of operating clock may be limited depending on the timer?s operating mode. for details, see table 3.9.1 and table 3.9.2.
tmp91cw40 2008-09-19 91cw40-88 timer/counter 6 control register 2 7 6 5 4 3 2 1 0 tc6cr2 (0903h) ? ? ? ? ? ? ? tc6sel (initial value: **** ***0) tc6sel timer input clock control 0: fc 1: fs r/w note 1: do not set =0 in slow or sleep mode. note 2: do not change ttreg6 when using for fs in normal mode. note 3: *: undefined value figure 3.9.3 timer registers and cont rol registers for timer/counter 6 tc5 tc6 tc7 tc8 tc5cr 0900h tc6cr 0901h tc7cr 0910h tc8cr 0911h tc5cr2 0902h tc6cr2 0903h tc7cr2 0912h tc8cr2 0913h ttreg5 0904h ttreg6 0905h ttreg7 0914h ttreg8 0915h pwreg5 0908h pwreg6 0909h pwreg7 0918h pwreg8 0919h note: do not access locations where no registers exist in the 0900h to 091fh area.
tmp91cw40 2008-09-19 91cw40-89 table 3.9.1 source clocks that ca n be used in each operating mode (in normal or idle2 mode) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fc/3 fc/2 fc or fs 8-bit timer yes yes yes yes no no no 8-bit pwm yes yes yes yes yes yes yes 16-bit timer yes yes yes yes no no no 16-bit pwm yes yes yes yes yes yes yes 16-bit ppg yes yes yes yes no no no note: in 16-bit mode (16-bit timer, 16-bit pwm, or 16-bit ppg), the source clock is s pecified by tc6cr1. table 3.9.2 source clocks that can be used in each operating mode (in slow or idle2 mode) operating mode fs/2 3 fs 8-bit timer yes no (* note 2) 8-bit pwm yes yes 16-bit timer yes no (* note 2) 16-bit pwm yes yes 16-bit ppg yes no (* note 2) note 1: in 16-bit mode (16-bit timer, 16-bit pwm, or 16-bi t ppg), the source clock is specified by tc6cr1. note 2: setting is prohibited. table 3.9.3 limitations on timer register settings operating mode timer register setting 8-bit timer 1 (ttregj) 255 8-bit pwm 2 (pwregj) 254 16-bit timer 1 (ttreg6, 5) 65535 16-bit pwm 2 (pwreg6, 5) 65534 16-bit ppg 1 (pwreg6, 5) < (ttreg6, 5) 65535 and (pwreg6, 5) + 1 < (ttreg6, 5) note: j = 5, 6
tmp91cw40 2008-09-19 91cw40-90 3. 3.9 3.9.3 functional description the timer/counters 5 and 6 (tc5 and tc6) have the following five operating modes: ? 8-bit timer mode ? 8-bit pulse width modulation (pwm) output mode ? 16-bit timer mode ? 16-bit pulse width modulation (pwm) output mode ? 16-bit programmable pulse generation (ppg) mode each 16-bit mode is realized by ca scading the timer/counters 5 and 6. (1) 8-bit timer mode (tc5 and tc6) in the 8-bit timer mode, the counter counts up internal clock pulses. when a match between the counter value and the timer register (ttregj) value is detected, an inttmrj interrupt is generated and the counter is cleared. the counter then continues counting up. note 1: in the 8-bit timer mode, do not change the ttregj register value while the timer is running. in this mode, the ttregj does not have a shift register and the value written to the ttregj is reflected immediately after the write operation. therefore, if the ttregj value is changed while the timer is running, unexpected operation may result. note 2: j = 5, 6 3.9.1 3.9.2 3.9.3 table 3.9.4 source clock in 8-bi t timer mode (internal clock/tc5) source clock resolution maximum setting time tc5cr2 = 0 tc5cr2 = 1 fc = 27 mhz fs = 32.768 khz fc = 27 mhz fs = 32.768 khz fc/2 11 [hz] fc/2 7 fc/2 5 fc/2 3 fs/2 3 [hz] ? ? ? 75.9 s 4.7 s 1.2 s 296.3 ns 244.14 s ? ? ? 19.3 ms 1.2 ms 302.2 s 75.6 s 62.3 ms ? ? ? figure 3.9.1figure 3.9.2figure 3.9.3 figure 3.9.4 8-bit timer mode timing chart (tc5) 1 ttreg5 inttmr5 interrupt internal source clock counter 0 2 3 tc5cr1 n ? 1 n 0 match detect counter clear 1 2 n ? 1 match detect n 0 1 2 0 ? n counter clear tc5out tc5cr1=0
tmp91cw40 2008-09-19 91cw40-91 programming sequences (be sure to follow these sequences.) ? setting initial values ld (tc5cr2),00h : set the bit. (=0 to select fc) ld (tc5cr1),30h : =0 (drive tc5out pin high) =011 (fc/2 3 ) =000 (8-bit timer mode) ld (ttreg5),55h : set the timer register. (ttreg5=55h) ld (tc5cr1),38h : start the timer. ? changing the timer register contents (after the timer is started) ld (tc5cr1),30h : stop the timer & clear the counter. ld (ttreg5),80h : set the timer register. (ttreg5=80h) ld (tc5cr1),38h : start the timer. ? changing the source clock to fs/2 3 (after the timer is started) ld (tc5cr1),30h : stop the timer & clear the counter. ld (tc5cr2),00h : set =0 to select fc. (normal mode only) note: in normal mode, do not change ttreg while fs is selected. ld (tc5cr1),00h : =0 (drive tc5out pin high) =000 (fs/2 3 ) ld (ttreg5),80h : set the timer register. (ttreg5=80h) ld (tc5cr2),01h : =1 (fs) ld (tc5cr1),08h : start the timer.
tmp91cw40 2008-09-19 91cw40-92 (2) 8-bit pulse width modulation (pwm) output mode (tc5 and tc6) this mode is used to generate puls e width modulated (pwm) signals with a resolution of 8 bits. the counter counts up internal clock pulses. when a match between the counter value and the pwregi value is detected, the timer flip-flop (f/fi) is toggled. the counter then continues count ing up. when an overflow occurs, the timer f/fi is toggled again and the counter is cleared. the output from the timer f/fi is output on the tciout pin after being inverted. when an overflow occurs, an inttmri interrupt is generated. in the pwm mode, the pwregi register is serially connected to a shift register, enabling the pwregi value to be changed while the timer is running. while the timer is running, the value written to the pwregi is shifted into the shift register and becomes valid by an inttmri interrupt. this feature makes it po ssible to change the pulse width continuously. when the timer is not running, the value written to the pwregi is immediately shifted into the shift register. when a read instruction is executed on the pwregi during pwm output, the shift register value is returned instead of the value set in the pwregi. this means that the new value written to the pwregi cannot be read out until an inttmri interrupt occurs; up to that point the previous pwregi value is read out. note 1: in the pwm mode, the pwregi register should be written to immediately after an inttmri interrupt occurred (normally in t he inttmri interrupt service routine). if a write to the pwregi and an inttmri interrupt occur simultaneously, an unstabl e value is shifted into the shift register, causing unexpected pulses to be generated until the next inttmri interrupt occurs. note 2: when the timer is stopped during pwm output, the tciout pin retains its current output state. after the timer stops, the tciout pin state can be c hanged to a desired level by using tcicr1. be careful not to set tcicr1 at the same time as stopping the timer. note 3: i = 5, 6 table 3.9.5 pwm output mode source clock resolution repeat cycle tc5sel = 0 tc5sel = 1 fc = 27 mhz fs = 32.768 khz fc = 27 mhz fs = 32.768 khz fc/2 11 [hz] fc/2 7 fc/2 5 fc/2 3 fc/3 fc/2 fc fs/2 3 [hz] fs 75.9 s 4.7 s 1.2 s 296.3 ns 111.1 ns 74.1 ns 37.0 ns 244.14 s 30.5 s 19.4 ms 1.2 ms 303.4 s 75.9 s 28.4 s 19.0 s 9.5 s 62.5 ms 7.81 ms
tmp91cw40 2008-09-19 91cw40-93 figure 3.9.5 8-bit pwm output mode timing chart (tc5) n ff n + 1 ff 1 0 n match detect tc5cr1 tc5cr1 internal source clock counte r pwreg5 timer f/f5 inttmr5 interrupt tc5out pin n shift registe r m p m p match detect match detect 1 n n + 1 ff 0 ? ? n n m p 1 cycle shift shift shift pwreg write pwreg write m m + 1 p match detect 1 0 1 0
tmp91cw40 2008-09-19 91cw40-94 programming sequences (be sure to follow these sequences.) ? setting initial values ld (tc5cr2),00h : set the bit. (=0 to select fc) ld (tc5cr1),62h : =0 (drive tc5out pin high) =110 (fc) =010 (8-bit pwm mode) ld (pwreg5),55h : set the timer register. (pwreg5=55h) ld (tc5cr1),6ah : start the timer. ? stopping the timer ld (tc5cr1),62h : stop the timer & clear the counter. ld (tc5cr1),62h : =0 (drive tc5out pin high) must be set again after the timer is stopped.
tmp91cw40 2008-09-19 91cw40-95 (3) 16-bit timer mode (tc5 + tc6) in the 16-bit timer mode, the counter co unts up internal clock pulses. the timer/counters 5 and 6 are cascaded to function as a 16-bit timer. after the timer is started by setting tc 6cr1, a match between the counter value and the timer register (ttreg5, ttreg6) value generates an inttmr6 interrupt and clears the counter. the counter then continues counting up. the timer register must be set in the order of lower byte (ttreg5) and upper byte (ttreg6). (it is also possible to change only the lower or upper byte of the timer register.) note 1: in the 16-bit timer mode, do not change the ttregj register value while the timer is running. in this mode, the ttregj does not have a shift register a nd the value written to the ttregj is reflected immediately after the write operation. therefore, if the ttregj value is changed while the timer is running, unexpected operation may result. note 2: j = 5, 6 table 3.9.6 1 source clock in 16-bit timer mode (tc6) source clock resolution repeat cycle tc6cr2 = 0 tc6cr2 = 1 fc = 27 mhz fs = 32.768 khz fc = 27 mhz fs = 32.768 khz fc/2 11 fc/2 7 fc/2 5 fc/2 3 fs/2 3 75.9 s 4.7 s 1.2 s 296.3 ns 244.14 s ? ? ? 4.97 s 310.7 ms 77.7 ms 19.4 ms 16 s ? ? ? figure 3.9.6 16-bit timer mode timing chart (tc5 + tc6) 1 ttreg5 (lower byte) inttmr6 interrupt internal source clock counter 0 2 3 tc6cr1 mn ? 1 mn 0 match detect counter clear 1 2 mn ? 1 match detect counter clear mn 0 1 2 0 ? n ttreg6 (upper byte) ? m
tmp91cw40 2008-09-19 91cw40-96 programming sequences (be sure to follow these sequences.) ? setting initial values ld (tc6cr2),00h : set the bit. (=0 to select fc) ld (tc5cr1),03h : =011 (16-bit mode) ld (tc6cr1),b4h : =1 (drive tc6out pin low) =011 (fc/2 3 ) =100 (16-bit timer mode) ld (ttreg5),55h : set the timer register. (ttreg5=55h) ld (ttreg6),aah : set the timer register. (ttreg6=aah) ld (tc6cr1),bch : start the timer. ? changing the timer register contents (after the timer is started) ld (tc6cr1),b4h : stop the timer & clear the counter. =1 (drive tc6out pin low) ld (ttreg5),80h : set the timer register. (ttreg5=80h) ld (tc6cr1),bch : start the timer. ? changing the source clock to fs/2 3 (after the timer is started) ld (tc6cr1),b4h : stop the timer & clear the counter. ld (tc6cr2),00h : set =0 to select fc once. (normal mode only) note: in normal mode, do not change ttreg while fs is selected. ld (tc6cr1),04h : = 0 (drive tc6out high) =000 (fs/2 3 ) =100 (16-bit timer mode) ld (ttreg5),80h : set the timer register. (ttreg5=80h) ld (tc6cr2),01h : =1 (fs) ld (tc6cr1),0ch : start the timer.
tmp91cw40 2008-09-19 91cw40-97 3.9 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 (4) 16-bit pulse width modulation (pwm) output mode (tc5 + tc6) this mode is used to generate puls e width modulated (pwm) signals with a resolution of 16 bits. the timer/counters 5 and 6 are cascaded to realize the 16-bit pwm output mode. when a match between the counter value and the timer register (pwreg5, pwreg6) value is detected, the timer flip-flo p 6 (f/f6) is toggled. the counter then continues counting up. when an overflow occu rs, the timer f/f6 is toggled again, the counter is cleared, and an inttm r6 interrupt is generated. in the pwm mode, the pwreg5 and pwreg6 registers are serially connected to a shift register, enabling the pwreg5 and pwreg6 values to be changed while the timer is running. while the timer is runni ng, the values written to the pwreg5 and pwreg6 are shifted into the shift regi ster and become valid by an inttmr6 interrupt. this feature makes it possible to change the pulse width continuously. when the timer is not running, the values written to the pwreg5 and pwreg6 are immediately shifted into the shift register. when writing to the pwreg5 and pwreg6, be sure to write in the order of lower byte (pwreg5) and upper byte (pwreg6). (it is also possible to change only the lower or upper byte of the timer register.) when a read instruction is executed on the pwreg5 and pwreg6 during pwm output, the shift register value is returned instead of the value set in the pwreg5 and pwreg6. this means that the new value written to the pwreg5 and pwreg6 cannot be read out until an inttmr6 interrut occurs; up to that point the previous pwreg5 abd pwreg6 values are read out. note 1: in the pwm mode, the timer registers pwreg6 and pwreg5 should be written to immediately after an inttmr6 interrupt occurred (normally in the inttmr6 interrupt service routine). if a write to the pwreg6 and pwreg5 and an inttmr6 interrupt occur simultaneously, an unstable value is shifted into the shift register, causing unexpected pulse s to be generated until the next inttmr6 interrupt occurs. note 2: if the timer is stopped during pwm output, the tc6out pin retaines its current output state. after the timer stops, the tc6out pin state can be chagned to a desired level by using tc6cr1. be careful not to set tc6cr1 at the same time as stopping the timer. (for example, the tc6out pin should be fixed to high level while the timer/counter is not running.) res 3, (tc6cr1) : stop the timer & clear the counter. res 7, (tc6cr1) : =0 (drive tc6out pin high) table 3.9.7 16-bit pwm output mode source clock resolution repeat cycle tc6cr2 = 0 tc6cr2 = 1 fc = 27 mhz fs = 32.768 khz fc = 27 mhz fs = 32.768 khz fc/2 11 fc/2 7 fc/2 5 fc/2 3 fc/3 fc/2 fc fs/2 3 fs 75.9 s 4.7 s 1.2 s 296.3 ns 111.1 ns 74.1 ns 37.0 ns 244.14 s ? ? ? ? ? 30.52 s 4.97 s 310.7 ms 77.7 ms 19.4 ms 7.3 ms 4.9 ms 2.4 ms 16 s ? ? ? ? ? 2 s
tmp91cw40 2008-09-19 91cw40-98 figure 3.9.7 16-bit pwm mode timing chart (tc5 + tc6) pwreg write pwreg write 1 0 n match detect tc6cr1 tc6cr1 internal source clock counter pwreg5 (lower byte) timer f/f6 inttmr6 interrupt a pwreg6 (upper byte) m p c match detect match detect 1 an + 1 ffff 0 ? ? an an bm cp 1 cycle shift shift shift pwreg write pwreg write bm + 1 p ffff cp + 1 ffff b an shift registe r (16-bit) bm ? cp shift match detect 1 1 0 cp bm 0 an tc6out pin
tmp91cw40 2008-09-19 91cw40-99 programming sequences (be sure to follow these sequences.) ? setting initial values ld (tc6cr2),00h : set the bit. (=0 to select fc) ld (tc5cr1),03h : =011 (16-bit mode) ld (tc6cr1),36h : =0 (drive tc6out pin high) =011 (fc/2 3 ) =110 (16-bit pwm mode) ld (pwreg5),55h : set the timer register. (pwreg5=55h) ld (pwreg6),0aah : set the timer register. (pwreg6=aah) ld (tc6cr1),3eh : start the timer. ? changing the timer register contents (after the timer is started) ld (tc6cr1),036h : stop the timer & clear the counter. =0 (drive tc6out pin high) ld (pwreg5),80h : set the timer register. (pwreg=80h). ld (tc6cr1),3eh : start the timer. ? changing the source clock to fs/2 3 (after the timer is started) ld (tc6cr1),36h : stop the timer & clear the counter. ld (tc6cr2),00h : set =0 to select fc once. (normal mode only) note: in normal mode, do not change pwreg while fs is selected. ld (tc6cr1),06h : =0 (drive tc6out pin high) =000 (fs/2 3 ) =110 (16-bit pwm mode) ld (pwreg5),80h : set the timer register. (pwreg5=80h) ld (tc6cr2),01h : =1 (fs) ld (tc6cr1),0eh : start the timer.
tmp91cw40 2008-09-19 91cw40-100 (5) 16-bit programmable pulse genera tion (ppg) mode (tc5 + tc6) in the 16-bit programmable pulse generation (ppg) mode, the timer/counters 5 and 6 are cascaded to function as a 16-bit timer. when a match between the counter value and the timer register (pwreg5, pwreg6) value is detected, the timer flip-flo p 6 (f/f6) is toggled. the counter then continues counting up. when a match between the counter value and the timer register (ttreg5, ttreg6) value is detected, the time r f/f6 is toggled again, the counter is cleared, and an inttmr6 interrupt is genera ted. a reset clears the timer f/f6 to 0. the timer f/f6 value can be set in tc6cr1 , enabling generation of either high-going or low-going pulses. the timer registers must be set in the order of lower byte and upper byte (i.e. ttreg5 ttreg6 pwreg5 pwreg6). (it is also possible to change only the lower or upper byte of the timer register.) note 1: in the ppg mode, do not change the pwregi and ttr egi register values while the timer is running. in this mode, the pwregi and ttregi do not have a shift register and the value set to the pwregi and ttregi is reflected immediately after the write operati on. therefore, if the pwregi or ttregi value is changed while the timer is running, unexpected operation may result. note 2: when the timer is stopped during ppg output, the tc6out pin retains its current output state. after the timer stops, the tc6out pin state can be changed to a desired level by using tc6cr1. be careful not to set tc6cr1 at the same time as stopping the timer. (for example, the tc6out pin should be fixed to high level when the timer is not running.) res 3, (tc6cr1) : stop the timer & clear the counter. res 7, (tc6cr1) : =0 (drive tc6out pin high) note 3: i = 5, 6
tmp91cw40 2008-09-19 91cw40-101 figure 3.9.8 16-bit ppg mode timing chart (tc5 + tc6) mn mn 1 0 match detect tc6cr1 tc6cr1 internal source clock counter pwreg5 (lower byte) timer f/f6 inttmr6 interrupt 1 mn mn + 1 qr ? 1 qr n ? mn qr mn + 1 1 0 qr ? 1 mn + 1 pwreg6 (upper byte) m ? ttreg5 (lower byte) r ? ttreg6 (upper byte) q ? match detect match detect match detect match detect 0 qr 0 mn mn ?0? write f/f clear retains the current level qr tc6out pin
tmp91cw40 2008-09-19 91cw40-102 programming sequences (be sure to follow these sequences.) ? setting initial values ld (tc6cr2),00h : set the bit. (=0 to select fc) ld (tc5cr1),03h : =011 (16-bit mode) ld (tc6cr1),37h :=0 (drive tc6out pin high) =011 (fc/2 3 ) =111 (16-bit ppg mode) ld (pwreg5),80h : set the timer register. (pwreg5=80h) ld (pwreg6),00h : set the timer register. (pwreg6=00h) ld (ttreg5),00h : set the timer register. (ttreg5=00h) ld (ttreg6),02h : set the timer register. (ttreg6=02h) ld (tc6cr1),3fh : start the timer. ? changing the timer register contents (after the timer is started) ld (tc6cr1),37h : stop the timer & clear the counter. =0 (drive tc6out pin high) ld (pwreg5),0ffh : set the timer register (pwreg5=ffh) ld (tc6cr1),3fh : start the timer. ? changing the source clock to fs/2 3 (after the timer is started) ld (tc6cr1),37h : stop the timer & clear the counter. ld (tc6cr2),00h : set =0 to select fc once. (normal mode only) note: in normal mode, do not change pwreg while fs is selected. ld (tc6cr1),07h : =0 (drive tc6out pin high) =000 (fs/2 3 ) =111 (16-bit ppg mode) ld (pwreg5),80h : set the timer register. (pwreg5=80h) ld (tc6cr2),01h : set =1 to select fs. ld (tc6cr1),0fh : start the timer.
tmp91cw40 2008-09-19 91cw40-103 3.10 serial i/o (sio) the tmp91cw40 contains four serial i/o channe ls (sio0, sio1, sio2 and sio3). for each channel, universal asynchronous receiver/t ransmitter (uart) mode or synchronous i/o interface mode can be selected. in mode 1 and mode 2, each character can includ e a parity bit. in mode 3, a wakeup mode is available for multidrop applications in which a master controller is connected to several slave controllers through a serial link. figure 3.10.2 to figure 3.10.5 show block diagrams of sio0, sio1, sio2 and sio3, respectively . the main co m ponents of each sio channel are a clock prescaler, a serial clock generator, a receive buffer, a receive controller, a transmit buffer and a transmit controller. each of the four channels operates independently, and is functionally equivalent. in the following sections, any references to sio0 also apply to other channels, unless otherwise noted. table 3.10.1 shows the pins used for each sio channel. t able 3.10.1 pins used for each sio ch annel sio0 sio1 sio2 sio3 pin txd0 (p90) rxd0 (p91) cts0 /sclk0 (p92) txd1 (p93) rxd1 (p94) cts1 /sclk1 (p95) txd2 (pa0) rxd2 (pa1) cts2 /sclk2 (pa2) txd3 (pa3) rxd3 (pa4) cts3 /sclk3 (pa5) ? i/o interface mode mode 0: transmits/receives a serial clock (sclk) as well as data streams for a synchronou s clock mode of operation. ? uart mode mode 1: 7 data bits mode 2: 8 data bits mode 3: 9 data bits
tmp91cw40 2008-09-19 91cw40-104 figure 3.10.1 data formats 7 no parity bit0 1 2 3 4 5 6 start stop bit0 1 2 3 4 5 6 start stop parity bit0 1 2 3 4 5 6 bit0 1 2 3 4 5 6 start stop start stop parity 7 7 7 bit0 1 2 3 4 5 6 start 8 7 stop bit0 1 2 3 4 5 6 start stop bit8 7 bit8: address/data bit flag 1: address character (select code) 0: data character mode 0 (i/o interface mode) transfer direction mode 1 (7-bit uart mode) mode 2 (8-bit uart mode) mode 3 (9-bit uart mode) parity no parity parity bit0 1 2 3 4 5 6 wakeup
tmp91cw40 2008-09-19 91cw40-105 3.10.1 block diagrams figure 3.10.2 sio0 block diagram prescaler br0cr 16 32 64 8 4 2 t2 t8 t32 t0 br0cr br0add selector selector selector divider t0 t2 t8 t32 br0cr f sys i/o interface mode 2 selector i/o interface mode sc0cr sc0mod0 receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc0buf) error flag sioclk uart mode sc0mod0 sc0mod0 tb8 transmit buffer (sc0buf) interrupt request intrx0 internal data bus sc0cr txd0 (shared with p90) cts0 (shared with p92) internal data bus inttx0 sc0mod0 rxd0 (shared with p91) sc0cr txdclk sc0mod0 parity control internal data bus serial clock generator sclk0 input (shared with p92) sclk0 output (shared with p92) baud rate generator rxdclk
tmp91cw40 2008-09-19 91cw40-106 figure 3.10.3 sio1 block diagram prescaler br1cr 16 32 64 8 4 2 t2 t8 t32 t0 br1cr br1add selector selector selector divider t0 t2 t8 t32 br1cr f sys i/o interface mode 2 selector i/o interface mode sc1cr sc1mod0 receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc1buf) error flag sioclk uart mode sc1mod0 sc1mod0 tb8 transmit buffer (sc1buf) interrupt request intrx1 internal data bus sc1cr txd1 (shared with p93) cts1 (shared with p95) internal data bus inttx1 sc1mod0 rxd1 (shared with p94) sc1cr txdclk sc1mod0 parity control internal data bus serial clock generator sclk1 input (shared with p95) sclk1 output (shared with p95) baud rate generator rxdclk
tmp91cw40 2008-09-19 91cw40-107 figure 3.10.4 sio2 block diagram prescaler br2cr 16 32 64 8 4 2 t2 t8 t32 t0 br2cr br2add selector selector selector divider t0 t2 t8 t32 br2cr f sys i/o interface mode 2 selector i/o interface mode sc2cr sc2mod0 receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc2buf) error flag sioclk uart mode sc2mod0 sc2mod0 tb8 transmit buffer (sc2buf) interrupt request intrx2 internal data bus sc2cr txd2 (shared with pa0) 2cts (shared with pa2) internal data bus inttx2 sc2mod0 rxd2 (shared with pa1) sc2cr txdclk sc2mod0 parity control internal data bus serial clock generator sclk2 input (shared with pa2) sclk2 output (shared with pa2) baud rate generator rxdclk
tmp91cw40 2008-09-19 91cw40-108 figure 3.10.5 sio3 block diagram prescaler br1cr 16 32 64 8 4 2 t2 t8 t32 t0 br3cr br3add selector selector selector divider t0 t2 t8 t32 br3cr f sys i/o interface mode 2 selector i/o interface mode sc3cr sc3mod0 receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc3buf) error flag sioclk uart mode sc3mod0 sc3mod0 tb8 transmit buffer (sc3buf) interrupt request intrx3 internal data bus sc3cr txd1 (shared with pa3) 3cts (shared with pa5) internal data bus inttx3 sc3mod0 rxd3 (shared with pa4) sc3cr txdclk sc3mod0 parity control internal data bus serial clock generator sclk3 input (shared with pa5) sclk3 output (shared with pa5) baud rate generator rxdclk
tmp91cw40 2008-09-19 91cw40-109 3.10.2 sio components (1) prescaler the sio0 has a 6-bit prescaler that slows the rate of a clocking source to the serial clock generator. the prescaler clock source ( t0) has one-fourth the frequency of the clock selected by the field in the syscr0 located within the clock gear. the prescaler is only enabled when the baud rate generator output clock is selected as a serial clock. table 3.10.2 shows prescaler output clock resolutions. table 3.10.2 prescaler output clo ck resolutions prescaler output clock resolution br0cr system clock source syscr1 t0(1/1) t2(1/4) t8(1/16) t32(1/64) 1 (fs) fs/4 fs/16 fs/64 fs/256 0 (fc) 1/4 fc/4 fc/16 fc/64 fc/256 the prescaler can output four types of clock ( t0, t2, t8, t32) to the baud rate generator.
tmp91cw40 2008-09-19 91cw40-110 (2) baud rate generator the frequency used to transmit and receiv e data through the sio0 is derived from the baud rate generator. the clock source for the baud rate generator can be selected from the 6-bit prescaler outputs ( t0, t2, t8, t32) through the programming of the field in the br0cr. the baud rate generator contains a clock divi sor that can divide the selected clock by 1, n+ (16 ? k)/16, or 16. the clock divisor is programmed into the and bits in the br0cr and the bits in the br0add. ? uart mode (1) when br0cr = 0 when the bit is cleared, the br0add field has no meaning or effect. the baud rate generato r input clock is divided down by a value of n (1 to 16) programmed in the br0cr field. (2) when br0cr = 1 setting the bit enables the n + (16 ? k)/16 clock division function. the baud rate generator input clock is di vided down according to a value of n (2 to 15) programmed in the br0cr field and a value of k (1 to 15) programmed in the br0add field. note: setting n to 1 or 16 disables the n + (16 ? k)/16 clock division function. when n=1 or 16, the br0cr bit must be cleared to 0. ? i/o interface mode in i/o interface mode, the n + (16 ? k)/16 clock division function cannot be used. the br0cr bit must be cleared to 0, so the baud rate generator input clock is divided down by a value of n (1 to 16) programmed in the br0cr field. when the baud rate generator is used, the baud rate is calculated as follows: ? uart mode = 16 ? i/o interface mode = 2 baud rate generator input clock baud rate generator divisor baud rate generator input clock baud rate generator divisor baud rate baud rate
tmp91cw40 2008-09-19 91cw40-111 ? integral clock division (divide-by-n) fc = 12.288 mhz input clock: t2 clock divisor n (br0cr) = 5 br0cr = 0 * clocking conditions: system clock: high-speed (fc) the baud rate is determined as follows: baud rate = 16 = = 12.288 10 6 16 5 16 = 9600 (bps) note: clearing the br0cr to 0 disables the n + (16 ? k)/16 clock division function. at this time, the br0add field is ignored. ? n + (16 ? k)/16 clock division (uart mode only) fc = 4.8 mhz input clock: t0 n (br0cr) = 7 k (br0add) = 3 br0cr = 1 * clocking conditions: system clock: high-speed (fc) the baud rate is determined as follows: baud rate = 16 = = 4.8 10 6 4 ( 7 + ) 16 = 9600 (bps) table 3.10.3 shows the uart baud rates obtained with various combinations of clock inputs and clocl divisor values. the sio can use an exte rnal cloc k as a serial clock, bypassing the baud rate generator. when an external clock is used, the baud rate is determined as shown below. ? uart mode baud rate = external clock input 16 the external clock period must be greater than or equal to 4/fc. ? i/o interface mode baud rate = external clock input the external clock period must be greater than or equal to 16/fc. (16 ? 3) 16 7 + fc/4 13 16 16 fc/16 5 baud rate generator input clock baud rate generator divisor baud rate generator input clock baud rate generator divisor 16
tmp91cw40 2008-09-19 91cw40-112 table 3.10.3 uart baud rate selection (when the baud rate generator is used and br0cr = 0) fc [mhz] input clock divisor n (programmed in br0cr ) t0 t2 t8 t32 9.830400 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 0 9.600 2.400 0.600 0.150 12.288000 5 38.400 9.600 2.400 0.600 a 19.200 4.800 1.200 0.300 14.745600 2 115.200 28.800 7.200 1.800 3 76.800 19.200 4.800 1.200 6 38.400 9.600 2.400 0.600 c 19.200 4.800 1.200 0.300 19.6608 1 307.200 76.800 19.200 4.800 2 153.600 38.400 9.600 2.400 4 76.800 19.200 4.800 1.200 8 38.400 9.600 2.400 0.600 10 19.200 4.800 1.200 0.300 22.1184 3 115.200 28.800 7.200 1.800 24.576 1 384.000 96.000 24.000 6.000 2 192.000 48.000 12.000 3.000 4 96.000 24.000 6.000 1.500 5 76.800 19.200 4.800 1.200 8 48.000 12.000 3.000 0.750 a 38.400 9.600 2.400 0.600 10 24.000 6.000 1.500 0.375 note 1: in i/o interface mode, the transfer rate is eight times the value shown in this table. note 2: this table assumes: system clock = fc. baud rate setting examples fc [mhz] 19,200 bps 9,600 bps 4,800 bps 8 mhz 19231bps (error +0.16%) t0, n=6, k=8 9615bps (error +0.16%) t0, n=13, k=not used 4808bps (error +0.16%) t2, n=6, k=8 16 mhz 19231bps (error +0.16%) t0, n=13, k=not used 9615bps (error +0.16%) t2, n=6, k=8 4808bps (error +0.16%) t2, n=13, k=not used 24 mhz 19231bps (error +0.16%) t2, n=4, k=2 9615bps (error +0.16%) t2, n=9, k=4 4808bps (error +0.16%) t8, n=4, k=2 note 1: this table assumes: system clock = fc. example: transferring data with fc = 16 mhz, 8-bit uart mode, transfer rate = 9600 bps ld (sc0mod0),09h : select the baud rate generator. ld (br0add),08h : k = 8 for n+(16-k)/16 division ld (br0cr),56h : select n+(16-k)/16 division. : select t2 as the baud rate generator source clock. : divisor n = 6 unit: (kbps)
tmp91cw40 2008-09-19 91cw40-113 (3) serial clock generator this block generates a basic clock (siocl k) for controlling transmit and receive operations. ? i/o interface mode when the sclk pin is configured as an output by clearing the sc0cr bit to 0, the output clock from the baud rate generator is divided by two to generate the sioclk clock. when the sclk pin is configured as an input by setting the sc0cr bit to 1, the external sclk clock is used as the sioclk clock; the sc0cr bit determines the active clock edge. ? uart mode the sioclk clock is selected from a clock produced by the baud rate generator, the system clock (f sys ), the trigger output signal from the timer tmra0, and the external sclk0 clock according to the se tting of the sc0mod0 field. (4) receive counter the receive counter is a 4-bit binary up counter used in uart mode. this counter is clocked by sioclk. the receiver uses 16 clocks for each received bit, and oversamples each bit three times around their center (with 7th to 9th clocks). the value of a bit is determined by voting logic which takes the va lue of the majority of three samples. for example, if the three samples of a bit are 1, 0 and 1, then that bit is interpreted as a 1; if the three samples of a bit are 0, 0 and 1, then that bit is interpreted as a 0. (5) receive controller ? i/o interface mode when the sclk pin is configured as an output by clearing the sc0cr bit to 0, the receive controller samples the rxd0 input at the rising or falling edge of the shift clock driven out from the sclk pin. when the sclk pin is configured as an input by setting the sc0cr bit to 1, the receive controller samples the rxd0 pin at either the rising or falling edge of the sclk clock, as programmed in the sc0cr bit. ? uart mode the receive controller contains the start bit detection logic. once a valid start bit is detected (at least two 0s are detected among three samples), the receive controller begins sampling the incoming da ta streams. the start bit, each data bit and the stop bit are sampled three times for 2-of-3 majority voting.
tmp91cw40 2008-09-19 91cw40-114 (6) receive buffer the receive buffer is double-buffered to prevent overrun errors. received data is serially shifted bit by bit into receive buffer 1. when a whole character (i.e., 7 or 8 bits, as programmed) is loaded into receive buffer 1, it is transferred to receive buffer 2 (sc0buf), and the receive-done interrupt (intrx0) is generated. the cpu reads a character from receive buffer 2 (sc0buf). receive buffer 1 can start accepting a new character before the cpu picks up the previous character in receive buffer 2. however, the cpu must read receive buffer 2 before receive buffer 1 is filled with a new character; otherwise, an overrun error occurs, causing the character previously in receive buffer 1 to be lost. even in that case, the contents of receive buffer 2 and the sc0cr bit are preserved. the sc0cr bit holds the parity bit in 8-bit uart mode with parity and the most-significant bit in 9-bit uart mode. in 9-bit uart mode, the slave controller wakeup feature allows the slave controller in a multidrop system to wake up whenever an address character is received. setting the sc0mod0 bit to 1 enables the wake up feature. when the sc0cr bit has received an address/data flag bit set to 1, the receiver generates the intrx interrupt. (7) transmit counter the transmit counter is a 4-bit binary up counter used in uart mode. like the receive counter, the transmit counter is also clocked by sioclk. the transmitter generates a transmit clock (txdclk) pulse every 16 sioclk pulses. figure 3.10.6 transmit clock generation (8) transmit controller ? i/o interface mode when the sclk pin is configured as an output by clearing the sc0cr to 0, the transmit controller shifts out each bit in the transmit buffer to the txd0 pin at the rising or falling edge of the shift clock driven out on the sclk0 pin. when the sclk0 pin is configured as an input by setting the sc0cr bit to 1, the transmit controller shift out each bit in the transmit buffer to the txd0 pin at the rising or falling edge of the sclk input, as programmed in the sc0cr bit. ? uart mode once the cpu loads a character into the transmit buffer, the transmit controller begins transmission at th e next rising edge of txdclk, producing a transmit shift clock (txdsft). sioclk txdclk 15 16 1 2 4 5 67 8 910 11 12 13 14 15 16 3 1 2
tmp91cw40 2008-09-19 91cw40-115 handshaking the sio each have the clear-to-send ( cts ) pin. when the cts operation is enabled, the cts input must be low in order for a character to be transmitted. this feature can be used for flow control to prevent overrun errors in the receiver. the sc0mod0 bit enables and disables the cts operation. if the cts0 pin goes high in the middle of a transmission, the transmit controller stops transmission upon co mpletion of the current character until cts0 goes low again. the transmit controller generates the inttx0 interrupt to notify the cpu that the transmit buffer is empty. after the cpu loads the next character into the transmit buffer, the transmit controller remains in idle state until it detects cts0 going low. although there do not have the rts pin, any general-purpose port pins can serve as the rts pin. the receiving device uses the rts output to control the cts input of the transmitting device. once the receiving device has received a character, rts should be set to high in the receive-done interrupt to temporarily stop the transmitting device from sending the next character. this way, the user can easily implement a two-way handshake protocol. figure 3.10.7 handshaking signals note: a. when cts goes high in the middle of transmission, th e transmiter stops transmission after the current character has been sent. b. the transmitter starts transmission at t he first falling edge of the txdclk clock after the cts signal goes low. figure 3.10.8 cts (clear-to-send) signal timing rxd rts (any port) receiving device transmitting device txd cts tmp91cw40 tmp91cw40 no transmission takes place during this period. write to the transmit buffer cts a b 13 14 15 16 1 2 3 14 15 16 1 2 3 sioclk txdclk txd bit0 start bit
tmp91cw40 2008-09-19 91cw40-116 (9) transmit buffer once the cpu loads a character into the transmit buffer (sc0buf), it is shifted out on the txd output, with the least-significan t bit first, clocked by the transmit shift clock txdsft from the transmit controller . when the transmit buffer is empty and ready to be loaded with the next character, the intt0 interrupt is generated to the cpu. (10) parity controller for transmit operations, setting the sc0cr bit to 1 enales parity generation in 7- and 8-bit uart modes. the sc0cr bit selects either even or odd parity. if enabled, the parity controller automatica lly generates parity for the character in the transmit buffer (sc0buf). in 7-bit uart mode, the sc0buf bit holds the parity bit. in 8-bit uart mode, the sc0m od0 bit holds the parity bit. the sc0cr and bits must be prog rammed prior to a write to the transmit buffer. for receive operations, the pa rity controller automatica lly computes the expected parity when a character in receive buffer 1 is transferred to receive buffer 2 (sc0buf) . the received parity bit is compared to th e sc0buf bit in 7-bit uart mode and to the sc0cr bit in 8-bit uart mode. if a character is received with incorrect parity, the sc0cr bit is set. (11) error flags the sc1cr register has the following error flag bits that indicate the status of the received character for improved data reception reliability. 1. overrun error an overrun error is reported if all bits of a new character are received into receive buffer 1 when receive buffer 2 (sc0 buf) still contains a valid character. the following shows an example processing flow when an overrun error occurs: (receive interrupt routine) 1) read the receive buffer. 2) read the error flags. 3) if = 1 then a) disable reception: write 0 to . b) wait until the current frame is completed. c) read the receive buffer. d) read the error flags. e) enable reception: write 1 to . f) request retransmission. 4) other processing
tmp91cw40 2008-09-19 91cw40-117 2. parity error a parity error is reported when the parity bit attached to a character received on the rxd pin does not match the expected parity computed from the character transferred to receive buffer 2 (sc0buf). 3. framing error a framing error is reported when a 0 is detected where a stop bit was expected. (the middle three of the 16 samples are used to determine the bit value.) (12) signal generation timing a. uart mode receive operation mode 9 data bits 8 data bits with parity 8 data bits with no parity 7 data bits with parity 7 data bits with no parity interrupt timing middle of the last bit (bit 8) middle of the last bit (parity bit) middle of the stop bit framing error timing middle of the stop bit mid dle of the stop bit middle of the stop bit parity error timing D middle of the last bit (parity bit) middle of the stop bit overrun error timing middle of the last bit (bit 8) middle of the last bit (parity bit) middle of the stop bit note: in 9 data bits and 8 data bits with parity mode, interrupts coincide with the ninth bit pulse. thus, when an interrupt occurs, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) before checking for a framing error. transmit operation mode 9 data bits 8 data bits with parity 8 data bits with no parity 7 data bits with parity 7 data bits with no parity interrupt timing immediately before the stop bit is shifted out immediately before the stop bit is shifted out immediately before the stop bit is shifted out b. i/o interface mode sclk output mode immediately after the last bit data. (see figure 3.10.16) transmit interrupt timing sclk input mode immediately after the r ising or falling edge of the last sclk pulse, as programmed. (see figure 3.10.17) sclk output mode when a received character has been transferred to receive buffer 2 (sc0buf) (i.e. immediately after the last sclk pulse) (see figure 3.10.18) receive interrupt timing sclk input mode when a received character has been transferred to receive buffer 2 (sc0buf) (i.e. immediately after the last sclk pulse) (see figure 3.10.19)
tmp91cw40 2008-09-19 91cw40-118 3.10.3 sfrs 7 6 5 4 3 2 1 0 bit symbol tb8 ctse rxe wu sm1 sm0 sc1 sc0 read/write r/w after reset 0 0 0 0 0 0 0 0 function bit 8 of a transmitted character handshake control 0: disable cts 1: enable cts receive control 0: disable 1: enable wakeup function 0: disable 1: enable serial transfer mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: setting prohibited 01: baud rate generator 10: internal clock f sys 11: external clock (sclkn input) figure 3.10.9 serial mode control register 0 sc0mod0 (0202h) sc1mod0 (020ah) sc2mod0 (0212h) sc3mod0 (021ah) serial clock (for uart) 00 setting prohibited 01 baud rate generator 10 internal clock f sys 11 external clock (sclkn input) note: in i/o interface mode, the serial control register (scncr) is used to select the clock source. serial transfer mode 00 i/o interface mode 01 7-bit 10 8-bit 11 uart mode 9-bit wakeup function 9-bit uart mode other modes 0 interrupt on every received character 1 interrupt only when scncr = 1 don?t care 0 disable 1 enable receive control 0 disable (data streams accepted at all times) 1 enable handshake ( cts pin) bit 8 of a transmitted character
tmp91cw40 2008-09-19 91cw40-119 7 6 5 4 3 2 1 0 bit symbol rb8 even pe oerr perr ferr sclks ioc read/write r r/w r (cleared when read) r/w after reset undefined 0 0 0 0 0 0 0 function bit 8 of a received character parity type 0: odd 1: even parity 0: disable 1: enable overrun error parity error framing error 0: sclkn 1: sclkn 0: baud rate generator 1: sclkn pin input note: all error flags are cleared to 0 when read. these bi ts should not be tested using a bit test instruction. figure 3.10.10 serial control register sc0cr (0201h) sc1cr (0209h) sc2cr (0211h) sc3cr (0219h) input clock in i/o interface mode framing error flag parity error flag overrun error flag 0 transmit/receive data on the sclkn rising edge. 1 transmit/receive data on the sclkn falling edge. active edge for the sclkn input/output 0 disable 1 enable parity generation parity type 1: error has occurred 0 baud rate generator 1 sclkn pin input these bits are cleared to 0 when read. 0 odd parity 1 even parity bit 8 of a received character a read -modify-write operation cannot be performed
tmp91cw40 2008-09-19 91cw40-120 7 6 5 4 3 2 1 0 bit symbol ? br0adde br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 read/write r/w after reset 0 0 0 0 0 0 0 0 function always write 0. + (16 ? k) /16 function 0: disable 1: enable 00: t0 01: t2 10: t8 11: t32 7 6 5 4 3 2 1 0 bit symbol br0k3 br0k2 br0k1 br0k0 read/write r/w after reset 0 0 0 0 function clock divisor value for baud rate generator br0cr = 1 br0cr = 0 br0cr br0add 0000 (n = 16) or 0001 (n = 1) 0010 (n = 2) to 1111 (n = 15) 0001 (n = 1) (uart only) to 1111 (n = 15) 0000 (n = 16) 0000 don?t use don?t use 0001 (k = 1) to 1111 (k = 15) don?t use divide by n + 16 k)(16 ? divide by n note1: availability of + (16 ? k)/16 division function n uart mode i/o mode 2 to15 allowed not allowed 1, 16 not allowed not allowed the baud rate generator can be set to ?1? in uart mode only when the +(16-k)/16 division function is not used. do not use in i/o interface mode. note2: set br0cr to 1 after setting k (k = 1 to 15) to br0add when +(16-k)/16 division function is used. if the unused bits in the br0add register is written, it does not affect operation. if that bits is read, it becomes undefined. figure 3.10.11 baud rate generator control register br0cr (0203h) br1cr (020bh) br2cr (0213h) br3cr (021bh) divisor n value k for n + (16 ? k)/16 division br0add (0204h) br1add (020ch) br2add (0214h) br3add (021ch) + (16 ? k)/16 function 00 internal clock t0 01 internal clock t2 10 internal clock t8 11 internal clock t32 clock source for baud rate generator 0 disable 1 enable
tmp91cw40 2008-09-19 91cw40-121 note: the scnbuf register does not support read-modify-write operation. figure 3.10.12 serial transmit/receive buffer register 7 6 5 4 3 2 1 0 bit symbol i2s0 fdpx0 read/write r/w r/w after reset 0 0 function idle2 0: stop 1: run duplex 0: half 1: full figure 3.10.13 serial mode control register 1 sc0mod1 (0205h) sc1mod1 (020dh) sc2mod1 (0215h) sc3mod1 (021dh) tb7 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 sc0buf (0200h) sc1buf (0208h) sc2buf (0210h) sc3buf (0218h) (for transmit) (for receive) tb6 tb5 tb4 tb3 tb2 tb1 tb0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0
tmp91cw40 2008-09-19 91cw40-122 3.10.4 operating modes (1) mode 0 (i/o interface mode) mode 0 is used to increase the number of input/output pins. in this mode, the tmp91cw40 transmits or receives data to and from an external device, such as a shift register. mode 0 uses a synchronization clock (sclk), which can be configured for either output mode in which the sclk clock is driven out from the tmp91cw40 or input mode in which the sclk clock is supplied externally. figure 3.10.14 example connect ion in sclk output mode figure 3.10.15 example conne ction in sclk input mode output expansion tmp91cw40 txd sclk port input expansion tc74hc595 tc74hc165 tmp91cw40 shift register a b c d e f g h rxd sclk port shift register a b c d e f g h si sck rck qh clock s/ l output expansion tmp91cw40 txd sclk port input expansion tc74hc595. tc74hc165 tmp91cw40 shift register a b c d e f g h rxd sclk port shift register a b c d e f g h si sck rck qh clock external clock external clock s/ l
tmp91cw40 2008-09-19 91cw40-123 a. transmit operations in sclk output mode, each time the cpu writes a character to the transmit buffer, the eight bits of the character are shifted out on the txd0 pin and the synchronization clock is driven out from the sclk pin. when all the bits have been shifted out, the intes0 is set and the transmit-done interrupt (inttx0) is generated. figure 3.10.16 transmit operation in i/o interface mode (sclk output mode) in sclk input mode, the cpu must write a character to the transmit buffer before the sclk input is activated. the 8 bits of a character in the transmit buffer are shifted out on the txd0 pin, synchronous to the programmed edge of the sclk0 input. when all the bits have been shifted out, the intes0 is set and the transmit-done interrupt (inttx0) is generated. figure 3.10.17 transmit operation in i/o interface mode (sclk0 input mode) timing to write transmission data sclk0 output (=0 rising edge mode) bit0 bit6 bit7 bit1 txd0 (inttx0 interru p t re q uest ) sclk0 output (=1 falling edge mode) sclk0 input ( = 0 rising edge mode) sclk0 ( = 1 falling edge mode) bit0 bit1 txd0 (inttx0 interrupt request) bit5 bit6 bit7 (internal clock timin g )
tmp91cw40 2008-09-19 91cw40-124 b. receive operations in sclk output mode, each time the cpu picks up a character in receive buffer 2 clearing the receive-done interrupt flag (intes0), the synchronization clock is driven out from the sclk pin to shift the next character into receive buffer 1. when a whole 8-bit character has been loaded into re ceive buffer 1, it is transferred to receive buffer 2 (sc0buf), and the intes0 fl ag is set to 1, generating the intrx0 interrupt. the sclk output is initiated by setting the sc0mod0 bit to 1. figure 3.10.18 receive operation in i/o interface mode (sclk output mode) in sclk input mode, the cpu must pick up a character in receive buffer 2, clearing the receive-done interrupt flag (intes0), before the sclk input is activated to shift the next character into receive buff er 1. when a whole 8-bit character has been loaded into receive buffer 1, it is transf erred to receive buffer 2 (sc0buf), and the intes0 flag is set to 1 again, generating the intrx0 interrupt. figure 3.10.19 receive operation in i/o interface mode (sclk0 input mode) note: regardless of whether sclk is in input mode or output mode, the receiver must be enabled by setting the sc0mod0 bit to 1 in order to perform receive operations. sclk0 output (=0 rising edge mode) rxd0 (intrx0 interrupt request) bit0 bit6 bit7 bit1 sclk0 output (=1 falling edge mode) sclk0 input ( = 0: risin g ed g e mode ) bit0 bit6 bit7 bit1 rxd0 (intrx0 interrupt request) bit5 sclk0 input ( = 1: fallin g ed g e mode )
tmp91cw40 2008-09-19 91cw40-125 c. full-duplex transmit/receive operations to perform full-duplex transmit/receive operations, the receive interrupt priority level must be set to 0, with the transmit in terrupt priority level set to an appropriate value (1 to 6). in the transmit interrupt service routin e, receive operation must be performed before loading the transmit buffer with a character, as shown below. example: channel 0 sclk output mode transfer rate: 9600 bps fc = 14.7456 mhz * clocking conditions system clock: high-speed (fc) settings in the main routine 7 6543210 intes0 x 0 0 1 x 0 0 0 set the transmit interrupt level and disable receive interrupts. p9cr ? ? ? ? ? 101 p9fc ? ? ? ? ? 1 ? 1 configure the p90 pin as txd0 and the p92 pin as sclk0. sc0mod0 0 0000000 select i/o interface m ode. sc0mod1 1 1xxxxxx select full- duplex mode. sc0cr 0 0000000 select sclk output m ode, receiving at the rising edge and transmitting at the rising edge. br0cr 0 0110011 set the transfer rate to 9600 bps. sc0mod0 0 0100000 enable receive operation. sc0buf * ******* load the transmit buffer with transmit data. transmit interrupt service routine acc sc0buf read received data. sc0buf * ******* load the transmit buffer with transmit data. x: don?t care ? : no change
tmp91cw40 2008-09-19 91cw40-126 (2) mode 1 (7-bit uart mode) setting the sc0mod0 field to 01 puts the sio0 in 7-bit uart mode. in this mode, the parity bit can be added to the transmitted character, and the receiver can perform a parity check on incoming data. parity can be enabled and disabled by programming the sc0cr bit. when is set to 1 to enable parity, the sc0cr bit selects even or odd parity. example: transmitting data with even parity in 7-bit uart mode * clock conditions system clock: high-speed (fc) 7 6 5 4 3 2 1 0 p9cr ? ? ? ? ? ? ? 1 p9fc ? ? ? ? ? ? ? 1 sc0mod0 x 0 ? x 0 1 0 1 select 7-bit uart mode. sc0cr x 1 1 x x x 0 0 select even parity. br0cr 0 0 1 0 0 1 0 1 set the transfer rate to 2400 bps. intes0 x 1 0 0 ? ? ? ? enable the inttx0 interrupt and set its interrupt level to 4. sc0buf * * * * * * * * load the transmit buffer with transmit data. x: don?t care ? : no change transfer direction (transfer rate: 2400 bps at fc = 12.288 mhz) start bit0 1 2 3 5 4 6 even parity stop configure the p90 pin as txd0.
tmp91cw40 2008-09-19 91cw40-127 (3) mode 2 (8-bit uart mode) setting the sc0mod0 field to 10 puts the sio0 in 8-bit uart mode. in this mode, the parity bit can be added to the transmitted character, and the receiver can perform a parity check on incoming data. parity can be enabled and disabled by programming the sc0cr bit. when is set to 1 to enable parity, the sc0cr bit selects even or odd parity. example: receiving data with odd parity in 8-bit uart mode * clock conditions system clock: high-speed (fc) settings in the main routine 7 6 5 4 3 2 1 0 p9cr ? ? ? ? ? ? 0 ? configure the p91(rxd0) pin as an input. sc0mod0 ? 0 1 x 1 0 0 1 select 8-bit uart mode and enable the receiver. sc0cr x 0 1 x x x 0 0 select odd parity. br0cr 0 0 0 1 0 1 0 1 set the transfer rate to 9600 bps. intes0 ? ? ? ? x 1 0 0 enable the intrx0 interrupt and set its interrupt level to 4. example of interrupt routine processing acc sc0cr and 00011100 check for errors. if acc 0 then error acc sc0buf read received data. x: don?t care ? : no change transfer direction (transfer rate: 9600 bps at fc = 12.288 mhz) start bit0 1 2 3 5 4 6 odd parity stop 7
tmp91cw40 2008-09-19 91cw40-128 (4) mode 3 (9-bit uart) setting the sc0mod0 field to 11 puts the sio0 in 9-bit uart mode. in this mode, no parity bit can be added. the most-significant bit (9th bit) is stored in the sc0mod0 bit in transmit operations and in the sc0cr bit in receive operations. transmit and receive data must be read and written with the mo st-significant bit first, followed by the sc0buf. wakeup feature in 9-bit uart mode, the receiver wakeup feature allows the slave controller in a multidrop system to wake up whenever an address character is received. setting the sc0mod0 bit to 1 enables the wakeup feature. when the sc0cr bit has received an address/data flag bit set to 1, th e receiver generates the intrx0 interrupt. note: the slave controller?s txd pin must be configured as an open-drain output by programming the ode register. figure 3.10.20 serial link using the wakeup function txd master slave 1 slave 2 slave 3 rxd txd rxd txd txd rxd rxd
tmp91cw40 2008-09-19 91cw40-129 1. put all the master and salve controllers in 9-bit uart mode. 2. enable the receiver in each slave controller by setting the sc0mod0 bit to 1. 3. the master controller transmits an address character (i.e., select code) that identifies a slave controller. the address character has the most-significant bit (bit 8) set to 1. 4. each slave controller compares the received select code to its own select code and clears the bit if they match. 5. the master controller transmits data character to the selected slave controller (with the sc1mod0 bit cleared). data characters have the most-significant bit (bit 8) cleared to 0. 6. slave controllers not addressed (with = 1) continue to monitor the data stream, but discard any characters with the most-sig nificant bit (rb8) cleared, and thus does not generate receive-done interrupts (intrx ). the addressed slave controller (with = 0) can transmit data to the master co ntroller to notify th at it has successfully received the message. protocol slave controller select code start bit0 1 2 3 5 4 6 stop 7 8 ?1? data ?0? start bit0 1 2 3 5 4 6 stop 7 bit8
tmp91cw40 2008-09-19 91cw40-130 example: connecting a master controller and two slave controllers through a serial link using the system clock (f sys ) as a serial clock ? master controller settings main routine p9cr ? ? ? ? ? ? 01 p9fc ? ? ? ? ? ? x1 intes0 x 1 0 0 x 1 0 1 enable inttx0 and set its interrupt level to 4. enable intrx0 and set its interrupt level to 5. sc0mod0 1 0 1 0 1 1 1 0 select 9-bit uart mode and select f sys as a serial clock. sc0buf 0 0 0 0 0 0 0 1 load the select code for slave 1. interrupt routine (inttx0) sc0mod0 0 ? ? ? ? ? ? ? set the bit to 0 . sc0buf * * * * * * * * loads the transmit data. ? salve controller settings main routine p9cr ? ? ? ? ? ? 01 p9fc ? ? ? ? ? ? x1 ode ? ? ? 1 ? ? ? ? set the p90 pin as txd0 (open-drain output) and the p91 pin as rxd0. intes0 x 1 0 1 x 1 1 0 enable inttx0 and intrx0. sc0mod0 0 0 1 1 1 1 1 0 select 9-bit uart mode, select f sys as a serial clock, and se t the bit to 1. interrupt routine (intrx0) acc sc0buf if acc = select code then sc0mod0 ? ? ? 0 ? ? ? ? clear the bit to 0. confi g ure the p90 p in as txd0 and the p91 p in as rxd0. txd master slave 1 slave 2 select code 00000001 rxd txd rxd txd rxd select code 00001010
tmp91cw40 2008-09-19 91cw40-131 3.11 lcd driver the tmp91cw40 contains a driver and a control circuit for directly driving a liquid crystal display (lcd). the lcd is connected using the following pins: a. segment output pins : 8 pins (seg7 to seg0) b. segment output/port (p0, p1, p2, pb) mu ltiplexed pins : 32 pins (seg39 to seg8) c. common output pins : 4 pins (com3 to com0) the c0, c1, v1, v2 and v3 pins are also available for the voltage reducer in the lcd driver. the lcd driver can directly drive the following four types of lcds: a. 1/4 duty (1/3 bias) lcd: up to 160 pixels (8 segments x 20 commons) b. 1/3 duty (1/3 bias) lcd: up to 120 pixels (8 segments x 15 commons) c. 1/2 duty (1/2 bias) lcd: up to 80 pixels (8 segments x 10 commons) d. static lcd: up to 40 pixles (8 segments x 5 commons) 3.11.1 configuration figure 3.11.1 lcd driver display data registers display data buffer registers segment driver regulated voltage reducer c0 c1 v1 v2 v3 common driver lcd driver control register lcdcr blanking control 7 6 5 4 3210 edsp bres vfsel duty slf duty control timing generator display data selection control fc/2 19 , fs/2 10 fc/2 18 , fs/2 9 fc/2 17 , fs/2 8 fc/2 16 , fs/2 7 fc/2 11 , fs/2 3 fc/2 10 , fs/2 2 fc/2 9 , fs/2 fc/2 8 , fs com0 com3 to seg0 to seg7 seg8 to seg39 counter fc fs selector lcdclk syscr3
tmp91cw40 2008-09-19 91cw40-132 3.11.2 control the lcd driver is controlled by the lcd co ntrol register (lcdcr). the bit in the lcdcr is used to enable lcd display. 7 6 5 4 3 2 1 0 lcdcr (03d0h) edsp bres vfsel duty slf (initial value: 0000 0000) syscr1=0 syscr1 =1 syscr3 =0 syscr3 =1 syscr3 =1 slf base frequency [hz] 00 01 10 11 fc/2 19 fc/2 18 fc/2 17 fc/2 16 fs/2 10 fs/2 9 fs/2 8 fs/2 7 fs/2 10 fs/2 9 fs/2 8 fs/2 7 duty lcd drive method 00: 1/4 duty (1/3 bias) 01: 1/3 duty (1/3 bias) 10: 1/2 duty (1/2 bias) 11: static syscr1=0 syscr1 =1 syscr3 =0 syscr3 =1 syscr3 =1 vfsel voltage reducer frequency [hz] 00 01 10 11 fc/2 11 fc/2 10 fc/2 9 fc/2 8 fs/2 3 fs/2 2 fs/2 fs fs/2 3 fs/2 2 fs/2 fs bres voltage reducer enable/disable 0: disable (use external divider resistors) 1: enable edsp lcd display control 0: disable 1: enable r/w note 1: when =0, v dd v 3 v 2 v 1 v ss must be satisfied. when =1, v dd = v 3 must be satisfied. ignoring these conditions may not only affect the quality of lcd display but also damage the device due to overcurrent that flows through ports. note 2: the and fields should be set when =0. (nor is it allowed to set these fields with the same instruction that sets to 0. ) otherwise, the expected duty cannot be obtained and the lcd cannot be displayed properly. note 3: the reference clock (lcdclk) for the base frequenc y of the lcd driver is independent of the system clock and can be switched between low-frequency (fs) and high-frequency (fc) by the programming of the syscr3 bit. for proper operation of the lcd, be careful about the following points: ? before changing lcdclk to low-frequency (fs), start up the low-frequency oscillator (fs) by programming syscr0 and make sure that t he warming-up period has completed by checking syscr0. ? it is not allowed to set the system clock to low-frequency (fs) and lcdclk to high-frequency (fc). ? before changing the system clock from high-frequency (fc) to low-frequency (fs), make sure to set lcdclk to low-frequency (fs). when the low-frequency (fs) clock is used for the system clock, it is recommended to set lcdclk to low-frequency (fs) in the application?s startup routine and to always use the low-frequency (fs) clock for lcdclk. note 4: to change the syscr3 bit, the bit must be 0. note 5: when the device enters stop mode, the bit is automatically cleared to 0. if halt mode is activated immediately after display data is written to the lcdr eg, the lcd is not displayed correctly and the device immediately enters halt mode. after exiting stop mode, do not make any settings for the lcd driver until the warming up of fs has completed. this can be checked by the syscr0 register. note 6 when used as lcd pins, com output pins output low level and seg output pins are placed in a high-impednce state when the bit is cleared to 0 (except when seg output pi ns are used as ports). when lcdcr2=1, seg0 to seg7 pins output low level. figure 3.11.2 lcd driver control register (1)
tmp91cw40 2008-09-19 91cw40-133 7 6 5 4 3 2 1 0 lcdcr2 (03deh) ?0? ?0? mseg07 ?0? ?0? ?0? ?0? ?0? (initial value: 0000 0000) lcdcr=0 lcdcr=1 0 high impedance display data output mseg07 seg0 to seg7 pins output control 1 low output don?t use w note 1: do not set the bit to 1 when the lcdcr bit is 1. note 2: except for bit 5, all the bits of this register must always be written as 0. note 3: this register does not support read-modify-write operation. figure 3.11.3 lcd driver control register (2)
tmp91cw40 2008-09-19 91cw40-134 (1) lcd drive method the lcd drive method can be selected from four types by the programming of the field in the lcdcr. the lcd drive method should be set in the initialization program according to the lcd to be used. figure 3.11.4 lcd drive waveforms (potent ial differences between com and seg pins) 1/f f v lcd3 0 ?v lcd3 data ?1? data ?0? (a) 1/4 duty (1/3 bias) 1/f f v lcd3 0 ?v lcd3 data ?1? data ?0? (b) 1/3 duty (1/3 bias) 1/f f v lcd3 0 ?v lcd3 data ?1? data ?0? (c) 1/2 duty (1/2 bias) 1/f f v lcd3 0 ?v lcd3 data ?1? data ?0? (d) static note: f f = frame frequency v lcd3 = lcd drive voltage
tmp91cw40 2008-09-19 91cw40-135 (2) frame frequency the frame frequency (f f ) is determined according to the lcd drive method and base frequency, as shown in table 3.11.1. the base frequency is select ed b y the lcdcr field according to the basic clock frequencies fc and fs to be used. table 3.11.1 frame frequency settings a. syscr3 = 0 frame frequency [hz] slf base frequency [hz] 1/4 duty 1/3 duty 1/2 duty static 00 fc/2 19 fc/2 19 4/3 fc/2 19 4/2 fc/2 19 fc/2 19 (fc = 24 mhz) 46 61 92 46 (fc = 16 mhz) 31 41 61 31 (fc = 8 mhz) 15 20 31 15 01 fc/2 18 fc/2 18 4/3 fc/2 18 4/2 fc/2 18 fc/2 18 (fc = 24 mhz) 92 122 183 92 (fc = 16 mhz) 61 81 122 61 (fc = 8 mhz) 31 41 61 31 10 fc/2 17 fc/2 17 4/3 fc/2 17 4/2 fc/2 17 fc/2 17 (fc = 24 mhz) 183 244 366 183 (fc = 16 mhz) 122 163 244 122 (fc = 8 mhz) 61 81 122 61 11 fc/2 16 fc/2 16 4/3 fc/2 16 4/2 fc/2 16 fc/2 16 (fc = 24 mhz) 366 488 732 366 (fc = 16 mhz) 244 326 488 244 (fc = 8 mhz) 122 163 244 122 note: fc = high-frequency clock frequency [hz] b. syscr3 = 1 frame frequency [hz] slf base frequency [hz] 1/4 duty 1/3 duty 1/2 duty static 00 fs/2 10 fs/2 10 4/3 fs/2 10 4/2 fs/2 10 fs/2 10 (fs = 32.768 khz) 32 43 64 32 01 fs/2 9 fs/2 9 4/3 fs/2 9 4/2 fs/2 9 fs/2 9 (fs = 32.768 khz) 64 85 128 64 10 fs/2 8 fs/2 8 4/3 fs/2 8 4/2 fs/2 8 fs/2 8 (fs = 32.768 khz) 128 171 256 128 11 fs/2 7 fs/2 7 4/3 fs/2 7 4/2 fs/2 7 fs/2 7 (fs = 32.768 khz) 256 341 512 256 note: fs = low-frequency clock frequency [hz]
tmp91cw40 2008-09-19 91cw40-136 (3) lcd drive power supply to obtain the lcd drive power supply, the tmp91cw40 can use either the voltage reducer incorporated in the lcd driver that reduces the external reference voltage, or external divider resistors that divide the exernal reference voltage. this selection is made in the field in the lcd control register (lcdcr). when the voltage reducer is used, the reference voltage connected to the v3 pin is reduced to two-thirds (2/3) or one-third (1/3) to generate the output voltage for segment/common signals. when external divider resistors are used, the external power supply is divided by external resistors and the divided voltages are input to the v1, v2 and v3 pins to generate the output voltage for segment/common signals. the voltage reducer only supports 1/3 bias. the base frequency for the voltage reducer is selected by the field in the lcdcr. the segment/common drive capability can be increased by selecting a higher frequency. table 3.11.2 shows the current carrying capacities of the v3 pin according to the sel ected base freque nc y for the voltage reducer. figure 3.11.5 example of lcd power supply connection when using the voltage reducer (lcdcr = 1) figure 3.11.6 example of lcd power supply connection when using external divider resistors (lcdcr = 0) 1/3 bias (r1 = r2 = r3) 1/2 bias (r1 = r2) static when external divider resistors are us ed, the following condition must be met: vcc v 3 v 2 v 1 vss vcc vss v3 v2 c0 c1 v1 r1 contrast adjustment open open r2 r3 vcc vss v3 v2 c0 c1 v1 r1 contrast adjustment open open r2 vcc vss v3 v2 c0 c1 v1 contrast adjustment open open r1 vcc vss v3 v2 v1 c1 c0 c c c v 3 vcc c = 0.1 to 0.47 f c
tmp91cw40 2008-09-19 91cw40-137 table 3.11.2 current carrying capacities of the v2 pin according to the voltage reducer frequency (typ.) vcc=v3=3.0v, ta=25 lcdcr voltage reducer frequency fc = 24 mhz fc = 16 mhz fc = 8 mhz fs = 32.768 khz 00 fc/2 11 or fs/2 3 ?1.63 mv / a ? 1.82 mv / a ?2.63 mv / a ?3.77 mv / a 01 fc/2 10 or fs/2 2 ?1.04 mv / a ? 1.12 mv / a ?1.42 mv / a ?1.60 mv / a 10 fc/2 9 or fs/2 ?0.97 mv / a ?1.06 mv / a ?1.07 mv / a ?1.16 mv / a 11 fc/2 8 or fs ?0.90 mv / a ? 0.90 mv / a ?0.90 mv / a ?0.97 mv / a note 1: the current carrying capacity indicates the amount of voltage that drops per 1 a. note 2: the base frequency for the voltage reducer shoul d be selected according to the lcd panel to be used. table 3.11.3 current carrying capacities of the v1 pin according to the voltage reducer frequency (typ.) vcc=v3=3.0v, ta=25 lcdcr voltage reducer frequency fc = 24 mhz fc = 16 mhz fc = 8 mhz fs = 32.768 khz 00 fc/2 11 or fs/2 3 ?0.57 mv / a ? 0.70 mv / a ?1.17 mv / a ?1.01 mv / a 01 fc/2 10 or fs/2 2 ?0.55 mv / a ? 0.60 mv / a ?0.78 mv / a ?0.72 mv / a 10 fc/2 9 or fs/2 ?0.53 mv / a ?0.54 mv / a ?0.61 mv / a ?0.57 mv / a 11 fc/2 8 or fs ?0.52 mv / a ? 0.53 mv / a ?0.56 mv / a ?0.54 mv / a note 1: the current carrying capacity indicates the amount of voltage that drops per 1 a . note 2: the base frequency for the voltage reducer shoul d be selected according to the lcd panel to be used.
tmp91cw40 2008-09-19 91cw40-138 3.11.3 lcd display operation (1) display data setting the display data stored in the display data area is automatically read and sent to the lcd driver by hardware. the lcd driver generates segment and common signals according to the received display data and the specified drive method. therefore, it is only required to program the contents of the display data area to change display patterns. after display data is written to the lcdreg0 to lcdreg19, a wait period of six lcdclk pulses is needed before new display data can be written. if new display data is written without wa iting for this interval, the previous display data may be overwritten. figure 3.11.7 shows the correspondence between the display data area and the seg and com pins. the lcd light is tur n ed on when display data is 1 and turned off when display data is 0. the number of pixels that can be driven varies with the lcd drive method, so the number of bits to be used in the display data area also varies. note: the contents of the display data area are initialized to 00h after reset. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcdreg0 03e0h seg1 seg0 lcdreg1 03e1h seg3 seg2 lcdreg2 03e2h seg5 seg4 lcdreg3 03e3h seg7 seg6 lcdreg4 03e4h seg9 seg8 lcdreg5 03e5h seg11 seg10 lcdreg6 03e6h seg13 seg12 lcdreg7 03e7h seg15 seg14 lcdreg8 03e8h seg17 seg16 lcdreg9 03e9h seg19 seg18 lcdreg10 03f0h seg21 seg20 lcdreg11 03f1h seg23 seg22 lcdreg12 03f2h seg25 seg24 lcdreg13 03f3h seg27 seg26 lcdreg14 03f4h seg29 seg28 lcdreg15 03f5h seg31 seg30 lcdreg16 03f6h seg33 seg32 lcdreg17 03f7h seg35 seg34 lcdreg18 03f8h seg37 seg36 lcdreg19 03f9h seg39 seg38 com3 com2 com1 com0 co m3 com2 com1 com0 figure 3.11.7 lcd display data table 3.11.4 bits used for storing display data drive method bits 7/3 bits 6/2 bits 5/1 bits 4/0 1/4 duty com3 com2 com1 com0 1/3 duty ? com2 com1 com0 1/2 duty ? ? com1 com0 static ? ? ? com0 note: ? ? ? indicates bits that are not used for storing display data. initial value: 00h
tmp91cw40 2008-09-19 91cw40-139 (2) blanking when the bit in the lcdcr is cleared to 0, the com pins are driven to gnd level and the seg pins are placed in a high-impedance state. when the tmp91cw40 enters stop mode, th e bit is cleared to 0. after stop mode is exited, the bit need be set to 1 to display data on the lcd again. the following shows a programming example for fixing the seg pins to low level. ld (p2cr),0ffh ld (p1cr),0ffh ld (p0cr),0ffh ld (pbcr),0ffh ld (p2),00h ld (p1),00h ld (p0),00h ld (pb),00h ld (lcdsw1),00h ld (lcdsw2),00h ld (lcdsw3),00h ld (lcdsw4),00h ld (lcdcr),00h =0 ld (lcdcr2),20h =1, setting seg0 to seg 7 for low output note: during reset, com outputs are initialized to gnd level, but seg outputs (seg0 to seg7) and port/seg multiplexed pins (p0, p1, p2 and pb ports) are placed in a high-impedance state. therefore, if a considerably long external reset input occu rs, the lcd may not be displayed properly. configure ports for low output. configure port/seg multiplexed pins as port pins. the seg pins become ports fixed to low level.
tmp91cw40 2008-09-19 91cw40-140 3. 3.11 3.11.1 3.11.2 3.11.3 3.11.4 3.11.5 3.11.6 3.11.1 3.11.2 3.11.3 3.11.4 lcd driver control method (1) initial setting figure 3.11.7 shows the flowchart for initializing the lcd driver. set lcd drive method. (lcdcr) set frame frequency. (lcdcr) set voltage reducer frequency. (lcdcr) set lcd base clock. (syscr3) set p0, p1, p2 and pb ports. set lcdsw0 to lcdsw4. initialize display data area. enable lcd display (lcdcr=1). figure 3.11.7 initial setting of lcd driver
tmp91cw40 2008-09-19 91cw40-141 (2) storing display data display data is normally stored in the program memory (rom) as fixed data, and transferred to the display data area by load instructions. example 1: table 3.11.4 shows the display data for displaying the numbers corresponding to the bcd data stored at address 1400h in ram using a 1/4 duty lcd, with the com and seg pins connected to the lcd as shown in figure 3.11.8. ld xhl,(1400h) add xhl,table ld b,(xhl) ld (lcdreg0),b ret table: db 11011111b, 00000110b db 11100011b, 10100111b db 00110110b, 10110101b db 11110101b, 00010111b db 11110111b, 10110111b note: db = byte data definition instruction table 3.11.4 example of display data (1/4 duty) seg0 seg1 com0 com1 com2 com3 figure 3.11.8 example of com and seg pin connections no. display display data 11011111 0. 9 4 8 3 2 1 7 6 5 00000110 10110101 10110111 00110110 11110111 10100111 11100011 00010111 11110101 no. display display data
tmp91cw40 2008-09-19 91cw40-142 example 2: table 3.11.5 shows the display data for displaying the numbers shown in tab le 3.11.4 using a 1/2 duty lcd, with the com and seg pins connected to the lcd as shown in figure 3.11.9. com1 com0 seg3 seg0 seg2 seg1 figure 3.11.9 example of com and seg pin connections table 3.11.5 example of display data (1/2 duty) display data display data number lcdreg1 lcdreg0 number lcdreg1 lcdreg0 0. **01**11 **11**11 5 **11**10 **01**01 1 **00**10 **00**10 6 **11**11 **01**01 2 **10**01 **01**11 7 **01**10 **00**11 3 **10**10 **01**11 8 **11**11 **01**11 4 **11**10 **00**10 9 **11**10 **01**11
tmp91cw40 2008-09-19 91cw40-143 seg0 seg1 com0 com1 com2 com3 seg0 seg1 com0 dvcc com1 com2 com3 com0 -seg0 (selected) com2 -seg1 (not selected) display data area lcdreg0 1011 0101 dvss dvcc dvss dvcc dvss dvcc dvss dvcc dvss dvss dvcc vlcd -vlcd vlcd -vlcd seg0 seg1 seg2 com0 com1 com2 com0 -seg1 (selected) vlcd com1 -seg2 (not selected) display data area lcdreg0 *111 *010 seg1 seg0 seg2 com0 com1 com2 lcdreg1 **** **01 dvcc dvss dvcc dvss dvcc dvcc dvcc dvcc dvss dvss dvss dvss -vlcd vlcd -vlcd figure3.11.10 1/4 duty (1/3 bias) figure 3.11.11 1/3 duty (1/3 bias)
tmp91cw40 2008-09-19 91cw40-144 seg0 seg1 seg2 dvcc seg3 com0 com1 com0-seg1 (selected) com0-seg2 (not selected) -vlcd vlcd display data area lcdreg0 **01 **01 lcdreg1 **11 **10 -vlcd vlcd seg1 seg0 seg3 seg2 com0 com1 dvss dvcc dvcc dvcc dvcc dvcc dvss dvss dvss dvss dvss seg0 seg1 seg2 dvcc seg3 com0 - seg0 (selected) com0 - seg4 (not selected) vlcd display data area lcdreg0 ***0 ***1 lcdreg1 ***1 ***1 com0 seg7 seg1 seg5 seg2 seg4 seg3 seg0 seg6 lcdreg2 ***1 ***0 lcdreg3 ***0 ***1 dvss dvcc dvcc dvcc dvss dvss dvss vlcd -vlcd -vlcd figure 3.11.13 static figure 3.11.12 1/2 duty (1/2 bias)
tmp91cw40 2008-09-19 91cw40-145 3.12 real time clock (rtc) 3.12.1 function description for rtc 1) clock function (hour, minute, second) 2) calendar function (month and day, day of the week, and leap year) 3) 24 or 12-hour (am/pm) clock function 4) +/ 30 second adjustment function (by software) 5) alarm function (alarm output) 6) alarm interrupt generate 3.12.2 block diagram figure 3.12.1 rtc block diagram note 1: western calendar year column: this product uses only the final two digits of the year. therefore, the year following 99 is 00 years. in use, please take into account the first two digits when handling years in the western calendar. note 2: leap year: a leap year is divisible by 4, but the exception is any leap year which is divisible by 100; this is not considered a leap year. however, any year which is divisible by 400, is a leap year. this product does not take into account the above exceptions . since this product accounts only for leap years divisible by 4, please adjust the system for any problems. 32 khz clock divider comparator alarm register r/w control carry hold ( 1s ) a ddress bus clock alarm selector alarm intrtc 16 hz clock 1hzclock alarm internal data bus address d0~d7 wr rd adjust
tmp91cw40 2008-09-19 91cw40-146 3.12.3 control registers table 3.12.1 page 0 (clock function) registers symbol a ddress bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 function read/write secr 0320h 40 sec 20 sec 10 sec 8 sec 4 sec 2 sec 1 sec second column r/w minr 0321h 40 min 20 min 10 min 8 min 4 min 2 min 1 min minute column r/w hourr 0322h 20 hours/ pm/am 10 hours 8 hours 4 hours 2 hours 1 hour hour column r/w dayr 0323h w2 w1 w0 day of the week column r/w dater 0324h day 20 day 10 day 8 day 4 day 2 day 1 day column r/w monthr 0325h oct. aug. apr. feb. jan. month column r/w yearr 0326h year 80 year 40 year 20 year 10 year 8 year 4 year 2 year 1 year column (lower two columns) r/w pager 0327h interrupt enable a djustment function clock enable alarm enable page setting page register w, r/w restr 0328h 1hz enable 16hz enable clock reset alarm reset always write ?0? reset register w only note: when reading secr, minr, hourr, dayr, dater, monthr, yearr of page0, the current state is read. table 3.12.2 page1 (alarm function) registers symbol a ddress bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 function read/write secr 0320h r/w minr 0321h 40 min 20 min 10 min 8 min 4 min 2 min 1 min minute column r/w hourr 0322h 20 hours/ pm/am 10 hours 8 hours 4 hours 2 hours 1 hour hour column r/w dayr 0323h w2 w1 w0 day of the week column r/w dater 0324h day 20 day 10 day 8 day 4 day 2 day 1 day column r/w monthr 0325h 24/12 24-hour clock mode r/w yearr 0326h leap1 leap0 leap-year mode r/w pager 0327h interrupt enable a djustment function clock enable alarm enable page setting page register w, r/w restr 0328h 1hz enable 16hz enable clock reset alarm reset always write ?0? reset register w only note: when reading secr, minr, hourr, dayr, dater, monthr, yearr of page1, the current state is read.
tmp91cw40 2008-09-19 91cw40-147 3.12.4 detailed explanation of control register rtc is not initialized by system reset. therefore, all registers must be initialized at the beginning of the program. (1) second column register (for page0 only) 7 6 5 4 3 2 1 0 bit symbol se6 se5 se4 se3 se2 se1 se0 secr (0320h) read/write r/w reset state undefined function "0" is read. 40 sec. column 20 sec. column 10 sec. column 8 sec. column 4 sec. column 2 sec. column 1 sec. column 0 0 0 0 0 0 0 0 sec 0 0 0 0 0 0 1 1 sec 0 0 0 0 0 1 0 2 sec 0 0 0 0 0 1 1 3 sec 0 0 0 0 1 0 0 4 sec 0 0 0 0 1 0 1 5 sec 0 0 0 0 1 1 0 6 sec 0 0 0 0 1 1 1 7 sec 0 0 0 1 0 0 0 8 sec 0 0 0 1 0 0 1 9 sec 0 0 1 0 0 0 0 10 sec : 0 0 1 1 0 0 1 19 sec 0 1 0 0 0 0 0 20 sec : 0 1 0 1 0 0 1 29 sec 0 1 1 0 0 0 0 30 sec : 0 1 1 1 0 0 1 39 sec 1 0 0 0 0 0 0 40 sec : 1 0 0 1 0 0 1 49 sec 1 0 1 0 0 0 0 50 sec : 1 0 1 1 0 0 1 59 sec note: do not set data other than as shown above.
tmp91cw40 2008-09-19 91cw40-148 (2) minute column register (for page0/1) 7 6 5 4 3 2 1 0 bit symbol mi6 mi5 mi4 mi3 mi2 mi1 mi0 minr (0321h) read/write r/w reset state undefined function "0" is read. 40 min, column 20 min, column 10 min, column 8 min, column 4 min, column 2 min, column 1 min, column 0 0 0 0 0 0 0 0 min 0 0 0 0 0 0 1 1 min 0 0 0 0 0 1 0 2 min 0 0 0 0 0 1 1 3 min 0 0 0 0 1 0 0 4 min 0 0 0 0 1 0 1 5 min 0 0 0 0 1 1 0 6 min 0 0 0 0 1 1 1 7 min 0 0 0 1 0 0 0 8 min 0 0 0 1 0 0 1 9 min 0 0 1 0 0 0 0 10 min : 0 0 1 1 0 0 1 19 min 0 1 0 0 0 0 0 20 min : 0 1 0 1 0 0 1 29 min 0 1 1 0 0 0 0 30 min : 0 1 1 1 0 0 1 39 min 1 0 0 0 0 0 0 40 min : 1 0 0 1 0 0 1 49 min 1 0 1 0 0 0 0 50 min : 1 0 1 1 0 0 1 59 min note: do not set data other than as shown above.
tmp91cw40 2008-09-19 91cw40-149 (3) hour column register (for page0/1) 1. in case of 24-hour clock mode (monthr= ?1?) 7 6 5 4 3 2 1 0 bit symbol ho5 ho4 ho3 ho2 ho1 ho0 hourr (0322h) read/write r/w reset state undefined function "0" is read. 20 hour column 10 hour column 8 hour column 4 hour column 2 hour column 1 hour column 0 0 0 0 0 0 0 o?clock 0 0 0 0 0 1 1 o?clock 0 0 0 0 1 0 2 o?clock : 0 0 1 0 0 0 8 o?clock 0 0 1 0 0 1 9 o?clock 0 1 0 0 0 0 10 o?clock : 0 1 1 0 0 1 19 o?clock 1 0 0 0 0 0 20 o?clock : 1 0 0 0 1 1 23 o?clock note: do not set data other than as shown above. 2. in case of 12-hour clock mode (monthr= ?0?) 7 6 5 4 3 2 1 0 bit symbol ho5 ho4 ho3 ho2 ho1 ho0 hourr (0322h) read/write r/w reset state undefined function "0" is read. pm/am 10 hour column 8 hour column 4 hour column 2 hour column 1 hour column 0 0 0 0 0 0 0 o?clock (am) 0 0 0 0 0 1 1 o?clock 0 0 0 0 1 0 2 o?clock : 0 0 1 0 0 1 9 o?clock 0 1 0 0 0 0 10 o?clock 0 1 0 0 0 1 11 o?clock 1 0 0 0 0 0 0 o?clock (pm) 1 0 0 0 0 1 1 o?clock note: do not set data other than as shown above.
tmp91cw40 2008-09-19 91cw40-150 (4) day of the week column register (for page0/1) 7 6 5 4 3 2 1 0 bit symbol we2 we1 we0 dayr (0323h) read/write r / w reset state undefined function "0" is read. w2 w1 w0 0 0 0 sunday 0 0 1 monday 0 1 0 tuesday 0 1 1 wednesday 1 0 0 thursday 1 0 1 friday 1 1 0 saturday note: do not set data other than as shown above. (5) day column register (page0/1) 7 6 5 4 3 2 1 0 bit symbol da5 da4 da3 da2 da1 da0 dater (0324h) read/write r/w reset state undefined function "0" is read. day 20 day 10 day 8 day 4 day 2 day 1 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day : 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day : 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day : 1 0 1 0 0 1 29th day 1 1 0 0 0 0 30th day 1 1 0 0 0 1 31st day note1: do not set data other than as shown above. note2: do not set for non-existent days (e.g.: 30th feb)
tmp91cw40 2008-09-19 91cw40-151 (6) month column register (for page0 only) 7 6 5 4 3 2 1 0 bit symbol mo4 mo4 mo2 mo1 mo0 monthr (0325h) read/write r/w reset state undefined function "0" is read. 10 months 8 months 4 months 2 months 1 month 0 0 0 0 1 january 0 0 0 1 0 february 0 0 0 1 1 march 0 0 1 0 0 april 0 0 1 0 1 may 0 0 1 1 0 june 0 0 1 1 1 july 0 1 0 0 0 august 0 1 0 0 1 september 1 0 0 0 0 october 1 0 0 0 1 november 1 0 0 1 0 december note: do not set data other than as shown above. (7) select 24-hour clock or 12-h our clock (for page1 only) 7 6 5 4 3 2 1 0 bit symbol m o 0 monthr (0325h) read/write r / w reset state undefined function "0" is read. 0: 12-hour 1: 24-hour
tmp91cw40 2008-09-19 91cw40-152 (8) year column register (for page0 only) 7 6 5 4 3 2 1 0 bit symbol ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 yearr (0326h) read/write r/w reset state undefined function 80 years 40 years 20 years 10 years 8 years 4 years 2 years 1 year 0 0 0 0 0 0 0 0 00 years 0 0 0 0 0 0 0 1 01 years 0 0 0 0 0 0 1 0 02 years 0 0 0 0 0 0 1 1 03 years 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years : 1 0 0 1 1 0 0 1 99 years note: do not set data other than as shown above. (9) leap-year register (for page1 only) 7 6 5 4 3 2 1 0 bit symbol leap1 leap0 yearr (0326h) read/write r / w reset state undefined function "0" is read. 00: leap-year 01: one year after leap-year 10: two years after leap-year 11: three years after leap-year 0 0 current year is a leap-year 0 1 current year is the year following a leap year 1 0 current year is two years after a leap year 1 1 current year is three years after a leap year
tmp91cw40 2008-09-19 91cw40-153 (10) page register (for page0/1) 7 6 5 4 3 2 1 0 bit symbol intena adjust enatmr enaalm page read/write r/w w r/w r/w pager (0327h) reset state 0 undefined undefined undefined a read- modify- write operation cannot be performed function interrupt 0: disable 1: enable ?0? is read. 0: don?t care 1: adjust clock 0: disable 1: enable alarm 0: disable 1: enable ?0? is read. page selection note: please keep the setting order below of , and . set difference time for clock/alarm setting and interrupt setting. example: clock setting/alarm setting ld (pager), 0ch : clock, alarm enable ld (pager), 8ch : interrupt enable 0 select page0 page 1 select page1 0 don?t care adjust 1 adjust sec. counter. when this bit is set to ?1? the sec. counter becomes to ?0? when the value of the sec. counter is 0-29. when the value of the sec. counter is 30-59, the min. counter is carried and sec. counter becomes "0". output adjust signal during 1 cycle of f sys . after being adjusted once, adjust is released automatically. (page0 only) (11) reset register (for page0/1) 7 6 5 4 3 2 1 0 bit symbol dis1hz dis16hz rsttmr rstalm ? ? ? ? restr (0328h) read/write w reset state undefined a read- modify- write operation cannot be performed function 1hz 0: enable 1: disable 16hz 0: enable 1: disable 1:clock reset 1:alarm reset always write ?0? 0 unused rstalm 1 reset alarm register 0 unused rsttmr 1 reset clock register pager interrupt source signal 1 1 1 alarm 0 1 0 1hz 1 0 0 16hz others output ?0?
tmp91cw40 2008-09-19 91cw40-154 3.12.5 operational description (1) reading clock data 1. using 1hz interrupt 1hz interrupt and the count up of internal data synchronize. therefore, data can read correctly if reading da ta after 1hz interrupt occurred. 2. using two times reading there is a possibility of incorrect clock data reading when the internal counter carries over. to ensure correct data read ing, please read twice, as follows: figure 3.12.2 flowchart of clock data read start end pager = ?0? , select page0 read the clock data (1st) read the clock data (2nd) 1st data = 2nd data no yes
tmp91cw40 2008-09-19 91cw40-155 (2) writing clock data when a carry over occurs during a write operation, the data cannot be written correctly. please use the following method to ensure data is written correctly. 1. using 1hz interrupt 1hz interrupt and the count up of internal data synchronize. therefore, data can write correctly if writing data after 1hz interrupt occurred. 2. resets counter there are 15-stage counter inside the rtc, which generate a 1hz clock from 32.768 khz. the data is written after reset this counter. however, if clearing the counter, it is count ed up only first writing at half of the setting time, first writing only. therefore, if setting the clock counter correctly, after clearing the counter, set the 1hz-in terrupt to enable. and set the time after the first interrupt (occurs at 0.5hz) is occurred. start end pager = ?0? , select page0 restr = ?1? reset counter restr = ?0? enable 1hz interrupt first interrupts occu r ( after 0.5 sec ) no yes sets the time
tmp91cw40 2008-09-19 91cw40-156 3. disabling the clock a clock carry over is prohibited when ?0? is written to pager in order to prevent malfunction caused by the carry hold circuit. while the clock is prohibited, the carry hold circuit holds a one sec. carry signal from a divider. when the clock becomes enabled, the carry signal is output to the clock, the time is revised and operation continues. however, the clock is delayed when clock-disabled state continue s for one second or more. note that at this time system power is down while the clock is di sabled. in this case the clock is stopped and clock is delayed. figure 3.12.3 flowchart of clock disable start end disable the clock write the clock data enable the clock
tmp91cw40 2008-09-19 91cw40-157 3.12.6 explanation of the interrupt signal and alarm signal the alarm function used by setting the page1 register and outputting either of the following three signals from alarm pin by writing ?1? to pager. intrtc outputs a 1-shot pulse when the falling edge is detected. rtc is not initialized by reset. therefore, when the clock or alarm function is used, clear interrupt request flag in intc (interrupt controller). (1) when the alarm register and the clock correspond, output ?0?. (2) 1hz output clock. (3) 16hz output clock. (1) when the alarm register and the clock correspond, output ?0? when pager= ?1?, and the value of page0 clock corresponds with page1 alarm register output ?0? to alarm pin and generate intrtc. the methods for using the alarm are as follows: initialization of alarm is done by writing in ?1? to restr. all alarm settings become don?t care. in this case, th e alarm always corresponds with value of the clock, and if pager is ?1?, intrtc interrupt request is generated. setting alarm min., alarm hour, alarm date an d alarm day is done by writing data to the relevant page1 register. when all setting contents correspond, rtc generates an intrtc interrupt, if pager is ?1?. however, contents which have not been set up (don't care state) are always considered to correspond. contents which have already been set up, cannot be returned independently to the don?t care state. in this case, the alarm mu st be initialized and alarm register reset. the following is an example program for outputting an alarm from alarm -pin at noon (pm12:00) every day. ld (pager), 09h ; alarm disable, setting page1 ld (restr), d0h ; alarm initialize ld (dayr), 01h ; w0 ld (datar),01h 1 day ld (hourr), 12h ; setting 12 o?clock ld (minr), 00h ; setting 00 min ; set up time 31 s (note) ld (pager), 0ch ; alarm enable ( ld (pager), 8ch ; interrupt enable ) when the cpu is operating at high frequency oscillation, it may take a maximum of one clock at 32 khz (about 30us) for the time register setting to become valid. in the above example, it is necessary to set 31us of set up time between setting the time register and enabling the alarm register. note: this set up time is unnecessary wh en you use only internal interruption.
tmp91cw40 2008-09-19 91cw40-158 (2) with 1hz output clock rtc outputs a clock of 1hz to alarm pin by setting up pager= ?0?, restr= ?0?, = ?1?. rtc also generates an intrtc interrupt on the falling edge of the clock. (3) with 16hz output clock rtc outputs a clock of 16hz to alarm pin by setting up pager= ?0?, restr= ?1?, = ?0?. rtc also generates intrtc an interrupt on the falling edge of the clock.
tmp91cw40 2008-09-19 91cw40-159 3.13 melody/alarm generator (mld) the tmp91cw40 contains a melody/alarm ge nerator (mld) for generating melody and alarm waveforms. the mld can output either alarm or melody waveforms on the mldalm pin. the alarm generator uses a 15-bit free-running counter that can generate five types of interrupts at fixed intervals. the mld has the following features: ? melody generator based on the low-frequency clock (32.768 kh z), the melody generator can generate clock waveforms at frequencies from 4 hz to 5461 hz on the mldalm pin. by connecting an external speaker, the melody output function can easily be implemented. ? alarm generator the alarm generator can generate eight patterns of alarm waveforms at a frequency of 4096 hz modulated from the low-frequenc y clock (32.768 khz). these waveforms are output on the mldalm pin and can also be inverted by register programming. by connecting an external speaker, the alarm output function can easily be implemented. the free-running counter in the alarm generato r can be used to generate five types of interrupts (1 hz, 2 hz, 64 hz, 512 hz, 8192 hz) at fixed intervals.
tmp91cw40 2008-09-19 91cw40-160 3.13.1 block diagram figure 3.13.1 mld block diagram internal data bus melfh, melfl registers comparator (cp0) 12-bit counter (uc0) melfh < melon > low-frequency clock 32.768 khz stop & clear invert f/f melout clear reset [melody generator] edge detector intalm0 (8192 hz) intalm1 (512 hz) intalm2 (64 hz) intalm3 (2 hz) intalm4 (1 hz) 15-bit free-running counter (uc1) a lm registe r melout a lmout selector mldalm pin internal data bus melalmc [alarm generator] reset 4096 hz inverter melalmc melalmc a lmint intalmh (for halt wakeup) 8-bit counter ( uc2 ) alarm generator
tmp91cw40 2008-09-19 91cw40-161 3.13.2 sfrs alm register 7 6 5 4 3 2 1 0 bit symbol al8 al7 al6 al5 al4 al3 al2 al1 read/write r/w after reset 0 0 0 0 0 0 0 0 function alarm pattern melalmc register 7 6 5 4 3 2 1 0 bit symbol fc1 fc0 alminv ? ? ? ? melalm read/write r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function free-running counter control 00: hold 01: resume 10: clear & stop 11: clear & start alarm waveform inversion 1: invert always write 0. output waveform select 0: alarm 1: melody note 1: the bit in the melalmc register is always read as 0. note 2: to set bits other than in the melalmc regist er while the free-running counter is running, must be set to 01. melfl register 7 6 5 4 3 2 1 0 bit symbol ml7 ml6 ml5 ml4 ml3 ml2 ml1 ml0 read/write r/w after reset 0 0 0 0 0 0 0 0 function melody frequency (lower 8 bits) melfh register 7 6 5 4 3 2 1 0 bit symbol melon ml11 ml10 ml9 ml8 read/write r/w r/w after reset 0 0 0 0 0 function melody counter control 0: stop & clear 1: start melody frequency (upper 4 bits) almint register 7 6 5 4 3 2 1 0 bit symbol ? ialm4e ialm3e ialm2e ialm1e ialm0e read/write r/w r/w after reset 0 0 0 0 0 0 function always write 0. 1:intalm4 (1hz) enable 1:intalm3 (2hz) enable 1:intalm2 (64hz) enable 1:intalm1 (512hz) enable 1:intalm0 (8192hz) enable alm (0330h) melalmc (0331h) melfl (0332h) melfh (0333h) almint (0334h)
tmp91cw40 2008-09-19 91cw40-162 3.13.3 operational description 3.13.3.1 melody generator based on the low-frequenc y clock (32.768 khz), the melody generator can generate clock waveforms at frequencies from 4 hz to 5461 hz on the mldalm pin. by connecting an external speaker, the melody output function can easily be implemented. (how to use the melody generator) first, set the melalmc bit to 1 so that melody wavefo rms can be output on the mldalm pin. then, set the desired melody output frequency in 12 bits of the melfh and melfl register s. finally, setting the melfh bit to 1 starts the counter and melody waveform generation. how to calculate the melody output frequency and a programming example are shown below. (how to calculate the melody output frequency) at fs = 32.768 [khz] melody output frequency: f mld [hz] = 32768/(2 n + 4) melody setting value: n = (16384/f mld ) ? 2 (the value n should be a natural number from 1 to 4095 (001h to fffh); 0 is not allowed.) (programming example) generating the scale ?a? (440 hz) ld (melalmc), ?? xxxxx1b ; select melody waveforms ld (melfl), 23h ; n = 16384/440 ? 2 = 35.2 = 023h ld (melfh), 80h ; start waveform generation (basic scale setting table) scale frequency [hz] register value: n c 264 03ch d 297 035h e 330 030h f 352 02dh g 396 027h a 440 023h b 495 01fh c 528 01dh
tmp91cw40 2008-09-19 91cw40-163 3.13.3.2 alarm generator the alarm generator can generate eight pa tterns of alarm wavefo rms at a frequency of 4096 hz modulated from the low-frequency clock (32.768 khz). these waveforms are output on the mldalm pin and can also be inverted by register programming. by connecting an external speaker, the alarm output function can easily be implemented. the free-running counter in the alarm generato r can be used to generate five types of interrupts (1 hz, 2hz, 64 hz, 512 hz, 8192 hz) at fixed intervals. (how to use the alarm generator) first, set the melalmc bit to 0 so that alarm waveforms can be output on the mldalm pin, and set the melalmc field to 10 to clear the free-running counter. next the alarm patte rn must then be set on the 8-bit register of alm. if it is inverted ou tput-data, set melalmc as invert. finally set the melalmc to 11 to start the free-running counter. to stop the alarm output, write 00h to the alm register. alarm pattern setting values, a programming example and alarm pattern output waveforms are shown below. (alarm pattern setting table) alm register value alarm waveform 00h fixed to 0 01h al1 pattern 02h al2 pattern 04h al3 pattern 08h al4 pattern 10h al5 pattern 20h al6 pattern 40h al7 pattern 80h al8 pattern other undefined (don?t use) (programming example) generating the al2 pattern (31.25 ms/8 times/1 s) alarm ld (melalmc), 80h ; select output alarm waveform ; free-running counter clear ld (alm), 02h ; set al2 pattern ld (melalmc), c0h ; free-running counter start
tmp91cw40 2008-09-19 91cw40-164 (alarm pattern output waveforms: no inversion) a l1 pattern (continuous output) a l2 pattern (31.25 ms/8 times/1 s) 1 2 31.25 ms 1 s 1 500 ms 1 2 1 1 s 1 2 1 3 1 250 ms modulated frequency (4096 hz) 1 8 62.5 ms 62.5 ms 1 s 62.5 ms 1 2 62.5 ms a l3 pattern (500 ms/once) a l4 pattern (62.5 ms/twice/1 s) a l5 pattern (62.5 ms/3 times/1 s) a l6 pattern (62.5 ms/once) a l7 pattern (62.5 ms/twice) a l8 pattern (250 ms/once)
tmp91cw40 2008-09-19 91cw40-165 3.14 program patch logic the tmp91cw40 has a program patch logic, which enables the user to fix the program code in the internal rom. patch program code must be read into the internal ram from external memory during the startup routine. up to six 2-byte sequences (12 bytes in tota l) can be replaced with patch code. more significant code correction can be performed by replacing program code with single-byte instruction code which generates a software interrupt (swi) to make a branch to a specified location in the internal ram area. the program patch logic only compares addresses in the internal rom area; it cannot fix the program code in the internal i/o, internal ram and external rom areas. each of six banks is independently programmable, and functionally equivalent. in the following sections, any references to bank0 also apply to other banks. 3.14.1 block diagram figure 3.14.1 program patch logic diagram address bus romrd data bus romrd rom cpu data substitution registers (bank0) (romsub0l/h) match signal output enable a ddress compare registers (bank2) (romcmp20 to romcmp22) a ddress compare registers (bank3) (romcmp30 to romcmp32) a ddress compare registers (bank4) (romcmp40 to romcmp42) a ddress compare registers (bank5) (romcmp50 to romcmp52) a ddress compare registers (bank1) (romcmp10 to romcmp12) a ddress compare registers (bank0) (romcmp00 to romcmp02) output control block address compare block data substitution registers (bank1) (romsub1l/h) data substitution registers (bank2) (romsub2l/h) data substitution registers (bank3) (romsub3l/h) data substitution registers (bank4) (romsub4l/h) data substitution registers (bank5) (romsub5l/h)
tmp91cw40 2008-09-19 91cw40-166 3.14.2 sfrs the program patch logic consists of six banks (0 to 5). each bank is provided with three bytes of address compare regi sters (romcmpx0 to romcmpx2) and two bytes of patch code registers (romsubxl and romsubxh). bank0 address compare register 0 7 6 5 4 3 2 1 0 bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 D read/write w w after reset 0 0 0 0 0 0 0 0 function target rom address (lower 7 bits) write ?0?. bank0 address compare register 1 7 6 5 4 3 2 1 0 bit symbol romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (middle 8 bits) bank0 address compare register 2 7 6 5 4 3 2 1 0 bit symbol romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (upper 8 bits) romcmp00 (0400h) romcmp02 (0402h) romcmp01 (0401h) bank0 data substitution register l 7 6 5 4 3 2 1 0 bit symbol roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (lower 8 bits) bank0 data substitution register h 7 6 5 4 3 2 1 0 bit symbol roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (upper 8 bits) romsub0l (0404h) romsub0h (0405h) note 1: the romcmp00/01/02 and romsub0l/h regist ers do not support read-modify-write operation. note 2: the romcmp00/01/02 and romsub0l/h is read as undefined. note 3: write 0 to bit 0 of the romcmp00. figure 3.14.2 program patch logic registers (bank0)
tmp91cw40 2008-09-19 91cw40-167 bank1 address compare register 0 7 6 5 4 3 2 1 0 bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 D read/write w w after reset 0 0 0 0 0 0 0 0 function target rom address (lower 7 bits) write 0 bank1 address compare register 1 7 6 5 4 3 2 1 0 bit symbol romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (middle 8 bits) bank1 address compare register 2 7 6 5 4 3 2 1 0 bit symbol romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (upper 8 bits) romcmp10 (0408h) romcmp12 (040ah) romcmp11 (0409h) bank1 data substitution register l 7 6 5 4 3 2 1 0 bit symbol roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (lower 8 bits) bank1 data substitution register h 7 6 5 4 3 2 1 0 bit symbol roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (upper 8 bits) romsub1l (040ch) romsub1h (040dh) note 1: the romcmp10/11/12 and romsub1l/h registers do not support read-modify-write operation. note 2: the romcmp10/11/12 and romsub1l/h is read as undefined. note 3: write 0 to bit 0 of the romcmp10. figure 3.14.3 program patch logic registers (bank1)
tmp91cw40 2008-09-19 91cw40-168 bank2 address compare register 0 7 6 5 4 3 2 1 0 bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 D read/write w w after reset 0 0 0 0 0 0 0 0 function target rom address (lower 7 bits) write 0. bank2 address compare register 1 7 6 5 4 3 2 1 0 bit symbol romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (middle 8 bits) bank2 address compare register 2 7 6 5 4 3 2 1 0 bit symbol romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (upper 8 bits) romcmp20 (0410h) romcmp22 (0412h) romcmp21 (0411h) bank2 data substitution register l 7 6 5 4 3 2 1 0 bit symbol roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (lower 8 bits) bank 2 data substitution register h 7 6 5 4 3 2 1 0 bit symbol roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (upper 8 bits) romsub2l (0414h) romsub2h (0415h) note 1: the romcmp20/21/22 and romsub2l/h registers do not support read-modify-write operation. note 2: the romcmp20/21/22 and romsub2l/h is read as undefined. note 3: write 0 to bit 0 of the romcmp20. figure 3.14.4 program patch logic registers (bank2)
tmp91cw40 2008-09-19 91cw40-169 bank3 address compare register 0 7 6 5 4 3 2 1 0 bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 read/write w w after reset 0 0 0 0 0 0 0 function target rom address (lower 7 bits) write 0. bank3 address compare register 1 7 6 5 4 3 2 1 0 bit symbol romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (middle 8 bits) bank3 address compare register 2 7 6 5 4 3 2 1 0 bit symbol romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (upper 8 bits) romcmp30 (0418h) romcmp32 (041ah) romcmp31 (0419h) bank3 data substitution register l 7 6 5 4 3 2 1 0 bit symbol roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (lower 8 bits) bank3 data substitution register h 7 6 5 4 3 2 1 0 bit symbol roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (upper 8 bits) romsub3l (041ch) romsub3h (041dh) note 1: the romcmp30/31/32 and romsub3l/h registers do not support read-modify-write operation. note 2: the romcmp30/31/32 and romsub3l/h is read as undefined. note 3: write 0 to bit 0 of the romcmp30. figure 3.14.5 program patch logic registers (bank3)
tmp91cw40 2008-09-19 91cw40-170 bank4 address compare register 0 7 6 5 4 3 2 1 0 bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 read/write w w after reset 0 0 0 0 0 0 0 0 function target rom address (lower 7 bits) write 0. bank4 address compare register 1 7 6 5 4 3 2 1 0 bit symbol romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (middle 8 bits) bank 4 address compare register 2 7 6 5 4 3 2 1 0 bit symbol romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (upper 8 bits) romcmp40 (0420h) romcmp42 (0422h) romcmp41 (0421h) bank4 data substitution register l 7 6 5 4 3 2 1 0 bit symbol roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (lower 8 bits) bank4 data substitution register h 7 6 5 4 3 2 1 0 bit symbol roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (upper 8 bits) romsub4l (0424h) romsub4h (0425h) note 1: the romcmp40/41/42 and romsub4l/h registers do not support read-modify-write operation. note 2: the romcmp40/41/42 and romsub4l/h is read as undefined. note 3: write 0 to bit 0 of the romcmp40. figure 3.14.6 program patch logic registers (bank4)
tmp91cw40 2008-09-19 91cw40-171 bank5 address compare register 0 7 6 5 4 3 2 1 0 bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 read/write w w after reset 0 0 0 0 0 0 0 function target rom address (lower 7 bits) write 0. bank5 address compare register 1 7 6 5 4 3 2 1 0 bit symbol romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (middle 8 bits) bank5 address compare register 2 7 6 5 4 3 2 1 0 bit symbol romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 read/write w after reset 0 0 0 0 0 0 0 0 function target rom address (upper 8 bits) romcmp50 (0428h) romcmp52 (042ah) romcmp51 (0429h) bank5 data substitution register l 7 6 5 4 3 2 1 0 bit symbol roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (lower 8 bits) bank5 data substitution register h 7 6 5 4 3 2 1 0 bit symbol roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 read/write w after reset 0 0 0 0 0 0 0 0 function patch code (upper 8 bits) romsub5l (042ch) romsub5h (042dh) note 1: the romcmp50/51/52 and romsub5l/h registers do not support read-modify-write operation. note 2: the romcmp50/51/52 and romsub5l/h is read as undefined. note 3: write 0 to bit 0 of the romcmp50. figure 3.14.7 program patch logic registers (bank5)
tmp91cw40 2008-09-19 91cw40-172 3.14.3 operational description (1) replacing data two consecutive bytes of data can be replac ed for each bank. a two-byte sequence to be replaced must start at an even address. if only a single byte at an even or odd address need be replaced, set the current masked rom data in the other byte. correction procedure: load the address compare registers (romcmp00 to romcmp02) with the target address where rom data need be replaced. store 2-byte patch code in the rmosub0l and romsub0h registers. when the cpu address matches the value stored in the romcmp00 to romcmp02 registers, the program patch logic disables rd output to the masked rom and drives out the code stored in the romsub0l and romsub0h to the internal bus. the cpu thus fetches the patch code. the following shows some examples: examples: a. replacing 00h at address ff1230h with aah 7 6 5 4 3210 romcmp00 0 0 1 1 0000 store 30 in address compare register 0 for bank0. romcmp01 0 0 0 1 0010 store 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1111 store ff in address compare register 2 for bank0. romsub0l 1 0 1 0 1010 store aa in data substitution register l for bank0. romsub0h 0 0 0 1 0001 store 11 in data substitution register h for bank0. internal i/o internal ram internal area (access not allowed) internal rom 00h 11h vector table ff1230h ff1231h replace with aah replace with 11h (same as current value) ffffffh a fe0000h 001000h 000000h figure 3.14.8 example patch code implementation
tmp91cw40 2008-09-19 91cw40-173 b. replacing 33h at address ff1233h with bbh 7 6 5 4 3210 romcmp00 0 0 1 1 0010 store 32 in address compare register 0 for bank0. romcmp01 0 0 0 1 0010 store 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1111 store ff in address compare register 2 for bank0. romsub0l 0 0 1 0 0010 store 22 in data substitution register l for bank0. romsub0h 1 0 1 1 1011 store bb in data substitution register h for bank0. internal i/o internal ram internal area (access not allowed ) internal rom 22h 33h vector table ff1232h ff1233h replace with bbh replace with 22h (same as current value) ffffffh b fe0000h 001000h 000000h figure 3.14.9 example patch code implementation c. replacing 44h at address ff1234h with cch and 55h at address ff1235h with ddh 7 6 5 4 3210 romcmp00 0 0 1 1 0100 store 34 in address compare register 0 for bank0. romcmp01 0 0 0 1 0010 store 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1111 store ff in address compare register 2 for bank0. romsub0l 1 1 0 0 1100 store cc in data substitution register l for bank0. romsub0h 1 1 0 1 1101 store dd in data substitution register h for bank0. internal i/o internal ram internal area (access not allowed) internal rom 44h 55h vector table ff1234h ff1235h replace with cch ffffffh c fe0000h 001000h 000000h replace with ddh figure 3.14.10 example patch code implementation
tmp91cw40 2008-09-19 91cw40-174 d. replacing 77h at address ff1237h with eeh and 88h at address ff1238h with ffh (requiring two banks) 7 6 5 4 3210 romcmp00 0 0 1 1 0110 store 36 in address compare register 0 for bank0. romcmp01 0 0 0 1 0010 store 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1111 store ff in address compare register 2 for bank0. romsub0l 0 1 1 0 0110 store 66 in data substitution register l for bank0. romsub0h 1 1 1 0 1110 store ee in data substitution register h for bank0. romcmp10 0 0 1 1 1000 store 38 in address compare register 0 for bank1. romcmp11 0 0 0 1 0010 store 12 in address compare register 1 for bank1. romcmp12 1 1 1 1 1111 store ff in address compare register 2 for bank1. romsub1l 1 1 1 1 1111 store ff in data substitution register l for bank1. romsub1h 1 0 0 1 1001 store 99 in data substitution register h for bank1. internal i/o internal ram external area (access not allowed) external rom 66h 77h 88h vector table 99h ff1236h ff1237h ff1238h ff1239h replace with 66h (same as current value) replace with eeh replace with ffh replace with 99h (same as current value) ffffffh d fe0000h 001000h 000000h figure 3.14.11 example patch code implementation
tmp91cw40 2008-09-19 91cw40-175 (2) using an interrupt to cause a branch a wider range of program code can also be fixed using a software interrupt (swi). with patch code loaded into the internal ram, the program patch logic can be used to replace program code at a specified address with a single-byte swi instruction, which causes a branch to the patch program. note that this method can only be used if the original masked rom has been developed with internal ram addresses specified as swi vector addresses. correction procedure: load the address compare registers (romcmp00 to romcmp02) with the start address of the program code that is to be fixed. if it is an even address, store an swi instruction code (e.g., swi: f9h) in the romsub0l. if the start address is an odd address, store an swi instruction code in the romsub0h and the current rom data at the preceding even address in the romsub0l. when the cpu address matches the value stored in the romcmp00 to romcmp02 registers, the program patch logic disables rd output to the masked rom and drives out the swi instruction code to the internal bus. upon fetching the swi code, the cpu makes a branch to the internal ram area to execute the preloaded code. at the end of the patch program executed from the internal ram, the cpu directly rewrites the saved pc value so that it points to the address following the patch code, and then executes a reti. the following shows an example: example: fixing a program within a range from ff5000h to ff507f before developing the original masked rom, set the swi1 vector reference address to address 001500h (in the internal ram area). use the startup routine to load the patch code to the internal ram (001500h to 0015efh). store the start address (ff5000h) of the rom area to be fixed in the romcmp00 to romcmp02. store the swi1 instruction code (f9h) in the romsub0l and the current data at ff5001h (aah) in the romsub0h. when the cpu address matches the value stored in the romcmp00 to romcmp02, the program patch logic replaces the rom-bas ed code at ff5000h with f9h. the cpu then executes the swi1 instruction, which causes a branch to 001500h in the internal ram area. after executing the patch program the cpu finally rewrites the saved pc value to ff5080h and executes a reti.
tmp91cw40 2008-09-19 91cw40-176 internal i/o internal ram internal area (access not allowed) internal rom 55h aah sw1 vector ff507fh ff5080h replace with f9h (swi1instruction code) replace with aah (same as current value) bug area fe0000h 001000h 000000h ff5001h ff5000h ffff04h ffff07h ffff00h vector table 001500h 002000h ? ? ? ? sw1 jump return int 001500h 0015efh 001500h 0015efh patch code ? ? ? ? stack rewrite reti patch code ~ figure 3.14.12 example patch code implementation
tmp91cw40 2008-09-19 91cw40-177 3.15 key-on wakeup in addition to the int0 and int1 interru pt source pins, the tmp91cw40 has four interrupt channels that enable the pressing of a key to terminate halt mode, called key-on wakeup interrupts (kwi). figure 3.15.1 shows a block diagram of the kwi circuit. 3.15.1 block diagram edge select register kwicr < kwi3edge > to < kw i0edge > internal data bus kw i3 (p53) kw i2 (p52) kw i1 (p51) kw i0 (p50) internal data bus enable register kwien < kwi3en > to < kw i0en > iint1 select rising or falling edge select rising or falling edge select rising or falling edge select rising or falling edge figure 3.15.1 kwi block diagram
tmp91cw40 2008-09-19 91cw40-178 3.15.2 sfrs key-on wakeup enable register 7 6 5 4 3 2 1 0 bit symbol kwi3en kwi2en kwi1en kwi0en read/write w after reset 0 0 0 0 function kwi3 interrupt input 0: disable 1: enable kwi2 interrupt input 0: disable 1: enable kwi1 interrupt input 0: disable 1: enable kwi0 interrupt input 0: disable 1: enable key-on wakeup control register 7 6 5 4 3 2 1 0 bit symbol kwi3edge kwi2edge kwi1edge kwi0edge read/write w after reset 0 0 0 0 function kwi3 edge polarity 0: rising 1: falling kwi2 edge polarity 0: rising 1: falling kwi1 edge polarity 0: rising 1: falling kwi0 edge polarity 0: rising 1: falling note: the kwien and kwicr registers do not support read-modify-write operation. figure 3.15.2 key-on wakeup registers 3.15.3 control the p50 to p53 pins function as kwi0 to kwi3 when the corresponding bits () in the kwien register are set. the mcu accepts kwi0 to kwi3 inputs as int1. the kwi0 to kwi3 pins can be used as external interrupt sources by setting an interrupt priority level in the bits of the inte1alm0 register. example: to detect a falling edge on key-on wakeup channel 0 to generate an interrupt, configure registers in the following sequence: kwicr - - - - - - - 1 select falling-edge detection for key-on wakeup channel 0. kwien - - - - - - - 1 enable key-on wakeup channel 0. inte1alm0 x 1 0 0 x --- enable int1 and set its priority level to 4. x: don?t care, ? : no change kwien (03a0h) kwicr (03a1h)
tmp91cw40 2008-09-19 91cw40-179 3.16 analog-to-digital converter (ad converter) the tmp91cw40 has a 10-bit successive-appro ximation analog-to-digital converter (ad converter) having 4 channels of analog inputs. figure 3.16.1 shows a block diagram of the ad converter. the four analog input channels (an0 to an3) can be used as gen e ral-purpose digital inputs (port 5) if not needed as analog channels. note: ensure that the ad converter has halted before executi ng the halt instruction to place the tmp91cw40 in idle2, idle1 or stop mode to reduce power supply current. otherwise, the tmp91cw40 might go into a standby mode while the internal analog comparator is still active. figure 3.16.1 ad converter block diagram interrupt request intad an3/ adtrg (p53) an2 (p52) an1 (p51) an0 (p50) comparator vrefh vrefl internal data bus multiplexer sample- and-hold a d mode control register 1 a dmod1 scan repeat interrupt busy end start + ? internal data bus internal data bus channel selector ad mode control register 0 admod0 adtrg ad conversion result register adreg04l to 37l adreg04h to 37h da converter ad converter control circuit
tmp91cw40 2008-09-19 91cw40-180 3.16.1 control registers the ad converter is controlled by the ad mode control registers (admod0 and admod1). ad conversion results are stored in four conversion result high/low register pairs (adreg04h/l, adreg15h/l, adreg26h/l and adreg37h/l). figure 3.16.2 to figure 3.16.5 show the registers related to the ad converter. ad mode control register 0 7 6 5 4 3 2 1 0 bit symbol eocf adbf ? ? itm0 repeat scan ads read/write r r/w after reset 0 0 0 0 0 0 0 0 function ad conversion end flag 0: converting 1: completed ad conversion busy flag 0: idle 1: converting always write 0. always write 0. interrupt in fixed-channel continuous conversion mode 0: after each conversion 1: after every four conversions continuous conversion mode 0: single 1: continuous channel scan mode 0: fixed- channel 1: channel scan ad conversion start 0: don?t care 1: start this bit is always read as 0. ad conversion start 0 don?t care 1 start ad conversion. note: this bit is always read as 0. channel scan mode 0 fixed-channel mode 1 channel scan mode continuous conversion mode 0 single conversion mode 1 continuous conversion mode interrupt in fixed-channel continuous conversion mode fixed-channel conti nuous conversion mode = 0, = 1 0 generate an interrupt after each conversion. 1 generate an interrupt after every four conversions. ad conversion busy flag 0 idle 1 converting ad conversion end flag 0 before or during conversion 1 completed figure 3.16.2 ad conver sion registers (1) admod0 (02b0h) read-modify- write instructions cannot be used.
tmp91cw40 2008-09-19 91cw40-181 ad mode control register 1 7 6 5 4 3 2 1 0 bit symbol vrefon i2ad adtrge adch2 adch1 adch0 read/write r/w r/w r/w after reset 0 0 0 0 0 0 function vref control 0: off 1: on adc operation in idle2 mode 0: stop 1: operation external conversion trigger 0: disable 1: enable analog input channel select analog input channel select 0 fixed-channel mode 1 channel scan mode 000 an0 an0 001 an1 an0 an1 010 an2 an0 an1 an2 011 (note) an3 an0 an1 an2 an3 100 101 110 111 must not be selected. ad conversion start by external trigger ( adtrg input) 0 disable 1 enable ad converter operation in idle2 mode 0 stop 1 operation reference voltage for ad converter 0off 1on set to 1 before setting admod0 to 1 to start a conversion. note: the an3 pin is shared with the adtrg pin. therefore, when the exte rnal conversion trigger input ( adtrg ) is enabled (i.e., admod1 = 1 ), the field must not be set to 011. figure 3.16.3 ad conv ersion registers (2) admod1 (02b1h)
tmp91cw40 2008-09-19 91cw40-182 ad conversion result low register 0/4 7 6 5 4 3 2 1 0 bit symbol adr01 adr00 adr0rf read/write r r after reset undefined 0 function lower 2 bits of an ad conversion result conversion result store flag 1: stored ad conversion result high register 0/4 7 6 5 4 3 2 1 0 bit symbol adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 read/write r after reset undefined function upper 8 bits of an ad conversion result ad conversion result low register 1/5 7 6 5 4 3 2 1 0 bit symbol adr11 adr10 adr1rf read/write r r after reset undefined 0 function lower 2 bits of an ad conversion result conversion result store flag 1: stored ad conversion result high register1/5 7 6 5 4 3 2 1 0 bit symbol adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 read/write r after reset undefined function upper 8 bits of an ad conversion result 9 8 76543210 channel x conversion result bits 7 6 543210 76543 2 1 0 figure 3.16.4 ad conver sion registers (3) adreg04l (02a0h) adreg04h (02a1h) adreg15l (02a2h) adreg15h (02a3h) a dregxh adregxl ? bits 5 to 1 are always read as 1. ? bit0 (), when set, indicates that the conversion result has been stored in the adregxh/l register pair. this bit is cleared when either the adregxh o r adregxl is read.
tmp91cw40 2008-09-19 91cw40-183 ad conversion result low register 2/6 7 6 5 4 3 2 1 0 bit symbol adr21 adr20 adr2rf read/write r r after reset undefined 0 function lower 2 bits of an ad conversion result conversion result store flag 1: stored ad conversion result high register 2/6 7 6 5 4 3 2 1 0 bit symbol adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r after reset undefined function upper 8 bits of an ad conversion result ad conversion result low register 3/7 7 6 5 4 3 2 1 0 bit symbol adr31 adr30 adr3rf read/write r r after reset undefined 0 function lower 2 bits of an ad conversion result conversion result store flag 1: stored ad conversion result high register 3/7 7 6 5 4 3 2 1 0 bit symbol adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 read/write r after reset undefined function upper 8 bits of an ad conversion result 9 8 76543210 channel x conversion result bits 7 6 543210 76543 2 1 0 figure 3.16.5 ad conver sion registers (4) adreg26l (02a4h) adreg26h (02a5h) adreg37l (02a6h) adreg37h (02a7h) a dregxh adregxl ? bits 5 to 1 are always read as 1. ? bit0 (), when set, indicates that the conversion result has been stored in the adregxh/l register pair. this bit is cleared when either the adregxh o r adregxl is read.
tmp91cw40 2008-09-19 91cw40-184 3.16.2 operational description (1) analog reference voltages the vrefh and vrefl pins provide the reference voltages for the ad converter. these pins establish the full-scale range for the internal resistor string, which divides the range into 1024 steps. the digital result of the conversion is derived by comparing the sampled analog input voltage to the resistor string voltages. clearing the bit in the admod1 turns off the switch between vrefh and vrefl. once is cleared, the internal reference voltage requires a recovery time of 3 s to stabilize after is set to 1. this recovery time is independent of the system clock frequency. the bit in the admod0 must then be set to initiate a conversion. (2) selecting an analog input channel(s) there are two basic conversion modes: fixed-channel mode and channel scan mode. the bit in the admod0 affects the conversion channel(s) that will be selected as follows: ? fixed-channel mode (admod0 = 0) in this mode, the ad converter runs conversions on a single analog input channel selected from an0 to an3 via the admod1 bits. ? channel scan mode (admod0 = 1) in this mode, the ad converter runs conversions on sequential channels selected from four patterns via th e admod1 bits. table 3.16.1 shows how analog input channels are selected in each conversion mode. aft er a reset, ad mod0 is initialized to 0 and admod1 to 000, selecting the an0 pin as the conversion channel in channel-fixed mode. the an0 to an3 pins can be used as general-purpose input ports when not used as analog input channels. table 3.16.1 analog input channel selection fixed-channel mode = 0 channel scan mode = 1 000 an0 an0 001 an1 an0 an1 010 an2 an0 an1 an2 011 an3 an0 an1 an2 an3 100 must not be selected. 101 110 111
tmp91cw40 2008-09-19 91cw40-185 (3) starting an ad conversion the ad converter starts a conversion when admod0 is set to 1, or when a falling edge is applied to the adtrg pin with admod1 set to 1. when a conversion starts, the ad conversion busy flag (admod0) is set to 1. setting the bit to 1 causes the ad converter to abort any ongoing conversion and start sampling the selected channel to begin a new conversion. the conversion result store flag (adregxl) indicates whether or not the result register contains a valid digital result at that point. in external conversion trigger mode, a falling edge on the adtrg pin is ignored while a conversion is in progress. (4) conversion modes and conversion end interrupts the ad converter supports the following four conversion modes: ? fixed-channel single conversion mode ? channel scan conversion mode ? fixed-channel continuous conversion mode ? channel scan continuous conversion mode the conversion mode is selected by the and bits in the admod0. at the end of the conversion process, an intad interrupt is generated and admod0 is set to 1. a. fixed-channel single conversion mode this mode is selected by programming the and bits in the admod0 to 00. in fixed-channel single conversion mode, the ad converter performs a single conversion on a single selected channel. when the conversion is completed, admod0 is set to 1, admod0 is cleared to 0, and an intad interrupt is generated. b. channel scan single conversion mode this mode is selected by programming the and bits in the admod0 to 01. in channel scan single conversion mode, the ad converter performs a single conversion on each of a selected group of channels. when the single conversion sequence is completed, admod0 is set to 1, admod0 is cleared to 0, and an intad interrupt is generated.
tmp91cw40 2008-09-19 91cw40-186 c. fixed-channel continuous conversion mode this mode is selected by programming the and bits in the admod0 to 10. in fixed-channel contin uous conversion mode, the ad converter repeatedly converts a single selected channel. when the conversion process is completed, admod0 is set to 1. admod0 is not cleared to 0 and remains set. the intad interrupt generation timing ca n be selected by admod0. when =0, an interrupt is generated afte r each conversion. when =1, an interrupt is generated after every four conversions. d. channel scan conti nuous conversion mode this mode is selected by programming the and bits in the admod0 to 11. in channel scan continuous conversion mode, the ad converter repeatedly converts a selected group of channels. when a single conversion sequence is completed, admod0 is set to 1 and an intad interrupt is generated. admod0 is not cleared to 0 and remains set. in fixed-channel continuous conversion and channel scan continuous conversion modes, setting admod0 to 0 stops the conversion sequence after the ongoing conversion is completed and clears admod0 to 0. when admod1 = 0, putting the tmp91cw40 in any halt mode (idle2, idle1, or stop) causes the ad converter to be immediately disabled, even if a conversion is in progress. once the tmp91cw40 exits the halt mode, the ad converter restarts a conversion sequence in fixed-channel continuous conversion or channel scan continuous conversion mode, bu t remains inactive in fixed-channel single conversion or channel scan single conversion mode. table 3.16.2 summarizes interrupt request generation in each of the conversion modes. table 3.16.2 interrupt request gene ration in each ad conversion mode admod0 mode interrupt request generation fixed-channel single conversion mode after each conversion x 0 0 channel scan single conversion mode after each scan conversion sequence x 0 1 after each conversion 0 fixed-channel continuous conversion mode after every four conversions 1 1 0 channel scan continuous conversion mode after each scan conversion sequence x 1 1 x: don?t care
tmp91cw40 2008-09-19 91cw40-187 (5) conversion time the conversion process requires 84 conversion states per channel (6.2 s when f fph = 27 mhz). (6) storing and reading ad conversion results ad conversion results are stored in the conversion result high/low register pairs (adreg04h/l to adreg37h/l). these registers are read only. in fixed-channel continuous conversion mode with set to 1, conversion data goes into the adreg04h/l to adreg37h/l sequentially. in other modes, conversion results in channels an0, an1, an2 an d an3 are stored in the adreg04h/l, adreg15h/l, adreg26h/l and adreg37h/l respectively. table 3.16.3 shows the relationships between the analog input channels and the ad conversion result registers. table 3.16.3 relationships betwee n analog input channels and ad conversion result registers ad conversion result registers analog input channel (port 5) other modes fixed-channel continuous conversion mode (=1) an0 adreg04h/l an1 adreg15h/l an2 adreg26h/l an3 adreg37h/l bit0 () in each adregxl register indicates whether or not the conversion result register has been read. this bit is set when the conversion result is loaded into the adregxh/adregxl register pair, and cleared when either the adregxh or adregxl is read. reading the conversion result also clears the conversion end flag (admod0). a dreg04h/l a dreg15h/l a dreg26h/l a dreg37h/l
tmp91cw40 2008-09-19 91cw40-188 programming examples: a. converting the analog inpu t voltage on the an3 pin to a digital value and storing the converted value in a memory location (1800 h) using the ad interrupt (intad) service routine settings in the main routine 7 6 5 4 3 2 1 0 inte0ad x 1 0 0 ? ? ? ? enable intad and set its priority level to 4. admod1 1 1 x x 0 0 1 1 select an3 as the analog input channel. admod0 x x 0 0 0 0 0 1 start conversion in fi xed-channel single conversion mode. interrupt routine processing example wa adreg37 load the conversion result into 16-bit general-purpose register wa from adreg37l and adreg37h. wa > > 6 shift the contents of wa 6 bits to the right, padding 0s to the vacated high-order bits. (1800h) wa store the contents of wa at address 1800h. b. converting the analog input voltages on the an0 to an2 pins sequentially in channel scan continuous conversion mode inte0ad x 0 0 0 ? ? ? ? disable intad. admod1 1 1 x x 0 0 1 0 select an0 to an2 as the analog input channels. admod0 x x 0 0 0 1 1 1 start conversion in c hannel scan continuous conversion mode. x: don?t care, ? : no change
tmp91cw40 2008-09-19 91cw40-189 3.17 watchdog timer (wdt) the tmp91cw40 contains a watchdog timer. the watchdog timer is used to regain control of the system in the event of software or system lockups due to spurious noise, etc. when a watchdog timer time-out occurs, the watchdog timer generates a nonmaskable interrupt to the cpu. connecting the watchdog timer output to the rese t pin internally enable s a forced reset. (the level of external reset pin is not changed.) 3.17.1 configuration figure 3.17.1 shows a block diagram of the watchdog timer. figure 3.17.1 watchdog timer block diagram noise: careful consideration must be gi ven in designing a system because the wa tchdog timer may not be able to realize its full functionality due to external noise, etc. internal reset wdmod wdmod reset watchdog timer control register wdcr q r s 2 21 internal reset wdmod interrupt request intwd f sys (f fph /2) selector 2 19 2 17 2 15 internal data bus write of b1h write of 4eh reset pin reset control 22-stage binary counter
tmp91cw40 2008-09-19 91cw40-190 3.17.2 operational description the watchdog timer is a kind of timer that generates an interrupt request if it times out. the watchdog timer allows the user to program the time-out period in the field in the wdmod register. while the watchdog timer is enabled, it can be cleared to 0 by software at any time by wr iting a special clear code. if the cpu loses control of the system and fails to execute an instruction to clear the counter before it reaches the time-out time due to noise or other causes, the watchdog timer generates an intwd interrupt. in response to the interru pt, the cpu jumps to a system recovery routine to regain control of the system. the watchdog timer begins count ing immediately after reset. the watchdog timer halted in idle1 or stop mode. in idle2 mode, the bit in the wdmod determines whether or not the watchdog timer is disabled. program the bit as necessary before placing the tmp91cw40 in idle2 mode. the watchdog timer contains a 22-stage bina ry counter clocked by the system clock f sys. the binary counter can output f sys /2 15 , f sys /2 17 , f sys /2 19 or f sys /2 21 , which is selected by wdmod. when the watchdog timer counter overflows, a watchdog timer interrupt is generated as shown in figure 3.17.2. figure 3.17.2 normal operation it is also poss ibl e to reset the system when the watchdog timer counter overflows. in this case, a reset operation takes 22 to 29 states (1.63 to 2.15 s when fc = 27 mhz) as shown in figure 3.17.3. after a reset, the system clock f sys (1 cycle = 1 state) is fc/2. figure 3.17.3 reset operation 0 wdt interrupt wdt clear (via software) write clear code wdt counter n overflow overflow wdt counter n wdt interrupt 22 to 29 states (1.63 to 2.15 s when fc = 27mhz) internal reset
tmp91cw40 2008-09-19 91cw40-191 3.17.3 control registers the watchdog timer is controlled by two registers called wdmod and wdcr. (1) watchdog timer mode register (wdmod) a. time-out period this 2-bit field determines the duration of the watchdog timer time-out interval. a reset initializes wdmod to 00. figure 3.17.4 shows possible time-out per iods. b. watchdog ti mer enable/disable control a reset initializes wdmod to 1, enabling the watchdog timer. to disable the watchdog timer, the clearing of the bit must be followed by a write of a special key code (b1h) to the wdcr register. this protects the watchdog timer from being inadvertently disabled. to re-enable the watchdog timer, it is only necessary to set the bit to 1. c. system reset this bit is used to program the watchdog timer to generate a system reset when it reaches the time-out time. a reset initializes wdmod = 0 so that a time-out does not cause a system reset. (2) watchdog timer control register (wdcr) this register is used to disable the watchdog timer and to clear the watchdog timer?s binary counter. ? disabling the watchdog timer the watchdog timer can be disabled by clearing wdmod to 0 and then writing the disable code (b1h) to the wdcr register. wdcr 0 1 0 0 1 1 1 0 write the clear code (4eh). wdmod 0 ? ? xx ? ? 0 clear to 0. wdcr 1 0 1 1 0 0 0 1 write the disable code (b1h). ? enabling the watchdog timer the watchdog timer can be enabled by setting wdmod to 1. ? clearing the watchdog timer counter writing the clear code (4eh) to the wdcr register clears the binary counter and causes the counter to start counting again. wdcr 0 1 0 0 1 1 1 0 write the clear code (4eh). note1: if the disable control is used, set the disable c ode (b1h) to wdcr after writing the clear code (4eh) once. (please refer to setting example.) note2: if the watchdog timer setting is changed, c hange setting after setting to disable condition once.
tmp91cw40 2008-09-19 91cw40-192 7 6 5 4 3 2 1 0 bit symbol wdte wdtp1 wdtp0 ? ? i2wdt rescr ? read/write r/w r/w r/w r/w r/w r/w after reset 1 0 0 0 0 0 0 0 function wdt control 0: disable 1: enable select detecting time 00: 2 15 /f sys 01: 2 17 /f sys 10: 2 19 /f sys 11: 2 21 /f sys always write 0. always write 0. idle2 0: stop 1: operate 1:internally connects wdt out to the reset pin always write 0 . figure 3.17.4 watchdog timer mode register 7 6 5 4 3 2 1 0 bit symbol ? read/write w after reset ? function b1h: wdt disable code 4eh: wdt clear code b1h disable code 4eh clear code other ? figure 3.17.5 watchdog timer control register 0 ? 1 internally route the wdt time-out signal to the system reset. 0 stop 1 operation watchdog timer detection time wdmod system clock syscr1 00 01 10 11 1 (fs) 2.0 s 8.0 s 32.0 s 128.0 s 0 (fc) 2.43 ms 9.71 ms 38.84 ms 155.34 ms 0 disable 1 enable watchdog timer enable wdmod ( 0300h ) idle2 control watchdog timer detection time at fc = 27 mhz, fs = 32.768 khz special code wdcr ( 0301h ) read-modify- write instructions cannot be used. watchdog timer out control
tmp91cw40 2008-09-19 91cw40-193 4. electrical characteristics 4.1 absolute maximum ratings parameter symbol rating unit supply voltage vcc ?0.5 to 4.0 v input voltage vin ?0.5 to vcc + 0.5 v output current (per pin) iol (other than port8) 2 ma iol (port8) 20 ma output current (per pin) ioh ?2 ma output current (total) iol (other than port8) 60 ma iol (port8) 80 ma output current (total) ioh ?80 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) tsolder 260 c storage temperature tstg ?65 to 150 c operating temperature topr ?40 to 85 c note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. solderability of lead free products te s t parameter test condition note (1) use of sn ? 37pb solder bath solder bath temperature = 230 c, dipping time = 5 seconds the number of times = one, use of r-type flux solderability (2) use of sn ? 3.0ag ? 0.5cu solder bath solder bath temperature = 245 c, dipping time = 5 seconds the number of times = one, use of r-type flux (use of lead free) pass: solderability rate until forming 95%
tmp91cw40 2008-09-19 91cw40-194 4.2 dc electrical characteristics (1/2) parameter symbol condition min typ. (note) max unit fc = 8 to 27 mhz 2.7 power supply voltage avcc = dvcc avss = dvss = 0 v vcc fc = 8 to 16 mhz fs = 30 to 34 khz 2.2 3.6 v vcc 2.7 v 0.3 vcc p0, p1, p2, p5, p62, p7, p8, p9, pa, pb vil1 vcc < 2.7 v 0.2 vcc vcc 2.7 v 0.25 vcc reset , nmi , p60(int0), p61(int1) vil2 vcc < 2.7 v 0.15 vcc vcc 2.7 v 0.3 am0, am1 vil3 vcc < 2.7 v 0.3 vcc 2.7 v 0.2 vcc low-level input voltage x1 vil4 vcc < 2.7 v ?0.3 0.1 vcc v vcc 2.7 v 0.7 vcc p0, p1, p2, p5, p62, p7, p8, p9, pa, pb vih1 vcc < 2.7 v 0.8 vcc vcc 2.7 v 0.75 vcc reset , nmi , p60(int0),p61(int1) vih2 vcc < 2.7 v 0.85 vcc vcc 2.7 v vcc ? 0.3 am0, am1 vih3 vcc < 2.7 v vcc ? 0.3 vcc 2.7 v 0.8 vcc high-level input voltage x1 vih4 vcc < 2.7 v 0.9 vcc vcc + 0.3 v iol = 1.6 ma vcc 2.7 v 0.45 low-level output voltage vol iol = 0.4 ma vcc < 2.7 v 0.15 vcc v high-level output voltage voh ioh = ?400 a vcc 2.7 v vcc ? 0.3 v vol = 1.0 v vcc 2.7 v 15 low-level output current (port 8) iol vol = 1.0 v vcc 2.2 v 10 ma note: ta = 25c, vcc = 3.0 v, unless otherwise noted.
tmp91cw40 2008-09-19 91cw40-195 dc electrical characteristics (2/2) parameter symbol condition min typ. (note 1) max unit input leakage current ili 0.0 v in vcc 0.02 5 output leakage current ilo 0.2 v in vcc ? 0.2 0.05 10 a power down voltage (while ram is being backed up in stop mode) vstop v il2 = 0.2 vcc, v ih2 = 0.8 vcc 2.2 3.6 v vcc 2.7 v 100 400 reset pull-up resistor rrst vcc < 2.7 v 200 1000 k pin capacitance cio fc = 1 mhz 10 pf vcc 2.7 v 0.4 schmitt width reset , nmi , int0, int1 vth vcc < 2.7 v 0.3 v normal (note 2) 34 46 idle2 25 34 idle1 vcc =2.7 v to 3.6 v fc = 27 mhz 18 26 ma normal (note 2) 15 21 idle2 11 16 idle1 vcc = 2.2 v to 3.6 v fc = 16 mhz 8 11 ma slow (note 2) 30 75 idle2 20 60 idle1 vcc = 2.2 v to 3.6 v fs = 32.768 khz 13 45 a stop icc vcc = 2.2 v to 3.6 v 1 10 a note 1: typical values are for when ta = 25c and vcc = 3.0 v unless otherwise noted. note 2: icc measurement c onditions (normal, slow): all functions are operating; output pins are input pins are fixed.
tmp91cw40 2008-09-19 91cw40-196 4.3 ad conversion electrical characteristics avcc = vcc , avss = vss parameter symbol condition min typ. max unit vcc 2.7v vcc 0.2v vcc vcc analog reference voltage vrefh vcc < 2.7 v vcc vcc vcc vcc 2.7v vss vss vss+0.2v analog reference voltage vrefl vcc < 2.7 v vss vss vss analog input voltage vain vrefl vrefh v vcc 2.7v 0.94 1.35 analog current for analog reference voltage = 1 vcc < 2.7 v 0.65 0.90 ma = 0 iref (vrefl=0v) v cc = 2.2v to 3.6v 0.02 5.0 a vcc 2.7v 1.0 4.0 total error (not including quantization error) ? vcc < 2.7 v 1.0 4.0 lsb note 1: 1 lsb = (vrefh ? vrefl)/1024 [v] note 2: minimum operating frequency the operation of the ad converter is guaranteed only when t he high-fequency oscillator (fc) is used and the clock selected with the clock gear is 4 mhz or higher (not guaranteed with fs). note 3: the supply current flowing through the av cc pin is included in the vcc pin supply current (i cc ).
tmp91cw40 2008-09-19 91cw40-197 4.4 sio timing (i/o interface mode) (1) sclk input mode equation 16 mhz 27 mhz parameter symbol min max min max min max unit sclk period t scy 16x 1.0 0.59 s t scy /2 ? 4x ? 110 (v cc = 2.7v to 3.6v) 140 38 output data sclk rising /falling edge* t oss t scy /2 ? 4x ? 180 (v cc = 2.2v to 2.7v) 70 ? ns sclk rising /falling edge* output data hold t ohs t scy /2 + 2x + 0 625 370 ns sclk rising /falling edge* input data hold t hsr 3x + 10 198 121 ns sclk rising /falling edge* valid data hold t srd t scy ? 0 1000 592 ns valid data input /falling edge * sclk rising /falling edge* t rds 0 0 0 ns (2) sclk output mode equation 16 mhz 27 mhz parameter symbol min max min max min max unit sclk period t scy 16x 8192x 1.0 512 0.59 303 s output data sclk rising /falling edge* t oss t scy /2 ? 40 460 256 ns sclk rising /falling edge* output data hold t ohs t scy /2 ? 40 460 256 ns sclk rising /falling edge* input data hold t hsr 0 0 0 ns sclk rising /falling edge* valid data hold t srd t scy ? 1x ? 180 757 375 ns valid data input /falling edge * sclk rising /falling edge* t rds 1x + 180 243 217 ns note 1: sclk rise or fall: measured relative to the programmed active edge of sclk. note 2: the values shown in the 27 mhz and 16 mhz columns are measured with t scy = 16x. note 3: in the above tables, the letter x represents the f fph cycle period, which is half the system clock (f sys ) cycle period used in the cpu core. the f fph cycle period varies depending on the clock gear setting and whether the high-frequency or low frequency oscillator is used. t rds t srd t hsr t scy output data txd sclk (input falling mode) sclk output mode/ input rising mode 0 t oss t ohs 1 3 0 1 3 2 2 valid input data rxd valid valid valid
tmp91cw40 2008-09-19 91cw40-198 4.5 timer/counter input (eci n) characteristics parameter symbol condition min typ. max unit count on a single edge frequency measurement mode vdd =2.7 to 3.6 v count on both edges ? ? count on a single edge timer/counter input (ecin1 to ecin3 input) t tc1 frequency measurement mode vdd =2.2 to 2.7 v count on both edges ? ? fc/2 (fc/2 = max. 8mhz) mhz 4.6 interrupts (1) nmi , int0 and int1 interrupts equation 16 mhz 27 mhz parameter symbol min max min max min max unit low pulse width for nmi , int0, int1 t intal 4x + 40 290 188 ns high pulse width for nmi , int0, int1 t intah 4x + 40 290 188 ns note 1: xc represents the cy cle period of the high-frequency oscillator clock (fc). note 2: in the above table, the letter x represents the f fph cycle period, which is half the system clock (f sys ) cycle period used in the cpu core. the f fph cycle period varies depending on the clock gear setting and whether the high-frequency or low frequency oscillator is used.
tmp91cw40 2008-09-19 91cw40-199 4.7 recommended crystal oscillation circuit TMP91CW40FG is evaluated by below oscillator vender. when selecting external parts, make use of this information. note: total loads value of oscillator is sum of external loads (c1 and c2) and floating loads of actual assemble board. there is a possibility of miss-operating using c1 and c2 value in below table. when designing board, it should design minimum length pattern around oscillator. and we recommend that oscillator evaluation try on your actual using board. (1) connection example (2) recommended ceramic oscillator: murata manufacturing co., ltd. (japan) for up-to-date information, plea se refer to the following url: http://www.murata.co.jp/ low-frequency oscillator high-frequency oscillator x1 x2 c1 c2 rd rf xt1 xt2 c1 c2 rd rf
tmp91cw40 2008-09-19 91cw40-200 5. table of sfrs the special function registers (sfrs) include the i/o ports and peripheral control registers allocated to the 4-kbyte address space from 000000h to 000fffh. (1) i/o ports (2) interrupt control (3) clock gear (4) uart/serial channel (5) ad converter (6) watchdog timer (7) real time clock (8) melody/alarm generator (9) divider output (10) key-on wakeup (11) lcd driver (12) program patch logic (13) 8-bit timer (14) 16-bit timer name 1 symbol address 7 6 0 bit symbol read/write initial value after reset remarks table layout note: ?prohibit rmw? in the table means that you cannot use rmw instructions on these register. example: when setting bit0 only of the register pxcr, the instruction ?set 0, (pxcr)? cannot be used. the ld (transfer) instructio n must be used to write all eight bits. read/write r/w: both read and write are possible. r: only read is possible. w: only write is possible. w * : both read and write are possible (when this bit is read as 1). prohibit rmw: read-modify-write instructions are prohibited. (the ex, add, adc, bus, sbc, inc, dec, and, or, xor, st cf, res, set, chg, tset, rlc, rrc, rl, rr, sla, sra, sll, srl, rld and rrd instruction are read-modify-write instructions.) r/w * : read-modify-write is prohibited when controlling the pull-up resistor.
tmp91cw40 2008-09-19 91cw40-201 5.1 sfr address map [1] port address name address name address name 0000h p0 0010h 0020h pacr 1h p1 1h 1h pafc 2h p0cr 2h p6 2h 3h 3h p7 3h 4h p1cr 4h p6cr 4h pb 5h 5h p6fc 5h pbcr 6h p2 6h p7cr 6h 7h 7h p7fc 7h 8h p2cr 8h p8 8h 9h 9h p9 9h ah ah p8cr ah bh bh p8fc bh ch ch p9cr ch dh p5 dh p9fc dh p7fc2 eh eh pa eh fh fh fh ode [2] intc address name address name address name 0080h dma0v 0090h inte0ad 00a0h intetc01 1h dma1v 1h inte1alm0 1h intetc23 2h dma2v 2h intealm12 2h 3h dma3v 3h intealm34 3h 4h 4h intetmr56 4h 5h 5h intetmr78 5h 6h 6h intetmr12 6h 7h 7h 7h 8h intclr 8h 8h 9h dmar 9h intetmr3 9h ah dmab ah intes0 ah bh bh intes1 bh ch iimc ch intertc ch dh dh intes2 dh eh eh intes3 eh fh fh fh [3] cgear address name 00e0h syscr0 1h syscr1 2h syscr2 3h emccr0 4h emccr1 5h syscr3 6h 7h 8h 9h ah bh ch dh eh fh note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
tmp91cw40 2008-09-19 91cw40-202 5.2 sfr address map [4] uart/sio [5]ad converter address name address name address name 0200h sc0buf 0210h sc2buf 02a0h adreg04l 1h sc0cr 1h sc2cr 1h adreg04h 2h sc0mod0 2h sc2mod0 2h adreg15l 3h br0cr 3h br2cr 3h adreg15h 4h br0add 4h br2add 4h adreg26l 5h sc0mod1 5h sc2mod1 5h adreg26h 6h 6h 6h adreg37l 7h 7h 7h adreg37h 8h sc1buf 8h sc3buf 8h 9h sc1cr 9h sc3cr 9h ah sc1mod0 ah sc3mod0 ah bh br1cr bh br3cr bh ch br1add ch br3add ch dh sc1mod1 dh sc3mod1 dh eh eh eh fh fh fh [6] wdt [7]rtc address name address name address name 02b0h admod0 0300h wdmod 0320h secr 1h admod1 1h wdcr 1h minr 2h 2h 2h hourr 3h 3h 3h dayr 4h 4h 4h dater 5h 5h 5h monthr 6h 6h 6h yearr 7h 7h 7h pager 8h 8h 8h restr 9h 9h 9h ah ah ah bh bh bh ch ch ch dh dh dh eh eh eh fh fh fh [8] mld [9] dvo [10] kwi address name address name address name 0330h alm 0340h tbtcr 03a0h kwien 1h melalmc 1h 1h kwicr 2h melfl 2h 2h 3h melfh 3h 3h 4h almint 4h 4h 5h 5h 5h 6h 6h 6h 7h 7h 7h 8h 8h 8h 9h 9h 9h ah ah ah bh bh bh ch ch ch dh dh dh eh eh eh fh fh fh note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
tmp91cw40 2008-09-19 91cw40-203 5.3 sfr address map [11] lcdd address name address name address name 03d0h lcdcr 03e0h lcdreg0 03f0h lcdreg10 1h 1h lcdreg1 1h lcdreg11 2h 2h lcdreg2 2h lcdreg12 3h 3h lcdreg3 3h lcdreg13 4h 4h lcdreg4 4h lcdreg14 5h 5h lcdreg5 5h lcdreg15 6h 6h lcdreg6 6h lcdreg16 7h 7h lcdreg7 7h lcdreg17 8h 8h lcdreg8 8h lcdreg18 9h 9h lcdreg9 9h lcdreg19 ah ah ah bh bh bh ch ch ch dh dh dh eh lcdcr2 eh eh fh fh fh [12] program patch logic address name address name address name 0400h romcmp00 0410h romcmp20 0420h romcmp40 1h romcmp01 1h romcmp21 1h romcmp41 2h romcmp02 2h romcmp22 2h romcmp42 3h 3h 3h 4h romsub0l 4h romsub2l 4h romsub4l 5h romsub0h 5h romsub2h 5h romsub4h 6h 6h 6h 7h 7h 7h 8h romcmp10 8h romcmp30 8h romcmp50 9h romcmp11 9h romcmp31 9h romcmp51 ah romcmp12 ah romcmp32 ah romcmp52 bh bh bh ch romsub1l ch romsub3l ch romsub5l dh romsub1h dh romsub3h dh romsub5h eh eh eh fh fh fh [13] 8-bit timer [14] 16-bit timer address name address name address name 0900h tc5cr1 0910h tc7cr1 0940h treg1al 1h tc6cr1 1h tc8cr1 1h treg1ah 2h tc5cr2 2h tc7cr2 2h 3h tc6cr2 3h tc8cr2 3h treg1b 4h ttreg5 4h ttreg7 4h tc1cr1 5h ttreg6 5h ttreg8 5h tc1cr2 6h 6h 6h tc1sr 7h 7h 7h 8h pwreg5 8h pwreg7 8h 9h pwreg6 9h pwreg8 9h ah ah ah bh bh bh ch ch ch dh dh dh eh eh eh fh fh fh note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
tmp91cw40 2008-09-19 91cw40-204 5.4 sfr address map address name address name 0950h treg2al 0960h treg3al 1h treg2ah 1h treg3ah 2h 2h 3h treg2b 3h treg3b 4h tc2cr1 4h tc3cr1 5h tc2cr2 5h tc3cr2 6h tc2sr 6h tc3sr 7h 7h 8h 8h 9h 9h ah ah bh bh ch ch dh dh eh eh fh fh note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
tmp91cw40 2008-09-19 91cw40-205 6. port section equivalent circuit diagrams ? reading the circuit diagrams basically, the gate symbols written are the same as those used for the standard cmos logic ic [74hcxx] series. the dedicated signal is described below. stop : this signal becomes active 1 when th e halt mode setting re gister is set to the stop mode (syscr2 = ?01?) and the cpu executes the halt instruction. when the drive enable bit syscr2 is set to ?1?, however stop remains at ?0?. ? the input protection resistance ranges from several tens of ohms to several hundreds of ohms. p0 (seg24~seg31), p1 (seg16~seg23), p2 (seg8~seg15), pb (seg32~seg39) p5 (an0~an3/kwi0~kwi3) p60 (int0) lcd output enable v cc output data p-ch input/output input data output enable stop input enable n-ch seg output analog input channel select input input data analog input input enable input input enable input data
tmp91cw40 2008-09-19 91cw40-206 p61 (int1) p62(alarm), p70~p75(ecnt1~ ecnt3, ecin1~ecin3), p91(rx d0), p92(sclk0/cts0), p94 (rxd1), p95(sclk1/cts1), pa1(rxd2), pa2( sclk2/cts2), pa4(rxd3), pa5(sclk3/cts3) p80~p83(tc5out~tc8out), p90(txd0), p93(txd1), pa0(txd2), pa3(txd3) v cc output data p-ch input/output input data output enable stop input enable n-ch vcc output data input data output enable stop input enable p-ch n-ch input/output open-drain output enable v cc output enable stop input enable n-ch output data p-ch input/output input data
tmp91cw40 2008-09-19 91cw40-207 xt1, xt2 x1, x2 nmi am0~am1 input nmi schmitt trigge r input x2 high-frequency oscillator enable oscillator circuit p-ch n-ch clock x1 xt1 xt2 clock low-frequency oscillation enable
tmp91cw40 2008-09-19 91cw40-208 reset vrefh, vrefl input wdtout reset enable reset schmitt trigge r p-ch vcc vrefh vrefon vrefl p-ch ladder resistors
tmp91cw40 2008-09-19 91cw40-209 7. points to note and restrictions (1) notation a. the notation for built-in i/o registers is as follows register symbol e.g.) tc5cr1 denotes bit tc5cr1 of register tc5s. b. read-modify-write instructions an instruction in which the cpu reads data from memory and writes the data to the same memory location in one instruction. example 1: set 3, (tc5cr1) ... set bit3 of tc5cr1. example 2: inc 1, (100h) ... increment the data at 100h. ? examples of read-modify-write instructions on the tlcs-900 exchange instruction ex (mem), r arithmetic operations add (mem), r/# adc (mem), r/# sub (mem), r/# sbc (mem), r/# inc #3, (mem) dec #3, (mem) logic operations and (mem), r/# or (mem), r/# xor (mem), r/# bit manipulation operations stcf #3/a, (mem) res #3, (mem) set #3, (mem) chg #3, (mem) tset #3, (mem) rotate and shift operations rlc (mem) rrc (mem) rl (mem) rr (mem) sla (mem) sra (mem) sll (mem) srl (mem) rld (mem) rrd (mem) c. fc, fs, f fph , f sys and one state the clock frequency input on pins x1 and x2 is called fc. the clock frequency input on pins xt1 and xt2 is called fs. the clock selected by syscr1 is called f fph . the clock frequency give by f fph divided by 2 is called f sys . one cycle of f sys is referred to as one state.
tmp91cw40 2008-09-19 91cw40-210 (2) points of note a. am0 and am1 pins this pin is connected to the dvcc pin. do not alter the level when the pin is active. b. emu0 and emu1 open pins. c. halt mode (idle1) when the halt instruction is executed in idle1 mode (in which only the oscillator operates), the internal special timer for clock operate. when necessary, stop the circuit by setting rtccr to ?0?, before the halt instructions is executed. d. warm-up counter the warm-up counter operates when stop mode is released, even if the system is using an external oscillator. as a result a time eq uivalent to the warm-up time elapses between input of the release request and output of the system clock. e. watchdog timer the watchdog timer starts operation immediately after a reset is released. when the watchdog timer is not to be used, disable it. when the bus is released, neither internal memory nor internal i/o can be accessed. however, the internal i/o continues to operate. hence the watchdog timer continues to run. therefore be careful about the bus releasing time and set the detection timer of watchdog timer. f. ad converter the string resistor between the vrefh and vrefl pins can be cut by a program so as to reduce power consumption. when stop mode is used, disable the resistor using the program before the halt instruction is executed. g. cpu (micro dma) only the ldc cr, r and ldc r, cr instructions can be used to access the control registers in the cpu (e.g., the transfer sou rce address register (dmasn)). h. undefined sfr the value of an undefined bit in an sfr is undefined when read. i. pop sr instruction please execute the pop sr instruction during di condition.
tmp91cw40 2008-09-19 91cw40-211 8. package lqfp100-p-1414-0.50f unit: mm

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