View DG409LEDY-T1-GE3_8638823.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 1 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 17 ? , +12 v / 5 v / +5 v / +3 v, 8-ch / dual 4-ch high performance analog multiplexers description the dg408le, dg409le are monolithic analog multiplexers / demultiplexe rs designed to operate on single and dual supplies. single supply voltage ranges from 3 v to 16 v while dual supply operation is recommended with 3 v to 8 v. the dg408le is an 8 channel single-ended analog multiplexer designed to conn ect one of eight inputs to a common output as determined by a 3 bit binary address (a 0 , a 1 , a 2 ). the dg409le is a dual 4 channel differential analog multiplexer designed to connect one of four differential inputs to a commo n dual output as determined by its 2 bit binary address (a 0 , a 1 ). break-before-make switching action to protect against momentary crosstalk between adjacent channels. an on channel conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails. an en able (en) function allows the user to reset the multiplexer / demultiplexer to all switches off for stacking seve ral devices. all control inputs, address (ax) and enable (en) are ttl compatible over the full specified operating temperature range. the dg408le, dg409le feature low on-resistance, fast switching time, and low leakage. they are ideal for data acquisition, control and auto mation, test instrument, and healthcare products. the dg408le, dg409le has an internal regulator powers th e logic circuit. such design reduces device power consumption and makes them ideal for battery operated applications. the dg408le, dg409le are available in tssop16, soic16, and qfn16 packages. features ? pin-for-pin compatibility with dg408, dg409, and dg508, dg509 ? 3 v to 16 v single supply or 3 v to 8 v dual supply operation ? low power consumption: 6 a/max., en = vx = 5 v ? lower on-resistance: r ds(on) - 17 ? typ. ? fast switching: t on - 55 ns, t off - 36 ns ? break-before-make guaranteed ? low leakage: i s(off) - 1 na max. ? ttl, cmos, lv logic (3 v) compatible ? -99 db off-isolation and -98 db crosstalk at 100 khz ? low parasitic capacitances: c s(off) = 5.5 pf, c d(on) = 35 pf (dg408le) ? esd protection: 2.5 kv human body model 100 v machine model ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 note * this datasheet provides information about parts that are rohs-compliant and / or parts th at are non-rohs-compliant. for example, parts with lead (pb) te rminations are not rohs-compliant. please see the information / tables in this datasheet for details. benefits ? high accuracy ? single and dual power rail capacity ? wide operating voltage range ? simple logic interface applications ? automatic test equipment ? data acquisition systems ? meters and instruments ? medical and healthcare systems ? communication systems ? audio and video signal routing ? relay replacement ? battery powered systems ? computer peripherals ? audio and video signal routing functional block diagrams and pin configurations available available available a 0 d a a 1 d b en gnd v- v+ s 1a s 1 b s 2a s 2 b s 3a s 3 b s 4a s 4 b decoders/dri v ers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg409le dual-in- line, soic and tssop s 3 a 0 s 6 d s 4 a 1 s 8 s 7 en a 2 v- gnd s 1 v+ s 2 s 5 decoders/dri v ers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg408le dual-in- line, soic and tssop
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 2 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 qfn outline note ? for low and high voltage levels for v ax and v en consult digital control parameters for specific v+ operation. note ? -t1 indicates tape and reel, -g e3 indicates lead (pb)-free and rohs-compliant, no -ge3 indica tes standard tin/lead finish. ? exposed pad of qfn packag e can be connected to gnd, v-, or left floating. en a 0 a 1 a 2 s 4 ds 8 s 7 v- s 1 s 2 s 3 gnd v+ s 5 s 6 decoder/driver 1 2 3 4 5678 12 11 10 9 16 15 14 13 decoder/driver v- s 1a s 2a s 3a 1 2 3 4 s 4a d a d b s 4b 56 78 v+ s 1b s 2b s 3b 12 11 10 9 en a 0 a 1 gnd 16 15 14 13 dg408le qfn16 (3 mm x 3 mm) dg409le qfn16 (3 mm x 3 mm) truth table (dg408le) a 2 a 1 a 0 en on switch xxx0 none 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 truth table (dg409le) a 1 a 0 en on switch xx0 none 001 1 011 2 101 3 111 4 ordering information temp. range configuration package par t number min. order / pack. quantity -40 c to +85 c lead-free 8 channel single ended dg408le 16-pin tssop dg408ledq-ge3 tube 360 units dg408ledq-t1-ge3 tape and reel, 3000 units 16-pin soic dg408ledy-ge3 tube 500 units dg408ledy-t1-ge3 tape and reel, 2500 units 16-pin qfn (3 mm x 3 mm) variation 2 dg408ledn-t1-ge4 tape and reel, 2500 units dual 4 channel differential dg409le 16-pin tssop dg409ledq-ge3 tube 360 units dg409ledq-t1-ge3 tape and reel, 3000 units 16-pin soic dg409ledy-ge3 tube 500 units DG409LEDY-T1-GE3 tape and reel, 2500 units 16-pin qfn (3 mm x 3 mm) variation 2 dg409ledn-t1-ge4 tape and reel, 2500 units
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 3 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. signals on s x , d x , a x , or en exceeding v+ or v- will be clamped by internal diodes. limit forward diode curr ent to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 8 mw/c above 75 c. d. derate 17.3 mw/c above 70 c e. also applies when v- = gnd stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. absolute maximum ratings parameter limit unit v+ to v- e 18 v gnd to v- -18 digital inputs a , v s , v d (v-) - 0.3 to (v) + 0.3 current (any terminal) 30 ma peak current, s or d (pulsed at 1 ms, 10 % duty cycle max.) 100 storage temperature (d suffix) -65 to +125 c power dissipation (package) b 16-pin plastic tssop c 600 mw 16-pin narrow soic c 600 16-pin miniqfn d 1385 esd human body model (hbm); per ansi / esda / jedec ? js-001 2500 v latch up current, per jesd78d 300 ma
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 4 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. leakage parameters are guaranteed by worst case test condition and not subj ect to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a mi nimum and the most positive a maxi mum, is used in this data s heet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not su bject to prod uction test. f. v in = input voltage to pe rform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occu rs on channel 4 do to pr oximity to the drain pin. specifications (single supply 12 v) parameter symbol test conditions unless otherwise specified v+ = 12 v, 10 %, v- = 0 v v en = 0.8 v or 2.4 v f temp. b typ. d d suffix -40 c to +85 c unit min. c max. c analog switch analog signal range e v analog full - 0 12 v drain-source on-resistance r ds(on) v d = 10.8 v, v d = 2 v or 9 v, i s = 10 ma sequence each switch on room 17 - 23 ? full - - 27 r ds(on) matching between channels g ? r ds v d = 10.8 v, v d = 2 v or 9 v i s = 10 ma room 1 - 3 on-resistance flatness r flat(on) room 3 6.5 switch off leakage current a i s(off) v en = 0 v, v d = 11 v or 1 v v s = 1 v or 11 v room - -1 1 na full - -5 5 i d(on) room - -1 1 full - -5 5 channel on leakage current a i d(on) v s = v d = 1 v or 11 v room - -1 1 full - -5 5 digital control logic high input voltage v inh full - 2.4 - v logic low input voltage v inl full - - 0.8 input current a i in v ax = v en = 2.4 v or 0.8 v full - -1 1 a dynamic characteristics transition time t trans v s1 = 8 v, v s8 = 0 v, (dg408le) v s1b = 8 v, v s4b = 0 v, (dg409le) see figure 2 room 85 - 100 ns full - - 110 break-before-make time t open v s(all) = v da = 5 v see figure 4 room 34 1 - full - - - enable turn-on time t on(en) v ax = 0 v, v s1 = 5 v (dg408le) v ax = 0 v, v s1b = 5 v (dg409le) see figure 3 room 55 - 72 full - - 82 enable turn-off time t off(en) room 36 - 47 full - - 50 charge injection e (dg408le) qc l = 1 nf, v gen = 6 v, r gen = 0 ? room -11 - - pc charge injection e (dg409le) room -10 - - off isolation e, h (dg408le) oirr f = 100 khz, r l = 50 ? room -99 - - db off isolation e, h (dg409le) room -87 - - crosstalk e (dg408le) x talk room -98 - - crosstalk e (dg409le) room -109 - - source off capacitance e (dg408le) c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 5.5 - - pf source off capacitance e (dg409le) room 5.5 - - drain off capacitance e (dg408le) c d(off) f = 1 mhz, v d = 2.4 v, v en = 0 v room 25 - - drain off capacitance e (dg409le) room 13.5 - - drain on capacitance (dg408le) c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v (dg409le only) room 35 - - drain on capacitance e (dg409le) room 23.5 - - power supplies power supply range v+ - 3 12 v power supply current i+ v en = v a = 0 v or 5 v room 3.5 6 a
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 5 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. leakage parameters are guaranteed by worst case test condition and not subj ect to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a mi nimum and the most positive a ma ximum, is used in this datash eet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not su bject to prod uction test. f. v in = input voltage to pe rform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occu rs on channel 4 do to pr oximity to the drain pin. specifications (dual supply v+ = 5 v, v - = -5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, 10 %, v- = -5 v v en = 0.6 v or 2.4 v f temp. b typ. d d suffix -40 c to +85 c unit min. c max. c analog switch analog signal range e v analog full - -5 5 v drain-source on-resistance r ds(on) v d = 3.5 v, i s = 10 ma sequence each switch on room 15 - 25 ? full - - 30 switch off leakage current a i s(off) v+ = 5.5, v- = 5.5 v v en = 0 v, v d = 4.5 v, v s = 4.5 v room - -1 1 na full - -5 5 i d(off) room - -1 1 full - -5 5 channel on leakage current a i d(on) v+ = 5.5 v, v- = -5.5 v v en = 2.4 v, v d = 4.5 v, v s = 4.5 v room - -1 1 full - -5 5 digital control logic high input voltage v inh full - 2.4 - v logic low input voltage v inl full - - 0.6 input current a i in v ax = v en = 2.4 v or 0.6 v full - -1 1 a dynamic characteristics transition time t trans v s1 = 3.5 v, v s8 = -3.5 v, (dg408le) v s1b = 3.5 v, v s4b = -3.5 v, (dg409le) see figure 2 room 87 - 100 ns full - - 120 break-before-make time t open v s(all) = v da = 3.5 v see figure 4 room 84 1 - full - - - enable turn-on time t on(en) v ax = 0 v, v s1 = 3.5 v (dg408le) v ax = 0 v, v s1b = 3.5 v (dg409le) see figure 3 room 58 - 73 full - - 80 enable turn-off time t off(en) room 31 - 46 full - - 51 source off capacitance e (dg408le) c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 6 - - pf source off capacitance e (dg409le) room 5.5 - - drain off capacitance e (dg408le) c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 26 - - drain off capacitance e (dg409le) room 14 - - drain on capacitance e (dg408le) c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v room 36 - - drain on capacitance e (dg409le) room 24 - -
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 6 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. leakage parameters are guaranteed by worst case test condition and not subj ect to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a mi nimum and the most positive a maxi mum, is used in this data s heet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not su bject to prod uction test. f. v in = input voltage to pe rform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occu rs on channel 4 do to pr oximity to the drain pin. specifications (single supply 5 v) parameter symbol test conditions unless otherwise specified v+ = 5 v, 10 %, v- = 0 v v en = 0.6 v or 2.4 v f temp. b typ. d d suffix -40 c to +85 c unit min. c max. c analog switch analog signal range e v analog full - 0 5 v drain-source on-resistance r ds(on) v+ = 4.5 v, v d or v s = 1 v or 3.5 v, i s = 5 ma room 28 - 36 ? full - - 41 r ds(on) matching between channels g ? r ds v+ = 4.5 v, v d = 1 v or 3.5 v, i s = 5 ma room 1 - 3 on-resistance flatness r flat(on) room - - 4 switch off leakage current a i s(off) v+ = 5.5 v, v s = 1 v or 4 v v d = 4 v or 1 v room - -1 1 na full - -5 5 i d(off) room - -1 1 full - -5 5 channel on leakage current a i d(on) v+ = 5.5 v, v d = v s = 1 v or 4 v sequence each switch on room - -1 1 full - -5 5 digital control logic high input voltage v inh v+ = 5 v full - 2.4 - v logic low input voltage v inl full - - 0.6 input current a i in v ax = v en = 2.4 v or 0.6 v full - -1 1 a dynamic characteristics transition time t trans v s1 = 3.5 v, v s8 = 0 v, (dg408le) v s1b = 3.5 v, v s4b = 0 v, (dg409le) see figure 2 room 113 - 135 ns full - - 165 break-before-make time t open v s(all) = v da = 3.5 v, see figure 4 room 75 1 - full - - - enable turn-on time t on(en) v ax = 0 v, v s1 = 3.5 v (dg408le) v ax = 0 v, v s1b = 3.5 v (dg409le) see figure 3 room 77 - 89 full - - 110 enable turn-off time t off(en) room 43 - 50 full - - 53 charge injection e (dg408le) qc l = 1 nf, r gen = 0 ? , v gen = 2.5 v room -2 - - pc charge injection e (dg409le) room -2 - - off isolation e, h (dg408le) oirr f = 100 khz, r l = 50 ? room -100 - - db off isolation e, h (dg409le) room -83 - - crosstalk e (dg408le) x talk room -101 - - crosstalk e (dg409le) room -108 - - source off capacitance e (dg408le) c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 6.5 - - pf source off capacitance e (dg409le) room 6.5 - - drain off capacitance e (dg408le) c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 30 - - drain off capacitance e (dg409le) room 16 - - drain on capacitance e (dg408le) c d(on) f = 1 mhz, v d = 0 v, v en = 2.4 v room 40 - - drain on capacitance e (dg409le) room 26.5 - -
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 7 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. leakage parameters are guaranteed by worst case test condition and not subj ect to production test. b. room = 25 c, full = as determined by the operating temperature suffix. c. the algebraic convention whereby the most negative value is a mi nimum and the most positive a maxi mum, is used in this data s heet. d. typical values are for design aid only, not guaranteed nor subject to production testing. e. guaranteed by design, not su bject to prod uction test. f. v in = input voltage to pe rform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occu rs on channel 4 do to pr oximity to the drain pin. specifications (single supply 3 v) parameter symbol test conditions unless otherwise specified v+ = 3 v, 10 %, v- = 0 v v en = 0.4 v or 2 v f temp. b typ. d d suffix -40 c to +85 c unit min. c max. c analog switch analog signal range e v analog full - 0 3 v drain-source on-resistance r ds(on) v+ = 2.7 v, v d = 0.5 or 2.2 v, i s = 5 ma room 63 - 80 ? full - - 92 switch off leakage current a i s(off) v+ = 3.3 v, v s = 2 or 1 v, v d = 1 or 2 v room - -1 1 na full - -5 5 i d(off) room - -1 1 full - -5 5 channel on leakage current a i d(on) v+ = 3.3 v, v d = v s = 1 v or 2 v sequence each switch on room - -1 1 full - -5 5 digital control logic high input voltage v inh full - 2 - v logic low input voltage v inl full - - 0.4 input current a i in v ax = v en = 2.4 v or 0.4 v full - -1 1 a dynamic characteristics transition time t trans v s1 = 1.5 v, v s8 = 0 v, (dg408le) v s1b = 1.5 v, v s4b = 0 v, (dg409le) see figure 2 room 211 - 275 ns full - - 300 break-before-make time t open v s(all) = v da = 1.5 v, see figure 4 room 209 1 - full - - - enable turn-on time t on(en) v ax = 0 v, v s1 = 1.5 v (dg408le) v ax = 0 v, v s1b = 1.5 v (dg409le) see figure 3 room 125 - 150 full - - 180 enable turn-off time t off(en) room 45 - 75 full - - 95 charge injection e (dg408le) qc l = 1 nf, r gen = 0 ? , v gen = 1.5 v room 0 - - pc charge injection e (dg409le) room -0.4 - - off isolation e, h (dg408le) oirr f = 100 khz, r l = 50 ? room -90 - - db off isolation e, h (dg409le) room -95 - - crosstalk e (dg408le) x talk room -95 - - crosstalk e (dg409le) room -93 - - source off capacitance e (dg408le) c s(off) f = 1 mhz, v s = 0 v, v en = 0 v room 7 - - pf source off capacitance e (dg409le) room 7 - - drain off capacitance e (dg408le) c d(off) f = 1 mhz, v d = 0 v, v en = 0 v room 33 - - drain off capacitance e (dg409le) room 18 - - drain on capacitance e (dg408le) c d(on) f = 1 mhz, v d = 0 v, v en = 2 v room 43 - - drain on capacitance e (dg409le) room 28 - -
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 8 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) r ds(on) vs. v d and power supply r ds(on) vs. v d and temperature (dual supply) input threshold vs. v+ supply voltage r ds(on) vs. v d and power supply r ds(on) vs. v d and temperature switching time vs. supply voltage 10 15 20 25 30 35 40 45 50 55 60 65 70 0123456789101112 r ds(on) - drain-source on-resistance ( ? ) v d - drain voltage (v) v+ = 3.3 v v+ = 12 v v+ = 5 v 5 10 15 20 25 30 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 r ds(on) - drain-source on-resistance ( ? ) v d - drain voltage (v) 25 c -40 c v+ = 5 v, v- = - 5 v 85 c 1.2 1.3 1.4 1.5 1.6 1.7 1.8 34567891011121314 v t (v) v+ - positive supply voltage (v) upper threshold limit lower threshold limit 10 15 20 25 -5 -4 -3 -2 -1 0 1 2 3 4 5 r ds(on) - drain-source on-resistance ( ? ) v d - drain voltage (v) v+ = +5 v v- = -5 v 15 20 25 30 35 40 45 50 0123456 r ds - on-resistance ( ? ) v d - drain voltage (v) v+ = 5 v, v- = 0 v 25 c 85 c -40 c 20 40 60 80 100 120 140 160 180 3456789101112 switching speed (ns) v+ - positive supply voltage(v) t off t trans t on
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 9 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) leakage current vs. analog voltage charge injection vs. analog voltage (dg409le) drain/source capa citance vs. analog voltage (dg408le) charge injection vs. analog voltage (dg408le) insertion loss, off isolation, and crosstalk vs. frequency -150 -100 -50 0 50 100 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 leakage current (pa) v d, v s C analog voltage (v) id(on) is(o ? ) id(o ? ) -15 -10 -5 0 5 10 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 q - charge injection (pc) v s - source voltage (v) v+ = +/- 5 v v+ = 12 v v+ = 5 v 0 5 10 15 20 25 30 35 40 45 50 0123456789101112 c d, c s C drain/sourcecapacitance (pf) drain/source capacitance vs. analog voltage (dg408l) id(on) is(o ? ) id(o ? ) v+ = 12 v, v- = 0 v -20 -15 -10 -5 0 5 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 q - charge injection (pc) v s - source voltage (v) v+ = +/- 5 v v+ = 12 v v+ = 5 v -110 -90 -70 -50 -30 -10 10 0 1 10 100 1000 loss (db) frequency (mhz) insertion loss (-3 db = 39 mhz) off isolation crosstalk v+ = 5 v, v- = 0
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 10 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 schematic diagram (typical channel) fig. 1 test circuits fig. 2 - transition time e n a 0 s 1 d v + s n v - decode/ drive level shift v - v + a x g n d v oltage regulator body snatcher v - v - v - a 1 a 0 a 2 a 1 a 0 v+ v- en v+ v- gnd d 35 pf v o s 1 s 2 - s 7 s 8 50 ? 300 ? v s8 v s1 v+ v- en v+ v- gnd 35 pf v o s 1 b s 1a - s 4a , d a s 4 b 300 ? d b logic inp u t switch o u tp u t v s1 v o t trans t r < 20 ns t f < 20 ns s 8 on (dg408le) or s 4 on (dg409le) s 1 on t trans 50 % v s8 50 % 90 % 3 v 0 v dg408le dg409le v sb4 v s1 3 v 3 v v ax 50 ? 90 %
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 11 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits fig. 3 - enable switching time fig. 4 - break-before-make interval logic inp u t switch o u tp u t v o t r < 20 ns t f < 20 ns 3 v 0 v 0 v t off(en) t on(en) 50 % 50 % 90 % 90 % v o en s 1 s 2 - s 8 a 0 a 1 a 2 50 ? 300 ? v o v+ gnd v- d 35 pf v- v+ s 1 b s 1a - s 4a , d a s 2 b - s 4 b d b en a 0 a 1 50 ? 300 ? v o v+ gnd v- 35 pf v- dg408le dg409le v s1 v+ v s1 50 % 80 % logic inp u t switch o u tp u t v o v s t open t r < 20 ns t f < 20 ns 0 v 3 v 0 v en v+ gnd v- 35 pf v- 3 v a 2 d b , d all s and d a 300 ? v o 50 ? bb m.5 4/9 a 1 a 0 dg408le dg409le v s1
dg408le, dg409le www.vishay.com vishay siliconix s16-0389-rev.a, 07-mar-16 12 document number: 78084 for technical questions, contact: analogswitchsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits fig. 5 - charge injection fig. 6 - off isolation fig. 7 - crosstalk fig. 8 - insertion loss fig. 9 - source drain capacitance vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?78084 . a 0 en a 1 a 2 v o v+ gnd v- d v g r g s x c l 1 nf channel select 3 v 0 v on logic inp u t switch o u tp u t ? v o ? v o is the meas u red v oltage d u e to charge transfer error q, when the channel t u rns off. q = c l x ? v o off v+ v- v o r l 50 ? v o v+ gnd v- a 2 d a 1 a 0 s 8 s x v s en r g = 50 ? off isolation = 20 log v out v in v in v+ v- r l 50 ? v o v+ gnd v- a 2 d a 1 a 0 s 8 s x v s en r g = 50 ? crosstalk = 20 log v out v in v in s 1 v+ v- r l 50 ? a 2 v o d r g = 50 ? insertion loss = 20 log v out a 1 v in a 0 v s s 1 v+ gnd v- en v- v+ f = 1 mhz s 1 d en gnd v+ v- meter hp4192a impedance analyzer or eq u i v alent s 8 a 1 a 2 a 0 channel select v- v+
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
package information www.vishay.com vishay siliconix revision: 09-may-16 1 document number: 72208 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 qfn-16 lead (3 x 3) notes (1) all dimensions are in millimeters. (2) n is the total num ber of terminals. (3) dimension b applies to metallized terminal and is me asured between 0.25 and 0. 30 mm from terminal tip. (4) coplanarity applies to the exposed heat sink slug as well as the terminal. (5) the pin #1 identifier may be either a mold or marked feature, it must be located within the zone indicated. dim. variation 1 variation 2 millimeters inches m illimeters inches min. nom max. min. nom max. min. nom max. min. nom max. a 0.80 0.90 1.00 0.031 0.035 0.039 0.80 0.90 1.00 0.031 0.035 0.039 b 0.18 0.23 0.30 0.007 0.009 0.012 0.18 0.25 0.30 0.007 0.010 0.012 d 2.90 3.00 3.10 0.114 0.118 0.122 2.90 3.00 3.10 0.114 0.118 0.122 d2 1.00 1.15 1.25 0.039 0.045 0.049 1.50 1.70 1.80 0.059 0.067 0.071 e 2.90 3.00 3.10 0.114 0.118 0.122 2.90 3.00 3.10 0.114 0.118 0.122 e2 1.00 1.15 1.25 0.039 0.045 0.049 1.50 1.70 1.80 0.059 0.067 0.071 e 0.50 bsc 0.020 bsc 0.50 bsc 0.020 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 0.30 0.40 0.50 0.012 0.016 0.020 ecn: t16-0233-rev. d, 09-may-16 dwg: 5899 -c- c 0.08 c 0.10 // -a- -b- e s eatin g plane a3 a1 a nx side view (3) terminal tip expo s ed pad d d/2 e/2 bottom view top view c 0.25 c 0.25 e2/2 e2 d2 d2/2 l e 3 x e 3 x e c 0.10 m a b 4xb (3) (4) (4)
vishay siliconix package information document number: 74417 23-oct-06 www.vishay.com 1 symbols dimensions in millimeters min nom max a - 1.10 1.20 a1 0.05 0.10 0.15 a2 - 1.00 1.05 b 0.22 0.28 0.38 c - 0.127 - d 4.90 5.00 5.10 e 6.10 6.40 6.70 e1 4.30 4.40 4.50 e-0.65- l 0.50 0.60 0.70 l1 0.90 1.00 1.10 y--0.10 1036 ecn: s-61920-rev. d, 23-oct-06 dwg: 5624 tssop: 16-lead
pad pattern www.vishay.com vishay siliconix revision: 02-sep-11 1 document number: 63550 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended minimum pad for tssop-16 0.281 (7.15) recommended minimum pads dimensions in inches (mm) 0.171 (4.35) 0.055 (1.40) 0.012 (0.30) 0.026 (0.65) 0.014 (0.35) 0.193 (4.90)
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

▲Up To Search▲

Price & Availability of DG409LEDY-T1-GE3

	To Download DG409LEDY-T1-GE3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .