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part number structure features ? ? small package: smd/th: 30.85 x 20.0 x 8.2 mm (1.215 x 0.787 x 0.323 in); sip: 33.0 x 7.6 x 18.1 mm (1.30 x 0.30 x 0.713 in) ? ? 0.6 v - 3.3 v output voltage range ? ? high ef? ciency, typ. 97.2% at 5vin, 3.3vout half load ? ? con? guration and monitoring via pmbus? ? ? synchonization & phase spreading ? ? current sharing, voltage tracking & voltage margining ? ? voltage setting via pin-strap or pmbus? ? ? mtbf 14.2 mh ? ? non-linear response for reduction of decou- pling capacitor ? ? remote control & power good ? ? output short-circuit, output over voltage, & over temperature protection ? ? certi? ed to ul/iec 60950-1 typical units pm typical units product overview the okdx-t/40-w12 series are high ef? - ciency, digital point-of-load (pol) dc-dc power converters capable of delivering 40a/132w. available in three different pack- age formats, through-hole, single-in-line, and surface mount, these converters have a typical ef? ciency of 97.2%. pmbus? compat- ibility allows monitoring and con? guration of critical system-level performance require- ments. apart from standard pol performance and safety features like ovp, ocp, otp, and uvlo, these digital converters have advanced features: digital current sharing (full power, no derating), non-linear transient response, optimized dead time control, synchronization, and phase spreading. these converters are ideal for use in telecommunications, network- ing, and distributed power applications. power management via pmbus? ? ? con? gurable soft-start/stop ? ? con? gurable output voltage (vout) and voltage margins (margin low and margin high) ? ? con? gurable protection limits for ovp, input over voltage, input under voltage, over current, on/off, and temperature ? ? status monitor vout, iout, vin, temp, power good, and on/off applications ? ? distributed power architectures ? ? intermediate bus voltage applications ? ? servers and storage applications ? ? network equipment okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 1 of 38 www.murata-ps.com www.murata-ps.com/support trimmable output voltage range 0.6 - 3.3vdc - t y = surface mount h = horizontal mount through-hole x = sip x digital non-isolated pol okd c - rohs hazardous substance compliance c = rohs-6 (does not claim eu rohs exemption 7b C lead in solder) maximum rated output current in amps / 40 input voltage range 4.5-14vdc w12 - xxx - software con? guration digits (001 is positive turn-on logic) (002 is negative turn-on logic)* *special quantity order is required; contact murata power solutions for moq and lead times.
characteristics min typ max unit t p1 , t p2 operating temperature (see thermal consideration section) -40 125 c t s storage temperature -40 125 c v i input voltage (see operating information section for input and output voltage relations) -0.3 16 v logic i/o voltage ctrl, sa0, sa1, salert, scl, sda, vset, sync, gcb, pg -0.3 6.5 v ground voltage differential -s, pref, gnd -0.3 0.3 v analog pin voltage vo, +s, vtrk -0.3 6.5 v absolute maximum ratings stress in excess of absolute maximum ratings may cause permanent damage. absolute maximum ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits in the electrical speci? cation. if exposed to stress above these limits, function and performance may degrade in an unspeci? ed manner. con? guration file this product is designed with a digital control circuit. the control circuit uses a con? guration ? le which determines the functionality and performance of the product. the electrical speci? cation table shows parameter values of functionality and performance with the default con? guration ? le, unless otherwise speci? ed. the default con? guration ? le is designed to ? t most application needs with focus on high ef? ciency. if different characteristics are required it is pos- sible to change the con? guration ? le to optimize certain performance characteristics. note that current sharing operation requires changed con? guration ? le. in this technical speci? cation examples are included to show the possibilities with digital control. see operating information section for information about trade offs when optimizing certain key performance characteristics. fundamental circuit diagram vout vout vin vin gnd gnd c i c o +sense -sense controller and digital interface (sa1) ctrl sync sda gcb pref pgood salert vset scl sa0 vtrk c i =140 f, c o =400 f general and safety conditions min typ max unit safety designed for ul/iec/en 60950 1 calculated mtbf telcordia sr-332, issue 2 method 1 14.2 mhrs okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 2 of 38 www.murata-ps.com/support ordering guide model number output okdy-t/40-w12-001-c 0.6-3.3 v, 40 a/ 132 w okdh-t/40-w12-001-c okdx-t/40-w12-001-c okdx-t/40-w12-002-c
electrical speci? cations, okdy-t/40-w12-xxx-c and okdh-t/40-w12-xxx-c t p1 = -30 to +95c, vin = 4.5 to 14 v, vin > vout + 1.0 v typical values given at: t p1 = +25 c, vin = 12.0 v, max iout, unless otherwise speci? ed under conditions. default con? guration ? le, 190 10-cda 102 0206/001. external cin = 470 f/10 m, cout = 470 f/10 m. see operating information section for selection of capacitor types. sense pins are connected to the output pins. characteristics conditions min typ max unit v i input voltage rise time monotonic 2.4 v/ms v o output voltage without pin strap 1.2 v output voltage adjustment range 0.60 3.3 v output voltage adjustment including margining see note 17 0.54 3.63 v output voltage set-point resolution 0.025 % vo output voltage accuracy including line, load, temp. see note 14 -1 1 % current sharing operation see note 15 -2 2 % internal resistance +s/-s to vout/gnd 4.7 line regulation v o = 0.6 v 2 mv v o = 1.0 v 3 v o = 1.8v 3 v o = 3.3 v 3 load regulation; i o = 0 - 100% v o = 0.6 v 2 mv v o = 1.0 v 2 v o = 1.8v 2 v o = 3.3 v 2 v oac output ripple & noise c o = 470 f (minimum external capacitance). see note 11 v o = 0.6 v 15 mvp-p v o = 1.0 v 20 v o = 1.8 v 25 v o = 3.3 v 35 i o output current see note 18 0.001 40 a i s static input current at max i o v o = 0.6 v 2.45 a v o = 1.0 v 3.80 v o = 1.8 v 6.49 v o = 3.3 v 11.58 i lim current limit threshold 42 52 a i sc short circuit current rms, hiccup mode, see note 3 v o = 0.6 v 10 a v o = 1.0 v 9 v o = 1.8 v 9 v o = 3.3 v 7 ? ef? ciency 50% of max i o v o = 0.6 v 84.6 % v o = 1.0 v 89.7 v o = 1.8 v 93.3 v o = 3.3 v 95.3 max i o v o = 0.6 v 81.8 % v o = 1.0 v 87.7 v o = 1.8 v 92.4 v o = 3.3 v 95.0 p d power dissipation at max i o v o = 0.6 v 5.37 w v o = 1.0 v 5.60 v o = 1.8 v 5.92 v o = 3.3 v 6.98 p li input idling power (no load) default con? guration: continues conduction mode, ccm v o = 0.6 v 1.10 w v o = 1.0 v 1.10 v o = 1.8 v 1.40 v o = 3.3 v 2.20 okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 3 of 38 www.murata-ps.com/support
characteristics conditions min typ max unit p ctrl input standby power turned off with ctrl-pin default con? guration: monitoring enabled, precise timing enabled 180 mw c i internal input capacitance 140 f c o internal output capacitance 400 f c out total external output capacitance see note 9 470 30 000 f esr range of capacitors (per single capacitor) see note 9 5 30 m v tr1 load transient peak voltage deviation (h to l) load step 25-75-25% of max?i o default con? guration di/dt = 2 a/s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v 250 mv v o = 1.0 v 250 v o = 1.8 v 240 v o = 3.3 v 220 t tr1 load transient recovery time, note 5 (h to l) load step 25-75-25% of max?i o default con? guration di/dt = 2 a/s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v 150 s v o = 1.0 v 100 v o = 1.8 v 100 v o = 3.3 v 50 f s switching frequency 320 khz switching frequency range pmbus con? gurable 200-640 khz switching frequency set-point accuracy -5 5 % control circuit pwm duty cycle 5 95 % minimum sync pulse width 150 ns input clock frequency drift tolerance external clock source -13 13 % input under voltage lockout, uvlo uvlo threshold 3.85 v uvlo threshold range pmbus con? gurable 3.85-14 v set point accuracy -150 150 mv uvlo hysteresis 0.35 v uvlo hysteresis range pmbus con? gurable 0-10.15 v delay 2.5 s fault response see note 3 automatic restart, 70 ms input over voltage protection, iovp iovp threshold 16 v iovp threshold range pmbus con? gurable 4.2-16 v set point accuracy -150 150 mv iovp hysteresis 1 v iovp hysteresis range pmbus con? gurable 0-11.8 v delay 2.5 s fault response see note 3 automatic restart, 70 ms power good, pg, see note 2 pg threshold 90 % v o pg hysteresis 5% v o pg delay 10 ms pg delay range pmbus con? gurable 0-500 s output voltage over/under voltage protection, ovp/uvp uvp threshold 85 % v o uvp threshold range pmbus con? gurable 0-100 % v o uvp hysteresis 5% v o ovp threshold 115 % v o ovp threshold range pmbus con? gurable 100-115 % v o uvp/ovp response time 25 s uvp/ovp response time range pmbus con? gurable 5-60 s fault response see note 3 automatic restart, 70 ms over current protection, ocp ocp threshold 48 a ocp threshold range pmbus con? gurable 0-48 a protection delay, see note 4 32 t sw protection delay range pmbus con? gurable 1-32 t sw fault response see note 3 automatic restart, 70 ms okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 4 of 38 www.murata-ps.com/support
characteristics conditions min typ max unit over temperature protection, otp at p1 see note 8 otp threshold 120 c otp threshold range pmbus con? gurable -40+120 c otp hysteresis 15 c otp hysteresis range pmbus con? gurable 0-160 c fault response see note 3 automatic restart, 240 ms v il logic input low threshold sync, sa0, sa1, scl, sda, gcb, ctrl, vset 0.8 v v ih logic input high threshold 2 v i il logic input low sink current ctrl 0.6 ma v ol logic output low signal level sync, scl, sda, salert, gcb, pg 0.4 v v oh logic output high signal level 2.25 v i ol logic output low sink current 4ma i oh logic output high source current 2ma t set setup time, smbus see note 1 300 ns t hold hold time, smbus see note 1 250 ns t free bus free time, smbus see note 1 2 ms c p internal capacitance on logic pins 10 pf initialization time see note 10 35 ms output voltage delay time see note 6 delay duration see note 16 10 ms delay duration range pmbus con? gurable 2-500000 delay accuracy turn-on default con? guration: ctrl controlled precise timing enabled 0.25 ms pmbus controlled precise timing disabled current sharing operation -0.25/+4 ms delay accuracy turn-off -0.25/+4 ms output voltage ramp time see note 13 ramp duration 10 ms ramp duration range pmbus con? gurable 0-200 ramp time accuracy 100 s current sharing operation 20 % vtrk input bias current v vtrk = 5.5 v 110 200 a vtrk tracking ramp accuracy (v o - v vtrk ) 100% tracking, see note 7 -100 100 mv current sharing operation 2 phases, 100% tracking v o = 1.0 v, 10 ms ramp 100 mv vtrk regulation accuracy (v o - v vtrk ) 100% tracking -1 1 % current sharing operation 100% tracking -2 2 % current difference between products in a current sharing group steady state operation max 2 x read_iout monitoring accuracy ramp-up 4 a number of products in a current sharing group 7 monitoring accuracy read_vin vs v i 3% read_vout vs v o 1% read_iout vs i o i o = 0-40 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 1.0 v 2.5 a read_iout vs i o i o = 0-40 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 0.6-3.3 v 4 a note 1: see section i2c/smbus setup and hold times C de? nitions. note 2: monitorable over pmbus interface. note 3: automatic restart ~70 or 240 ms after fault if the fault is no longer present. continuous restart attempts if the fault reappear after restart. see operating information and an302 for other fault response options. note 4: t sw is the switching period. note 5: within +/-3% of v o note 6: see section soft-start power up. note 7: tracking functionality is designed to follow a vtrk signal with slew rate < 2.4 v/ms. for faster vtrk signals accuracy will depend on the regulator bandwidth. note 8: see section over temperature protection (otp). note 9: see section external capacitors. note 10: see section initialization procedure. note 11: see graph output ripple vs external capacitance and operating information section output ripple and noise. note 12: see graph load transient vs. external capacitance and operating information section external capacitors. note 13: time for reaching 100% of nominal vout. note 14: for vout < 1.0 v accuracy is +/-10 mv. for further deviations see section output voltage adjust using pmbus. note 15: accuracy here means deviation from ideal output voltage level given by con? gured droop and actual load. includes line, load and temperature variations. note 16: for current sharing the output voltage delay time must be recon? gured to minimum 15 ms. note 17: for steady state operation above 1.05 x 3.3 v, please contact your local murata sales representative. note 18: a minimum load current is not required if low power mode is used (monitoring disabled). okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 5 of 38 www.murata-ps.com/support
power dissipation vs. output current, v i = 5 v typical characteristics ef?ciency and power dissipation ef?ciency vs. output current, v i = 5 v ef?ciency vs. load current and output voltage: t p1 = +25 c, v i =5 v, f sw = 320 khz, c o = 470 f/10 m. ef?ciency vs. output current, v i = 12 v dissipated power vs. load current and output voltage: t p1 = +25 c, v i = 5 v, f sw = 320 khz, c o = 470 f/10 m. power dissipation vs. output current, v i = 12 v ef?ciency vs. load current and output voltage at t p1 = +25 c, v i = 12 v, f sw = 320 khz, c o = 470 f/10 m. dissipated power vs. load current and output voltage: t p1 = +25 c, v i = 12 v, f sw = 320 khz, c o = 470 f/10 m. ef?ciency vs. output current and switching frequency power dissipation vs. output current and switching frequency ef?ciency vs. load current and switch frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m default con?guration except changed frequency 75 80 85 90 95 100 0 8 16 24 32 40 [%] [a] 0.6 v 1.0 v dissipated power vs. load current and switch frequency at t p1 = +25 c. v i = 12 v, v o = 1.0 v, c o = 470 f/10 m default con?guration except changed frequency 1.8 v 3.3 v 0 2 4 6 8 0 8 16 24 32 40 [w] [a] 0.6 v 1.0 v 1.8 v 3.3 v 75 80 85 90 95 100 0 8 16 24 32 40 [%] [a] 0.6 v 1.0 v 1.8 v 3.3 v 0 2 4 6 8 0 8 16 24 32 40 [w] [a] 0.6 v 1.0 v 1.8 v 3.3 v 70 75 80 85 90 95 0 8 16 24 32 40 [%] [a] 200 khz 320 khz 480 khz khz 640 0 2 4 6 8 0 8 16 24 32 40 [w] [a] 200 khz 320 khz 480 khz 640 khz okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 6 of 38 www.murata-ps.com/support
load transient vs. external capacitance, v o = 3.3 v typical characteristics load transient load transient vs. external capacitance, v o = 1.0 v load transient peak voltage deviation vs. external capacitance. step-change (10-30-10 a). parallel coupling of capacitors with 470 f/10 m, t p1 = +25 c, v i = 12 v, v o = 1.0 v, f sw = 320 khz, di/dt = 2 a/s load transient vs. switch frequency output load transient response, default pid/nlr load transient peak voltage deviation vs. external capacitance. step-change (10-30-10 a). parallel coupling of capacitors with 470 f/10 m, t p1 = +25 c, v i = 12 v, v o = 3.3 v, f sw = 320 khz, di/dt = 2 a/s load transient peak voltage deviation vs. frequency. step-change (10-30-10 a). t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m output voltage response to load current step- change (10-30-10 a) at: t p1 = +25 c, v i = 12 v, v o = 1.0 v di/dt = 2 a/s, f sw = 320 khz, c o = 470 f/10 m top trace: output voltage (200 mv/div.). bottom trace: load current (10 a/div.). time scale: (0.1 ms/div.). 0 50 100 150 200 250 0123 5 4 [mv] [mf] default pid/nlr nlr opt. pid, no note: in the load transient graphs, the worst-case scenario (load step 30-10 a) has been considered. opt. nlr default pid, opt. pid/nlr 0 50 100 150 200 250 1 024 35 [mv] [mf] default pid/nlr nlr opt. pid, no default pid, opt. nlr opt. pid/nlr 50 100 150 200 250 300 200 300 400 500 600 [mv] [khz] default pid/nlr opt. pid, no nlr opt. nlr default pid, opt. pid/nlr okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 7 of 38 www.murata-ps.com/support
output current derating, v o = 1.0 v typical characteristics output current characteristic output current derating, v o = 0.6 v available load current vs. ambient ai r temperature and air?ow at v o = 0.6 v, v i = 12 v. see thermal consideration section. output current derating, v o = 1.8 v output current derating, v o = 3.3 v available load current vs. ambien t air temperature and air?ow at v o = 1.0 v, v i = 12 v. see thermal consideration section. available load current vs. ambient ai r temperature and air?ow at v o = 1.8 v, v i = 12 v. see thermal consideration section. current limit characteristics, v o = 1.0 v current limit characteristics, v o = 3.3 v available load current vs. ambient air temperature and air?ow at v o = 3.3 v, v i = 12 v. see thermal consideration section. o utput voltage vs. load current at t p1 = +25 c, v o = 1.0 v. note: output enters hiccup mode at current limit. 0 10 20 30 40 60 40 80 100 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s o utput voltage vs. load current at t p1 = +25 c, v o = 3.3 v. note: output enters hiccup mode at current limit. 0.5 m/s nat. conv. 0 10 20 30 40 40 60 80 100 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 10 20 30 40 40 60 80 100 [a] 120 [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 10 20 30 40 40 60 80 100 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0.0 0.3 0.6 0.9 1.2 40 42 44 46 48 50 [v] [a] 4.5 v 5.0 v 12 v 14 v v i = 12, 14 v 0.0 1.0 2.0 3.0 4.0 40 42 44 46 48 50 [v] [a] 4.5 v 5.0 v 12 v 14 v v i = 12, 14 v v i = 4.5, 5.0 v v i = 4.5, 5.0 v okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 8 of 38 www.murata-ps.com/support
output ripple & noise, v o = 1.0 v typical characteristics output voltage output ripple & noise, v o =3.3 v output voltage ripple at: t p1 = +25 c, v i = 12 v, c o = 470 f/10 m i o = 40 a trace: output voltage (10 mv/div.). time scale: (2 s/div.). output voltage ripple at: t p1 = +25 c, v i = 12 v, c o = 470 f/10 m i o = 40 a output ripple vs. input voltage trace: output voltage (10 mv/div.). time scale: (2 s/div.). output ripple vs. frequency output voltage ripple v pk-pk at: t p1 = +25c, c o = 470 f/10 m, i o = 40 a. output ripple vs. external capacitance load regulation, v o =1.0v output voltage ripple v pk-pk at: t p1 = +25c, v i = 12 v , c o = 470 f/10 m, i o = 40 a. default con?guration except changed frequency. output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v, i o = 40 a. parallel coupling of capacitors with 470 f/10 m, 0 10 load regulation at v o =1.0 v at: t p1 = +25 c, c o = 470 f/10 m 20 30 40 5791113 [v] [mv pk-pk ] 0.6 v 1.0 v 1.8 v 3.3 v 0 20 40 60 80 100 200 300 250 400 450 350 500 550 600 [khz] [mv pk-pk ] 0.6 v 1.0 v 1.8 v 3.3 v 0 10 20 30 40 5 4 3 2 1 0 [mv] [mf] 0.6 v 1.0 v 1.8 v 3.3 v 0.990 0.995 1.000 1.005 08 1.010 16 24 32 40 [v] [a] 4.5 v 5.0 v 12 v 14 v okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 9 of 38 www.murata-ps.com/support
typical characteristics start-up and shut-down start-up by input source shut-down by input source start-up enabled by connecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 40 a top trace: output voltage (0.5 v/div.). bottom trace: input voltage (5 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 40 a start-up by ctrl signal shut-down by ctrl signal top trace: output voltage (0.5 v/div). bottom trace: input voltage (5 v/div.). time scale: (2 ms/div.). start-up by enabling ctrl signal at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 40 a top trace: output voltage (0.5 v/div.). bottom trace: ctrl signal (5 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m, i o = 40 a top trace: output voltage (0.5 v/div). bottom trace: ctrl signal (5 v/div.). time scale: (2 ms/div.). okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 10 of 38 www.murata-ps.com/support
electrical speci? cations, okdx-t/40-w12-xxx-c t p1 = -30 to +95 c, v i = 4.5 to 14 v, v i > v o + 1.0 v typical values given at: t p1 = +25 c, v i = 12.0 v, max i o , unless otherwise speci? ed under conditions. default con? guration ? le, 190 10-cda 102 0259/001. external c in = 470 f/10 m, c out = 470 f/10 m. see operating information section for selection of capacitor types. sense pins are connected to the output pins. characteristics conditions min typ max unit v i input voltage rise time monotonic 2.4 v/ms v o output voltage without pin strap 1.2 v output voltage adjustment range 0.60 3.3 v output voltage adjustment including margining see note 17 0.54 3.63 v output voltage set-point resolution 0.025 % vo output voltage accuracy including line, load, temp. see note 14 -1 1 % current sharing operation see note 15 -2 2 % internal resistance +s/-s to vout/gnd 4.7 line regulation v o = 0.6 v 2 mv v o = 1.0 v 2 v o = 1.8v 2 v o = 3.3 v 2 load regulation; i o = 0 - 100% v o = 0.6 v 2 mv v o = 1.0 v 2 v o = 1.8v 2 v o = 3.3 v 2 v oac output ripple & noise c o = 470 f (minimum external capacitance). see note 11 v o = 0.6 v 20 mvp-p v o = 1.0 v 25 v o = 1.8 v 30 v o = 3.3 v 45 i o output current see note 18 0.001 40 a i s static input current at max i o v o = 0.6 v 2.46 a v o = 1.0 v 3.81 v o = 1.8 v 6.51 v o = 3.3 v 11.61 i lim current limit threshold 42 52 a i sc short circuit current rms, hiccup mode, see note 3 v o = 0.6 v 9 a v o = 1.0 v 8 v o = 1.8 v 8 v o = 3.3 v 6 ef? ciency 50% of max i o v o = 0.6 v 85.8 % v o = 1.0 v 90.5 v o = 1.8 v 93.7 v o = 3.3 v 95.5 max i o v o = 0.6 v 81.4 % v o = 1.0 v 87.5 v o = 1.8 v 92.1 v o = 3.3 v 94.7 p d power dissipation at max i o v o = 0.6 v 5.48 w v o = 1.0 v 5.70 v o = 1.8 v 6.12 v o = 3.3 v 7.32 p li input idling power (no load) default con? guration: contin- ues conduction mode, ccm v o = 0.6 v 0.90 w v o = 1.0 v 0.90 v o = 1.8 v 1.10 v o = 3.3 v 1.70 p ctrl input standby power turned off with ctrl-pin default con? guration: monitoring enabled, precise timing enabled 170 mw okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 11 of 38 www.murata-ps.com/support
characteristics conditions min typ max unit c i internal input capacitance 140 f c o internal output capacitance 400 f c out total external output capacitance see note 9 470 30 000 f esr range of capacitors (per single capacitor) see note 9 5 30 m v tr1 load transient peak voltage deviation (h to l) load step 25-75-25% of max?i o default con? guration di/dt = 2 a/s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v 240 mv v o = 1.0 v 240 v o = 1.8 v 220 v o = 3.3 v 200 t tr1 load transient recovery time, note 5 (h to l) load step 25-75-25% of max?i o default con? guration di/dt = 2 a/s c o = 470 f (minimum external capacitance) see note 12 v o = 0.6 v 120 s v o = 1.0 v 100 v o = 1.8 v 80 v o = 3.3 v 40 f s switching frequency 320 khz switching frequency range pmbus con? gurable 200-640 khz switching frequency set-point accuracy -5 5 % control circuit pwm duty cycle 5 95 % minimum sync pulse width 150 ns input clock frequency drift tolerance external clock source -13 13 % input under voltage lockout, uvlo uvlo threshold 3.85 v uvlo threshold range pmbus con? gurable 3.85-14 v set point accuracy -150 150 mv uvlo hysteresis 0.35 v uvlo hysteresis range pmbus con? gurable 0-10.15 v delay 2.5 s fault response see note 3 automatic restart, 70 ms input over voltage protection, iovp iovp threshold 16 v iovp threshold range pmbus con? gurable 4.2-16 v set point accuracy -150 150 mv iovp hysteresis 1 v iovp hysteresis range pmbus con? gurable 0-11.8 v delay 2.5 s fault response see note 3 automatic restart, 70 ms power good, pg, see note 2 pg threshold 90 % v o pg hysteresis 5 % v o pg delay 10 ms pg delay range pmbus con? gurable 0-500 s output voltage over/under voltage protection, ovp/uvp uvp threshold 85 % v o uvp threshold range pmbus con? gurable 0-100 % v o uvp hysteresis 5 % v o ovp threshold 115 % v o ovp threshold range pmbus con? gurable 100-115 % v o uvp/ovp response time 25 s uvp/ovp response time range pmbus con? gurable 5-60 s fault response see note 3 automatic restart, 70 ms over current protection, ocp ocp threshold 48 a ocp threshold range pmbus con? gurable 0-48 a protection delay, see note 4 32 t sw protection delay range pmbus con? gurable 1-32 t sw fault response see note 3 automatic restart, 70 ms okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 12 of 38 www.murata-ps.com/support
characteristics conditions min typ max unit over temperature protection, otp at p1 see note 8 otp threshold 120 ? c otp threshold range pmbus con? gurable -40+120 ? c otp hysteresis 15 ? c otp hysteresis range pmbus con? gurable 0-160 ? c fault response see note 3 automatic restart, 240 ms v il logic input low threshold sync, sa0, sa1, scl, sda, gcb, ctrl, vset 0.8 v v ih logic input high threshold 2 v i il logic input low sink current ctrl 0.6 ma v ol logic output low signal level sync, scl, sda, salert, gcb, pg 0.4 v v oh logic output high signal level 2.25 v i ol logic output low sink current 4ma i oh logic output high source current 2ma t set setup time, smbus see note 1 300 ns t hold hold time, smbus see note 1 250 ns t free bus free time, smbus see note 1 2 ms c p internal capacitance on logic pins 10 pf initialization time see note 10 35 ms output voltage delay time see note 6 delay duration see note 16 10 ms delay duration range pmbus con? gurable 2-500000 delay accuracy turn-on default con? guration: ctrl controlled precise timing enabled 0.25 ms pmbus controlled precise timing disabled current sharing operation -0.25/+4 ms delay accuracy turn-off -0.25/+4 ms output voltage ramp time see note 13 ramp duration 10 ms ramp duration range pmbus con? gurable 0-200 ramp time accuracy 100 s current sharing operation 20 % vtrk input bias current v vtrk = 5.5 v 110 200 a vtrk tracking ramp accuracy (v o - v vtrk ) 100% tracking, see note 7 -100 100 mv current sharing operation 2 phases, 100% tracking v o = 1.0 v, 10 ms ramp 100 mv vtrk regulation accuracy (v o - v vtrk ) 100% tracking -1 1 % current sharing operation 100% tracking -2 2 % current difference between products in a current sharing group steady state operation max 2 x read_iout monitoring accuracy ramp-up 4 a number of products in a current sharing group 7 monitoring accuracy read_vin vs v i 3% read_vout vs v o 1% read_iout vs i o i o = 0-40 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 1.0 v 2.5 a read_iout vs i o i o = 0-40 a, t p1 = 0 to +95 c v i = 4.5-14 v, v o = 0.6-3.3 v 4 a note 1: see section i2c/smbus setup and hold times C de? nitions. note 2: monitorable over pmbus interface. note 3: automatic restart ~70 or 240 ms after fault if the fault is no longer present. continuous restart attempts if the fault reappear after restart. see operating information and an302 for other fault response options. note 4: t sw is the switching period. note 5: within +/-3% of v o note 6: see section soft-start power up. note 7: tracking functionality is designed to follow a vtrk signal with slew rate < 2.4 v/ms. for faster vtrk signals accuracy will depend on the regulator bandwidth. note 8: see section over temperature protection (otp). note 9: see section external capacitors. note 10: see section initialization procedure. note 11: see graph output ripple vs external capacitance and operating information section output ripple and noise. note 12: see graph load transient vs. external capacitance and operating information section external capacitors. note 13: time for reaching 100% of nominal vout. note 14: for vout < 1.0 v accuracy is +/-10 mv. for further deviations see section output voltage adjust using pmbus. note 15: accuracy here means deviation from ideal output voltage level given by con? gured droop and actual load. includes line, load and temperature variations. note 16: for current sharing the output voltage delay time must be recon? gured to minimum 15 ms, see an307 for details. note 17: for steady state operation above 1.05 x 3.3 v, please contact your local murata sales representative. note 18: a minimum load current is not required if low power mode is used (monitoring disabled). okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 13 of 38 www.murata-ps.com/support
typical characteristics efficiency and power dissipation efficiency vs. output current, v i = 5 v power dissipation vs. output current, v i = 5 v 75 80 85 90 95 100 048121620[a] [%] 0,6 v 1,0 v 1,8 v 3,3 v 0 1 2 3 4 5 048121620[a] [w] 0,6 v 1,0 v 1,8 v 3,3 v efficiency vs. load current and output voltage: t p1 = +25 c, v i = 5 v, f sw = 320 khz, c o = 470 f/10 m ? . dissipated power vs. load current and output voltage: t p1 = +25 c, v i = 5 v, f sw = 320 khz, c o = 470 f/10 m ? . efficiency vs. output current, v i = 12 v power dissipation vs. output current, v i =12v 75 80 85 90 95 100 048121620[a] [%] 0,6 v 1,0 v 1,8 v 3,3 v 0 1 2 3 4 5 0 4 8 12 16 20 [a] [w] 0,6 v 1,0 v 1,8 v 3,3 v efficiency vs. load current and output voltage at t p1 = +25 c, v i =12 v, f sw =320 khz,c o =470 f/10 m ? . dissipated power vs. load current and output voltage: t p1 = +25 c, v i =12 v, f sw =320 khz, c o =470 f/10 m ? . efficiency vs. output current and switching frequency power dissipation vs. output current and switching frequency 70 75 80 85 90 95 0 4 8 121620[a] [%] 200 khz 320 khz 480 khz 640 khz 0 1 2 3 4 5 048121620[a] [w] 200 khz 320 khz 480 khz 640 khz efficiency vs. load current and switch frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m ? default configuration except changed frequency dissipated power vs. load current and switch frequency at t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m ? default configuration except changed frequency okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 14 of 38 www.murata-ps.com/support
typical characteristics load transient load transient vs. external capacitance, v o = 1.0 v load transient vs. external capacitance, v o = 3.3 v 0 40 80 120 160 200 012345[mf] [mv] default pid/nlr opt. pid, no nlr default pid, opt. nlr opt. pid/nlr 0 50 100 150 200 012345 [mf] [mv] default pid/nlr opt. pid, no nlr default pid, opt. nlr opt. pid/nlr load transient peak voltage deviation vs. external capacitance. step-change (5-15-5 a). parallel coupling of capacitors with 470 f/10 p , t p1 = +25 c, v i = 12 v, v o = 1.0 v, f sw = 320 khz, di/dt = 2 a/ s load transient peak voltage deviation vs. external capacitance. step-change (5-15-5 a). parallel coupling of capacitors with 470 f/10 p , t p1 = +25 c, v i =12 v, v o = 3.3 v, f sw =320 khz, di/dt=2 a/ s load transient vs. switch frequency output load transient response, default pid/nlr 0 40 80 120 160 200 240 200 300 400 500 600 [khz] [mv] default pid/nlr opt. pid, no nlr default pid, opt. nlr opt. pid/nlr load transient peak voltage deviation vs. frequency. step-change (5-15-5 a). t p1 = +25 c, v i = 12 v, v o = 1.0 v, c o = 470 f/10 m ? output voltage response to load current step-change (5-15-5 a) at: t p1 = +25 c, v i = 12 v, v o = 1.0 v di/dt = 2 a/ s, f sw = 320 khz, c o =470 f/10 m ? top trace: output voltage (200 mv/div.). bottom trace: load current (5 a/div.). time scale: (0.1 ms/div.). okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 15 of 38 www.murata-ps.com/support
typical characteristics output current characteristic output current derating, v o = 0.6 v output current derating, v o = 1.0 v 0 5 10 15 20 25 60 70 80 90 100 110 120 [c] [a] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0 5 10 15 20 25 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. c onv. available load current vs. ambient air temperature and airflow at v o = 0.6 v, v i = 12 v. see thermal consideration section. available load current vs. ambient air temperature and airflow at v o = 1.0 v, v i = 12 v. see thermal consideration section. output current derating, v o = 1.8 v output current derating, v o =3.3v 0 5 10 15 20 25 60 70 80 90 100 110 120 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. c onv. 0 5 10 15 20 25 60 70 80 90 100 110 120 [c] [a] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. a vailable load current vs. ambient air temperature and airflow at v o = 1.8 v, v i = 12 v. see thermal consideration section. a vailable load current vs. ambient air temperature and airflow at v o = 3.3 v, v i = 12 v. see thermal consideration section. current limit characteristics, v o = 1.0 v current limit characteristics, v o = 3.3 v 0,0 0,2 0,4 0,6 0,8 1,0 1,2 20 22 24 26 28 30 [v] [a] 4.5 v 5.0 v 12 v 14 v 0,0 1,0 2,0 3,0 4,0 20 22 24 26 28 30 [v] [a] 4.5 v 5.0 v 12 v 14 v o utput voltage vs. load current at t p1 = +25 c, v o = 1.0 v. note: output enters hiccup mode at current limit. o utput voltage vs. load current at t p1 = +25 c, v o = 3.3 v. output enters hiccup mode at current limit. okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 16 of 38 www.murata-ps.com/support
typical characteristics output voltage output ripple & noise, v o = 1.0 v output ripple & noise, v o =3.3 v output voltage ripple at: t p1 = +25 c, v i = 12 v, c o =4 70 f/10 m ? i o =20a trace: output voltage (20 mv/div.). time scale: (2 s/div.). output voltage ripple at: t p1 = +25 c, v i = 12 v, c o = 470 f/10 m ? i o =20 a trace: output voltage (20 mv/div.). time scale: (2 s/div.). output ripple vs. input voltage output ripple vs. frequency 0 10 20 30 40 50 60 70 5791113 [v] [mv pk-pk ] 0.6 v 1.0 v 1.8 v 3.3 v 0 10 20 30 40 50 60 70 80 200 300 400 500 600 [khz] [mv pk-pk ] 0.6 v 1.0 v 1.8 v 3.3 v output voltage ripple v pk-pk at: t p1 = +25 c, c o = 470 f/10 m ? , i o = 20 a output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v , c o = 470 f/10 m ? , i o = 20 a. default configuration except changed frequency. output ripple vs. external capacitance load regulation, v o =1.0v 0 10 20 30 40 50 60 012345 [mf] [mv] 0.6v 1.0 v 1.8 v 3.3 v 0,990 0,995 1,000 1,005 1,010 0 4 8 12 16 20 [v] [a] 4.5 v 5.0 v 12 v 14 v output voltage ripple v pk-pk at: t p1 = +25 c, v i = 12 v, i o =20a. parallel coupling of capacitors with 470 f/10 m , load regulation at v o = 1.0 v, t p1 = +25 c, c o = 470 f/10 m ? okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 17 of 38 www.murata-ps.com/support
typical characteristics start-up and shut-down start-up by input source shut-down by input source start-up enabled by connecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m ? , i o =20 a top trace: output voltage (0.5 v/div.). bottom trace: input voltage (5 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m ? , i o =20 a top trace: output voltage (0.5 v/div.). bottom trace: input voltage (5 v/div.). time scale: (2 ms/div.). start-up by ctrl signal shut-down by ctrl signal start-up by enabling ctrl signal at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m ? , i o =20 a top trace: output voltage (0.5 v/div.). bottom trace: ctrl signal (5 v/div.). time scale: (20 ms/div.). shut-down enabled by disconnecting v i at: t p1 = +25 c, v i = 12 v, v o = 1.0 v c o = 470 f/10 m ? , i o =20 a top trace: output voltage (0.5 v/div). bottom trace: ctrl signal (5 v/div.). time scale: (2 ms/div.). okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 18 of 38 www.murata-ps.com/support
emc speci? cation conducted emi measured according to test set-up below. the funda- mental switching frequency is 320 khz at v i = 12 v, max io. layout recommendations the radiated emi performance of the product will depend on the pwb layout and ground layer design. it is also important to consider the stand- off of the product. if a ground layer is used, it should be connected to the output of the product and the equipment ground or chassis. a ground layer will increase the stray capacitance in the pwb and improve the high frequency emc performance. output ripple and noise output ripple and noise is measured according to ? gure below. a 50 mm conductor works as a small inductor forming together with the two capacitors as a damped ? lter. operating information power management overview this product is equipped with a pmbus interface. the product incorpo- rates a wide range of readable and con? gurable power management features that are simple to implement with a minimum of external components. additionally, the product includes protection features that continuously safeguard the load from damage due to unexpected system faults. a fault is also shown as an alert on the salert pin. the following product parameters can continuously be monitored by a host: input voltage, output voltage/current, and internal temperature. if the monitoring is not needed it can be disabled and the product enters a low power mode reducing the power consumption. the protection features are not affected. the product is delivered with a default con? guration suitable for a wide range operation in terms of input voltage, output volt- age, and load. the con? guration is stored in an internal non-volatile memory (nvm). all power management functions can be recon? gured using the pmbus interface. please contact your local murata power solutions representative for design support of custom con? gura- tions or appropriate sw tools for design and download of your own con? gurations. input voltage the input voltage range, 4.5 - 14 v, makes the product easy to use in intermediate bus applications when powered by a non-regulated bus converter or a regulated bus converter. see ordering information for input voltage range. conducted emi input terminal value (typical for default con? guration) emi without ? lter conducted emi test set-up rf current probe c1 1khz C 50mhz to spectrum analyzer pol load resistive supply battery 800mm 200mm 50mm c1 = 10uf / 600vdc feed- thru rf capacitor output ripple and noise test set-up. vout +s Cs gnd ceramic 0.1 f capacitor tantalum capacitor 10 f load 50 mm conductor bnc-contact to 50 mm conductor oscilloscope output capacitor 470 f/10 m okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 19 of 38 www.murata-ps.com/support
input under voltage lockout, uvlo the product monitors the input voltage and will turn-on and turn-off at configured levels. the default turn-on input voltage level setting is 4.20 v, whereas the corresponding turn-off input voltage level is 3.85 v. hence, the default hys teresis between turn-on and turn-off input voltage is 0.35 v. once an input turn-off condition occurs, the device can respond in a number of ways as follows: 1. continue operating without inte rruption. the unit will continue to operate as long as the input volt age can be supported. if the input voltage continues to fall, there will come a point where the unit will cease to operate. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdown until the fault has been cleared. the user can select a specific number of retry attempts. the default response from a turn -off is an immediate shutdown of the device. the device will continuously ch eck for the presen ce of the fault condition. if the fault condition is no longer present, the product will be re- enabled. the turn-on and turn-off levels and response can be reconfigured using the pmbus interface. remote control the product is equi pped with a remote control function, i.e., the ctrl pin. the remote control can be connected to either the primary negative input connection (gnd) or an external voltage (vext), which is a 3 - 5 v positive supply volta ge in accordance to the smbus specific ation version 2.0. the ctrl function allows the product to be turned on/off by an external device like a semico nductor or mechanica l switch. by defa ult the product will turn on when the ct rl pin is left open and tu rn off when the ctrl pin is applied to gnd. the ctrl pin has an internal pull-up resistor. when the ctrl pin is left open, the voltage generated on the ctrl pin is max 5.5 v. if the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the ctrl pin. the product can also be configured using the pmbus interface to be always on or turn on/off can be performed with pmbus commands. input and output impedance the impedance of both the input source and the load will interact with the impedance of the product. it is impor tant that the input source has low characteristic impedan ce. the performance in some applications can be enhanced by addition of external capa citance as descri bed under external decoupling capacitors. if the input voltage source contains significant inductance, the addition a capacitor with low esr at the input of the product will ensure stable operation. external capacitors input capacitors: the input ripple rms curre nt in a buck converter is equal to i inputrms =i load d (1? d ), where load i is the output load current and d is the duty cycle. the maximum load ripple current becomes 2 load i . the ripple current is divided into three parts, i.e., currents in the i nput source, external input capacitor, and internal input capacitor. how the curre nt is divided depends on the impedance of the input source , esr and capacitance values in the capacitors. a minimum capacitance of 300 f with low esr is recommended. the ripple current rating of the capacitors must follow eq. 1. for high-performance/transient applications or wh erever the input source performance is degraded, additional low esr ceramic type capacitors at the input is recommended. the additional input low esr capacitance above the minimum level insures an opti mized performance. output capacitors: when powering loads wi th significant dynamic curre nt requirements, the voltage regulation at the point of load can be improved by addition of decoupling capacitors at the load. the most effective technique is to locate low esr ceramic and electrolytic capacitors as close to the load as po ssible, using several capacitors in parallel to lower the effective esr. the ceramic capacitors will handle high- frequency dynamic load changes while the electrolytic capa citors are used to handle low frequency dynamic load changes. ceramic capacitors will also reduce high frequency noise at the load. it is equally important to use low resistance and low inductance pwb layouts and cabling. external decoupling capacitors are a part of the control loop of the product and may affect the stability margins. stable operation is guaranteed for the following total capacitance o c in the output decoupling ca pacitor bank where eq. 2. >@> @ 0 3000 , 470 , max min c c c o f. the decoupling capa citor bank should consist of capaci tors which has a capacitance value larger than min c c t and has an esr range of eq. 3. >@>@ 30 , 5 , max min esr esr esr m the control loop stability margins are limited by the minimum time constant min w of the capacitors. hence, the time constant of the cap acitors should follow eq. 4. eq. 4. s 35 . 2 min min min p w w t esr c this r elation can be used if your prefe rred capacitors have parameters outside the above stated range s in eq. 2 and eq.3. x if the capacitors capacitance value is min c c one must use at least n capacitors where ? ? o ? ? a t c c n min and c c esr esr min min t . x if the esr value is max esr esr ! one must use at least n capacitors of that type where ctrl gnd vext okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 20 of 38 www.murata-ps.com/support
? ? o ? ? a t max esr esr n and n c c min t . x if the esr value is min esr esr the capacitance value should be esr esr c c min min t . for a total capacitance outside the above stated range or capacitors that do not follow the stated above requirements above a re-design of the control loop parameters will be necessary for robust dynamic operation and stability. control loop the product uses a voltage-mode synchronous buck controller with a ? xed frequency pwm scheme. although the product uses a digital control loop, it operates much like a traditional analog pwm controller. as in the analog controller case, the control loop compares the output voltage to the desired voltage reference and compensation is added to keep the loop stable and fast. the resulting error signal is used to drive the pwm logic. instead of using external resistors and capacitors required with traditional analog control loops, the product uses a digi- tal proportional-integral-derivative (pid) compensator in the control loop. the characteristics of the control loop is con? gured by setting pid compensation parameters. these pid settings can be recon? gured using the pmbus interface. control loop compensation setting this product is by default con? gured with a robust control loop com- pensation setting (pid setting) which allows for a wide range opera- tion of input and output voltages and capacitive loads as de? ned in the section external decoupling capacitors. for an application with a speci? c input voltage, output voltage, and capacitive load, the control loop can be optimized for a robust and stable operation and with an improved load transient response. this optimization will minimize the amount of required output decoupling capacitors for a given load transient requirement yielding an optimized cost and minimized board space. the optimization can be made using the murata power designer software. load transient response optimization the product incorporates a non-linear transient response, nlr, loop that decreases the response time and the output voltage deviation during a load transient. the nlr results in a higher equivalent loop bandwidth than is possible using a traditional linear control loop. the product is pre-con? gured with appropriate nlr settings for robust and stable operation for a wide range of input voltage and a capacitive load range as de? ned in the section external decoupling capacitors. for an application with a speci? c input voltage, output voltage, and capacitive load, the nlr con? guration can be optimized for a robust and stable operation and with an improved load transient response. this will also reduce the amount of output decoupling capacitors and yield a reduced cost. however, the nlr slightly reduces the ef? - ciency. in order to obtain maximal energy ef? ciency the load transient requirement has to be met by the standard control loop compensation and the decoupling capacitors. the nlr settings can be recon? gured using the pmbus interface. remote sense the product has remote sense that can be used to compensate for voltage drops between the output and the point of load. the sense traces should be located close to the pwb ground layer to reduce noise susceptibility. due to derating of internal output capacitance the voltage drop should be kept below v dropmax = (5.5C v o )/2. a large voltage drop will impact the electrical performance of the regulator. if the remote sense is not needed, +s should be connected to vout and ?s should be connected to gnd. output voltage adjust using pin-strap resistor using an external pin-strap resis- tor, rset, the output voltage can be set in the range 0.6 v to 3.3 v at 28 different levels shown in the table below. the resistor should be applied between the vset pin and the pref pin. rset also sets the maximum output voltage, see section output voltage range limitation. the resistor is sensed only during product start-up. changing the resistor value during normal operation will not change the output voltage. the input voltage must be at least 1 v larger than the output voltage in order to deliver the correct output voltage. see ordering information for output voltage range. the following table shows recommended resistor values for rset. maximum 1% tolerance resistors are required. v o [v] r set [k] v o [v] r set [k] 0.60 10 1.50 46.4 0.65 11 1.60 51.1 0.70 12.1 1.70 56.2 0.75 13.3 1.80 61.9 0.80 14.7 1.90 68.1 0.85 16.2 2.00 75 0.90 17.8 2.10 82.5 0.95 19.6 2.20 90.9 1.00 21.5 2.30 100 1.05 23.7 2.50 110 1.10 26.1 3.00 121 1.15 28.7 3.30 133 1.20 31.6 1.25 34.8 1.30 38.3 1.40 42.2 the output voltage and the maximum output voltage can be pin strapped to three ? xed values by connecting the vset pin according to the table below. v o [v] vset 0.60 shorted to pref 1.2 open high impedance 2.5 logic high, gnd as reference vset r set pref okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 21 of 38 www.murata-ps.com/support
1. initiate an immediate shutdown until the fault has been cleared. the user can select a speci? c number of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosfet remains on until the device attempts a restart, i.e. the output voltage is pulled to ground level (crowbar function). the default response from an overvoltage fault is to immediately shut down as in 2. the device will continuously check for the pres- ence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. for continuous ovp when operating from an external clock for synchronization, the only allowed response is an immediate shutdown. the ovp limit and fault response can be recon? gured using the pmbus interface. under voltage protection (uvp) the product includes output under voltage limiting circuitry for protection of the load. the default uvp limit is 15% below the nominal output voltage. the uvp limit can be recon? gured using the pmbus interface. power good the product provides a power good (pg) ? ag in the status word reg- ister that indicates the output voltage is within a speci? ed tolerance of its target level and no fault condition exists. if speci? ed in section connections, the product also provides a pg signal output. the pg pin is active high and by default open-drain but may also be con? gured as push-pull via the pmbus interface. by default, the pg signal will be asserted when the output reaches above 90% of the nominal voltage, and de-asserted when the output falls below 85% of the nominal voltage. these limits may be changed via the pmbus interface. a pg delay period is de? ned as the time from when all conditions within the product for asserting pg are met to when the pg signal is actually asserted. the default pg delay is set to 10 ms. this value can be recon? gured using the pmbus interface. switching frequency the fundamental switching frequency is 320 khz, which yields optimal power ef? ciency. the switching frequency can be set to any value between 200 khz and 640 khz using the pmbus interface. the switching frequency will change the ef? ciency/power dissipation, load transient response and output ripple. for optimal control loop performance, the control loop must be re-optimized when changing the switching frequency. synchronization synchronization is a feature that allows multiple products to be syn- chronized to a common frequency. synchronized products powered from the same bus eliminate beat frequencies re? ected back to the input supply, and also reduces emi ? ltering requirements. eliminating the slow beat frequencies (usually <10 khz) allows the emi ? lter to be output voltage adjust using pmbus the output voltage set by pin-strap can be overridden by con? guration ? le or by using a pmbus command. see electrical speci? cation for adjustment range. when setting the output voltage by con? guration ? le or by a pmbus command, the speci? ed output voltage accuracy is valid only when the set output voltage level falls within the same bin range as the voltage level de? ned by the pin-strap resistor rset. the applicable bin ranges are de? ned in the table below. valid accuracy for voltage levels outside the applicable bin range is two times the speci? ed. example: nominal vo is set to 1.10 v by rset = 26.1 k. 1.10 v falls within the bin range 0.988-1.383 v, thus speci? ed accuracy is valid when adjust- ing vo within 0.988-1.383v. v o bin ranges [v] 0.600 C 0.988 0.988 C 1.383 1.383 C 1.975 1.975 C 2.398 2.398 C 2.963 2.963 C 3.753 output voltage range limitation the output voltage range that is possible to set by con? guration or by the pmbus interface is limited by the pin-strap resistor rset. the maximum output voltage is set to 110% of the nominal output value de? ned by r set , v o,max = 1.1 x v o,rset . this protects the load from an over voltage due to an accidental wrong pmbus command. output voltage adjust limitation using pmbus in addition to the maximum output voltage limitation by the pin-strap resistor rset, there is also a limitation in how much the output volt- age can be increased while the output is enabled. if output is disabled then rset resistor is the only limitation. example: if the output is enabled with output voltage set to 1.0 v, then it is only possible to adjust/change the output voltage up to 1.7- v as long as the output is enabled. v o setting when enabled [v] v o set range while enabled [v] 0.000 C 0.988 ~0.2 to >1.2 0.988 C 1.383 ~0.2 to >1.7 1.383 C 1.975 ~0.2 to >2.5 1.975 C 2.398 ~0.2 to >2.97 2.398 C 2.963 ~0.2 to >3.68 2.963 C 3.753 ~0.2 to >4.65 over voltage protection (ovp) the product includes over voltage limiting circuitry for protection of the load. the default ovp limit is 15% above the nominal output voltage. if the output voltage exceeds the ovp limit, the product can respond in different ways: okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 22 of 38 www.murata-ps.com/support
down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared. ef? ciency optimized dead time control the product utilizes a closed loop algorithm to optimize the dead- time applied between the gate drive signals for the switch and synch fets. the algorithm constantly adjusts the deadtime non-overlap to minimize the duty cycle, thus maximizing ef? ciency. this algorithm will null out deadtime differences due to component variation, tem- perature and loading effects. the algorithm can be con? gured via the pmbus interface. over current protection (ocp) the product includes current limiting circuitry for protection at con- tinuous overload. the following ocp response options are available: 1. initiate a shutdown and attempt to restart an in? nite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through the fault (this could result in perma- nent damage to the power supply). 5. initiate an immediate shutdown. the default response from an over current fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be re-enabled. the load distribution should be designed for the maximum output short circuit current speci? ed. the ocp limit and response of the product can be recon? gured using the pmbus interface. initialization procedure the product follows a speci? c internal initialization procedure after power is applied to the vin pin: 1. status of the address and output voltage pin-strap pins are checked and values associated with the pin settings are loaded to ram. 2. values stored in the murata default non-volatile memory are loaded to ram. this overwrites any previously loaded values. 3. values stored in the user non-volatile memory are loaded to ram. this overwrites any previously loaded values. once the initialization process is completed, the product is ready to be enabled using the ctrl pin. the product is also ready to accept commands via the pmbus interface, which will overwrite any values loaded during the initialization procedure. soft-start power up the soft-start control introduces a time-delay before allowing the output voltage to rise. once the initialization time has passed the device will wait for the con? gured delay period prior to starting to designed to attenuate only the synchronization frequency. synchroni- zation can also be utilized for phase spreading, described in section phase spreading. the products can be synchronized with an external oscillator or one product can be con? gured with the sync pin as a sync output working as a master driving the synchronization. all others on the same synchro- nization bus must be con? gured with sync input. default con? guration is using the internal clock, independently of signal at the sync pin. phase spreading when multiple products share a common dc input supply, spreading of the switching clock phase between the products can be utilized. this dramatically reduces input capacitance requirements and ef? - ciency losses, since the peak current drawn from the input supply is effectively spread out over the whole switch period. this requires that the products are synchronized. up to 16 different phases can be used. the phase spreading of the product can be con? gured using the pmbus interface. parallel operation (current sharing) paralleling multiple products can be used to increase the output cur- rent capability of a single power rail. by connecting the gcb pins of each device and con? guring the devices as a current sharing rail, the units will share the current equally, enabling up to 100% utilization of the current capability for each device in the current sharing rail. the product uses a low-bandwidth, ? rst-order digital current sharing by aligning the output voltage of the slave devices to deliver the same current as the master device. arti? cial droop resistance is added to the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and pwb layout. up to 7 devices can be con? gured in a given current sharing group. in order to avoid interference with other algorithms executing during parallel operation, the dead-time algorithm should be turned off and ? xed dead-times be used. phase adding and shedding for parallel operation during periods of light loading, it may be bene? cial to disable one or more phases (modules) in order to eliminate the current drain and switching losses associated with those phases, resulting in higher ef? ciency. the product offers the ability to add and drop phases (modules) using a pmbus command in response to an observed load current change. all phases (modules) in a current share rail are considered active prior to the current sharing rail ramp to power-good. phases can be dropped after power-good is reached. any member of the current sharing rail can be dropped. if the reference module is dropped, the remaining active module with the lowest member posi- tion will become the new reference. additionally, any change to the number of members of a current sharing rail will precipitate autono- mous phase distribution within the rail where all active phases realign their phase position based on their order within the number of active members. if the members of a current sharing rail are forced to shut okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 23 of 38 www.murata-ps.com/support
1. coincident. this mode con? gures the product to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. 2. ratiometric. this mode con? gures the product to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but a different tracking ratio may be set by an external resistive voltage divider or through the pmbus interface. the master device in a tracking group is de? ned as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is not con? gured for tracking mode. all of the ctrl pins in the track- ing group must be connected and driven by a single logic source. it should be noted that current sharing groups that are also con? gured to track another voltage do not offer pre-bias protection; a minimum load should therefore be enforced to avoid the output voltage from being held up by an outside force. voltage margining up/down the product can adjust its output higher or lower than its nominal voltage setting in order to determine whether the load device is capa- ble of operating over its speci? ed supply voltage range. this provides a convenient method for dynamically testing the operation of the load circuit over its supply margin or range. it can also be used to verify the function of supply voltage supervisors. margin limits of the nominal output voltage 5% are default, but the margin limits can be recon? g- ured using the pmbus interface. pre-bias startup capability pre-bias startup often occurs in complex digital systems when current from another power source is fed back through a dual-supply logic ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the con? gured soft-start ramp time. the default settings for the soft-start delay period and the soft- start ramp time is 10 ms. hence, power-up is completed within 20 ms in default con? guration using remote control. when the soft-start delay time is set to 0 ms, the module will begin its ramp-up after the internal circuitry has initialized (approximately 2 ms). it is generally recommended to set the soft-start ramp-up time to a value greater than 500 s to prevent inadvertent fault conditions due to excessive inrush current. the acctual minimum ramp-up time will however normally be limited by the control loop settings and ramp-up times of internal interface voltages in the controller circuit to approximately 2 ms. the soft-start power up of the product can be recon? gured using the pmbus interface. output voltage sequencing a group of products may be con? gured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another. multi-product sequencing can be achieved by con? guring the start delay and rise time of each device through the pmbus interface and by using the ctrl start signal. voltage tracking the product integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin with no external components required. during ramp-up, the output voltage follows the vtrk voltage until the preset output voltage level is met. the product offers two modes of tracking as follows: vin ctrl vout time delay initialization time ramp time illustration of power up procedure illustration of output voltage sequencing. t v1 v2 vout illustration of ratiometric voltage tracking t master slave vout illustration of coincident voltage tracking. t master slave vout okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 24 of 38 www.murata-ps.com/support
approximately 120 c the product will shut down. the speci? ed otp threshold and hysteresis are valid for worst case operation regarding cooling conditions, input voltage and output voltage. the actually con- ? gured default value in the controller circuit in position p2 is 110 c, but at worst case operation the temperature is approximately 10 c higher at position p1. at light load the temperature is approximately the same in position p1 and p2. this means the otp threshold and hysteresis will be lower at light load conditions when p1 is used as a reference for otp. products with p2 as reference otp: when tp2 as de? ned in thermal consideration section exceeds 120c the product will shut down. for products with p2 as a reference for otp the con? gured default value in the controller circuit in position p2 is 120c. the otp threshold, hysteresis, and fault response of the product can be recon? gured using the pmbus interface. the fault response can be con? gured as follows: 1. initiate a shutdown and attempt to restart an in? nite number of times with a preset delay period between attempts (default con? guration). 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through the fault (this could result in perma- nent damage to the power supply). 5. initiate an immediate shutdown. optimization examples this product is designed with a digital control circuit. the control circuit uses a con? guration ? le which determines the functionality and performance of the product. it is possible to change the con? gura- tion ? le to optimize certain performance characteristics. in the table below is a schematic view on how to change different con? guration parameters in order to achieve an optimization towards a wanted performance. ? increase ? no change ? decrease config. parameters switching frequency control loop bandwidth nlr threshold diode emulation (dcm) min. pulse optimized performance maximize ef? ciency ??? enable disable minimize ripple ampl. ??? enable or disable enable or disable improve load transient response ??? disable disable minimize idle power loss ??? enable enable component, such as fpgas or asics. the product family incorporates synchronous recti? ers, but will not sink current during startup, or turn off, or whenever a fault shuts down the product in a pre-bias condi- tion. pre-bias protection is not offered for current sharing groups that also have voltage tracking enabled. group communication bus the group communication bus, gcb, is used to communicate between products. this dedicated bus provides the communica- tion channel between devices for features such as sequencing, fault spreading, and current sharing. the gcb solves the pmbus data rate limitation. the gcb pin on all devices in an application should be con- nected together. a pull-up resistor is required on the common gcb in order to guarantee the rise time as follows: eq. 5. ? = r gcb c gcb 1s, where r gcb is the pull up resistor value and c gcb is the bus loading. the pull-up resistor should be tied to an external supply voltage in range from 3.3 to 5 v, which should be present prior to or during power-up. if exploring untested compensation or deadtime con? gurations, it is recommended that 27 series resistors are placed between the gcb pin of each product and the common gcb connection. this will avoid propagation of faults between products potentially caused by hazard- ous con? guration settings. when the con? gurations of the products are settled the series resistors can be removed. the gcb is an internal bus, such that it is only connected across the modules and not the pmbus system host. gcb addresses are assigned on a rail level, i.e. modules within the same current sharing group share the same gcb address. addressing rails across the gcb is done with a 5 bit gcb id, yielding a theoretical total of 32 rails that can be shared with a single gcb bus. fault spreading the product can be con? gured to broadcast a fault event over the gcb bus to the other devices in the group. when a non-destructive fault occurs and the device is con? gured to shut down on a fault, the device will shut down and broadcast the fault event over the gcb bus. the other devices on the gcb bus will shut down together if con? g- ured to do so, and will attempt to re-start in their prescribed order if con? gured to do so. over temperature protection (otp) the products are protected from thermal overload by an internal over temperature shutdown function in the controller circuit n1, located at position p2 (see section thermal consideration). some of the products that this speci? cation covers use the temperature at position p2 (tp2) as a reference for speci? ed otp threshold and some use position p1 (tp1) as a reference for speci? ed otp threshold. see the over tempera- ture protection section in the electrical speci? cation for each product. products with p1 as reference for otp: when tp1 as de? ned in thermal consideration section exceeds okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 25 of 38 www.murata-ps.com/support
de? nition of reference temperature tp1 the reference temperature is used to monitor the temperature limits of the product. temperature above maximum tp1, measured at the reference point p1 is not allowed and may cause degradation or permanent damage to the product. tp1 is also used to de? ne the temperature range for normal operating conditions. tp1 is de? ned by the design and used to guarantee safety margins, proper operation and high reliability of the product. pin designation function 1a, 1b vin input voltage 2a, 2b gnd power ground 3a, 3b vout output voltage 4a vtrk voltage tracking input 4b pref pin-strap reference 5a +s positive sense 5b ?s negative sense 6a sa0 pmbus address pinstrap 0 6b gcb group communication bus 7a scl pmbus clock 7b sda pmbus data 8a vset output voltage pinstrap 8b sync synchronization i/o 9a salert pmbus alert 9b ctrl remote control 10a pg power good 10b sa1 pmbus address pinstrap 1 thermal consideration general the product is designed to operate in different thermal environments and suf? cient cooling must be provided to ensure reliable operation. cooling is achieved mainly by conduction, from the pins to the host board, and convection, which is dependent on the air? ow across the product. increased air? ow enhances the cooling of the product. the output current derating graph found in the output section for each model provides the available output current vs. ambient air temperature and air velocity at speci? ed vi. the product is tested on a 254 x 254 mm, 35 m (1 oz), test board mounted vertically in a wind tunnel with a cross-section of 608 x 203 mm. the test board has 8 layers. proper cooling of the product can be veri? ed by measuring the tem- perature at positions p1 and p2. the temperature at these positions should not exceed the max values provided in the table below. note that the max value is the absolute maximum rating (non destruction) and that the electrical output data is guaranteed up to tp1 +95c. de? nition of product operating temperature the product operating temperatures are used to monitor the tempera- ture of the product, and proper thermal conditions can be veri? ed by measuring the temperature at positions p1 and p2. the temperature at these positions (tp1, tp2) should not exceed the maximum tem- peratures in the table below. the number of measurement points may vary with different thermal design and topology. temperatures above maximum tp1, measured at the reference point p1 are not allowed and may cause permanent damage. it should also be noted that depending on setting of the over temperature protection (otp) and operating conditions, the product may shut down before the maximum allowed temperature at tp1 is reached. position description max temp. p1 reference point, l1, inductor 125c * p2 n1, control circuit 125c * * a guard band of 5 c is applied to the maximum recorded component temperatures when calculating output current derating curves. pin layout, top view (component placement for illustration only). p1 p2 air flow sip version:temperature positions and air ? ow direction. top view bottom view p1 air flow p2 temperature positions and air ? ow direction. okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 26 of 38 www.murata-ps.com/support
typical application circuit unused input pins unused sda, scl and gcb pins should still have pull-up resistors as speci? ed. unused vtrk or sync pins should be left open or connected to the pref pin. unused ctrl pin can be left open due to internal pull-up. vset and sa0/sa1 pins must be used. these pins must have pin- strap resistors or strapping settings as speci? ed. pwb layout considerations the pin-strap resistors, rset, and rsa0/rsa1 should be placed as close to the product as possible to minimize loops that may pick up noise. avoid current carrying planes under the pin-strap resistors and the pmbus signals. the capacitor ci (or capacitors implementing it) should be placed as close to the input pins as possible. capacitor co (or capacitors implementing it) should be placed close to the load. care should be taken in the routing of the connections from the sensed output voltage to the s+ and sC terminals. these sensing connections should be routed as a differential pair, preferably between ground planes which are not carrying high currents. the routing should avoid areas of high electric or magnetic ? elds. pin designation function 1a, 1b vin input voltage 2a, 2b gnd power ground 3a, 3b vout output voltage 4a +s positive sense 4b ?s negative sense 5a vset output voltage pinstrap 5b vtrk voltage tracking input 6a salert pmbus alert 6b sda pmbus data 7a scl pmbus clock 7b sa1 pmbus address pinstrap 1 8a sa0 pmbus address pinstrap 0 8b sync synchronization i/o 9a pg power good 9b ctrl remote control 10a gcb group communication bus 10b pref pin-strap reference standalone operation with pmbus communication. top view of product footprint. sip version: pin layout, top view (component placement for illustration only). okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 27 of 38 www.murata-ps.com/support
typical application circuit (sip version) typical application circuit (parallel operation) standalone operation with pmbus communication. top view of product footprint. okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 28 of 38 www.murata-ps.com/support
the snapshot feature enables the user to read the parameters via the pmbus interface during normal operation, although it should be noted that reading the 22 bytes will occupy the bus for some time. the snapshot enables the user to store the snapshot parameters to flash memory in response to a pending fault as well as to read the stored data from flash memory after a fault has occurred. automatic store to flash memory following a fault is triggered when any fault threshold level is exceeded, provided that the speci? c fault response is to shut down. writing to flash memory is not allowed if the device is con? gured to restart following the speci? c fault condition. it should also be noted that the device supply voltage must be maintained during the time the device is writing data to flash memory; a process that requires between 700-1400 s depending on whether the data is set up for a block write. undesirable results may be observed if the input voltage of the product drops below 3.0 v during this process. non-volatile memory (nvm) the product incorporates two non-volatile memory areas for storage of the supported pmbus commands; the default nvm and the user nvm. the default nvm is pre-loaded with murata factory default values. the default nvm is write-protected and can be used to restore the murata factory default values through the command restore_default_all. the user nvm is pre-loaded with murata factory default values. the user nvm is writable and open for customization. the values in nvm are loaded into operational ram during initialization according to sec- tion initialization procedure, where after commands can be changed through the pmbus interface. the store_user_all command will store the changed parameters to the user nvm. software tools for design and production murata provides software tools for con? guration and monitoring of this product via the pmbus interface. for more information please contact your local murata sales representative. pmbus addressing the pmbus address should be con? gured with resistors connected between the sa0/sa1 pins and the pref pin, as shown in the pmbus interface this product provides a pmbus digital interface that enables the user to con? gure many aspects of the device operation as well as to moni- tor the input and output voltages, output current and device tem- perature. the product can be used with any standard two-wire i2c or smbus host device. in addition, the product is compatible with pmbus version 1.1 and includes an salert line to help mitigate bandwidth limitations related to continuous fault monitoring. the product sup- ports 100 khz bus clock frequency only. the pmbus signals, scl, sda and salert require passive pull-up resistors as stated in the smbus speci? cation. pull-up resistors are required to guarantee the rise time as follows: eq. 6. ? = r p c p 1s, where r p is the pull-up resistor value and c p is the bus loading, the maximum allowed bus load is 400 pf. the pull-up resistor should be tied to an external supply voltage in range from 2.7 to 5.5 v, which should be present prior to or during power-up. if the proper power supply is not available, voltage dividers may be applied. note that in this case, the resistance in the equation above corresponds to parallel connection of the resistors forming the voltage divider. monitoring via pmbus it is possible to monitor a wide variety of parameters through the pmbus interface. fault conditions can be monitored using the salert pin, which will be asserted when any number of pre-con? gured fault or warning conditions occurs. it is also possible to continuously moni- tor one or more of the power conversion parameters including but not limited to the following: ? ? input voltage (read_vin) ? ? output voltage (read_vout) ? ? output current (read_iout) ? ? internal junction temperature (read_temperature_1) ? ? switching frequency (read_frequency) ? ? duty cycle (read_duty_cycle) in the default con? guration monitoring is enabled also when the output voltage is disabled. this can be changed in order to reduce standby power consumption. snap shot parameter capture this product offers a special feature that enables the user to capture parametric data during normal operation or following a fault. the fol- lowing parameters are stored: ? ? input voltage ? ? output voltage ? ? output current ? ? internal junction temperature ? ? switching frequency ? ? duty cycle ? ? status registers user nvm factory default customizable ram restore_default_all default nvm factory default write-protected read write pmbus interface store_user_all initialization initialization restore user all okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 29 of 38 www.murata-ps.com/support
reserved addresses address 4bh is allocated for production needs and cannot be used. addresses listed in the table below are reserved or assigned according to the smbus speci? cation and may not be usable. refer to the smbus speci? cation for further information. address (decimal) comment 0 general call address / start byte 1 cbus address 2 address reserved for different bus format 3-7 reserved for future use 8 smbus host 9-11 assigned for smart battery 12 smbus alert response address 40 reserved for access.bus host 44-45 reserved by previous versions of the smbus speci? cation 55 reserved for access.bus default address 64-68 reserved by previous versions of the smbus speci? cation 72-75 unrestricted addresses 97 smbus device default address 120-123 10-bit slave addressing 124-127 reserved for future use i 2 c/smbus C timing the setup time, tset, is the time data, sda, must be stable before the rising edge of the clock signal, scl. the hold time thold, is the time data, sda, must be stable after the rising edge of the clock signal, scl. if these times are violated incorrect data may be captured or meta-stability may occur and the bus communication may fail. when con? guring the product, all standard smbus protocols must be fol- lowed, including clock stretching. refer to the smbus speci? cation, for smbus electrical and timing requirements. this product does not support the busy ? ag in the status commands to indicate product being too busy for smbus response. instead a bus- free time delay according to this speci? cation must occur between every smbus transmission (between every stop & start condition). in case of storing the ram content into the internal non-volatile memory (commands store_user_all and store_default_all) an addi- tional delay of 100 ms has to be inserted. a 100 ms delay should be inserted after a restore from internal non-volatile memory (commands restore_default_all and restore_user_all). ? gure below. recommended resistor values for hard-wiring pmbus addresses are shown in the table. 1% tolerance resistors are required. index r sa [k] index r sa [k] 0 10 13 34.8 1 11 14 38.3 2 12.1 15 42.2 3 13.3 16 46.4 4 14.7 17 51.1 5 16.2 18 56.2 6 17.8 19 61.9 7 19.6 20 68.1 8 21.5 21 75 9 23.7 22 82.5 10 26.1 23 90.9 11 28.7 24 100 12 31.6 the pmbus address follows the equation below: eq. 7. pmbus address (decimal) = 25 x (sa1 index) + (sa0 index) the user can theoretically con? gure up to 625 unique pmbus addresses, however the pmbus address range is inherently limited to 128. therefore, the user should use index values 0 - 4 on the sa1 pin and the full range of index values on the sa0 pin, which will provide 125 device address combinations. the user shall also be aware of further limitations of the address space as stated in the smbus speci? cation. note that address 0x4b is allocated for production needs and cannot be used. optional pmbus addressing alternatively the pmbus address can be de? ned by connecting the sa0/sa1 pins according to the table below. sa1 = open for products with no sa1 pin. sa0 low open high sa1 low 20h 21h 22h open 23h 24h 25h high 26h 27h reserved low = shorted to pref open = high impedance high = logic high, gnd as reference, logic high de? nitions see electrical speci? cation sa0 sa1 pref r sa1 r sa0 schematic of connection of address resistor. setup and hold times timing diagram okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 30 of 38 www.murata-ps.com/support
designation cmd impl ton_rise 61h yes toff_delay 64h yes toff_fall 65h yes ton_max_fault_limit 62h no status commands (read only) clear_faults 03h yes status_byte 78h yes status_word 79h yes status_vout 7ah yes status_iout 7bh yes status_input 7ch yes status_temperature 7dh yes status_cml 7eh yes status_mfr_specific 80h yes monitor commands (read only read_vin 88h yes read_vout 8bh yes read_iout 8ch yes read_temperature_1 8dh yes read_temperature_2 8eh no read_fan_speed_1 90h no read_duty_cycle 94h yes read_frequency 95h yes group commands interleave 37h yes phase_control f0h yes identi? cation commands pmbus_revision 98h yes mfr_id 99h yes mfr_model 9ah yes mfr_revision 9bh yes mfr_location 9ch yes mfr_date 9dh yes mfr_serial 9eh yes supervisory commands store_default_all 11h yes restore_default_all 12h yes store_user_all 15h yes restore_user_all 16h yes product speci? c commands output commands xtemp_scale d9h no xtemp_offset dah no time setting commands power_good_delay d4h yes fault limit commands iout_avg_oc_fault_limit e7h yes iout_avg_uc_fault_limit e8h yes fault response commands mfr_iout_oc_fault_response e5h yes mfr_iout_uc_fault_response e6h yes ovuv_config d8h yes con? guration and control commands mfr_config d0h yes user_config d1h yes misc_config e9h yes track_config e1h yes pid_taps d5h yes pid_taps_calc * f2h yes inductor d6h yes nlr_config d7h yes pmbus commands the products are pmbus compliant. the following table lists the implemented pmbus read commands. for more detailed information see pmbus power system management protocol speci? cation; part i C general requirements, transport and electrical interface and pmbus power system management protocol; part ii C command language. designation cmd impl standard pmbus commands control commands page 00h no operation 01h yes on_off_config 02h yes write_protect 10h no output commands vout_mode (read only) 20h yes vout_command 21h yes vout_trim 22h yes vout_cal_offset 23h yes vout_max 24h yes vout_margin_high 25h yes vout_margin_low 26h yes vout_transition_rate 27h yes vout_droop 28h yes max_duty 32h yes frequency_switch 33h yes vin_on 35h no vin_off 36h no iout_cal_gain 38h yes iout_cal_offset 39h yes vout_scale_loop 29h no vout_scale_monitor 2ah no coefficients 30h no fault limit commands power_good_on 5eh yes power_good_off 5fh no vout_ov_fault_limit 40h yes vout_ov_warn_limit 42h no vout_uv_warn_limit 43h no vout_uv_fault_limit 44h yes iout_oc_fault_limit 46h yes iout_oc_warn_limit 4ah no iout_uc_fault_limit 4bh yes ot_fault_limit 4fh yes ot_warn_limit 51h yes ut_warn_limit 52h yes ut_fault_limit 53h yes vin_ov_fault_limit 55h yes vin_ov_warn_limit 57h yes vin_uv_warn_limit 58h yes vin_uv_fault_limit 59h yes fault response commands vout_ov_fault_response 41h yes vout_uv_fault_response 45h yes ot_fault_response 50h yes ut_fault_response 54h yes vin_ov_fault_response 56h yes vin_uv_fault_response 5ah yes iout_oc_fault_response 47h no iout_uc_fault_response 4ch no time setting commands ton_delay 60h yes okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 31 of 38 www.murata-ps.com/support
designation cmd impl tempco_config dch yes iout_omega_offset beh yes deadtime ddh yes deadtime_config deh yes deadtime_max bfh yes snapshot eah yes snapshot_control f3h yes device_id e4h yes user_data_00 b0h yes group commands sequence e0h yes gcb_config d3h yes gcb_group e2h yes ishare_config d2h yes phase_control f0h yes supervisory commands private_password fbh yes public_password fch yes unprotect fdh yes security_level fah yes notes: cmd is short for command. impl is short for implemented. okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 32 of 38 www.murata-ps.com/support
mechanical specifications-through-hole mount all component placements ? whether shown as physical components or symbolical outline ? are for reference only and are subject to change throughout the product?s life cycle, unless explicitly described and dimensioned in this drawing. okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 33 of 38 www.murata-ps.com/support
mechanical specifications-surface mount all component placements ? whether shown as physical components or symbolical outline ? are for reference only and are subject to change throughout the product?s life cycle, unless explicitly described and dimensioned in this drawing. okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 34 of 38 www.murata-ps.com/support
mechanical specifications-sip version all component placements ? whether shown as physical components or symbolical outline ? are for reference only and are subject to change throughout the product?s life cycle, unless explicitly described and dimensioned in this drawing. okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 35 of 38 www.murata-ps.com/support
soldering information - surface mounting and hole mount through pin in paste assembly the product is intended for forced convection or vapor phase re? ow soldering in snpb or pb-free processes. the re? ow pro? le should be optimised to avoid excessive heating of the product. it is recommended to have a suf? ciently extended preheat time to ensure an even temperature across the host pwb and it is also recommended to minimize the time in re? ow. a no-clean ? ux is recommended to avoid entrapment of cleaning ? uids in cavities inside the product or between the product and the host board, since cleaning residues may affect long time reliability and isolation voltage. general reflow process specifications snpb eutectic pb-free average ramp-up (t product ) 3c/s max 3c/s max typical solder melting (liquidus) temperature t l 183c 221c minimum re? ow time above t l 60 s 60 s minimum pin temperature t pin 210c 235c peak product temperature t product 225c 260c average ramp-down (t product ) 6c/s max 6c/s max maximum time 25c to peak 6 minutes 8 minutes minimum pin temperature recommendations pin number 2b is chosen as reference location for the minimum pin temperature recommendation since this will likely be the coolest solder joint during the re? ow process. snpb solder processes for snpb solder processes, a pin temperature (tpin) in excess of the solder melting temperature, (t l , 183c for sn63pb37) for more than 60 seconds and a peak temperature of 220c is recommended to ensure a reliable solder joint. for dry packed products only: depending on the type of solder paste and ? ux system used on the host board, up to a recommended maximum temperature of 245c could be used, if the products are kept in a controlled environment (dry pack handling and storage) prior to assembly. lead-free (pb-free) solder processes for pb-free solder processes, a pin temperature (t pin ) in excess of the solder melting temperature (t l , 217 to 221c for snagcu solder alloys) for more than 60 seconds and a peak temperature of 245c on all solder joints is recommended to ensure a reliable solder joint. maximum product temperature requirements top of the product pwb near pin 10b is chosen as reference location for the maximum (peak) allowed product temperature (t product ) since this will likely be the warmest part of the product during the re? ow process. snpb solder processes for snpb solder processes, the product is quali? ed for msl 1 accord- ing to ipc/jedec standard j std 020c. during re? ow t product must not exceed 225 c at any time. pb-free solder processes for pb-free solder processes, the product is quali? ed for msl 3 according to ipc/jedec standard j-std-020c. during re? ow t product must not exceed 260 c at any time. dry pack information products intended for pb-free re? ow soldering processes are delivered in standard moisture barrier bags according to ipc/jedec standard j std 033 (handling, packing, shipping and use of moisture/ re? ow sensitivity surface mount devices). using products in high temperature pb-free soldering processes requires dry pack storage and handling. in case the products have been stored in an uncontrolled environment and no longer can be considered dry, the modules must be baked according to j std 033. thermocoupler attachment t product maximum t pin minimum time n i p profile product profile t l time in reflow time in preheat / soak zone time 25c to peak temperature pin 10b for measurement of maximum product temperature t product pin 2b for measurement of minimum pin (solder joint) temperature t pin okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 36 of 38 www.murata-ps.com/support
soldering information - hole mounting the hole mounted product is intended for plated through hole mount- ing by wave or manual soldering. the pin temperature is speci? ed to maximum to 270c for maximum 10 seconds. a maximum preheat rate of 4c/s and maximum preheat tempera- ture of 150c is suggested. when soldering by hand, care should be taken to avoid direct contact between the hot soldering iron tip and the pins for more than a few seconds in order to prevent overheating. a no-clean ? ux is recommended to avoid entrapment of cleaning ? uids in cavities inside the product or between the product and the host board. the cleaning residues may affect long time reliability and isolation voltage. delivery package information the products are delivered in antistatic carrier tape (eia 481 standard). carrier tape specifications material antistatic ps surface resistance <10 7 ohm/square bakeability the tape is not bakable tape width, w 56 mm [2.20 inch] pocket pitch, p 1 32 mm [1.26 inch] pocket depth, k 0 13 mm [0.51 inch] reel diameter 381 mm [15 inch] reel capacity 130 products /reel reel weight 1.8 kg/full reel okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 37 of 38 www.murata-ps.com/support
soldering information - hole mounting (sip version) the product is intended for plated through hole mounting by wave or manual soldering. the pin temperature is speci? ed to maximum to 270c for maximum 10 seconds. a maximum preheat rate of 4c/s and maximum preheat tempera- ture of 150c is suggested. when soldering by hand, care should be taken to avoid direct contact between the hot soldering iron tip and the pins for more than a few seconds in order to prevent overheating. a no-clean ? ux is recommended to avoid entrapment of cleaning ? uids in cavities inside the product or between the product and the host board. the cleaning residues may affect long time reliability and isolation voltage. delivery package information (sip version) the products are delivered in antistatic trays. tray specifications material antistatic polyethylene foam surface resistance 10 5 < ohms/square <10 11 bakability the trays are not bakeable tray thickness 15 mm [0.709 inch] box capacity 100 products, 2 full trays/box) tray weight 35 g empty tray, 549 g full tray okdx-t/40-w12-xxx-c 40a digital pol dc-dc converter series mdc_okdx-t/40-w12-xxx-c.a05 page 38 of 38 www.murata-ps.com/support murata power solutions, inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained her ein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to cha nge without notice. ? 2016 murata power solutions, inc. murata power solutions, inc. 11 cabot boulevard, mans? eld, ma 02048-1151 u.s.a. iso 9001 and 14001 registered this product is subject to the following operating requirements and the life and safety critical application sales policy: refer to: http://www.murata-ps.com/requirements/

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