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1 40a drmos power module with integrated diode emulation and thermal warning output isl99140 the isl99140 is a high performance drmos power module designed for high frequency po wer conversion. by combining a high performance fet driver and mosfets in an advanced package, high density dc/dc converters may be created. combined with an intersil pwm controller, a complete voltage regulator solution can be created with reduced external components and minimum overall pcb real estate. the isl99140 features a three-state pwm input that, working together with intersil?s multiphase pwm controllers, will provide a robust solution in the event of abnormal operating conditions. to further support robust applications, the isl99140 features a thermal warning output that may be used to notify the power system of an impending thermal fail event. the isl99140 supports high effici ency operation not only at heavy loads, but also at ligh t loads via its diode emulation capability. diode emulation can be disabled for those applications where variable frequency operation is not desired at light loads. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? features ? compliant with intel drmos rev 4.0 specifications ? 40a average output current capability ? supports 3-state 3.3v pwm input ? supports 2-state 5v pwm input ? thermal warning output ? diode emulation option ? adaptive shoot-through protection ? integrated high-side gate-to-sour ce resistor to prevent self turn-on due to high input bus dv/dt ? undervoltage lockout ? switching frequencies up to 2mhz ? pb-free (rohs compliant) ?6x6 qfn package applications ? high frequency and high efficiency vrm and vrd ? core, graphic, and memory regulators for microprocessors ? high density vr for server, ne tworking and cloud computing ? pol dc/dc converters and video gaming consoles figure 1. simplified application block diagram intersil controller pwm phase boot +5v en thdn shoot through protection logic control en vcc pvcc pvcc agnd pgnd vin +12v gnd smod l out v out c out caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. may 5, 2014 fn8642.0
isl99140 2 fn8642.0 may 5, 2014 submit document feedback pin configuration isl99140 (40 ld qfn) top view ordering information part number ( notes 1, 2, 3 )part marking temp range (c) package (pb-free) pkg. dwg. # ISL99140IRZ 99140 irz -40 to +85 40 ld exposed pad 6x6 qfn l40.6x6a notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see product information page for isl99140 . for more information on msl, please see tech brief tb363 . 10987654321 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 pwm en thdn gnd gl sw sw sw sw sw vin vin vin vin sw pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw vin vin vin phase gh agnd boot pvcc vcc smod vin pad2 agnd pad1 sw pad3
isl99140 3 fn8642.0 may 5, 2014 submit document feedback pin descriptions pin # pin name description 1 smod input pin to enable or disable di ode emulation with built-in pull up of 10 a. when smod is low, diode emulation is allowed. otherwise, continuous conduction mode is forced. 2 vcc +5v logic bias supply. place a high quality low esr ceramic capacitor from this pin to gnd. 3 pvcc +5v driver bias supply. place a high quality low esr ceramic capacitor from this pin to gnd. vcc and pvcc often share the decoupling capacitor (~1 f/0402~0603/ x5r~x7r). 4 boot floating bootstrap supply pin for the upper gate drive. place a high quality low esr ceramic capacitor (~0.1 f to 0.22 f) in close proximity across boot and phase pins. 5, 37, pad1 agnd, gnd return of logic bias supply vcc. connect directly to system ground plane. 6 gh high-side gate drive output for monitoring/testing. no circuit connection needed. 7 phase return of bootstrap capacitor. internally connected to sw node. external connection is not needed. 8, 9, 10, 11, 12, 13, 14, pad2 vin input of power stage. pl ace couple high quality low esr ceramic capacitor (couple 10 f or higher, x7r) in close proximity across vin and gnd planes. 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 pgnd power stage return. connect directly to system ground plane. 15, 29, 30, 31, 32, 33, 34, 35, pad3 sw switching junction node between low and high-side mosfets. connect directly to output inductor. 36 gl low-side gate drive output for monitori ng/testing. no circuit connection needed. 38 thdn thermal warning flag, an output open drain pin. high = normal operation; low = shutdown. 39 en enable input pin with 2 a internal weak pull-down. high = enable; low = disable. 40 pwm pwm input of gate driver. the pwm signal can enter three distinct states during operation. connect this pin to the pwm output of the controller. functional block diagram gh boot thdn shoot through protection en vcc pvcc pvcc vin 20 k pwm logic por pwm zero detect sw pgnd gl smod agnd sw pgnd phase gl gh thermal monitor 12.5 k 29.16 k 500 k
isl99140 4 fn8642.0 may 5, 2014 submit document feedback typical application circuit with isl6388 ntc1 network is not needed if tms is used for vr1, gpu vcc imon svdata vr_rdy rset load vinf en_pwr_cfp isl6388 +5v sm_pm_i2da vr_hot# svclk svalert# vinf vin isenin+ isenin- r isenin1 tm_en_otp +5v ntc r isenin2 cfp r senin auto gnd sm_pm_i2clk vrsel_addr nvm_bank_bt sm_pmalert# +5v 2x isen1- isen1+ pwm1 +5v vcc boot phase vinf pwm isl99140 ug lg isen4- isen4+ pwm4 +5v vcc boot phase vinf pwm isl99140 ug lg isen3- isen3+ pwm3 +5v vcc boot phase vinf pwm isl99140 ug lg isen6- isen6+ pwm6 +5v vcc boot phase vinf pwm isl99140 ug lg isen2,5- isen2,5+ pwm2,5 vsen vsen_ovp rgnd
isl99140 5 fn8642.0 may 5, 2014 submit document feedback typical application circuit with zl8800 v in v out c out zl8800 pwmh0 pwmh1 v in vdd sda scl pg en sgnd dgnd pwml0 pwml1 ddc 10.8 to 13.2v isena0 isenb0 isena1 isenb1 inter-device coordination (optional) pmbus (optional) control and status u3 isl99140 vin pgnd boot pvcc u2 vcc agnd sw pwm en c8 c2 c3 1f 0.1f c9 cin1 cin2 l2 c1 r1 r2 l1 sync vsen0n vsen0p 10f 10f 10f c10 c11 v25 v5 v6 r11 r12 r13 sa vset0 uvlo r14 1 m iinp iinn r10 sync r9 10 k v5 isl99140 vin pgnd boot pvcc u1 vcc agnd sw pwm en c5 0.1 f thdn smod thdn smod phase phase 5v 5v 1f c4 1f c7 ?? ??
isl99140 6 fn8642.0 may 5, 2014 submit document feedback / absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 30v supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v i/o voltage (v en , v pwm , v smod, v thdn ). . . . . . . . . . . -0.3v to vcc + 0.3v boot voltage (v boot-gnd ) . . . . . . . . . . -0.3v to 25v (dc) or 36v (<200ns) boot to phase voltage (v boot-phase ). . . . . . . . . . . . . . . . -0.3v to 7v (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 9v (<10ns) thermal resistance ? ja (c/w) ? jc (c/w) 40 ld 6x6 qfn package ( notes 4 , 5 ). . . . . 50 5 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c maximum operating junction temperature . . . . . . . . . . . . . . . . . . +125c supply voltage, vcc, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% input supply voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 18v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fea tures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. jedec class ii pulse conditions and failure criterion used. electrical specifications t a = +25c; v in = 12v, v vcc = v pvcc = 5v unless otherwise noted. boldface limits apply across the recommended operating temperature range . parameter symbol test conditions min ( note 7 )typ max ( note 7 )units supply current v cc standby supply bias current i vcc en = low, v vcc = 5v 187 a en = high, v pwm = open 467 a en = high, v pwm = 0v 664 a pvcc supply bias current i pvcc en = high, v pwm = 300khz, 50% duty cycle 23 ma en = high, v pwm = 1mhz, 50% duty cycle 51 ma power-on reset and enable por rising threshold v porr 3.40 3.9 v por falling threshold v porf 2.3 2.92 v por hysteresis v porh 570 mv en high threshold v enh 2.0 v en low threshold v enl 0.8 v en pull down current i enl 2a pwm input pull-up impedance 29.1 k pull-down impedance 12.5 k pwm rising threshold v pwmh v vcc = 5v 1.70 2.05 2.35 v pwm falling threshold v pwml v vcc = 5v 0.75 1.00 1.25 v pwm tri-state rising threshold v trih v vcc = 5v 1.10 1.32 1.50 v pwm tri-state falling threshold v tril v vcc = 5v 1.60 1.75 1.95 v pwm tri-state rising hysteresis v trrh v vcc = 5v 310 mv pwm tri-state falling hysteresis v trfh v vcc = 5v 310 mv
isl99140 7 fn8642.0 may 5, 2014 submit document feedback switching time gh turn-on propagation delay t pdhu v vcc = 5v, see figure 2 (gl low to gh high) 15 ns gh turn-off propagation delay t pdlu v vcc = 5v, see figure 2 (pwm low to gh low) 18 ns gl turn-on propagation delay t pdhl v vcc = 5v, see figure 2 (gh low to gl high) 20 ns gl turn-off propagation delay t pdll v vcc = 5v, see figure 2 (pwm high to gl low) 18 ns gh/gl exit tri state propagation delay t pdts v vcc = 5v, see figure 2 (tri-state to gh/gl high) 20 ns tri-state shutdown hold-off time t tsshd v vcc = 5v, see figure 2 75 150 225 ns minimum gl on-time in dcm t lgmin v vcc = 5v 350 ns smod input smod high threshold v smodh 2.0 v smod low threshold vsmodl 0.8 v smod pin pull-up current ismod 10 a thermal shutdown (thdn) pull-down impedance 1ma 60 output low 1ma 70 mv thermal shutdown flag set ( note 8 ) 150 c thermal shutdown flag clear ( note 8 ) 135 c hysteresis ( note 8 )15c notes: 7. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. 8. limits established by characteriza tion and are not production tested. electrical specifications t a = +25c; v in = 12v, v vcc = v pvcc = 5v unless otherwise noted. boldface limits apply across the recommended operating temperature range . (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl99140 8 fn8642.0 may 5, 2014 submit document feedback operation the isl99140 is an optimized driver and power stage solution for high density synchronous dc\dc power conversion. the isl99140 includes a high performance driver, integrated schottky bootstrap diode and mosfet pair optimized for high switching frequency buck voltage regulators. the isl99140 includes a driver with advanced power management features that allow direct control of th e lower mosfet, diode emulation and thermal protection. power-on reset (por) and en during initial start-up, the v cc voltage rise is monitored. once the rising v cc voltage exceeds 3.5v (typic ally), normal operation of the driver is enabled. if v cc drops below the falling threshold of 2.95v (typically), operation of the driver is disabled. should the en pin be pulled low, the driver will immediately force both mosfets to their off states. this action does not depend on the state of the pwm input. shoot-through protection prior to v cc exceeding its por level, the undervoltage protection function is activated and both gh and gl are held active low (off). once the v cc voltage surpasses the ri sing threshold (see ?electrical specifications? on page 6) the pwm, smod and de signals are used to control both high-side and low-side mosfets. the rising edge on pwm initiates the turn-off of the lower mosfet. adaptive shoot-through circuitry monitors the gl voltage and determines a safe time for the upper mosfet to turn-on. this prevents the mosfet?s from conducting simultaneously. the falling pwm transition causes the upper fet to turn-off and the lower fet to turn-on. adaptive shoot-through circuitry monitors the gh to sw voltage to determine a safe time for low-side mosfet turn-on. this prevents the mosfet?s from conducting simultaneously. should the driver have no bias voltage applied and be unable to actively hold the mosfets off, an integrated 20k ? resistor from the upper mosfet gate-to-source will aid in keeping the device in its off state. this can be especial ly critical in applications where the input voltage rises prior to the isl99140 v cc /pvcc supplies. tri-state pwm input the isl99140 supports a tri-level input on the pwm pin. should the pin be pulled into and remain in the tri-state window for a set holdoff time, the driver will force both mosfets to their off states. when the pwm signal moves outside the shutdown window, the driver immediatel y resumes driving the mosfets according to the pwm commands. this feature is utilized by intersil pwm controllers as a method of forcing both mosfets off. should the pwm input be left floating, the pin will be pulled into the tri- state window internally and force both mosfets to a safe off state. the isl99140?s tri-state levels are compatible with 3.3v pwm logic. although pwm input can sustain as high as v cc , the isl99140 is not compatible with a controller (such as isl637x family) that actively drives its mid level in tri-state higher than 1.7v. however, figure 2. timing diagram pwm ugate lgate t fl t pdhu t pdll t rl t tsshd t pdts t pdts t fu t ru t pdlu t pdhl t tsshd table 1. gate drive truth table enable smod pwm gl gh lx x l l hl l h* l hl h l h hh l h l hh h l h note: the lg stays high until inductor current drops to zero.
isl99140 9 fn8642.0 may 5, 2014 submit document feedback the isl99140 can be configured to be compatible with zl8800 by connecting pwmh to pwm and pwml to en, as shown in ? typical application circuit with zl8800 ? on page 5 . in this example, the tri-state operation is controlled by pwml output of zl8800 through isl99140?s en input. for detailed design information, consult the zl8800 datasheet. diode emulation diode emulation allows for higher converter efficiency under light load situations. with diode emulation active (smod pulled low), the isl99140 will detect the zero current crossing of the output inductor and turn off the low-side gate after the minimum lgate on time of 350ns expires. this ensures that discontinuous conduction mode (dcm) is achiev ed to minimize losses. diode emulation is asynchronous to the pwm signal. therefore, the isl99140 will respond to the smod input immediately after it changes state. bootstrap function the isl99140 features an internal bootstrap schottky diode. a high quality ceramic capacitor should be place in close proximity across boot and phase pins. the bootstrap capacitor can range between 0.1f~0.22f/0402~0603/x5r~x7r for normal buck switching applications. thermal shutdown warning (thdn) the thdn pin is an open drain output and is pulled low when the internal junction temperatur e exceeds +150c. the isl99140 does not stop operation when the flag is set. this signal is often fed back to the controller to issue a system thermal shutdown. when the junction temperature drops below +135c, the device will clear the thdn signal. pcb layout considerations proper pcb layout will reduce noise coupling to other circuits, improve thermal performance, and maximize the efficiency. the following is meant to lead to an optimized layout: ? place multiple 10f or greater ceramic capacitors directly at device between v in and pgnd as indicated in figure 3 . this is the most critical decoupling an d reduced parasitic inductance in the power switching loop. this will reduce overall electrical stress on the device as well as reduce coupling to other circuits. best practice is to place the decoupling capacitors on the same pcb side as the device. ? connect pgnd to the system gnd plane with a large via array as close to the pgnd pins as design rules allow. this improves thermal and electrical performance. ?place pvcc, v cc and boot-phase decoupling capacitors at the ic pins as shown in figure 3 . ? note that the sw plane connecting the isl99140 and inductor must carry full load current and will create resistive loss if not sized properly. however, it is also a very noisy node that should not be oversized or routed close to any sensitive signals. best practice is to place the inductor as close to the device as possible and thus minimizing the required area for the sw connection. if one must choose a long route of either the v out side of the inductor or the sw side, choose the quiet v out side. best practice is to locate the isl99140 as close to the final load as possible and thus avoid noisy or lossy routes to the load. table 2. available evaluation boards evaluation boards description smbus/ pmbus/i 2 c isl6388eval1z 6-phase core vr with isl99140, 6x6 drmos, and th e isl6388, eapp digital controller; socket r3 yes isl6398eval1z 3-phase pol vr with isl99140, 6x6 drmos, and the isl638 8, eapp digital controller; on-board transient load yes
isl99140 10 fn8642.0 may 5, 2014 submit document feedback figure 3. pcb layout for minimizing current loops
isl99140 11 fn8642.0 may 5, 2014 submit document feedback typical performance characteristics figure 4. 1.0v v out power stage efficiency (v in = 12v, v cc =p vcc =5v; l out = 0.23 h, 0.23m , slc1175-231; include inductor and isl99140 losses) figure 5. 1.8v v out power stage efficiency (vin = 12v, v cc =p vcc = 5v; l out = 0.23 h, 0.23m , slc1175-231; include inductor and isl99140 losses) figure 6. 1.0v v out power stage dissipation (v in = 12v, v cc =p vcc = 5v; l out = 0.23 h, 0.23m , slc1175-231; include inductor and isl99140 loss) figure 7. 1.8v v out power stage dissipation (v in = 12v, v cc = pvcc = 5v; l out = 0.23 h, 0.23m , slc1175-231; include inductor and isl99140 losses) 300khz 600khz 800khz output current (a) efficiency (%) 800khz 300khz 600khz output current (a) efficiency (%) 800khz 300khz 600khz power loss (w) output current (a) power loss (w) output current (a) 800khz 300khz 600khz
isl99140 12 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8642.0 may 5, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change may 5, 2014 fn8642.0 initial release.
isl99140 13 fn8642.0 may 5, 2014 submit document feedback package outline drawing l40.6x6a 40 lead thin quad flat no-lead plastic package rev 0, 3/14 11 21 1 31 20 30 40 d/2 d 2 index area (d/2 x e/2) b a e/2 e a3 top view 2x 2x aaa c 10 seating plane c 40 x b a side view 4 c bbb m a b 3 ddd c a1 a3 ccc c 11 21 1 31 20 30 10 40 pin #1 ida d1 d2 d1 l1 l1 e e/2 l5 l5 l c0.30 x 45 bottom view l2 e1 e1 e2 l6 l l3 l4 coplanarity applies to the terminals and all other measured between 0.20mm and 0.35mm from the dimension b applies to metallized terminal and is the location of the terminal #1 identifier and 4. 3. 2. dimensions are in millimeters. 1. notes: e aaa c terminal numbering convention conforms to terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b bottom surface metallization. dimensions in millimeters symbols min typ max 0.73 l3 0.26 0.21 0.15 l2 0.25 0.20 0.15 l1 0.80 0.05 0.75 0.02 2.00 0.70 0.00 a a1 e d2 d1 6.00 bsc bbb aaa l a3 0.20 ref 0.35 0.25 0.20 b 0.50 0.40 0.30 0.50 bsc d6.00 bsc e1 ccc ddd 0.15 0.10 0.10 0.08 1.40 1.60 1.50 e 1.90 2.10 4.30 4.40 4.50 e2 2.17 2.37 2.27 0.83 0.63 0.54 l4 0.64 0.44 0.37 l6 0.47 0.27 0.40 l5 0.50 0.30 should not be measured in that radius area. jedec publication 95 spp-002.
isl99140 14 fn8642.0 may 5, 2014 submit document feedback 0.30 x 45 0.73 1.50 0.52 0.21 2.23 2.27 2.20 4.40 2.00 2.00 0.20 0.50 ref 0.37 0.55 0.54 recommended land pattern 0.25 0.25 0.40 0.20 2.87 2.87 2.87 2.87 0.75 dimensions are in millimeters. 1. note:

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