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dallas semiconductor preliminary quad t1/e1 transceiver (5v)quad t1/e1 transceiver (3.3v) ds21q552/ds21q554ds21q352/ds21q354 december 29, 1998 features p four (4) completely independent t1 or e1 transceivers in one small 27mm x 27mm package each transceiver contains a short & long haul line interface plus a full featured framer with alarm detection/generation, elastic stores, hardware based signaling support, per ds0 channel control and hdlc controller each multi-chip module (mcm) contains four die of: ds21352 (ds21q352) ds21552 (ds21q552) ds21354 (ds21q354) ds21554 (ds21q554) selection guide: supply device t1 3.3v ds21q352 t1 5v ds21q552 e1 3.3v ds21q354 e1 5v ds21q554 see the specific ds21352/ds21552 and ds21354/ds21554 data sheets for details on their feature set and operation all four t1 or e1 transceivers can be concatenated into a single 8.192mhz backplane data stream ieee 1149.1 jtag-boundary scan architecture ds21q352/ds21q552 and ds21q354/ds21q554 are pin compatible to allow the same footprint to support t1 and e1 applications 256?lead mcm bga package (27mm x 27mm) low power 5v cmos or low power 3.3v cmos with 5vtolerant input & outputs descriptionthe quad t1 and e1 transceiver mcms offer a high density packaging arrangement for the ds21352/ds21552 t1 single-chip transceivers and the ds21354/ds21554 e1 single-chip transceivers.four silicon die of one of these devices is packaged in a multi-chip module (mcm) with the electrical connections as shown in figure 1. all of the functions available on the ds21352/ds21552 and ds21354/ds21554 are also available in the mcm packaged version however in order to minimize package size , some signals have been deleted. these differences are detailed in table 1. this data sheet describes the electrical connections and the mechanical dimensions only. please see theds21352/ds21552 and ds21354/ds21554 data sheets for full details on all of the features and the operating characteristics of the device. downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 2 changes from normal ds21q352/ds21q552 & ds21q354/ds21q554 configuration table 1 1. the following signals are not available : xtald / 8xclk / teso / tdata / rcl / rdata ds21q352 / ds21q552 / ds21q354 / ds21q554 schematic figure 1 rclk ci rlos/lotc 8mclk rlink rlclk rchblk rchclk rsig tssync tsysclk tser tsig rmsymc tclk jtdo jtdi jtclk jtms jtrst int* d0/ad0 to d7/ad7 a0 to a7/ale rd* wr* btscs* mux test signals not connected & left open circuited include: 8xclk / xtald / rdata / rcl sct # 1 ds21352 / ds21552 / ds21354 / ds21554 8 8 rsigf rtiprring ttip tring rser rsysclk rsync co tchblk tchclk tlink tlclk liuc mclk rfsync teso tdata tsync rclkorposo rnego rnegi rposi rclkitclko tclki tposotnego tposi tnegi fms see connecting page dvss rvsstvss dvddtvdd rvdd downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 3 ds21q352 / ds21q552 / ds21q354 / ds21q554 schematic figure 1 (continued) rclk ci rlos/lotc 8mclk rlink rlclk rchblk rchclk rsig tssync tsysclk tser tsig rmsymc tclk jtdo jtdi jtclk jtms jtrst int* d0/ad0 to d7/ad7 a0 to a7/ale rd* wr* btscs* mux test signals not connected & left open circuited include: 8xclk / xtald / rdata / rcl sct # 2 ds21352 / ds21552 / ds21354 / ds21554 rsigf rtiprring ttip tring rser rsysclk rsync co tchblk tchclk tlink tlclk liuc mclk rfsync teso tdata tsync rclkorposo rnego rnegi rposi rclkitclko tclki tposotnego tposi tnegi fms see connecting page see connecting page dvss rvsstvss dvddtvdd rvdd downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 4 ds21q352 / ds21q552 / ds21q354 / ds21q554 schematic figure 1 (continued) rclk ci rlos/lotc 8mclk rlink rlclk rchblk rchclk rsig tssync tsysclk tser tsig rmsymc tclk jtdo jtdi jtclk jtms jtrst int* d0/ad0 to d7/ad7 a0 to a7/ale rd* wr* btscs* mux test signals not connected & left open circuited include: 8xclk / xtald / rdata / rcl sct # 3 ds21352 / ds21552 / ds21354 / ds21554 rsigf rtiprring ttip tring rser rsysclk rsync co tchblk tchclk tlink tlclk liuc mclk rfsync teso tdata tsync rclkorposo rnego rnegi rposi rclkitclko tclki tposotnego tposi tnegi fms see connecting page see connecting page dvss rvsstvss dvddtvdd rvdd downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 5 ds21q352 / ds21q552 / ds21q354 / ds21q554 schematic figure 1 (continued) rclk ci rlos/lotc 8mclk rlink rlclk rchblk rchclk rsig tssync tsysclk tser tsig rmsymc tclk jtdo jtdi jtclk jtms jtrst int* d0/ad0 to d7/ad7 a0 to a7/ale rd* wr* btscs* mux test signals not connected & left open circuited include: 8xclk / xtald / rdata / rcl sct # 4 ds21352 / ds21552 / ds21354 / ds21554 rsigf rtiprring ttip tring rser rsysclk rsync co tchblk tchclk tlink tlclk liuc mclk rfsync teso tdata tsync rclkorposo rnego rnegi rposi rclkitclko tclki tposotnego tposi tnegi fms see connecting page dvss rvsstvss dvddtvdd rvdd downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 6 lead description sorted by symbol table 2 lead symbol i/o description m1 8mclk1 o 8.192 mhz clock based on rclk1. h17 8mclk2 o 8.192 mhz clock based on rclk2. f4 8mclk3 o 8.192 mhz clock based on rclk3. v13 8mclk4 o 8.192 mhz clock based on rclk4. u3 a0 i address bus bit 0 (lsb). l17 a1 i address bus bit 1. v2 a2 i address bus bit 2. t4 a3 i address bus bit 3. v8 a4 i address bus bit 4. h4 a5 i address bus bit 5. u8 a6 i address bus bit 6. p4 a7/ale i address bus bit 7 (msb) / address latch enable. p2 bts i bus type select (0 = intel / 1 = motorola), w6 ci1 i carry input for interleaved bus operation for sct1. f18 ci2 i carry input for interleaved bus operation for sct2. d7 ci3 i carry input for interleaved bus operation for sct3. t20 ci4 i carry input for interleaved bus operation for sct4. v9 co1 o carry output for interleaved bus operation for sct1. b17 co2 o carry output for interleaved bus operation for sct2. a6 co3 o carry output for interleaved bus operation for sct3. j20 co4 o carry output for interleaved bus operation for sct4. p3 cs1* i chip select for sct1. a14 cs2* i chip select for sct2. b5 cs3* i chip select for sct3. k17 cs4* i chip select for sct4. u11 d0/ad0 i/o data bus bit 0/ address/data bus bit 0 (lsb). j19 d1/ad1 i/o data bus bit 1/ address/data bus bit 1. w15 d2/ad2 i/o data bus bit 2/address/data bus bit 2. u7 d3/ad3 i/o data bus bit 3/address/data bus bit 3. u9 d4/ad4 i/o data bus bit 4/address/data bus bit 4. u5 d5/ad5 i/o data bus bit 5/address/data bus bit 5. v4 d6/ad6 i/o data bus bit 6/address/data bus bit 6. u4 d7/ad7 i/o data bus bit 7/address/data bus bit 7 (msb). j3 dvdd1 ? digital positive supply. n4 dvdd1 ? digital positive supply. u2 dvdd1 ? digital positive supply. v5 dvdd1 ? digital positive supply. b12 dvdd2 ? digital positive supply. c12 dvdd2 ? digital positive supply. c16 dvdd2 ? digital positive supply. d18 dvdd2 ? digital positive supply. a9 dvdd3 ? digital positive supply. b3 dvdd3 ? digital positive supply. b6 dvdd3 ? digital positive supply. c4 dvdd3 ? digital positive supply. g20 dvdd4 ? digital positive supply. m17 dvdd4 ? digital positive supply. m20 dvdd4 ? digital positive supply. p18 dvdd4 ? digital positive supply. h3 dvss1 ? digital signal ground. j4 dvss1 ? digital signal ground. u6 dvss1 ? digital signal ground. w8 dvss1 ? digital signal ground. downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 7 a17 dvss2 ? digital signal ground. a20 dvss2 ? digital signal ground. b11 dvss2 ? digital signal ground. c13 dvss2 ? digital signal ground. a5 dvss3 ? digital signal ground. b7 dvss3 ? digital signal ground. b9 dvss3 ? digital signal ground. c3 dvss3 ? digital signal ground. h20 dvss4 ? digital signal ground l20 dvss4 ? digital signal ground n17 dvss4 ? digital signal ground u13 dvss4 ? digital signal ground u1 int* o interrupt for all four scts. y15 jtclk i jtag clock. n1 jtdi i jtag data input. h18 jtdo2 o jtag data output from sct2. v17 jtdo3 o jtag data output from sct3. v19 jtdo4 o jtag data output from sct4. w13 jtms i jtag test mode select. v18 jtrst* i jtag reset. k2 liuc i line interface connect for all four scts. t1 mclk1 i master clock for sct1 and sct3. w20 mclk2 i master clock for sct2 and sct4. u10 mux i mux bus select. m2 rchblk1 o receive channel block for sct1. g17 rchblk2 o receive channel block for sct2. g4 rchblk3 o receive channel block for sct3. y12 rchblk4 o receive channel block for sct4. j1 rchclk1 o receive channel clock for sct1. d14 rchclk2 o receive channel clock for sct2. f3 rchclk3 o receive channel clock for sct3. u14 rchclk4 o receive channel clock for sct4. n3 rclk1 o receive clock output from the framer on sct1. b13 rclk2 o receive clock output from the framer on sct2. e3 rclk3 o receive clock output from the framer on sct3. m18 rclk4 o receive clock output from the framer on sct4. m4 rclki1 i receive clock input for the liu on sct1. a15 rclki2 i receive clock input for the liu on sct2. a4 rclki3 i receive clock input for the liu on sct3. r17 rclki4 i receive clock input for the liu on sct4. m3 rclko1 o receive clock output from the liu on sct1. c14 rclko2 o receive clock output from the liu on sct2. b4 rclko3 o receive clock output from the liu on sct3. t17 rclko4 o receive clock output from the liu on sct4. n2 rd*(ds*) i read input (data strobe) k4 rfsync1 o receive frame sync (before the receive elastic store) for sct1. d17 rfsync2 o receive frame sync (before the receive elastic store) for sct2. a2 rfsync3 o receive frame sync (before the receive elastic store) for sct3. v14 rfsync4 o receive frame sync (before the receive elastic store) for sct4. f1 rlclk1 o receive link clock for sct1. a12 rlclk2 o receive link clock for sct2. d3 rlclk3 o receive link clock for sct3. k18 rlclk4 o receive link clock for sct4. g2 rlink1 o receive link data for sct1. a13 rlink2 o receive link data for sct2. a3 rlink3 o receive link data for sct3. u12 rlink4 o receive link data for sct4. downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 8 h2 rlos/lotc1 o receive loss of sync / loss of transmit clock for sct1. e17 rlos/lotc2 o receive loss of sync / loss of transmit clock for sct2. e1 rlos/lotc3 o receive loss of sync / loss of transmit clock for sct3. v11 rlos/lotc4 o receive loss of sync / loss of transmit clock for sct4. l1 rmsync1 o receive multiframe sync for sct1. d16 rmsync2 o receive multiframe sync for sct2. f2 rmsync3 o receive multiframe sync for sct3. w16 rmsync4 o receive multiframe sync for sct4. r3 rnegi1 i receive negative data for the framer on sct1. d13 rnegi2 i receive negative data for the framer on sct2. a1 rnegi3 i receive negative data for the framer on sct3. p17 rnegi4 i receive negative data for the framer on sct4. l3 rnego1 o receive negative data from the liu on sct1. b15 rnego2 o receive negative data from the liu on sct2. c2 rnego3 o receive negative data from the liu on sct3. u17 rnego4 o receive negative data from the liu on sct4. r4 rposi1 i receive positive data for the framer on sct1. b14 rposi2 i receive positive data for the framer on sct2. b2 rposi3 i receive positive data for the framer on sct3. v15 rposi4 i receive positive data for the framer on sct4. l4 rposo1 o receive positive data from the liu on sct1. a16 rposo2 o receive positive data from the liu on sct2. b1 rposo3 o receive positive data from the liu on sct3. u15 rposo4 o receive positive data from the liu on sct4. y11 rring1 i receive analog ring input for sct1. y14 rring2 i receive analog ring input for sct2. y17 rring3 i receive analog ring input for sct3. y20 rring4 i receive analog ring input for sct4. j2 rser1 o receive serial data for sct1. d15 rser2 o receive serial data for sct2. e2 rser3 o receive serial data for sct3. w17 rser4 o receive serial data for sct4. l2 rsig1 o receive signaling output for sct1. b16 rsig2 o receive signaling output for sct2. c1 rsig3 o receive signaling output for sct3. y18 rsig4 o receive signaling output for sct4. k1 rsigf1 o receive signaling freeze output for sct1. c15 rsigf2 o receive signaling freeze output for sct2. d2 rsigf3 o receive signaling freeze output for sct3. v16 rsigf4 o receive signaling freeze output for sct4. g1 rsync1 i/o receive sync for sct1. d12 rsync2 i/o receive sync for sct2. d1 rsync3 i/o receive sync for sct3. v12 rsync4 i/o receive sync for sct4. h1 rsysclk1 i receive system clock for sct1. f17 rsysclk2 i receive system clock for sct2. g3 rsysclk3 i receive system clock for sct3. w14 rsysclk4 i receive system clock for sct4. y10 rtip1 i receive analog tip input for sct1. y13 rtip2 i receive analog tip input for sct2. y16 rtip3 i receive analog tip input for sct3. y19 rtip4 i receive analog tip input for sct4. p1 rvdd1 ? receive analog positive supply. j17 rvdd2 ? receive analog positive supply. e4 rvdd3 ? receive analog positive supply. w18 rvdd4 ? receive analog positive supply. r2 rvss1 ? receive analog signal ground downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 9 t2 rvss1 ? receive analog signal ground h19 rvss2 ? receive analog signal ground j18 rvss2 ? receive analog signal ground d4 rvss3 ? receive analog signal ground d5 rvss3 ? receive analog signal ground v20 rvss4 ? receive analog signal ground w19 rvss4 ? receive analog signal ground w1 tchblk1 o transmit channel block for sct1. f20 tchblk2 o transmit channel block for sct2. c11 tchblk3 o transmit channel block for sct3. u20 tchblk4 o transmit channel block for sct4. v10 tchclk1 o transmit channel clock for sct1. a18 tchclk2 o transmit channel clock for sct2. b8 tchclk3 o transmit channel clock for sct3. l18 tchclk4 o transmit channel clock for sct4. y9 tclk1 i transmit clock for sct1. b19 tclk2 i transmit clock for sct2. b10 tclk3 i transmit clock for sct3. m19 tclk4 i transmit clock for sct4. v6 tclki1 i transmit clock input for the liu on sct1. d19 tclki2 i transmit clock input for the liu on sct2. c8 tclki3 i transmit clock input for the liu on sct3. p20 tclki4 i transmit clock input for the liu on sct4. w7 tclko1 o transmit clock output from the framer on sct1. e18 tclko2 o transmit clock output from the framer on sct2. a7 tclko3 o transmit clock output from the framer on sct3. p19 tclko4 o transmit clock output from the framer on sct4. u16 test i test (0 = normal operation / 1 = tri-state all outputs). v3 tlclk1 o transmit link clock for sct1. e20 tlclk2 o transmit link clock for sct2. d6 tlclk3 o transmit link clock for sct3. t18 tlclk4 o transmit link clock for sct4. w5 tlink1 i transmit link data for sct1. e19 tlink2 i transmit link data for sct2. c6 tlink3 i transmit link data for sct3. t19 tlink4 i transmit link data for sct4. r1 tnegi1 i transmit negative data input for the liu on sct1. f19 tnegi2 i transmit negative data input for the liu on sct2. d8 tnegi3 i transmit negative data input for the liu on sct3. r20 tnegi4 i transmit negative data input for the liu on sct4. t3 tnego1 o transmit negative data output from framer on sct1. b20 tnego2 o transmit negative data output from framer on sct2. d9 tnego3 o transmit negative data output from framer on sct3. n20 tnego4 o transmit negative data output from framer on sct4. w3 tposi1 i transmit positive data input for the liu on sct1. c20 tposi2 i transmit positive data input for the liu on sct2. a8 tposi3 i transmit positive data input for the liu on sct3. r19 tposi4 i transmit positive data input for the liu on sct4. v7 tposo1 o transmit positive data output from framer on sct1. c19 tposo2 o transmit positive data output from framer on sct2. c9 tposo3 o transmit positive data output from framer on sct3. n19 tposo4 o transmit positive data output from framer on sct4. y2 tring1 o transmit analog ring output for sct1. y4 tring2 o transmit analog ring output for sct2. y6 tring3 o transmit analog ring output for sct3. y8 tring4 o transmit analog ring output for sct4. w9 tser1 i transmit serial data for sct1. downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 10 c17 tser2 i transmit serial data for sct2. c10 tser3 i transmit serial data for sct3. k20 tser4 i transmit serial data for sct4. w10 tsig1 i transmit signaling input for sct1. c18 tsig2 i transmit signaling input for sct2. a10 tsig3 i transmit signaling input for sct3. l19 tsig4 i transmit signaling input for sct4. w12 tssync1 i transmit system sync for sct1. b18 tssync2 i transmit system sync for sct2. d10 tssync3 i transmit system sync for sct3. k19 tssync4 i transmit system sync for sct4. v1 tsync1 i/o transmit sync for sct1. d20 tsync2 i/o transmit sync for sct2. c7 tsync3 i/o transmit sync for sct3. r18 tsync4 i/o transmit sync for sct4. w11 tsysclk1 i transmit system clock for sct1. a19 tsysclk2 i transmit system clock for sct2. a11 tsysclk3 i transmit system clock for sct3. n18 tsysclk4 i transmit system clock for sct4. y1 ttip1 o transmit analog tip output for sct1. y3 ttip2 o transmit analog tip output for sct2. y5 ttip3 o transmit analog tip output for sct3. y7 ttip4 o transmit analog tip output for sct4. w2 tvdd1 ? transmit analog positive supply. g19 tvdd2 ? transmit analog positive supply. d11 tvdd3 ? transmit analog positive supply. u19 tvdd4 ? transmit analog positive supply. w4 tvss1 ? transmit analog signal ground. g18 tvss2 ? transmit analog signal ground. c5 tvss3 ? transmit analog signal ground. u18 tvss4 ? transmit analog signal ground. k3 wr* (r/w*) i write input (read/write). downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 11 ds21q352 / ds21q552 / ds21q354 / ds21q554 pcb land pattern figure 2 the diagram shown below is the lead pattern that will be placed on the target pcb. this is the samepattern that would be seen as viewed through the mcm from the top. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a rneg i 3 rf sync 3 rlink 3 rclk i 3 dvss 3 co 3 tclko 3 tpos i 3 dvdd 3 tsig 3 tsys clk 3 rlclk 3 rlink 2 cs 2* rclki 2 rpos o2 dvss 2 tch clk 2 tsys clk 2 dvss 2 b rpos o3 rposi 3 dvdd 3 rclk o3 cs 3* dvdd 3 dvss 3 tch clk 3 dvss 3 tclk 3 dvss 2 dvdd 2 rclk 2 rpos i 2 rneg o2 rsig 2 co 2 ts sync 2 tclk 2 tneg o2 c rsig 3 rneg o3 dvss 3 dvdd 3 tvss 3 tlink 3 tsync 3 tclk i 3 tpos o3 tser 3 tch blk 3 dvdd 2 dvss 2 rclk o2 rsigf 2 dvdd 2 tser 2 tsig 2 tpos o2 tpos i 2 d rsync 3 rsigf 3 rlclk 3 rvss 3 rvss 3 tlclk 3 ci 3 tneg i 3 tneg o3 ts sync 3 tvdd 3 rsync 2 rneg i 2 rch clk 2 rser 2 rm sync 2 rf sync 2 dvdd 2 tclk i 2 tsync 2 e rlos 3 rser 3 rclk 3 rvdd 3 rlos 2 tclk o2 tlink 2 tlclk 2 f rlclk 1 rm sync 3 rch clk 3 8m clk 3 rsys clk 2 ci 2 tneg i 2 tch blk 2 g rsync 1 rlink 1 rsys clk 3 rch blk 3 rch blk 2 tvss 2 tvdd 2 dvdd 4 h rsys clk 1 rlos 1 dvss 1 a5 8m clk 2 jtdo 2 rvss 2 dvss 4 j rch clk 1 rser 1 dvdd 1 dvss 1 rvdd 2 rvss 2 d1/ ad1 co 4 k rsigf 1 liuc wr* rf sync 1 cs 4* rlclk 4 ts sync 4 tser 4 l rm sync 1 rsig 1 rneg o1 rpos o1 a1 tch clk 4 tsig 4 dvss 4 m 8m clk 1 rch blk 1 rclk o1 rclk i 1 dvdd 4 rclk 4 tclk 4 dvdd 4 n jtdi rd* rclk 1 dvdd 1 dvss 4 tsys clk 4 tpos o4 tneg o4 p rvdd 1 bts cs 1* a7/ ale rneg i 4 dvdd 4 tclk o4 tclk i 4 r tneg i 1 rvss 1 rneg i 1 rpos i 1 rclk i 4 tsync 4 tpos i 4 tneg i 4 t mclk 1 rvss 1 tneg o1 a3 rclk o4 tlclk 4 tlink 4 ci 4 u int* dvdd 1 a0 d7/ ad7 d5/ ad5 dvss 1 d3/ ad3 a6 d4/ ad4 mux d0/ ad0 rlink 4 dvss 4 rch clk 4 rpos o4 test rneg o4 tvss 4 tvdd 4 tch blk 4 v tsync 1 a2 tlclk 1 d6/ ad6 dvdd 1 tclk i 1 tpos o1 a4 co 1 tch clk 1 rlos 4 rsync 4 8m clk 4 rf sync 4 rpos i 4 rsigf 4 jtdo3 jtrst* jtdo4 rvss 4 w tch blk 1 tvdd 1 tpos i 1 tvss 1 tlink 1 ci 1 tclk o1 dvss 1 tser 1 tsig 1 tsys clk 1 ts sync 1 jtms rsys clk 4 d2/ ad2 rm sync 4 rser 4 rvdd 4 rvss 4 mclk 2 y ttip 1 tring 1 ttip 2 tring 2 ttip 3 tring 3 ttip 4 tring 4 tclk 1 rtip 1 rring 1 rch blk 4 rtip 2 rring 2 jtclk rtip 3 rring 3 rsig 4 rtip 4 rring 4 downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 12 power supply de-couplingin a typical pcb layout for the ds21x5y, all of the vdd pins will connect to a common power plane and all the vss lines will connect to a common ground plane. there are three recommended methods for de- coupling shown below in both schematic and pictorial form. as shown in the pictorials, the capacitors should be symmetrically located about the device. the first shown in figure 3 uses standard capacitors, two 33uf tantalums, two .33uf ceramics and two .01uf ceramics. the second method shown in figure 4 uses a single 68uf tantalum, two .33uf ceramics and two .01uf ceramics. the third method shown in figure5 uses only four capacitors, two 1.5uf mlc and two .01uf ceramics. the 1.5uf is an mlc (multi layer ceramic) type. the mlc construction is a low inductance type, which allows a smaller value ofcapacitance to be used. since vdd and vss signals will typically pass vertically to the power and ground planes of a pcb, the de-coupling caps must be placed as close to the ds21qx5y as possible and routed vertically to power and ground planes. de-coupling scheme using standard tantalum caps . figure 3 de-coupling scheme using single 68uf cap . figure 4 de-coupling scheme using mcl caps . figure 5 all capacitor values in figures 3 , 4 and 5 are in uf. 33 .33 .01 33 .33 .01 vdd vdd ds21qx5y .01 .01 .33 .33 33 33 ds21qx5y .01 .01 vdd vdd ds21qx5y 1.5 1.5 .01 .01 1.5 1.5 ds21qx5y .33 .01 .33 vdd vdd ds21qx5y 68 .01 .01 .01 .33 .33 68 ds21qx5y downloaded from: http:///
dallas semiconductor ds21q352/ds21q552/ds21q354/ds21q554 preliminary data sheet december 29, 1998 13 ds21q352 / ds21q552 / ds21q354 / ds21q554 mechanical dimensions downloaded from: http:///

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