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? semiconductor components industries, llc, 2012 january, 2012 ? rev. 0 1 publication order number: cav25010/d cav25010, cav25020, cav25040 1-kb, 2-kb and 4-kb spi serial cmos eeprom description the cav25010/20/40 are 1 ? kb/2 ? kb/4 ? kb serial cmos eeprom devices internally organized as 128x8/256x8/512x8 bits. they feature a 16 ? byte page write buffer and support the serial peripheral interface (spi) protocol. the device is enabled through a chip select (cs ) input. in addition, the required bus signals are a clock input (sck), data input (si) and data output (so) lines. the hold input may be used to pause any serial communication with the cav25010/20/40 device. these devices feature software and hardware write protection, including partial as well as full array protection. features ? automotive temperature grade 1 ( ? 40 c to +125 c) ? 10 mhz spi compatible ? 2.5 v to 5.5 v supply voltage range ? spi modes (0,0) & (1,1) ? 16 ? byte page write buffer ? self ? timed w rite cycle ? hardware and software protection ? block write protection ? protect 1/4, 1/2 or entire eeprom array ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature range ? soic and tssop 8 ? lead packages ? these devices are pb ? free, halogen free/bfr free, and rohs compliant si so cav25010 cav25020 cav25040 sck v ss v cc cs wp hold figure 1. functional symbol http://onsemi.com pin configuration si hold v cc v ss wp so cs 1 see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ordering information soic ? 8 v suffix case 751bd sck soic (v), tssop (y) tssop ? 8 y suffix case 948al chip select cs serial data output so write protect wp ground v ss serial data input si serial clock sck function pin name pin function hold transmission input hold power supply v cc for the location of pin 1, please consult the corresponding package drawing.
cav25010, cav25020, cav25040 http://onsemi.com 2 marking diagrams 25010e = cav25010 25020e = cav25020 25040e = cav25040 a = assembly location y = production year (last digit) m = production month (1 ? 9, o, n, d) xxx = last three digits of xxx = assembly lot number = pb ? free package 25xx0e aymxxx s01e = cav25010 s02e = cav25020 s04e = cav25040 a = assembly location y = production year (last digit) m = production month (1 ? 9, o, n, d) xxx = last three digits of xxx = assembly lot number = pb ? free package sxxe aymxxx (soic ? 8) (tssop ? 8) table 1. absolute maximum ratings parameters ratings units operating temperature ? 45 to +130 c storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to v cc + 0.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program / erase cycles t dr data retention 100 years table 3. d.c. operating characteristics ( v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter test conditions min max units i ccr supply current (read mode) read, v cc = 5.5 v, 10 mhz, so open 2 ma i ccw supply current (write mode) write, v cc = 5.5 v, 10 mhz, so open 2 ma i sb1 standby current v in = gnd or v cc , cs = v cc , wp = v cc , v cc = 5.5 v 2 a i sb2 standby current v in = gnd or v cc , cs = v cc , wp = gnd, v cc = 5.5 v 5 a i l input leakage current v in = gnd or v cc ? 2 2 a i lo output leakage current cs = v cc , v out = gnd or v cc ? 1 2 a v il input low voltage ? 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 3.0 ma 0.4 v v oh output high voltage i oh = ? 1.6 ma v cc ? 0.8 v v table 4. pin capacitance (note 2) (t a = 25 c, f = 1.0 mhz, v cc = +5.0 v) symbol test conditions min typ max units c out output capacitance (so) v out = 0 v 8 pf c in input capacitance (cs , sck, si, wp , hold ) v in = 0 v 8 pf 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c.
cav25010, cav25020, cav25040 http://onsemi.com 3 table 5. a.c. characteristics (t a = ? 40 c to +125 c) (note 4) symbol parameter v cc = 2.5 v ? 5.5 v units min max f sck clock frequency dc 10 mhz t su data setup time 10 ns t h data hold time 10 ns t wh sck high time 40 ns t wl sck low time 40 ns t lz hold to output low z 25 ns t ri (note 5) input rise time 2 s t fi (note 5) input fall time 2 s t hd hold setup time 0 ns t cd hold hold time 10 ns t v output valid from clock low 35 ns t ho output hold time 0 ns t dis output disable time 20 ns t hz hold to output high z 25 ns t cs cs high time 40 ns t css cs setup time 30 ns t csh cs hold time 30 ns t cns cs inactive setup time 20 ns t cnh cs inactive hold time 20 ns t wps wp setup time 10 ns t wph wp hold time 10 ns t wc (note 6) write cycle time 5 ms 4. ac test conditions: input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 10 ns input and output reference voltages: 0.5 v cc output load: current source i ol max /i oh max ; c l = 30 pf 5. this parameter is tested initially and after a design or process change that affects the parameter. 6. t wc is the time from the rising edge of cs after a valid write sequence to the end of the internal write cycle. table 6. power ? up timing (notes 7, 8) symbol parameter min max units t pur power ? up to read operation 0.1 1 ms t puw power ? up to write operation 0.1 1 ms 7. this parameter is tested initially and after a design or process change that affects the parameter. 8. t pur and t puw are the delays required from the time v cc is stable at the operating voltage until the specified operation can be initiated.
cav25010, cav25020, cav25040 http://onsemi.com 4 pin description si: the serial data input pin accepts op ? codes, addresses and data. in spi modes (0,0) and (1,1) input data is latched on the rising edge of the sck clock input. so: the serial data output pin is used to transfer data out of the device. in spi modes (0,0) and (1,1) data is shifted out on the falling edge of the sck clock. sck: the serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and cav25010/20/40. cs : the chip select input pin is used to enable/disable the cav25010/20/40. when cs is high, the so output is tri ? stated (high impedance) and the device is in standby mode (unless an internal write operation is in progress). every communication session between host and cav25010/20/40 must be preceded by a high to low transition and concluded with a low to high transition of the cs input. wp : the write protect input pin will allow all write operations to the device when held high. when wp pin is tied low all write operations are inhibited. hold : the hold input pin is used to pause transmission between host and cav25010/20/40, without having to retransmit the entire sequence at a later time. to pause, hold must be taken low and to resume it must be taken back high, with the sck input low during both transitions. when not used for pausing, the hold input should be tied to v cc , either directly or through a resistor. functional description the cav25010/20/40 devices support the serial peripheral interface (spi) bus protocol, modes (0,0) and (1,1). the device contains an 8 ? bit instruction register. the instruction set and associated op ? codes are listed in t able 7. reading data stored in the cav25010/20/40 is accomplished by simply providing the read command and an address. writing to the cav25010/20/40, in addition to a write command, address and data, also requires enabling the device for writing by first setting certain bits in a status register, as will be explained later. after a high to low transition on the cs input pin, the cav25010/20/40 w ill accept any one of the six instruction op ? codes listed in table 7 and will ignore all other possible 8 ? bit combinations. the communication protocol follows the timing from figure 2. table 7. instruction set (note 9) instruction opcode operation wren 0000 0110 enable write operations wrdi 0000 0100 disable write operations rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 x011 read data from memory write 0000 x010 write data to memory 9. x = 0 for cav25010, cav25020. x = a8 for cav25040 figure 2. synchronous data timing cs sck si so t cnh t css t wh t wl t su t h hi ? z valid in valid out t csh t ri t fi t v t v t ho t cns t cs hi ? z t dis status register the status register, as shown in table 8, contains a number of status and control bits. the rdy (ready) bit indicates whether the device is busy with a write operation. this bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. for the host, this bit is read only. the wel (write enable latch) bit is set/reset by the wren/wrdi commands. when set to 1, the device is in a write enable state and when set to 0, the device is in a w rite disable state. the bp0 and bp1 (block protect) bits determine which blocks are currently write protected. they are set by the user with the wrsr command and are non ? volatile. the user is allowed to pr otect a quarter, one half or the entire memory, by setting these bits according to table 9. the protected blocks then become read ? only.
cav25010, cav25020, cav25040 http://onsemi.com 5 table 8. status register 7 6 5 4 3 2 1 0 1 1 1 1 bp1 bp0 wel rdy table 9. block protection bits status register bits array address protected protection bp1 bp0 0 0 none no protection 0 1 cav25010: 060 ? 07f, cav25020: 0c0 ? 0ff, cav25040: 180 ? 1ff quarter array protection 1 0 cav25010: 040 ? 07f, cav25020: 080 ? 0ff, cav25040: 100 ? 1ff half array protection 1 1 cav25010: 000 ? 07f, cav25020: 000 ? 0ff, cav25040: 000 ? 1ff full array protection write operations the cav25010/20/40 device powers up into a write disable state. the device contains a write enable latch (wel) which must be set before attempting to write to the memory array or to the status register. in addition, the address of the memory location(s) to be written must be outside the protected area, as defined by bp0 and bp1 bits from the status register. write enable and write disable the internal write enable latch and the corresponding status register wel bit are set by sending the wren instruction to the cav25010/20/40. care must be taken to take the cs input high after the wren instruction, as otherwise the write enable latch will not be properly set. wren timing is illustrated in figure 3. the wren instruction must be sent prior to any write or wrsr instruction. the internal write enable latch is reset by sending the wrdi instruction as shown in figure 4. disabling write operations by resetting the wel bit, will protect the device against inadvertent writes. figure 3. wren timing sck si so 00000 110 high impedance dashed line = mode (1, 1) cs figure 4. wrdi timing sck si so 00000 100 high impedance dashed line = mode (1, 1) cs
cav25010, cav25020, cav25040 http://onsemi.com 6 byte write once the wel bit is set, the user may execute a write sequence, by sending a write instruction, a 8 ? bit address and data as shown in figure 5. for the cav25040, bit 3 of the write instruction opcode contains a8 address bit. internal programming will start after the low to high cs transition. during an internal write cycle, all commands, except for rdsr (read status register) will be ignored. the rdy bit will indicate if the internal write cycle is in progress (rdy high), or the device is ready to accept commands (rdy low). page write after sending the first data byte to the cav25010/20/40, the host may continue sending data, up to a total of 16 bytes, according to timing shown in figure 6. after each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. if during this process the end of page is exceeded, then loading will ?roll over? to the first byte in the page, thus possibly overwriting previously loaded data. following completion of the write cycle, the cav25010/20/40 is automatically returned to the write disable state. figure 5. byte write timing sck si so 0 0 0 0 x* 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 012345678 opcode data in high impedance byte address 13 14 15 16 17 18 19 20 21 22 23 dashed line = mode (1, 1) * x = 0 for cav25010, cav25020. x = a8 for cav25040 cs a 0 a 7 figure 6. page write timing sck si so 0 0 0 0 x* 0 1 0 byteaddress data byte 1 012345678 131415 16 ? 23 24 ? 31 data byte n opcode 7..1 0 16+(n ? 1)x8 ? 1..16+(n ? 1)x8 16+nx8 ? 1 data in high impedance dashed line = mode (1, 1) * x = 0 for cav25010, cav25020. x = a8 for cav25040 cs a 7 a 0 data byte 3 data byte 2
cav25010, cav25020, cav25040 http://onsemi.com 7 write status register the status register is written by sending a wrsr instruction accor ding to timing shown in figure 7. only bits 2 and 3 can be written using the wrsr command. write protection when wp input is low all write operations to the memory array and status register are inhibited. wp going low while cs is still low will interrupt a write operation. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register or memory array. the wp input timing is shown in figure 8. figure 7. wrsr timing 01 23 45678 10 911121314 sck si msb high impedance data in 15 so 7 6 5 4 3 2 10 0000000 1 opcode dashed line = mode (1, 1) cs figure 8. wp timing sck wp dashed line = mode (1, 1) wp cs t wph t wps
cav25010, cav25020, cav25040 http://onsemi.com 8 read operations read from memory array to read from memory, the host sends a read instruction followed by a 8 ? bit address (for the cav25040, bit 3 of the read instruction opcode contains a8 address bit). after receiving the last address bit, the cav25010/20/40 will respond by shifting out data on th e so pin (as shown in figure 9). sequentially stored data can be read out by simply continuing to run the clock. the internal address pointer is automatically incremented to the next higher address as data is shifted out. after reaching the highest memory address, the address counter ?rolls over? to the lowest memory address, and the read cycle can be continued indefinitely. the read operation is terminated by taking cs high. read status register to read the status register, the host simply sends a rdsr command. after receiving the last bit of the command, the cav25010/20/40 will shift out the contents of the status register on the so pin (figure 10). the status register may be read at any time, including during an internal write cycle. while the internal write cycle is in progress, the rdsr command will output the full content of the status register. for easy detection of the internal write cycle completion, both during writing to the memory array and to the status register, we recommend sampling the rdy bit only through the polling routine. after detecting the rdy bit ?0?, the next rdsr instruction will always output the expected content of the status register. figure 9. read timing sck si so byte address 0123456789 d7 d6 d5 d4 d3 d2 d1 d0 data out msb high impedance opcode 13 12 14 15 16 17 18 19 20 21 22 0 0 0 0 x* 0 1 1 dashed line = mode (1, 1) * x = 0 for cav25010, cav25020. x = a8 for cav25040 a 0 a 7 cs figure 10. rdsr timing 01 2345678 10 911121314 sck si data out msb high impedance opcode so 7 6 5 4 3 2 1 0 00000 1 01 dashed line = mode (1, 1) cs
cav25010, cav25020, cav25040 http://onsemi.com 9 hold operation the hold input can be used to pause communication between host and ca v25010/20/40. to pause, hold must be taken low while sck is low (figure 11). during the hold condition the device must remain selected (cs low). during the pause, the data output pin (so) is tri ? stated (high impedance) and si transitions are ignored. to resume communication, hold must be taken high while sck is low. design considerations the cav25010/20/40 devices incorporate power ? on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi ? directional por behavior protects the device against ?brown ? out? failure following a temporary loss of power. the cav25010/20/40 device powers up in a write disable state and in a low power standby mode. a wren instruction must be issued prior to any writes to the device. after power up, the cs pin must be brought low to enter a ready state and receive an instruction. after a successful byte/page write or status register write, the device goes into a write disable mode. the cs input must be set high after the proper number of clock cycles to start the internal write cycle. access to the memory array during an internal write cycle is ignored and programming is continued. any invalid op ? code will be ignored and the serial output pin (so) will remain in the high impedance state. figure 11. hold timing sck so high impedance dashed line = mode (1, 1) t lz cs hold t cd t hd t hd t cd t hz
cav25010, cav25020, cav25040 http://onsemi.com 10 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cav25010, cav25020, cav25040 http://onsemi.com 11 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cav25010, cav25020, cav25040 http://onsemi.com 12 ordering information device order number specific device marking (note 10) package type temperature range lead finish shipping cav25010ve ? g 25010e soic ? 8, jedec ? 40 c to +125 c nipdau tube, 100 units / tube cav25010ve ? gt3 25010e soic ? 8, jedec ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cav25010ye ? g s01e tssop ? 8 ? 40 c to +125 c nipdau tube, 100 units / tube cav25010ye ? gt3 s01e tssop ? 8 ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cav25020ve ? gt3 25020e soic ? 8, jedec ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cav25020ye ? gt3 s02e tssop ? 8 ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cav25040ve ? g 25040e soic ? 8, jedec ? 40 c to +125 c nipdau tube, 100 units / tube cav25040ve ? gt3 25040e soic ? 8, jedec ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cav25040ye ? gt3 s04e tssop ? 8 ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel 10. specific device marking shows the first row top package marking. 11. all packages are rohs ? compliant (lead ? free, halogen ? free). 12. the standard lead finish is nipdau. 13. for additional package and temperature options, please contact your nearest on semiconductor sales office. 14. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. 15. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor devic e nomenclature document, tnd310/d, available at www.onsemi.com on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cav25010/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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