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prm ? regulator rev 1.2 vicorpower.com page 1 of 23 7/2015 800 735.6200 dc to dc regulator prm ? regulator prm48dh480t250b03 features description ? optimized for vr12.0 ? 48v (38 to 60 v in ), non-isolated zvs buck-boost regulator ? 5 to 55 v adjustable output range ? building block for high efficiency dc-dc systems ? 145w output power in 0.57 in 2 footprint ? 97% typical efficiency, at full load ? 1,342 w/in 3 (82 w/cm 3 ) power density ? enables a 48 v to 1.2 v, 130 a isolated, regulated solution with total footprint of 1.7in 2 (11cm 2 ) ? flexible ?remote sense? architecture optimizes regulation / feedback loop design to fit application requirements ? current feedback signal allows dynamic adjustment of current limit setpoint ? 9.32 mhrs mtbf (mil-hdbk-217plus parts count) typical applications ? high efficiency server processor and memory power ? high density ate system dc-dc power ? telecom npu and asic core power ? led drivers ? high density power supply dc-dc rail outputs ? non-isolated power converters the vi chip prm ? regulator is a high efficiency converter, operating from a 38 to 60 vdc input to generate a regulated 5 to 55 vdc output. the zvs buck ? boost topology enables high switch ing frequency (~1.5 mhz) operation with high conversion efficiency. high switching frequency reduces the size of reactive components enabling power density up to 1,342 w/in 3 . the half vi chip package is co mpatible with standard pick- and-place and surface mount as sembly processes with a planar thermal interface area and superior thermal conductivity. in a factorized power architecture? system, the prm48dh480t250b03 and downstream vtm? transformer minimize distribution and conversion losses in a high power solution. an external control loop and current sensor maintain regulation and enable flexibility both in the design of voltage and current compensation loops to control of output voltages and currents. 48 v to 1.2 v , 130a volta g e re g ulato r
prm ? regulator rev 1.2 vicorpower.com page 2 of 23 7/2015 800 735.6200 prm48dh480t250b03 1.0 absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to device. electrical specifications do not apply when operating beyond rated operating conditions. all voltages are specified relative to sg unless otherwise noted. po sitive pin current represents cu rrent flowing out of the pin. 2.0 electrical characteristics specifications apply over all line and load conditions, t j = 25 oc and output voltage from 20v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of 0 oc < t j < 125 oc.
prm ? regulator rev 1.2 vicorpower.com page 3 of 23 7/2015 800 735.6200 prm48dh480t250b03 3.0 signal characteristics specifications apply over all line and load conditions, t j = 25 oc and output voltage from 20v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of 0 oc < t j < 125 oc.
prm ? regulator rev 1.2 vicorpower.com page 4 of 23 7/2015 800 735.6200 prm48dh480t250b03
prm ? regulator rev 1.2 vicorpower.com page 5 of 23 7/2015 800 735.6200 prm48dh480t250b03 4.0 functional block diagram +vout -vout +vin tm pc temperature dependent voltage source -vin v pc_en 100ua 5v 2ma max 16v internal vcc regulator 3v vref (130c) fault logic t off delay r l overtemperature protection modulator enable q1 q2 q3 q4 cout cin pr 0.5ma 2.5ma min 9v vin (ov, uv) vout (ov) if current limit overcurrent protection v if_il v if_oc 8.2v re 3 v @ 27c re vc vtm vc start up pulse vs 9v 0.01uf sg uc 8051 3.3v linear regulator pc re vout var. vclamp vcc 14v 10ms +vout output discharge (od) 3.3v vcc 3.3v instant latch latch after 120us 2130 pr q q set clr s r 10ua vcc 93.3k pc pr enable
prm ? regulator rev 1.2 vicorpower.com page 6 of 23 7/2015 800 735.6200 prm48dh480t250b03 high level function al state diagram conditions that cause state transitions are shown along arro ws. sub-sequence activities listed inside the state bubbles.
prm ? regulator rev 1.2 vicorpower.com page 7 of 23 7/2015 800 735.6200 prm48dh480t250b03 5.0 timing diagrams module inputs are shown in blue ; module outputs are shown in brown ; timing diagrams assumes the following: ? single prm ? (no array) ? vs powers error amplifier ? re powers voltage reference a nd output current transducer ? i out is sensed, scaled, and fed back to if pin such that if = 2.00 v at full load re v out pc pr v in vc vs tm if input input / output output uv ov vpc_en vpc vvc vpr_max vvs_amb vtm_amb vre_amb t vc vif_oc t blnk 1 start up with 1.2v/ms < dv in /dt < maximum vpr_min t < t blnk ov 2 quick oc (t prm ? regulator rev 1.2 vicorpower.com page 8 of 23 7/2015 800 735.6200 prm48dh480t250b03 input output input / output
prm ? regulator rev 1.2 vicorpower.com page 9 of 23 7/2015 800 735.6200 prm48dh480t250b03 6.0 applications characteristics the following figures present typical performance at t c = 25oc, unless otherwise noted. see associated figures for general trend data. 1.0 2.0 3.0 4.0 38 40 42 44 46 48 50 52 54 56 58 60 power dissipation [w] input voltage [v] no load power dissipation vs. line module enabled - nominal v out -40 oc 25 oc 100 oc t case : figure 1 - no load power dissipation vs. v in , module enabled 0 2 4 6 8 10 12 14 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 00.511.522.533.544.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 20 v t case = -40 oc 38 48 60 38 48 60 v in : figure 3 ? total efficiency and power dissipation vs. v in and i out , v out = 20v, t case = -40oc 0.1 0.2 0.3 0.4 38 40 42 44 46 48 50 52 54 56 58 60 power dissipation [w] input voltage [v] power dissipation vs. line module disabled, pc=low -40 oc 25 oc 100 oc t case : figure 2 - power dissipation vs. v in , module disabled 2 4 6 8 10 12 14 16 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.544.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 48 v t case = -40 oc 38 48 60 38 48 60 v in : figure 4 ? total efficiency and power dissipation vs. v in and i out , v out = 48v, t case = -40oc
prm ? regulator rev 1.2 vicorpower.com page 10 of 23 7/2015 800 735.6200 prm48dh480t250b03 2 4 6 8 10 12 14 16 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 55 v t case = -40 oc 38 48 60 38 48 60 v in : figure 5 ? total efficiency and power dissipation vs. v in and i out , v out = 55v, t case = -40oc 2 4 6 8 10 12 14 16 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.544.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 48 v t case = 25 oc 38 48 60 38 48 60 v in : figure 7 ? total efficiency and power dissipation vs. v in and i out , v out = 48v, t case = 25oc 2 4 6 8 10 12 14 16 18 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.544.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 20 v t case = 100 oc 38 48 60 38 48 60 v in : figure 9 ? total efficiency and power dissipation vs. v in and i out , v out = 20v, t case = 100oc 2 4 6 8 10 12 14 16 18 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.544.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 20 v t case = 25 oc 38 48 60 38 48 60 v in : figure 6 ? total efficiency and power dissipation vs. v in and i out , v out = 20v, t case = 25oc 2 4 6 8 10 12 14 16 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 55 v t case = 25 oc 38 48 60 38 48 60 v in : figure 8 ? total efficiency and power dissipation vs. v in and i out , v out = 55v, t case = 25oc 2 4 6 8 10 12 14 16 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.544.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 48 v t case = 100 oc 38 48 60 38 48 60 v in : figure 10 ? total efficiency and power dissipation vs. v in and i out , v out = 48v, t case = 100oc
prm ? regulator rev 1.2 vicorpower.com page 11 of 23 7/2015 800 735.6200 prm48dh480t250b03 2 4 6 8 10 12 14 16 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00.511.522.533.5 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation v out = 55 v t case = 100 oc 38 48 60 38 48 60 v in : figure 11 ? total efficiency and power dissipation vs. v in and i out , v out = 55v, t case = 100oc figure 13 ? typical output voltage ripple waveform, 200 mv/div, 500 ns/div t case = 30oc, v in = 48v, v out = 48v, i out = 3.2 a, no external output capacitance. 0 2 4 6 8 10 12 400 600 800 1000 1200 1400 1600 38 40 42 44 46 48 50 52 54 56 58 60 total input charge per switching cycle [ ? c] f sw [khz] input voltage [v] powertrain switching frequency and periodic input charge vs. input voltage - full load 20 48 55 20 48 55 v out : ? c f sw figure 15 ? powertrain switching frequency and periodic input charge vs. v in , v out ; i out = 3.2 a 3.15 3.18 2.86 4.32 4.41 4.08 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40-20 0 20406080100 v pr [v] temperature [oc] v pr vs. case temperature v in = 48 v; v out = 48 v 2.0827 4.1673 i out : figure 12 ? typical control node voltage vs. t case , and i out ; v in = 48v, v out = 48v 0 2 4 6 8 10 12 400 600 800 1000 1200 1400 1600 38 40 42 44 46 48 50 52 54 56 58 60 total output charge per switching cycle [ ? c] f sw [khz] input voltage [v] powertrain switching frequency and periodic output charge vs. input voltage - full load 20 48 55 20 48 55 v out : ? c f sw figure 14 ? powertrain switching frequency and periodic output charge vs. v in , v out ; i out = 3.2 a 0 30 60 90 120 150 180 210 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 5 1015202530354045505560 output power [w] output current [a] output voltage [v] dc safe operating area iout continuous iout 5 s pout continuous pout 5 s figure 16 ? dc output safe operating area
prm ? regulator rev 1.2 vicorpower.com page 12 of 23 7/2015 800 735.6200 prm48dh480t250b03 0 50 100 150 200 250 300 350 -6 -4 -2 0 2 4 6 8 00.511.522.533.5 r eq_out [ ? ] g pr [dbs] output current [a] dc modulator gain and powertrain equivalent output resistance vs. output current, v out = 55v 38 45 60 38 45 60 v in : g pr r eq_out figure 17 ? powertrain characteristics vs. i out; resistive load, v out = 55v, various v in 0 50 100 150 200 250 300 350 -6 -4 -2 0 2 4 6 8 00.511.522.533.544.5 r eq_out [ ? ] g pr [dbs] output current [a] dc modulator gain and powertrain equivalent output resistance vs. output current, v out = 48v 38 45 60 38 45 60 v in : r eq_out g pr figure 19 ? powertrain characteristics vs. i out; resistive load, v out = 48v, various v in 0 20 40 60 80 100 120 140 160 180 200 1.5 2.0 2.5 3.0 3.5 4.0 4.5 output power [w] pr voltage [v] output power vs. v pr v in = 48v, v out = 48v, t c =25oc typical min nominal typical max figure 21 ? output power vs. v pr ; v in = 48v, v out = 48v, t case = 25oc -2 11 24 37 50 63 76 89 -4 -2 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 r eq_out [ ? ] g pr [dbs] output current [a] dc modulator gain and powertrain equivalent output resistance vs. output current, v out = 20v 38 45 60 38 45 60 v in : g pr r eq_out figure 18 ? powertrain characteristics vs. i out; resistive load, v out = 20v, various v in 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 10 15 20 25 30 35 40 45 50 55 effective capacitance [ ? f] voltage [v] effective internal capacitance vs. applied voltage, input (c in_int ) and output (c out_int ) figure 20 ? effective internal input and output capacitance vs. voltage ? ceramic type 0 4 8 12 16 20 24 28 32 36 0 0.5 1 1.5 2 2.5 3 3.5 r eq_in [ ? ] output current [a] powertrain equivalent input resistance vs. output current, v out = 55v 38 45 60 v in : figure 22 ? magnitude of powertrain dynamic input impedance vs. v in , i out ; v out = 55v
prm ? regulator rev 1.2 vicorpower.com page 13 of 23 7/2015 800 735.6200 prm48dh480t250b03 0 50 100 150 200 250 300 350 400 00.511.522.533.544.5 r eq_in [ ? ] output current [a] powertrain equivalent input resistance vs. output current, v out = 20v 38 45 60 v in : figure 23 ? magnitude of powertrain dynamic input impedance vs. v in , i out ; v out = 20v 0 5 10 15 20 25 30 35 40 45 00.511.522.533.544.5 r eq_in [ ? ] output current [a] powertrain equivalent input resistance vs. output current, v out = 48v 38 45 60 v in : figure 24 ? magnitude of powertrain dynamic input impedance vs. v in , i out ; v out = 48v 7.0 general characteristics specifications apply over all line and load conditions, t j = 25 oc and output voltage from 20v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of 0 oc < t j < 125 oc. attribute symbol min typ max unit mechanical length l 21.8 / [0.86] 22.0 / [0.87] 22.3 / [0.88] mm / [in] width w 16.3 / [0.64] 16.5 / [0.65] 16.8 / [0.66] mm / [in] height h [0.255] [0.265] [0.275] mm / [in] volume vol 2.44 / [0.15] cm 3 / [in 3 ] weight w 7 g 0.51 2.03 0.02 0.15 0.003 0.050 thermal operating temperature t j 0 125 oc operating case temperature t c 0 100 oc thermal capacity 5 ws/oc assembly 3 lbs 5.33 lbs / in 2 storage temperature t st -40 125 oc esd hbm 1000 esd cdm 400 soldering 245 oc oc maximum time above [ 217] oc 150 s peak heating rate during reflow 1.5 2 oc / s peak cooling rate post reflow 2.5 3 oc / s safety and reliability 5.41 mhrs 6.22 mhrs conditions / notes peak compressive force applied to case (z-axis) supported by j-lead only lead finish v ? m no heatsink any operating condition charged device model, "jedec jesd 22-c101d" gold specifications apply over all line and load conditions, and output voltage from 20v to 55v unless otherwise noted; boldface specifications apply over the temperature range of -40 oc < t j < 125 oc (t-grade) ; all other specifications are at t j = 25 oc unless otherwise noted. general characteristics agency approvals / standards peak temperature during reflow mtbf human body model, "jedec jesd 22-a114c.01" esd rating msl 4 (datecode 1528 and later) nickel palladium ce mark ce marked for low voltage directive and rohs recast directive, as applicable mil-hdbk-217plus parts count - 25c ground benign, stationary, indoors / computer profile telcordia issue 2 - method i case 1; ground benign, controlled c tuv us
prm ? regulator rev 1.2 vicorpower.com page 14 of 23 7/2015 800 735.6200 prm48dh480t250b03 product outline drawing and recommended pcb footprint
prm ? regulator rev 1.2 vicorpower.com page 15 of 23 7/2015 800 735.6200 prm48dh480t250b03 8.0 product details a nd design guidelines 8.1 control pins description and characteristics control node (pr) is the input to the control node which determines the powertrain timing and ultimately the module output power (figure 21). an internal 0.5ma current sink is always active. the bi-directional buffer between pr and the control node has two states. in normal operation, pr will be above the 0.79v switching threshold, and will drive the control node through the buffer. an internal 7.4v clamp determines the maximum output power that can be re quested of the modulator. when pr falls below 0.79 v, the converter will stop switching. an internal circuit clamps the modulator input control node to 0.79 v, and a buffer will source up to 2.5 ma out of the pin at that clam p level. for this reason, the output impedance of the amplif ier driving pr must be taken into account. a rail-to-rail operational amplifier with low output impedance is always recommended. the powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage, as shown in figures 17, 18 and 19. as the load increases, the powertrain pole moves to higher frequency. as a result, the closed loop crossover frequency will be the highest at full load and lowest at minimum load. figure 25 shows a reference ac small-signal model. current feedback (if) is the input for the module output overcurrent protection and current limit features (see functional block diagram in section 4.0). a voltage proportional to the powertrain output current must be applied to if in order for overcurrent protection to operate properly. if the if voltage exceeds the if pin?s overcurrent protection threshold, the powertrain will stop switching. if the if voltage falls below the overcurrent protection threshold within t blank time, then the powertrain will immediately resumes switching. otherwise a fault is latched. the current limit threshold for the if pin is set lower than the protection threshold. w hen the if pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amp lifier which ov errides the modulator input maximum level. this causes the powertrain to maintain a constant output current. the bandwidth of this current limit integrator is significantly slower than that of the pr control node input. therefore this current limit can not be used in lieu of properly compensating the (external) pr control loop to avoid exceeding maximum current or power ratings for the device. if the if pin is not driven, it must be resistively terminated to sg. a 1k ? resistor to sg is recommended in this case. figure 25 ? prm48dh480t250b03 ac small signal model + - v pr g pr c out_int v pr + - i pr_low r pr v ou t + - r eq_out r eq_in v in + - c in_int prm48dh480t250b03 v pr g in
prm ? regulator rev 1.2 vicorpower.com page 16 of 23 7/2015 800 735.6200 prm48dh480t250b03 vtm control (vc) pin supplies an initial v cc voltage to downstream vtms, enabling them and synchronizing their startup with the prm ? . the v cc voltage is a pulse, typically 10 ms duration at 14 v. if vc is not loaded by a vtm, it must be terminated with a 1 k ?? resistor to ?vout. primary control (pc) is both an input and an output. it can provide the following features: ? delayed start: upon application of voltage (>uvlo) to the module power input and after t off , the pc pin will source a constant 90 a current. ? output disable: pc may be pulled down externally in order to disable the module. pull down resistance should be less than 300 to sg. ? fault detection flag: the pc 5 v voltage source is internally turned off when a fault condition is latched. note that aside from the short circuit fault condition, pc does not have significant current sinking capability. therefore in the case of an array of prms with interconnected pc pins, pc does not in general reflect the fault state of all prms. the common pc line will not disable neighboring modules when a fault is detected except for a latched output short circuit fault. conversely any unit in the array latching a short circuit fault will disable the array for t scr . temperature monitor (tm) pin outputs a voltage proportional to the absolute temperature of the converter analog control ic. it can be used to accomplish the following functions: ? monitor the control ic temperature: the gain and setpoint of tm are such that the temperature, in kelvin, of the prm controller ic is equal to the voltage on the tm pin scaled by 100. (i.e. 3.0 v = 300 k = 27 oc). ? closed loop thermal management at the system level (e.g. variable speed fans or coolant flow) ? fault detection flag: the tm voltage source is turned off as soon as a fault is detect ed. for system monitoring purposes (microcontroller interface) faults are detected on falling edges of tm. reference enable (re) pin outputs a regulated 3.3 v, 8 ma voltage source. it is enabled only after successful startup of the prm powertrain (see chapters 5.0 and 6.0.) re is intended to power t he output current transducer and also the voltage reference for the control loop. powering the reference generator with re helps provide a controlled startup, since the output voltage of the system is able to track the reference level as it comes up. voltage source (vs) pin outputs a gated (e.g. mirrors pc status), non-isolated, regulat ed 9 v, 5 ma voltage source. it can be used to power external control circuitry; it always leads re. signal ground (sg) pin provides a kelvin connection to the prm?s internal signal ground. it should be used as the reference for pr, tm, if, and should return all pc, vs and re pin currents. in array configurations with common ground control circuits, a series resistor (~1 ? ) is recommended in order to decouple power and signal current returns. 8.2 control circuit requirements and design procedure the prm48dh480t250b03 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. these two external circuits are illustrat ed in figure 26, which shows an example of the prm in a standalone application with local voltage feedback and high side current sensing. in general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense ic. the following design procedures refer to the circuit shown in figure 26. 8.2.1 setting the output voltage level the output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. with reference to fig. 26, r1 and r2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference ic provides the reference voltage to the positive input of the error amplifier. under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by: 2 2 1 r r r v v ref out ? ? ? note that the component r1 will also factor into the compensation as described in a later section. it is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. the recommended range for reference rise time is 1 ms to 9 ms. the lower rise time limit will ensure optimized modulator timing performance during startup, and to allow the current limit feature (through if pin) to fully protect the device during power-up. the upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream vtm input before the end of the vc pulse.
prm ? regulator rev 1.2 vicorpower.com page 17 of 23 7/2015 800 735.6200 prm48dh480t250b03 8.2.2 setting the output current limit and overcurrent protection level the current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense amplifier. the output of the current sense ic provi des the if voltage which has v if_il and v if_oc thresholds for the two functions respectively. the set points are therefore defined by: cs s il if il g r v i ? ? _ and cs s oc if oc g r v i ? ? _ where g cs is the gain of the current sense amplifier. 8.2.3 control loop compensation requirements in order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. figure 25 shows the ac small signal model for the module. modulator dc gain g pr and powertrain equivalent resistance r eq_out are shown. these modeling parameters will support a design cut-off frequency up to 50 khz. standard bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. the recommended stability criteria are as follows: 1) phase margin > 45o : for the closed loop response, the phase should be greater than 45o where the gain crosses 0db. 2) gain margin > 10db : the closed loop gain should be lower than -10db where the phase crosses 0o. 3) gain slope = -20db / decade : the closed loop gain should have a slope of -20db / decade at the crossover frequency. the compensation characteristics must be selected to meet these stability criteria. refer to figure 27 for a local sense, voltage-mode control example based on the configuration in figure 26. in this example, it is assumed that the maximum crossover frequency (f cmax ) has been selected to occur between b and c. type-2 compensation (curve ijkl) is sufficient in this case. the following data must be gathered in order to proceed: ? modulator gain g pr : see figures 17, 18, 19 ? powertrain equivalent resistance r eq : see figures 17, 18, 19 ? internal output capacitance: see figure 20 ? external output capacitance value in the case of ceramic capacitors, the esr can be considered low enough to push the associated zero well above the frequency of interest. applications with high esr capacitor may require a different type of compensation, or cascade control. the system poles and zeros of the closed loop can then be defined as follows: ? powertrain pole, assuming the external capacitor esr can be neglected: load out eq load out eq c r r r r r ext out ? ? ?? _ _ _ ? main pole frequency: ?? ext out int out load out eq load out eq p c r r r r _ _ _ _ c 2 1 f ? ? ? ? ? ? ? compensation mid-band gain: 1 3 mb r r log 20 g ? [1] ? compensation zero: 1 3 1 z c r 2 1 f ? ? ? [2] ? compensation pole: 2 1 2 1 3 2 2 1 f c c c c r p ? ? ? ? ? and for f p2 >>f z1 (c 1 + c 2 c 1 ): 2 3 2 2 1 f c r p ? ? ? ? [3]
prm ? regulator rev 1.2 vicorpower.com page 18 of 23 7/2015 800 735.6200 prm48dh480t250b03 8.2.4 midband gain design (r1,r3): with reference to figure 27: curve abc is the: ? minimum output voltage in the application ? maximum input voltage expected in the application ? maximum load prm ? open loop response, and is where the maximum crossover frequency occurs. in order for the maximum crossover frequency to occur at the design choice f cmax , the compensation gain must be equal and opposite of the powertrain gain at this freque ncy. for stability purposes, the compensation should be in the mid-band (j-k) at the crossover. using equation [1], the mid-band gain can be selected appropriately. 8.2.5 compensation zero design (c1): with reference to figure 27: curve efg is the: ? maximum output voltage in the application ? minimum input voltage expected in the application ? minimum load in the application prm open loop response, and is where the minimum crossover frequency f cmin occurs. based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore f cmin will occur where efg is equal and opposite of g mb . c1 can be selected using equation [2] so that f z1 occurs prior to f cmin . prm vs pr +in -in if re sg -out +out f1 i sense ic vref + - c2 c1 r3 r1 r2 vref ic vref c in_int c out_int c out_ext c in_ext r s figure 26 ? control circuit example
prm ? regulator rev 1.2 vicorpower.com page 19 of 23 7/2015 800 735.6200 prm48dh480t250b03 open loop gain vs. frequency -40 -20 0 20 40 60 80 frequency (hz) gain (db) prm open loop max load prm open loop min load a b e f i j k l compensation gain 10mhz gbw c g f cmax f cmin figure 27 ? reference asymptotic bode pl ot for the considered system 8.2.6 high frequency pole design (c2): using equation [3], c2 should be selected so that f p2 is at least one decade above f cmax and prior to the gain bandwidth product of the operat ional amplifier (10mhz for this example). for applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. 8.2.7 verifying stability: the preferred method for veri fying stability is to use a network analyzer, measuring the closed loop response across various lines and load conditions. in the absence of a network analyzer, a load step transient response can be used in order to estimate stability. figure 28 illustrates an exampl e of a load step response. equation [4] can be used to predict the phase margin based on the ratio of the ?kick? to ?droop? (as defined in fig. 28). figure 28 ? load step response example and ?droop? vs. ?kick? definition
prm ? regulator rev 1.2 vicorpower.com page 20 of 23 7/2015 800 735.6200 prm48dh480t250b03 2 2 2 ln ln 100 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d k d k m [4] 8.3 burst mode operation: at light loads, the prm ? will operate in a burst mode due to minimum timing constraints. an example burst operation waveform is illustrated in figure 29. for very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. in this case the external error amplifier will periodically drive pr below the switching threshold in order to maintain regulation. switching will cease momentarily until the error amplifier once again drives pr volt age above the threshold. figure 29 ? light load burst mode of operation note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. the variability depends on many factors including input voltage, output voltages, load impedance, and external error amplifier output impedance. in burst mode, the gain of the pr input to the plant which is modeled in the previous sections is time varying. therefore the small signal analysis can not be directly applied to burst mode operation. 8.4 input and output filter design figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the prm at full load under various input and output voltages conditions. figure 20 provides the effective internal capacitance of the module. a conservative estimate of input and output peak- peak voltage ripple at nominal line and trim is provided by equation [5]: ext int sw fl tot c c f i q v ? ? ? ? ? 4 . 0 [5] q tot is the total input (fig. 15) or output (fig. 14) charge per switching cycle at full load, while c int is the module internal effective capacitance at the considered voltage (fig. 20) and c ext is the external effective capacitance at the considered voltage. 8.5 input filter stability the prm can provide very high dynamic transients. it is therefore very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. for this purpose, the converter dynamic input impedance magnitude in eq r _ is provided in figures 22, 23, 24. it is recommended to provide adequate design margin with respect to the st ability conditions illustrated in 10.5.1 and 10.5.2. 8.5.1 inductive source and local, external input decoupling capacitance with negligible esr (i.e.: ceramic type) the voltage source impedance can be modeled as a series r line l line circuit. the high performance ceramic decoupling capacitors will not significantly damp the network because of their low esr; therefore in order to guarantee stability the following conditions must be verified: in eq ext in int in line line r c c l r _ _ _ ) ( ? ? ? [6] in eq line r r _ ?? [7] it is critical that the line source impedance be at least an octave lower than the converter?s dynamic input resistance, [7]. however, r line cannot be made arbitrarily low otherwise equation [6] is violated and the system will show instability, due to under-damped rlc input network.
prm ? regulator rev 1.2 vicorpower.com page 21 of 23 7/2015 800 735.6200 prm48dh480t250b03 8.5.2 inductive source and local, external input decoupling capacitance with significant r cin_ext esr (i.e.: electrolytic type) in order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor l line . notice that, the high performance ceramic capacitors c in_int within the prm should be included in the external electrolytic capacitance value for this purpose. the stability criteria will be ext in c in eq r r _ _ ? [8] in eq c ext in line r r c l ext in _ _ _ ? ? [9] equation [9] shows that if the aggregate esr is too small ? for example by using very high quality input capacitors (c in_ext ) ? the system will be under-damped and may even become destabilized. again, an oc tave of design margin in satisfying [8] should be considered the minimum. 8.6 arrays up to ten prms of the same type may be placed in parallel to expand the power capacity of the system. the following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. ? ?in pins of all prms must be connected together. both inductance and resistance from the common power source to each prm should be minimized, and matched. ? input voltage to all prms must be the same. independent fuses for each prm are recommended. ? pc pins must be connected together for synchronization and proper fault response. ? reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules? re pins have reached their operational voltage levels. ? there must be one single external voltage control loop. the control loop must drive each pr pin relative to each module?s sg pin, and the local pr voltage must be the same across all modules. ? each prm must have its own local current shunt and current sense circuitry to drive its if pin. ? the number of prms required to achieve a given array capacity must consider all sources of mismatch to avoid overstress of any prm in the array. imbalances in sharing are not only due to current sharing accuracy specifications, but also temperature differences among prms, vin variations, and error terms in the buffering of the error amplifier output to the pr pins. ? control loop compensation procedures above will hold for an array, in general, although many parameters must be scaled against the number of prms in the system. please contact vicor applications for assistance. 8.7 input fuse recommendations a fuse should be incorporated at the input to each prm, in series with the +in pin. a 10 a or smaller input fuse (littelfuse ? nano 2? 451/453 series, or equivalent) is required to safety agency conditions of acceptability. always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. 8.8 layout considerations application note an:005 details board layout using v?i chip components. additional consideration must be given to the external control circuit components. the current sense shunt signal voltage is highly sensitive to noise. as such, current sensing circuitry should be located close to the shunt to minimize the length of the sense signals. a kelvined connection at the shunt is recommended for best results. the control signal from a remote voltage sense circuit to the prm should be shielded. avoid routing this, or other control signals directly underneath the prm, if possible. components that tie directly to the prm should be located close to their respective pins. it is also critical that all control components be referenced to sg, and that sg not be tied to any other ground in the system, including ?in or ?out of the prm.
prm ? regulator rev 1.2 vicorpower.com page 22 of 23 7/2015 800 735.6200 prm48dh480t250b03 vicor?s comprehensive line of power solutions incl udes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-d c and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reli able. however, no responsibility is assumed by vicor for its use. vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. vicor reserves the right to make changes to any products , specifications, and product descriptions at any time without no tice. information pu blished by vicor has been checked and is believed to be accurate at the time it was printed; however, vicor assumes no responsibility for inaccuracies. testing and other quality controls are used to t he extent vicor deems necessary to support vicor?s product warra nty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. specifications are subject to change without notice. vicor?s standard terms and conditions all sales are subject to vicor?s standard terms and conditions of sale, which are available on vicor?s webpage or upon request. product warranty in vicor?s standard terms and conditions of sale, vicor warrants that its products are free from non-conformity to its standard specifications (the ?express limited warranty ?). this warranty is extended only to the original buyer for the period expiring t wo (2) years after the date of shipment and is not transferable. unless otherwise expressly stated in a written sal es agreement signed by a duly authorized vicor signatory, vicor disclaims all representations, liabi lities, and warranties of any kind (whether arising by implication or by operation of law) with respect to the products, includin g, without limitation, any warranties or representations as to merchantability , fitness for particular purpose, infringement of any patent, copyright, or other intellectual property right, or any other matter. this warranty does not extend to products subjected to misuse, a ccident, or improper application, maintenance, or storage. vico r shall not be liable for collateral or consequential damage. vicor di sclaims any and all liability arisin g out of the application or use of any product or circuit and assumes no liability for applications assist ance or buyer product design. buyers are responsible for the ir products and applications using vicor products and components. prior to using or distributing any produc ts that include vicor component s, buyers should provide adequate design, testing and operating safeguards. vicor will repair or replace defective products in accordance with its own best judgment. for service under this warranty, the buyer must contact vicor to obtain a return material authorization (rma) number and shipping instructions. products returned without prio r authorization will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all reshipment charges if the product was de fective within the terms of this warranty. life support policy vicor?s products are not authorized for use as cri tical components in life support devices or systems without the express prior written approval of the chief executive officer and general counsel of vicor corporation. as used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance wi th instructions for use provided in the labeling can be reasonably ex pected to result in a significant injury to the user. a criti cal component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. per vicor terms and conditions of sale, the user of vicor p roducts and components in life support applications assumes all risks of su ch use and indemnifies vicor against all liability and damages. intellectual property notice vicor and its subsidiaries own intellectual property (including issued u.s. and foreign patents and pending patent applications ) relating to the products described in this data sheet. no license, whether express, implied, or arising by estoppel or otherwise, to an y intellectual property rights is granted by this document. inte rested parties should contact vicor's intellectual property depa rtment. the products described on this data sheet are protec ted by the following u. s. patents numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,90 9; 7,038,917; 7,145,18 6; 7,166,898; 7,187, 263; 7,202,646; 7,361,844; d496 ,906; d505,114; d506,438; d509,472; and for use under 6,975,098 and 6,984,965. vicor corporation 25 frontage road andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email customer service: custserv@vicorpower.com technical support: apps@vicorpower.com

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