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1. introduction this document describes the functionality and electrical specificati ons of the contactless reader/writer ic slrc610. 2. general description the slrc610 is a highly integrated transce iver ic for contactless communication at 13.56 mhz. the slrc610 transceiver ic supports the following operating modes ? read/write mode supp orting iso/iec 15693 ? read/write mode supporting icode epc uid/ epc otp ? read/write mode supporting iso/ iec 18000-3 mode 3/ epc class-1 hf the slrc610 supports the vicinity protocol according to iso/iec15693, epc uid and iso/iec 18000-3 mode 3/ epc class-1 hf. the following host interfaces are supported: ? serial peripheral interface (spi) ? serial uart (similar to rs232 with voltage levels dependent on pin voltage supply) ? i 2 c-bus interface (two versions are implemented: i2c and i2cl) the slrc610 supports the connection of a secure access module (sam). a dedicated separate i2c interface is implemented for a connection of the sam. the sam can be used for high secure key storage and acts as a very performant crypto coprocessor. a dedicated sam is available for connection to the slrc610. 3. features and benefits ? high rf output power frontend ic ? supports iso/iec15693, icode epc uid and iso/iec 18000-3 mode 3/ epc class-1 hf ? low-power card detection ? antenna connection with minimum number of external components ? supported host interfaces: ? spi up to 10 mbit/s ? i 2 c-bus interfaces up to 400 kbd in fast mode, up to 1000 kbd in fast mode plus slrc610 high performance iso/iec 15693 reader solution rev. 3.4 ? 6 february 2014 227634 product data sheet company public
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 2 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution ? rs232 serial uart up to 1228.8 kbd, with voltage levels dependent on pin voltage supply ? separate i 2 c-bus interface for connection of a secure access module (sam) ? fifo buffer with size of 512 byte for highest transaction performance ? flexible and efficient power saving modes including hard power down, standby and low-power card detection ? cost saving by integrated pll to derive system cpu clock from 27.12 mhz rf quartz crystal ? 3 v to 5.5 v power supply ? up to 8 free programmable input/output pins 4. quick reference data [1] vdd(pvdd) must always be the same or lower voltage than vdd. [2] i pd is the sum of all supply currents [3] i dd(tvdd) depends on vdd(tvdd) and the external circuitry connected to tx1 and tx2. [4] typical value: assumes the usage of a complem entary driver configuration and an antenna matched to 40 ? between pins tx1, tx2 at 13.56 mhz. 5. ordering information [1] delivered in one tray [2] delivered in five trays [3] delivered on reel with 6000 pieces table 1. quick reference data symbol parameter conditions min typ max unit v dd supply voltage 3 5 5.5 v v dd(pvdd) pvdd supply voltage [1] 35v dd v v dd(tvdd) tvdd supply voltage 3 5 5.5 v i pd power-down current pdown pin pulled high [2] - 8 40 na i dd supply current - 17 20 ma i dd(tvdd) tvdd supply current [3] [4] - 100 200 ma t amb ambient temperature ? 25 +25 +85 ?c t stg storage temperature no supply voltage applied ? 40 +25 +100 ?c table 2. ordering information type number package name description version SLRC61002HN/trayb [1] hvqfn32 plastic thermal enhanced very thin quad flat package; no leads; msl1, 32 terminals + 1 central ground; body 5 ? 5 ? 0.85 mm sot617-1 SLRC61002HN/traybm [2] SLRC61002HN/t/r [3]
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 3 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 6. block diagram the analog interface handles the modulation an d demodulation of the antenna signals for the contactless interface. the contactless uart manages the protocol dependency of the contactless interface settings managed by the host. the fifo buffer ensures fast and convenient data transfer between host and the contactless uart. the register bank contains the settings for the analog and digital functionality. 7. pinning information fig 1. simplified block diagram of the slrc610 001aaj627 host antenna fifo buffer analog interface contactless uart serial uart spi i 2 c-bus register bank (1) pin 33 vss - heatsink connection fig 2. pinning configuration hvqfn32 (sot617-1) 001aam004 clrc663 transparent top view tx1 (1) dvdd vdd tvdd sigout xtal1 sigin xtal2 tck pdown tms clkout tdi scl tdo sda avdd aux1 aux2 rxp rxn vmid tx2 tvss irq if3 if2 if1 if0 ifsel1 ifsel0 pvdd 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 4 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 7.1 pin description [1] this pin is used for connection of a buffer capaci tor. connection of a supply voltage might damage the device. table 3. pin description pin symbol type description 1 tdo o test data output for boundary scan interface 2 tdi i test data input boundary scan interface 3 tms i test mode select boundary scan interface 4 tck i test clock boundary scan interface 5 sigin i contactless communication interface output. 6 sigout o contactless communi cation interface input. 7 dvdd pwr digital power supply buffer [1] 8 vdd pwr power supply 9 avdd pwr analog power supply buffer [1] 10 aux1 o auxiliary outputs: pin is used for analog test signal 11 aux2 o auxiliary outputs: pin is used for analog test signal 12 rxp i receiver input pin for the received rf signal. 13 rxn i receiver input pin for the received rf signal. 14 vmid pwr internal receiver reference voltage [1] 15 tx2 o transmitter 2: delivers the modulated 13.56 mhz carrier 16 tvss pwr transmitter ground, supplie s the output stage of tx1, tx2 17 tx1 o transmitter 1: delivers the modulated 13.56 mhz carrier 18 tvdd pwr transmitter voltage supply 19 xtal1 i crystal oscillator input: input to the inverting am plifier of the oscillator. this is pin is also the input for an externally generated clock (fosc = 27,12 mhz) 20 xtal2 o crystal oscillator output: output of the inverting amplifier of the oscillator 21 pdown i power down 22 clkout o clock output 23 scl o serial clock line 24 sda i/o serial data line 25 pvdd pwr pad power supply 26 ifsel0 i host interface selection 0 27 ifsel1 i host interface selection 1 28 if0 i/o interface pin, multifunction pin: can be assigned to host interface rs232, spi, i 2 c, i 2 c-l 29 if1 i/o interface pin, multifunction pin: can be assigned to host interface spi, i 2 c, i 2 c-l 30 if2 i/o interface pin, multifunction pin: can be assigned to host interface rs232, spi, i 2 c, i 2 c-l 31 if3 i/o interface pin, multifunction pin: can be assigned to host interface rs232, spi, i 2 c, i 2 c-l 32 irq o interrupt request: output to signal an interrupt event 33 vss pwr ground and heatsink connection
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 5 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8. functional description fig 3. detailed block diagram of the slrc610 001aam005 i 2 c, logical fifo 512 bytes registers statemachines eeprom 8 kbyte spi sam interface voltage regulator 3/5 v => 1.8 v dvdd por adc pll lfo rx osc tx voltage regulator 3/5 v => 1.8 v avdd rng analogue front-end boundary scan if0 ifsel0 ifsel1 if1 if2 if3 tck tdi tms tdo reset logic pdown i 2 c rs232 spi host interfaces interrupt controller irq sigin timer0..3 crc timer4 (wake-up timer) sigpro tx codec rx decod cl- copro sigin/ sigout control sigout vmid rxn rxp tx1 tx2 xtal1 xtal2 sda scl vdd vss pvdd tvdd tvss aux1 aux2 avdd dvdd clkout
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 6 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.1 interrupt controller the interrupt controller handles the enabling/disabling of interrupt requests. all of the interrupts can be co nfigured by firmware. additionally , the firmware has possibilities to trigger interrupts or clear pending interrupt requests. two 8-bit interrupt registers irq0 and irq1 are implemented, accompanied by two 8-bit interrupt enable registers irq0en and irq1en. a dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt controller registers is implemented. the slrc610 indicates certain events by sett ing bit irq in the register status1reg and additionally, if activated, by pin irq. the si gnal on pin irq may be used to in terrupt the host using its interrupt handlin g capabilities. this allows th e implementation of efficient host software. the following table shows the available interr upt bits, the corresponding source and the condition for its activation. the interrupt bi t timernirq in register irq1 indicates an interrupt set by the timer unit. the se tting is done if the timer underflows. the txirq bit in register irq0 indicates that the transmission is finished. if the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit sets the interr upt bit automatically. the bit rxirq in register irq0 indicates an interrupt when the end of the received data is detected. the bit idleirq in register ir q0 is set if a command finishes and the content of the command register changes to idle. the waterlevel defines both - minimum and maximum warning levels - counting from top and from bottom of the fifo by a single value. the bit hialertirq in register irq0 is set to lo gic 1 if the hialert bit is set to logic 1, that means the fifo data number has reached the top level as configured by the bit waterlevel. the bit loalertirq in register irq0 is set to lo gic 1 if the loalert bit is set to logic 1, that means the fifo data number has reached the bottom level as configured by the bit waterlevel. the bit errirq in register irq0 indicates an error detected by the contactless uart during receive. this is indicated by any bi t set to logic 1 in register error. the bit lpcdirq in register ir q0 indicates a card detected. the bit rxsofirq in register irq0 indicates a detection of a sof or a subcarrier by the contactless uart during receiving. the bit globalirq in register irq1 indicates an interrupt occurring at any other interrupt source when enabled.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 7 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution table 4. interrupt sources interrupt bit interrupt source is set automatically, when timer0irq timer unit the timer register t0 counterval underflows timer1irq timer unit the timer register t1 counterval underflows timer2irq timer unit the timer register t2 counterval underflows timer3irq timer unit the timer register t3 counterval underflows txirq transmitter a transmitted data stream ends rxirq receiver a received data stream ends idleirq command register a command execution finishes hialertirq fifo-buffer pointer the fifo data number has reached the top level as configured by the bit waterlevel loalertirq fifo-buffer pointer the fifo data number has reached the bottom level as configured by the bit waterlevel errirq contactless uart a communication error had been detected lpcdirq lpcd a card was detected w hen in low-power card detection mode rxsofirq receiver detection of a sof or a subcarrier globalirq all interrupt sources will be set if another interrupt request source is set
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 8 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.2 timer module timer module overview the slrc610 implements five timers. four timers -timer0 to timer3 - have an input clock that can be configured by register t(x)cont rol to be 13.56 mhz, 212 khz, (derived from the 27.12 mhz quartz) or to be the underflow event of the fifth timer (timer4). each timer implements a counter register which is 16 bit wide. a reload value for the counter is defined in a range of 0000h to ffffh in the registers txreloadhi and txreloadlo. the fifth timer timer4 is intended to be used as a wakeup timer and is connected to the internal lfo (low frequency osc illator) as input clock source. the tcontrol register allows the global start and stop of each of the four timers timer0 to timer3. additionally, this regist er indicates if one of the timers is running or stopped. each of the five timers implements an individual configuration register set defining timer reload value (e.g. t0reloadhi,t0re loadlo), the timer value (e.g. t0countervalhi, t0countervallo) and the conditions which define start, stop and clockfrequency (e.g. t0control). the external host may use these timers to manage timing relevant tasks. the timer unit may be used in one of the following configurations: ? time-out counter ? watch-dog counter ? stop watch ? programmable one-shot timer ? periodical trigger the timer unit can be used to measure the time interval between two events or to indicate that a specific event has occurred after an elapsed time. the timer register content is modified by the timer unit, which can be used to generate an interrupt to allow an host to react on this event. the counter value of the timer is available in the r egisters t(x)countervalhi, t(x)countervallo. the content of these registers is decremented at each timer clock. if the counter value has reached a value of 0000h and the interrupts are enabled for this specific timer, an interrup t will be generated as soon as the next clock is received. if enabled, the timer event can be indicated on the pin irq (interrupt request). the bit timer(x)irq can be set and reset by the host controller. depending on the configuration, the timer will stop counting at 0000h or rest art with the value lo aded from registers t(x)reloadhi, t(x)reloadlo. the counting of the timer is indi cated by bit tcontrol.t(x)running. the timer can be started by setting bits tcontrol.t(x)running and tcontrol.t(x)startstopnow or stopped by sett ing the bits tcontrol.t(x)startstopnow and clearing tcontrol.t(x)running. another possibility to start the timer is to set the bit t( x)mode.t(x)start, this can be useful if dedicated protocol requir ements need to be fulfilled.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 9 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.2.1 timer modes 8.2.1.1 time-out- and watch-dog-counter having configured the timer by setting register t(x)reloadvalue and starting the counting of timer(x) by setting bit tcontrol.t(x)start stop and tcontrol.t(x)r unning, the timer unit decrements the t(x)countervalue register beginning with the configured start event. if the configured stop event occurs before the timer(x) underflows (e.g. a bit is received from the card), the timer unit stops (no interrupt is generated). if no stop event occurs, the timer unit conti nues to decrement the counter registers until the content is zero and generates a timer inte rrupt request at the ne xt clock cycle. this allows to indicate to a host that the event did not occur during the configured time interval. 8.2.1.2 wake-up timer the wake-up timer4 allows to wakeup the system from standby after a predefined time. the system can be configured in such a way t hat it is entering the standby mode again in case no card had been detected. this functionality can be used to implemen t a low-power card dete ction (lpcd). for the low-power card detection it is recommended to set t4control.t4autowakeup and t4control.t4autorestart, to activate the ti mer4 and automatically set the system in standby. the internal low frequency oscillator (l fo) is then used as input clock for this timer4. if a card is detected the host-co mmunication can be started. if bit t4control.t4autowakeup is not set, the sl rc610 will not enter th e standby mode again in case no card is detected but stays fully powered. 8.2.1.3 stop watch the elapsed time between a configured start- and stop event may be measured by the slrc610 timer unit. by setting the registers t(x)reloadvaluehi, t(x)reloadvaluelo the timer starts to decrement as soon as activa ted. if the configured stop event occurs, the timers stops decrementing. the elapsed time between start and stop event can then be calculated by the host dependent on the timer interval ttimer: (1) if an underflow occurred which can be identifi ed by evaluating the corresponding irq bit, the performed time measurement according to the formula above is not correct. 8.2.1.4 programmable one-shot timer the host configures the interrupt and the timer, starts the timer and waits for the interrupt event on pin irq. after the configured time the interrupt request will be raised. 8.2.1.5 periodical trigger if the bit t(x)control.t(x)autorest art is set and the interrupt is activated , an interrupt request will be indicated periodically after every elapsed timer period . ?? timer value value t timer treload t * ? ? ?
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 10 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.3 contactless interface unit the contactless interface unit of the slrc6 10 supports the following read/write operating modes: ? iso/iec15693/icode ? icode epc uid ? iso/iec 18000-3 mode 3/ epc class-1 hf a typical system using the slrc610 is using a microcontroller to implement the higher levels of the contactless communication protocol and a power supply (battery or external supply). 8.3.1 iso/iec15693 functionality the physical parameters are described in ta b l e 5 . fig 4. read/write mode aaa-002468 battery/power supply reader/writer microcontroller reader ic iso/iec 15693 tag table 5. communication overview for iso/ie c 15693 reader/writer reader to label communication direction signal type transfer speed fc / 8192 kbit/s fc / 512 kbit/s reader to label (send data from the slrc610 to a card) reader side modulation 10 % to 30 % ask or 100 % ask 10 % to 30 % ask 90 % to 100 % ask bit encoding 1/256 1/4 data rate 1,66 kbit/s 26,48kbit/s table 6. communication overview for iso/ie c 15693 reader/writer label to reader communication direction signal type transfer speed 6.62 (6.67) kbit/s 13.24 kbit/s [1] 26.48 (26.69) kbit/s 52.96 kbit/s label to reader (slrc610 receives data from a card) fc = 13.56 mhz card side modulation not supported not supported single (dual) subcarrier load modulation ask single subcarrier load modulation ask bit length (? s) - - 37.76 (37.46) 18.88 bit encoding - - manchester coding manchester coding subcarrier frequency [mhz] --f c / 3 2 (fc / 28) fc / 32
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 11 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution [1] fast inventory (page) read command only (icode proprietary command). fig 5. data coding according to iso/iec 15693. standard mode reader to label 001aam272 pulse modulated carrier ~9.44 s 0 1 2 3 4 ~18.88 s . 2 . . . ... .. . . . . . . . . . 22. .... 2 2 25 555 5 ~4,833 ms 3 245
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 12 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.3.2 epc-uid/uid-otp functionality the physical parameters are described in ta b l e 7 . data coding and framing according to epc global 13.56 mhz ism (industrial, scientific and medical) band class 1 radio frequency id entification tag interface specification (candidate recommendation, version 1.0.0). 8.3.3 iso/iec 18000-3 mode 3/ epc class-1 hf functionality the iso/iec 18000-3 mode 3/ epc class-1 hf is not described in this document. for a detailed explanation of the protocol, refer to the iso/iec 18000-3 mode 3/ epc class-1 hf standard. 8.3.4 epc class-1 hf and icode 8.3.4.1 data encoding icode the icode protocols have mainly three different methods of data encoding: ? ?1? out of ?4? coding scheme ? ?1? out of ?256? coding scheme ? ?return to zero? (rz) coding scheme data encoding for all three coding schemes is done by the icode generator. the supported epc class-1 hf modes are: ? 2 pulse for 424 kbit subcarrier ? 4 pulse for 424 kbit subcarrier ? 2 pulse for 848 kbit subcarrier ? 4 pulse for 848 kbit subcarrier 8.4 host interfaces 8.4.1 host interface configuration the slrc610 supports direct interfacing of various hosts as the spi, i 2 c, i 2 cl and serial uart interface type. the slrc610 resets its interface and checks the current host interface type automatically having performed a power-up or resuming from power down. the slrc610 identifies the host interface by the means of the logic levels on the control table 7. communication overview for epc/uid communication direction signal type transfer speed 26.48 kbit/s 52.96 kbit/s reader to card (send data from the slrc610 to a card) reader side modulation 10 % to 30 % ask bit encoding rtz bit length 37.76 ? s card to reader (slrc610 receives data from a card) card side modulation single subcarrier load modulation bit length 18.88 ? s bit encoding manchester coding
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 13 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution pins after the cold reset phase. this is done by a combination of fixed pin connections.the following table shows the possible configurations defined by ifsel1,ifsel0: 8.4.2 spi interface 8.4.2.1 general the slrc610 acts as a slave during the spi communication. the spi clock sck has to be generated by the master. data communication from the master to the slave uses the line mosi. line miso is used to send data back from the slrc610 to the master. a serial peripheral interface (spi compatible) is supported to enable high speed communication to a host. the implemented spi compatible interfac e is according to a standard spi interface. the spi compatible inte rface can handle data speed of up to 10 mbit/s. in the communication with a host slrc61 0 acts as a slave receiving data from the external host for register settings and to send and receive data relevant for the communication on the rf interface. on both data lines (mosi, miso) each data byte is sent by msb first. data on mosi line shall be stable on rising edge of the clock line (sck) and is allowed to change on falling edge. the same is valid for the miso line. data is prov ided by the slrc610 on the falling edge and is stable on the rising edge.the polarity of the clock is low at spi idle. 8.4.2.2 read data to read out data from the slrc610 by using the spi compatible interface the following byte order has to be used. the first byte that is sent defines the mode (lsb bit) and the address. table 8. connection scheme for detecting the different interface types pin pin symbol uart spi i 2 c i 2 c-l 28 if0 rx mosi adr1 adr1 29 if1 - sck scl scl 30 if2 tx miso adr2 sda 31 if3 1 nss sda adr2 26 ifsel0 0 0 1 1 27 ifsel1 0 1 0 1 fig 6. connection to host with spi 001aal998 reader ic if1 sck if0 mosi if2 miso if3 nss
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 14 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution remark: the most significant bit (msb) has to be sent first. 8.4.2.3 write data to write data to the slrc610 using the spi in terface the following byte order has to be used. it is possible to write more than on e byte by sending a single address byte (see.8.5.2.4). the first send byte defines both, the mode itself and the address byte. remark: the most significant bit (msb) has to be sent first. 8.4.2.4 address byte the address byte has to fulfil the following format: the lsb bit of the first byte defines the used mode. to read data from the slrc610 the lsb bit is set to logic 1. to write data to t he slrc610 the lsb bit has to be cleared. the bits 6 to 0 define the address byte. note: when writing the sequence [address byte ][data1][data2][data3]..., [data1] is written to address [address byte], [data2] is written to address [addre ss byte + 1] and [data3] is written to [address byte + 2]. exception: this auto increment of the address byte is not performed if data is written to the fifo address 8.4.2.5 timing specification spi the timing condition for sp i interface is as follows: table 9. byte order for mosi and miso byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1 mosi address 0 address 1 address 2 ??.. address n 00h miso x data 0 data 1 ??.. data n ? 1data n table 10. byte order for mosi and miso byte 0 byte 1 byte 2 3 to n-1 byte n byte n + 1 mosi address 0 data 0 data 1 ??.. data n ?? 1 data n m i s oxxx? ? . .xx table 11. address byte 0 register; address mosi 7 6 5 4 3 2 1 0 address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read) 0 (write) msb lsb table 12. timing conditions spi symbol parameter min typ max unit t sckl sck low time 50 - - ns t sckh sck high time 50 - - ns t h(sckh-d) sck high to data input hold time 25 - - ns t su(d-sckh) data input to sck high set-up time 25 - - ns
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 15 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution remark: to send more bytes in one data stream the nss signal must be low during the send process. to send more than one data stream the nss signal must be high between each data stream. 8.4.3 rs232 interface 8.4.3.1 selection of the transfer speeds the internal uart interf ace is compatible to a rs232 serial interface. table 14 ? selectable transfer speeds ? describes examples for different transfer speeds and relevant register settings. the resulting transfer speed error is less than 1.5 % for all described transfer speeds. the defau lt transfer speed is 115.2 kbit/s. to change the transfer speed, the host contro ller has to write a value for the new transfer speed to the register serialspeedreg. the bits br_t0 and br_t1 define factors to set the transfer speed in the serialspeedreg. table 13 ? settings of br_t0 and br_t1 ? describes the settings of br_t0 and br_t1. t h(sckl-q) sck low to data output hold time - - 25 ns t (sckl-nssh) sck low to nss high time 0 - - ns t nssh nss high time 50 - - ns table 12. timing conditions spi ?continued symbol parameter min typ max unit fig 7. connection to host with spi 001aaj641 t sckl t nssh t sckh t sckl t h(sckl-q) t su(d-sckh) t h(sckh-d) t h(sckl-q) t (sckl-nssh) sck mosi miso msb msb lsb lsb nss table 13. settings of br_t0 and br_t1 br_t0 01234567 factor br_t011248163264 range br_t1 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 16 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution the selectable transfer speeds as shown are calculated according to the following formulas: if br_t0 = 0: transfer speed = 27.12 mhz / (br_t1 + 1) if br_t0 > 0: transfer speed = 27.12 mhz / (br_t1 + 33)/2 (br_t0 ? 1) remark: transfer speeds above 1228.8 kbits/s are not supported. 8.4.3.2 framing remark: for data and address bytes the lsb bit has to be sent first. no parity bit is used during transmission. read data: to read out data using the uart interface the flow described below has to be used. the first send byte defines both the mode itself and the address.the trigger on pin if3 has to be set, otherwise no read of data is possible. table 14. selectable transfer speeds transfer speed (kbit/s) serial speedreg transfer speed accuracy (%) (hex.) 7.2 fa ? 0.25 9.6 eb 0.32 14.4 da ? 0.25 19.2 cb 0.32 38.4 ab 0.32 57.6 9a ? 0.25 115.2 7a ? 0.25 128 74 ? 0.06 230.4 5a ? 0.25 460.8 3a ? 0.25 921.6 1c 1.45 1228.8 15 0.32 table 15. uart framing bit length value start bit (sa) 1 bit 0 data bits 8 bit data stop bit (so) 1 bit 1 table 16. byte order to read data mode byte 0 byte 1 rx address - tx - data 0
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 17 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution write data: to write data to the slrc610 using the uart interface the following sequence has to be used. the first send byte defines both, the mode itself and the address. remark: data can be sent before address is received. fig 8. timing diagram for uart read data 001aam298 a0 a1 sa a2 a3 tx rx a4 a5 a6 rd/ nwr so d0 data address d1 sa d2 d3 d4 d5 d6 d7 so table 17. byte order to write data mode byte 0 byte 1 rx address 0 data 0 tx address 0 fig 9. timing diagram for uart write data 001aam299 a0 a1 sa a2 a3 tx rx a4 a5 a6 rd/ nwr so a0 address address a1 sa a2 a3 a4 a5 a6 rd/ nwr so d0 data d1 sa d2 d3 d4 d5 d6 d7 so
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 18 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.4.4 i 2 c-bus interface 8.4.4.1 general an inter ic (i 2 c) bus interface is supported to enable a low cost, low pin count serial bus interface to the host. the implemented i 2 c interface is mainly im plemented according the nxp semiconductors i 2 c interface specificatio n, rev. 3.0, june 2007. the slrc610 can act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode plus. the following features defined by the nxp semiconductors i 2 c interface specification, rev. 3.0, june 2007 are not supported: ? the slrc610 i2c interface does not stretch the clock ? the slrc610 i2c interface does not support the general call. this means that the slrc610 does not support a software reset ? the slrc610 does not support the i2c device id ? the implemented interface can only act in slave mode. therefore no clock generation and access arbitration is implemented in the slrc610. ? high speed mode is not supported by the slrc610 sda is a bidirectional line, connected to a positive supply voltage via a pull-up resistor. both lines sda and scl are set to high leve l if no data is transmitted. data on the i 2 c-bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 mbit/s in the fast mode+. if the i 2 c interface is selected, a spike suppression acco rding to the i 2 c interface specification on scl and sda is automatically activated. for timing requirements refer to table 195 ? i 2 c-bus timing in fast mode and fast mode plus ? 8.4.4.2 i 2 c data validity data on the sda line shall be stable during the high period of the clock. the high state or low state of the data line shall only ch ange when the clock signal on scl is low. fig 10. i 2 c-bus interface 001aam000 reader ic sda scl pull-up network pull-up network microcontroller
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 19 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.4.4.3 i 2 c start and stop conditions to handle the data transfer on the i 2 c-bus, unique start (s) and stop (p) conditions are defined. a start condition is defined with a high-to- low transition on the sda line while scl is high. a stop condition is defined with a low-to-high transition on the sda line while scl is high. the master always generates the start and st op conditions. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in this respect, the start (s) and repeated start (sr) conditions are functionally identical. therefore, the s symbol will be us ed as a generic term to re present both the start and repeated start (sr) conditions. 8.4.4.4 i 2 c byte format each byte has to be followed by an ackno wledge bit. data is transferred with the msb first, see figure 12 ? start and stop conditions ? . the number of transmitted bytes during one data transfer is unrestricted but shall fulfil the read /write cycle format. fig 11. bit transfer on the i 2 c-bus. 001aam300 data line stable; data valid change of data allowed sda scl fig 12. start and stop conditions 001aam301 start condition s scl sda scl sda stop condition p
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 20 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.4.4.5 i 2 c acknowledge an acknowledge at the end of one data byte is mandatory. the acknowledge-related clock pulse is generated by the master. the transmitte r of data, either master or slave, releases the sda line (high) during the acknowledge clock pulse. the receiver shall pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. the master can then generate either a stop (p) condition to stop the transfer, or a repeated start (sr) condition to start a new transfer. a master-receiver shall indicate the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. the slave-transmitter shall release the data line to allow the master to generate a stop (p) or repeated start (sr) condition. 8.4.4.6 i 2 c 7-bit addressing during the i 2 c-bus addressing procedure, the first by te after the start condition is used to determine which slave will be selected by the master. fig 13. acknowledge on the i 2 c- bus fig 14. data transfer on the i 2 c- bus 001aam302 clock pulse for acknowledgement 1 scl from master data output by receiverer data output by transmitter 289 acknowledge start condition s not acknowledge 001aam303 msb acknowledgement signal from slave acknowledgement signal from receiver clock line held low while interrupts are serviced byte complete, interrupt within slave 1 2789 12 9 ack ack 3 - 8 sr or p p sr s or sr
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 21 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution alternatively the i 2 c address can be configured in the eeprom. several address numbers are reserved for this purpose. during device configuration, the designer has to ensure, that no collision with these reserved addresses in the system is possible. check the corresponding i 2 c specification for a complete list of reserved addresses. for all slrc610 devices the upper 5 bits of the device bus address are reserved by nxp and set to 01010(bin). the remaining 2 bits (a dr_2, adr_1) of the slave address can be freely configured by the customer in order to prev ent collisions with other i 2 c devices by using the interface pins (refer to ta b l e 8 ) or the value of the i 2 c address eeprom register (refer to ta b l e 2 9 ). 8.4.4.7 i 2 c-register write access to write data from the host controller via i 2 c to a specific register of the slrc610 the following frame format shall be used. the first byte of a frame indicates th e device address according to the i 2 c rules. the second byte indicates the register address fo llowed by up to n-data bytes. in case the address indicates the fifo, in one frame all n- data bytes are written to the fifo register address. this enables for example a fast fifo access. for any other address, the address pointer is incremented automatically an d data is written to the locations [address], [address+1], [address+2] ... [address+(n-1)] the read/write bit shall be set to logic 0. 8.4.4.8 i 2 c-register read access to read out data from a specific register address of the slrc610 the host controller shall use the procedure: first a write access to the specific register address has to be performed as indicated in the following frame: the first byte of a frame indicates th e device address according to the i 2 c rules. the second byte indicates the register address. no data bytes are added. the read/write bit shall be logic 0. having performed this write access, the re ad access starts. the host sends the device address of the slrc610. as an answer to this device address the slrc610 responds with the content of the addressed register. in one frame n-data bytes could be read using the same register address. the address pointing to the register is incremented automatically (exception: fifo register addr ess is not incremented automatically). this enables a fast transfer of register cont ent. the address pointer is incremented automatically and data is read from the lo cations [address], [addr ess+1], [address+2]... [address+(n-1)] fig 15. first byte following the start procedure 001aam304 bit 6 bit 5 bit 4 slave address bit 3 bit 2 bit 1 bit 0 r/w msb lsb
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 22 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution in order to support a fast fifo data transfer, the address pointer is not incremented automatically in case the address is pointing to the fifo. the read/write bit shall be set to logic 1. 8.4.4.9 i 2 cl-bus interface the slrc610 provides an interface option according to of a logical handling of an i 2 c interface. this logical interface fulfills the i 2 c specification, but the rise/fall timings will not be according the i 2 c standard. standard i/o pads are used for communication and the communication speed is limited to 5 mbaud. the protocol itself is equivalent to the fast mode protocol of i 2 c. the address is 01010xxb, where t he last two bits of the address can be defined by the application. th e definition of this bits can be done by two options. with a pin, where the higher bit is fixed to 0 or the configuration can be defined via eeprom. refer to the eeprom configuration in section 8.7 . fig 16. register read and write access 001aam305 ack 0 (w) ack 0 sa i2c slave address a7-a0 clrc663 register address a6-a0 ack data [7..0] so so [0..n] ack 0 (w) ack optional, if the previous access was on the same register address read cycle write cycle 0 sa i2c slave address a7-a0 clrc663 register address a6-a0 1 (r) ack sa sent by master sent by slave i2c slave address a7-a0 ack data [7..0] so [0..n] 0..n nack data [7..0] table 18. timing parameter i 2 cl parameter min max unit f scl 05m h z t hd;sta 80 - ns t low 100 - ns t high 100 - ns t su;sda 80 - ns t hd;dat 05 0n s t su;dat 02 0n s t su;sto 80 - ns t buf 200 - ns
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 23 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution the pull-up resistor is not required for the i 2 cl interface. instead, a on chip buskeeper is implemented in the slrc610 for sda of the i 2 cl interface. this protoc ol is intended to be used for a point to point connection of devi ces over a short distance and does not support a bus capability.the driver of the pin must fo rce the line to the desired logic voltage. to avoid that two drivers are pushing the line at the same time following regulations must be fulfilled: scl: as there is no clock stretching, the scl is always under control of the master. sda: the sda line is shared between master and slave. therefore the master and the slave must have the control over the own driv er enable line of the sda pin. the following rules must be followed: ? in the idle phase the sda line is driven high by the master ? in the time between start and stop condition the sda line is driven by master or slave when scl is low. if scl is high the sda line is not driven by any device ? to keep the value on the sda line a on chip buskeeper structure is implemented for the line 8.4.5 sam interface i 2 c 8.4.5.1 sam functionality the slrc610 implements a dedicated i2c inte rface to integrate a mifare sam (secure access module) in a very convenient way in to applications (e.g . a proximity reader). the sam can be connected to the microcontroller to operate like a cryptographic co-processor. for any cryptographic task, the microcontroller requests a operation from the sam, receives the answer and sends it over a host interface (e.g. i2c, spi) interface to the connected reader ic. the mifare sam supports a optimized method to integrate the sam in a very efficient way to reduce the protocol overhead. in this system configuration, the sam is integrated between the microprocessor and the reader ic, connected by one interface to the reader ic and by another interface to the microcontroller. in this application the microcontroller accesses the sam using the t=1 protocol and the sam accesses the reader ic using an i2c interface. as the sam is directly commu nicating with reader ic, the communication overhead is reduced. in this configuration, a performance boost of up to 40% can be achieved for a transaction time. the mifare sam supports applications us ing mifare cards. for multi application purposes an architecture connecting the microcon troller additionally directly to the reader ic is recommended. this is po ssible by connecting the slrc610 on one interface (sam interface sda, scl) with the mifare sam av2.6 (p5df081xx/t1ar1070) and by connecting the microcontroller to the s2c or spi interface.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 24 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.4.5.2 sam connection the slrc610 provides an interface to connect a sam dedicated to the slrc610. both interface options of the slrc610, i 2 c or i 2 cl can be used for this purpose. the interface option of the sam itself is configured by a host command sent from the host to the sam. the i 2 cl interface is intended to be used as connection between two ic?s over a short distance. the protocol fulfills the i 2 c specification, but does support a single device connected to the bus only. 8.4.6 boundary scan interface the slrc610 provides a boundary scan interface according to the ieee 1149.1. this interface allows to test interconnections with out using physical test probes. this is done by test cells, assigned to each pin, whic h override the functi onality of this pin. to be able to program the test cells, the following commands are supported: the standard ieee 1149.1 describe s the four basic blocks necessa ry to use this interface: test access port (tap), tap controller, t ap instruction register, tap data register; fig 17. i2c interface enables convenient mifare sam integration c reader t=1 i2c i2c aaa-002963 sam av2.6 reader ic table 19. boundary scan command value (decimal) command parameter in parameter out 0 bypass - - 1 preload data (24) - 1 sample - data (24) 2 id code (default) - data (32) 3 user code - data (32) 4clamp - - 5high z - - 7 extest data (24) data (24) 8 interface on/off interface (1) - 9 register access read address (7) data (8) 10 register access write address (7) - data (8) -
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 25 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.4.6.1 interface signals the boundary scan interface implements a four line interface between the chip and the environment. there are three inputs: test cl ock (tck); test mode select (tms); test data input (tdi) and one output test data output (tdo). tck and tms are broadcast signals, tdi to tdo generate a serial line called scan path. advantage of this technique is that indepen dent of the numbers of boundary scan devices the complete path can be han dled with four signal lines. the signals tck, tms are directly connecte d with the boundary scan controller. because these signals are responsible for the mode of the chip, all boundary scan devices in one scan path will be in the same boundary scan mode. 8.4.6.2 test clock (tck) the tck pin is the input clock for the module. if this clock is provided, the test logic is able to operate independent of any other system cl ocks. in addition, it ensures that multiple boundary scan controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock. when necessary, tck can be stopped at 0 or 1 for extended periods of time. while tck is stoppe d at 0 or 1, the state of the boundary scan controller does not change and data in the in struction and data registers is not lost. the internal pull-up resistor on the tck pin is enabled. this assures that no clocking occurs if the pin is not driven from an external source. 8.4.6.3 test mode select (tms) the tms pin selects the next state of the bou ndary scan controller. tms is sampled on the rising edge of tck. depending on the current boundary scan state and the sampled value of tms, the next state is entered. because the tms pin is sampled on the rising edge of tck, the ieee standard 1149.1 expe cts the value on tms to change on the falling edge of tck. holding tms high for five consecutive tck cycles drives the bo undary scan controller state machine to the test-logic-reset state. when the boundary scan controller enters the test-logic-reset state, the instruction regist er (ir) resets to th e default instruction, idcode. therefore, this sequence c an be used as a reset mechanism. the internal pull-up resistor on the tms pin is enabled. 8.4.6.4 test data input (tdi) the tdi pin provides a stream of serial info rmation to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current tap state and the current instruction, presents this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck, the i eee standard 1149.1 expects the value on tdi to change on t he falling edge of tck. the internal pull-up resistor on the tdi pin is enabled. 8.4.6.5 test data output (tdo) the tdo pin provides an output stream of seri al information from the ir chain or the dr chains. the value of tdo depends on the curr ent tap state, the current instruction, and the data in the chain being accessed. in order to save power when the port is not being
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 26 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution used, the tdo pin is placed in an inactive drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1149.1 ex pects the value on tdo to change on the falling edge of tck. 8.4.6.6 data register according to the ieee1149.1 standard there ar e two types of data register defined: bypass and boundary scan the bypass register enable the possibility to bypass a device when part of the scan path.serial data is allowed to be transferred through a device from the tdi pin to the tdo pin without affecting the operation of the device. the boundary scan register is the scan-chain of the boundary cells. the size of this register is dependent on the command. 8.4.6.7 boundary scan cell the boundary scan cell opens th e possibility to control a hard ware pin independent of its normal use case. basically the cell can only do one of the following: control, output and input. 8.4.6.8 boundary scan path this chapter shows the boundary scan path of the slrc610. fig 18. boundary scan cell path structure 001aam306 ta p logic logic ta p ic1 ic2 tck tms tck tms tdo tdo boundary scan cell tdi tdi table 20. boundary scan path of the slrc610 number (decimal) cell port function 23 bc_1 - control 22 bc_8 clkout bidir 21 bc_1 - control 20 bc_8 scl2 bidir 19 bc_1 - control 18 bc_8 sda2 bidir 17 bc_1 - control 16 bc_8 ifsel0 bidir 15 bc_1 - control 14 bc_8 ifsel1 bidir
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 27 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution refer to the slrc610 bsdl file. 8.4.6.9 boundary scan description language (bsdl) all of the boundary scan devices have a uni que boundary structure which is necessary to know for operating the device. important components of this language are: ? available test bus signal ? compliance pins ? command register ? data register ? boundary scan structure (number and types of the cells, their function and the connection to the pins.) the slrc610 is using the cell bc_8 for the io-lines. the i 2 c pin is using a bc_4 cell. for all pad enable lines the cell bc1 is used. the manufacturer's iden tification is 02bh. ? attribute idcodeister of slrc610: en tity is "0001" and -- version ? "0011110010000010b" and -- part number (3c82h) ? "00000010101b" and -- manufacturer (02bh) ? "1b"; -- mandatory the user code data is coded as followed: ? product id (3 bytes) ? version these four bytes are stored as th e first four bytes in the eeprom. 13 bc_1 - control 12 bc_8 if0 bidir 11 bc_1 - control 10 bc_8 if1 bidir 9 bc_1 - control 8b c _ 8i f 2b i d i r 7 bc_1 if2 output2 6b c _ 4i f 3b i d i r 5 bc_1 - control 4 bc_8 irq bidir 3 bc_1 - control 2 bc_8 sigin bidir 1 bc_1 - control 0 bc_8 sigout bidir table 20. boundary scan path of the slrc610 number (decimal) cell port function
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 28 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.4.6.10 non-ieee1149.1 commands interface on/off: with this command the host/sam interface can be deactivated and the read and write command of the boundary scan in terface is activated. (data = 1). with update-dr the value is taken over. register access read: at capture-dr the actual address is read and stored in the dr. shifting the dr is shifting in a new address. with update-dr this address is taken over into the actual address.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 29 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.5 buffer 8.5.1 overview an 512 ? 8-bit fifo buffer is implemented in the slrc610. it buffers the input and output data stream between the host and the internal state machine of the slrc610. thus, it is possible to handle data streams with lengths of up to 512 bytes without taking timing constraints into account. the fifo can also be lim ited to a size of 255 byte. in this case all the parameters (fifo length, wa termark...) require a single by te only for definition. in case of a 512 byte fifo length the definition of this values requires 2 bytes. 8.5.2 accessing the fifo buffer when the ? -controller starts a command, the slrc610 may, while the command is in progress, access the fifo-buffer according to that command. physically only one fifo-buffer is implemented, which can be used in input and output direction. therefore the ? -controller has to take care, not to access th e fifo buffer in a way that corrupts the fifo data. 8.5.3 controlling the fifo buffer besides writing to and reading from the fifo buffer, the fifo-buffer pointers might be reset by setting the bit fifofl ush in fifocontrol to 1. consequently, the fifolevel bits are set to logic 0, the actually stored bytes are not accessible any more and the fifo buffer can be filled with another 512 bytes (or 255 bytes if the bit fifosize is set to 1) again. 8.5.4 status information about the fifo buffer the host may obtain the following da ta about the fifo-buffers status: ? number of bytes already stored in the fifo-buffer. writing increments, reading decrements the fifo level: fifolength in register fifolength (and fifocontrol register in 512 byte mode) ? warning, that the fifo-buffer is almost full: hialert in register fifocontrol according to the value of the water level in register waterlevel (register 02 h bit [2], register 03h bit[7:0]) ? warning, that the fifo-buffer is almost empty: loalert in register fifocontrol according to the value of the water level in register waterlevel (register 02h bit [2], register 03h bit[7:0]) ? fifoovl bit indicates, that bytes were wr itten to the fifo buffer although it was already full: errirq in register irq0. waterlevel is one single value defining both hialert (counting from the fifo top) and loalert (counting from the fifo bottom). the slrc610 can generate an interrupt signal if: ? loalertirqen in register irq0 en is set to logic 1 it will activate pin irq when loalert in the register fifocontrol changes to 1. ? hialertirqen in register irq0 en is set to logic 1 it will activate pin irq when hialert in the register fifocontrol changes to 1.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 30 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution the bit hialert is set to logic 1 if maximum water level bytes (a s set in register waterlevel) or less can be stored in the fifo-buffer. it is generated according to the following equation: (2) the bit loalert is set to logic 1 if water level bytes (as set in register waterlevel) or less are actually stored in the fifo-buffer. it is generated according to the following equation: (3) hialert fifosize fifolength ? ? ? waterlevel ? = loalert fifolength waterlevel ? =
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 31 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.6 analog interface and contactless uart 8.6.1 general the integrated contactless uart supports the external host online with framing and error checking of the protocol requirements up to 848 kbit/s. an external circuit can be connected to the communication interface pins sigin and sigout to modulate and demodulate the data. the contactless uart handles the protocol requirements for the communication schemes in co-operation with the host. the protocol handling itself generates bit- and byte-oriented framing and handles error detection like pa rity and crc according to the different contactless communication schemes. the size, the tuning of the antenna, and the su pply voltage of the output drivers have an impact on the achievable field strength. the operating distance between reader and card depends additionally on the type of card used. 8.6.2 tx transmitter the signal delivered on pin tx1 and pin tx2 is the 13.56 mhz carrier modulated by an envelope signal for energy and data transmission. it can be used to drive an antenna directly, using a few passive componen ts for matching and filtering, see section 14 ? application information ? . the signal on tx1 and tx2 can be configured by the register drvmode, see section 9.8.1 ? txmode ? . the modulation index can be set by the txamp. following figure shows the general relations during modulation note: when changing the continuous carrier amp litude, the residual carrier amplitude also changes, while the modulation index remains the same. fig 19. general dependences of modulation 001aan355 time influenced by set_clk_mode envelope tx ask100 1: defined by set_cw_amplitude. 2: defined by set_residual_carrier. tx ask10 (1) (2)
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 32 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution the registers section 9.8 and section 9.10 control the data rate, the framing during transmission and the setting of the antenna driver to support the requirements at the different specified modes and transfer speeds. register txamp and the bits for set_residual_carrier define the modulation index: table 21. settings for tx1 and tx2 txclkmode (binary) tx1 and tx2 output remarks 000 high impedance - 001 0 output pulled to 0 in any case 010 1 output pulled to 1 in any case 110 rf high side push open drain, only high side (push) mos supplied with clock, clock parity defined by invtx; low side mos is off 101 rf low side pull open drain, only low side (pull) mos supplied with clock, clock parity defined by invtx; high side mos is off 111 13.56 mhz clock derived from 27.12 mhz quartz divided by 2 push/pull operation, clock polarity defined by invtx; setting for 10% modulation table 22. setting residual carrier and modula tion index by txamp.set_residual_carrier set_residual_carrier (decimal) residual carrier [%] modulation index [%] 0990.5 1981.0 2962.0 3943.1 4914.7 5895.8 6877.0 7867.5 8858.1 9848.7 10 83 9.3 11 82 9.9 12 81 10.5 13 80 11.1 14 79 11.7 15 78 12.4 16 77 13.0 17 76 13.6 18 75 14.3 19 74 14.9 20 72 16.3 21 70 17.6 22 68 19.0
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 33 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution note: at vdd(tvdd) <5 v and residual carrier settings <50%, the accuracy of the modulation index may be low in dependency of the antenna tuning impedance 8.6.2.1 overshoot protection the slrc610 provides an overshoot pr otection for 100% ask to avoid overshoots during a pcd communication. therefore two timers ov ershoot_t1 and overshoot_t2 can be used. during the timer overshoot_t1 runs an amp litude defined by set_cw_amplitude bits is provided to the output driver. followed by an amplitude denoted by set_residual_carrier bits with the duration of overshoot_t2. 23 65 21.2 24 60 25.0 25 55 29.0 26 50 33.3 27 45 37.9 28 40 42.9 29 35 48.1 30 30 53.8 31 25 60.0 table 22. setting residual carrier ?continued and modulation index by set_residual_carrier (decimal) residual carrier [%] modulation index [%] fig 20. example 1: overshoot_t1 = 2d; overhoot_t2 = 5d. 001aan356 2.50 3.03 3.56 4.10 time (s) 7.0 5.0 (v) 3.0 1.0 -1.0
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 34 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.6.2.2 bit generator the default coding of a data stream is done by using the bit-generator. it is activated when the value of txframecon.dcodetype is set to 0000 (bin). the bit-generator encodes the data stream byte-wise and can apply the following encoding steps to each data byte. 1. add a start-bit of specified type at beginning of every byte 2. add a stop-bit and egt bits of a specified type. the maximum number of egt bit is 6, only full bits are supported 3. add a parity-bit of a specified type 4. txfirstbits (skips a given number of bits at the beginning of the first byte in a frame) 5. txlastbits (skips a given number of bits at the end of the last byte in a frame) 6. encrypt data-bit (mifare encryption) txfirstbits and txlastbits can be used at the same time. if only a single data byte is sent, it must be ensured that the range of txfirstbits and txlastbits do not overlap. it is not possible to skip more than 8 bi t of a single byte! ( (8 - txfirs tbits) + (8 - txlastbits) ) < 8 by default, data bytes are always treated lsb fi rst. to make use of a msb first coding, the txmsbfirst in the register clcon1 needs to be set. 8.6.3 receiver circuitry 8.6.3.1 general the slrc610 features a versatile quadrature rece iver architecture with fully differential signal input at rxp and rxn. it can be co nfigured to achieve optimum performance for reception of various 13.56 mhz based protocols. for all processing units various adjustments can be made to obtain optimum performance. fig 21. example 2: overshoot_t1 = 0d; overhoot_t2 = 5d 0 -1.0 1234 t 1.0 3.0 5.0 (v) 7.0
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 35 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.6.3.2 block diagram figure 22 shows the block diagram of the receiver circuitry. the receiving process includes several steps. first the quadratu re demodulation of the carrier signal of 13.56 mhz is done. several tuning steps in this circuit are possible. the receiver can also be operated in a single ended mode. in this case the rcv_rx_single bit has to be set. in the singl e ended mode, the two receiver pins rxp and rxn need to be connected toge ther and will provide a single ended signal to the receiver circuitry. when using the receiver in a single ended mo de the receiver sensitivity is decreased and the achievable reading distance might be reduc ed, compared to the fully differential mode. the quadrature-demodulator uses two different clocks, q-clock and i-clock, with a phase shift of 90 ? between them. both resulting baseband si gnals are amplified, filtered, digitized and forwarded to a correlation circuitry. the typical application is intend ed to implement the fully diff erential mode and will deliver maximum reader/writer distance. the quasi diff erential mode can be used together with dedicated antenna topologies that allow a re duction of matching components at the cost of overall reading performance. fig 22. block diagram of receiver circuitry table 23. configuration for sing le or differential receiver mode rcv_rx_single pins rxp and rxn fully differential 0 provide differential signal from differential antenna by separate rx-coupling branches quasi differential 1 connect rxp and rxn together and provide single ended signal from antenna by a single rx-coupling branch 001aan358 13.56 mhz i/o clock generation i-clks q-clks clk_27 mhz timing generation adc data data adc_data_ready clk_27 mhz mixer mix_out_i_p 2-stage bba mix_out_i_n out_i_p out_i_n rx_p rx_n rx_p rx_n mixer mix_out_q_p 2-stage bba mix_out_q_n out_q_p out_q_n rcv_gain<1:0> rcv_hpcf<1:0> fully/quasi-differential fully/quasi-differential rcv_gain<1:0> rcv_hpcf<1:0> rx_p rx_n
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 36 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution during low power card detection the dc levels at the i- and q-channel mixer outputs are evaluated. this requires that mixers are directly connected to the adc. this can be configured by setting the bit rx_adcmode in register rcv (38h). 8.6.4 active antenna concept two main blocks are implemented in the slrc610. a digital circuitry, comprising state machines, coder and decoder logic and an analog circuitry with the modulator and antenna drivers, receiver and amplification ci rcuitry. for example, the interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins sigin and sigout. the most important use of this topology is the active antenna concept where the digital and the analog blocks are separated. this opens the possibility to connect e.g. an additional digital block of another slrc610 device with a single analog antenna front-end. the ta b l e 2 4 and table 25 describe the necessary register configuration for the use case active antenna concept. the interface between these two blocks can be configured in the way, that the interfacing signals may be routed to th e pins sigin and sigout (see figure 24 ? overview sigin/sigout si gnal routing ? ). this topology supports, that some parts of the analog part of the slrc610 may be connected to the digital part of another device. the switch sigoutsel in register sigout can be used to measur e signals. this is especially important during the design in phase or for test purposes to check the transmitted and received data. fig 23. block diagram of the active antenna concept table 24. register configuration of slrc610 active antenna concept (digital) register value (binary) description sigout.sigoutsel 0100 txenvelope rcv.siginsel 11 receive over sigin (generic code) drvcon.txsel 00 low (idle) table 25. register configuration of slrc610 active antenna concept (antenna) register value (binary) description sigout.sigoutsel 0110 generic code (manchester) rcv.siginsel 01 internal drvcon.txsel 10 external (sigin) rxctrl.rxmultiple 1 rxmultiple on 001aam307 sigin sigin sigout sigout reader ic (digital) reader ic (antenna)
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 37 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution however, the most important use of sigin/si gout pins is the active antenna concept. an external active antenna circuit can be conn ected to the digital circuit of the slrc610. sigoutsel has to be configured in that way that the signal of the internal miller coder is sent to sigout pin (sigoutsel = 4). siginsel has to be configured to receive manchester signal with sub-carrier from sigin pin (siginsel = 1). it is possible, to connect a passive antenna to pins tx1, tx2 and rx (via the appropriate filter and matching circuit) and at the same time an active antenna to the pins sigout and sigin. in this configurat ion, two rf-parts may be driven (one after another) by a single host processor.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 38 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution fig 24. overview sigin/sigout signal routing 001aam001 coder sigoutsel[4:0] sigpro_in_sel [1:0] sigout sigin tx bit stream digital module analog module rx bit stream 0, 1 2 3 4 5 6 7 9 tri-state low high tx envelope tx active s3c signal rx envelope 8 rx active rx bit signal decoder subcarrier demodulator txcon.txsel [1:0] 0 1 2 3 no_nodulation tx envelope rfu sigin 0 1 2 3 tri-state internal analog block sigin over envelope sigin generic modulator driver tx2 tx1 rxn rxp demodulator
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 39 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.6.5 symbol generator the symbol generator is used to create vari ous protocol symbols like the cs symbol as used by the icode epc protocol. symbols are defined by means of the symbol definition registers an d the mode registers. four different symbols can be used. tw o of them, symbol0 and symbol1 have a maximum pattern length of 16 bit and feature a burst length of up to 256 bits of either logic ?0? or logic ?1?. the symbol2 and symbol3 are limited to 8 bit pattern length and do not support a burst. the definition of symbol patterns is done by writing the bit sequence of the pattern to the appropriate register. the last bit of the pattern to be sent is located at the lsb of the register. by setting the symbol length in the symbol-length register (txsym10len and txsym32len) the definition of the symbol pa ttern is completed. all other bits at bit-position higher than the symbol length in the definition register are ignored. (example: length of symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define th e symbol pattern, bit5 is sent first) which symbol-pattern is sent can be confi gured in the txframecon register. symbol0, symbol1 and symbol2 can be sent before da ta packets, symbol1, symbol2 and symbol3 can be sent after data packets. each symbol is defined by a set of registers. symbols are configured by a pair of registers. symbol0 and symbol1 share the same configuration and symbol2 and symbol3 share the same configur ation. the configuration includes setting of bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length and the envelope type. 8.7 memory 8.7.1 memory overview the slrc610 implements three different memories: eeprom , fifo and registers. at startup, the initializatio n of the registers which defin e the behavior of the ic is performed by an automatic copy of an eeprom area (read/write eeprom section1 and section2, register reset) into the registers. the behavior of the slrc610 can be changed by executing the command loadprotocol, which copies a selected default protocol from the eeprom (read only eeprom section4, register set protocol area) into the registers. the read/write eeprom se ction2 can be used to store any user data or predefined register settings. these predefined se ttings can be copied with the command "loadregister" into the internal registers. the fifo is used as input/out buffer and is able to improve the performance of a system with limited interface speed.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 40 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.7.2 eeprom memory organization the slrc610 has implemented a eeprom non- volatile memory with a size of 8 kb.the eeprom is organized in pages of 64 bytes. one page of 64 bytes can be programmed at a time. defined purpose s had been assigned to specific memory areas of the eeprom, which are called sections. five sections 0..4 with different purpose do exist. the following figure show the structure of the eeprom: table 26. eeprom memo ry organization section page byte addresses access rights memory content 0 0 00 to 31 r product information and configuration 32 to 63 r/w product configuration 1 1 to 2 64 to 191 r/w register reset 2 3 to 111 192 to 7167 r/w free 3 112 to 128 7168 to 8191 r register set protocol (rsp) fig 25. sector arrangement of the eeprom aaa-002467 production and config section 0: register reset section 1: free section 2: rsp-area for tx section 3_tx: rsp-area for rx section 3_rx:
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 41 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.7.2.1 product information and configuration - page 0 the first eeprom page include s production data as well as configuration information. productid : identifier for this slrc610 product, only address 01h shall be evaluated for identifying the product clrc663, address 00h and 02h shall be ignored by software. version : this register indicate s the version of the eeprom initialization data during production. (identification of th e hardware version is available in the register 7fh, not in the eeprom version address. t he hardware information in re gister 7fh is hardwired and therefore independent from any eeprom configuration.) unique identifier: unique identifier for this device manufacturer data: this data is programmed during production. the content is not intended to be used by any application and might be not the same for different devices. therefore this content needs to be considered to be undefined. i 2 c-address: two possibilities exist to de fine the address of the i 2 c interface. this can be done either by configuring the pins if0, if2 ( address is then 10101xx, xx is defined by the interface pins if0, if2) or by writing value into the i 2 c address area. the selection, which of this 2-information pi n configuration or eeprom content - is used as i 2 c-address is done at eeprom address 21h (interface, bit4) interface: this section describes the in terface byte configuration. table 27. production area (page 0) address (hex.) 0 1 2 3 4 5 6 7 00 productid version unique identifier 08 unique identifier manufacturer data 10 manufacturerdata 18 manufacturerdata table 28. product id overview of clrc663 family address 01h product id clrc663 01h mfrc631 c0h mfrc630 80h slrc610 20h table 29. configuration area (page 0) address (hex.) 0 1 2 3 4 5 6 7 20 i 2 c_address interface i 2 c sam_address defaultprotrx defaultprottx - txcrcpreset 28 rxcrcpreset - - - - - - 30 - 38 -
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 42 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution i 2 c_sam_address: the i 2 c sam address is always defi ned by the eeprom content. the register set protocol (rsp) area contains settings for the tx registers (16 bytes) and for the rx registers (8 bytes). txcrcpreset: the data bits are send by the anal og module and are automatically extended by a crc. table 30. interface byte bit 7 6 5 4 3 2 1 0 i 2 c_hsp - - i2c_address boundary scan host access rights r/w rfu rfu r/w r/w r/w table 31. interface bits bit symbol description 7 i 2 c_hsp when cleared, the high speed mode is used when set, the high speed+ mode is used (default) 6, 5 rfu - 4i 2 c_address when cleared, the pins are used (default) when set, the eeprom is used 3 boundary scan when cleared, the boundary scan interface is on (default) when set, the boundary scan is off 2 to 0 host 000b - rs232 001b - i 2 c 010b - spi 011b - i 2 cl 1xxb - pin selection table 32. tx and rx arrangements in the register set protocol area section section 4 tx tx0 tx1 tx2 tx3 section 4 tx tx4 tx5 tx6 tx7 section 4 rx rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 section 4 rx rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 43 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.7.3 eeprom initialization content loadprotocol the slrc610 eeprom is initializ ed at production with val ues which are used to reset certain registers of the slrc610 to default settings by copying the eeprom content to the registers. only registers or bi ts with ?read/write? or ?dynamic ? access rights are initialized with this default values copied from the eeprom. note that the addresses used for copying reset values from eeprom to registers are dependent on the configured protocol and can be changed by the user. the register reset values are configuration parameters used after startup of the ic. they can be changed to modify the default behavior of the device. in addition to this register reset values, is the po ssibility to load settings for various user implemented protocols.the load protocol command is used for this purpose. table 33. register reset values (hex.) (page0) address 0 (8) 1 (9) 2 (a) 3 (b) 4 (c) 5 (d) 6 (e) 7 (f) function product id version unique serial number 00 xx see table 34 xx xx xx xx xx xx function unique serial number factory trim value 08 xx xx xx xx xx xx xx xx function trimlfo factory trim values 10 xx xx xx xx xx xx xx xx function factory trim values 18....xxxxxxxxxxxxxxxx factory trim values ....38xxxxxxxxxxxxxxxx table 34. register reset values (hex.)(page1 and page 2) address 0 (8) 1 (9) 2 (a) 3 (b) 4 (c) 5 (d) 6 (e) 7 (f) command hostctrl fifocontrol waterlevel fifolength fifodata irq0 irq1 40 40 00 80 05 00 00 00 00 irq0en irq1en error status rxbitctrl rxcoll tcontrol t0control 48 10 00 00 00 00 00 00 00 t0reloadhi t0reloadlo t0counter valhi t0counter vallo t1control t1reloadhi t1reloadlo t1counter valhi 50 00 80 00 00 00 00 80 00 t1counter vallo t2control t2reloadhi t2reloadlo t2counter valhi t2counter vallo t3control t3reloadhi 58 00 00 00 80 00 00 00 00 t3reloadlo t3counter valhi t3counter valhi t4control t4reloadhi t4reloadlo t4counter valhi t4counter vallo 60 80 00 00 00 00 80 00 00
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 44 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution drvmode txamp drvcon txl txcrc preset rxcrc preset txdatanum txmodwith 68 86 15 11 06 18 18 08 27 txsym10 burstlen txwaitctrl txwaitlo framecon rxsofd rxctrl rxwait rxthres hold 70 00 c0 12 cf 00 04 90 3f rcv rxana rfu serialspeed lfo_trimm pll_ctrl pll_div lpcd_qmi n 78 12 0a 00 7a 80 04 20 48 lpcd_ qmax lpcd_imin lpcd _result_i lpcd _result_q paden padout padin sigout 80 12 88 00 00 00 00 00 00 txbitmod rfu txdatacon txdatamod txsymfreq txsym0h tysym0l txsym1h 88 20 xx 04 50 40 00 00 00 table 34. register reset values (hex.)(page1 and page 2) ?continued address 0 (8) 1 (9) 2 (a) 3 (b) 4 (c) 5 (d) 6 (e) 7 (f)
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 45 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.8 clock generation 8.8.1 crystal oscillator the clock applied to the slrc610 acts as time basis for generation of the carrier sent out at tx and for the quadrature mixer i and q cl ock generation as well as for the coder and decoder of the synchronous system. therefore stability of the clock frequency is an important factor for proper performance. to ob tain highest performance, clock jitter has to be as small as possible. this is best achieved by using the internal oscillator buffer with the recommended circuitry. 8.8.2 integern pll clock line the slrc610 is able to provide a clock with configurable frequency at clkout from 1 mhz to 24 mhz (pll_ctrl and pll_div). t here it can serve as a clock source to a microcontroller which avoids the need of a second crystal osc illator in the reader system. clock source for the integern-pll is the 27.12 mhz crystal oscillator. two dividers are determining the output frequency. first a feedback integer-n divider configures the vco frequency to be n ? fin/2 (control signal pll_set_divfb). as supported feedback divider ratios are 23, 27 and 28, vco frequencies can be 23 ? fin / 2 (312 mhz), 27 ? fin / 2 (366 mhz) and 28 ? fin / 2 (380 mhz). the vco frequency is divided by a factor which is defined by the output divider (pll_set_divout). table 36 ? divider values for selected frequencies using the integern pll ? shows the accuracy achieved fo r various frequencies (integer multiples of 1 mhz and some typical rs232 frequencies) and the divi der ratios to be used. the register bit clkouten enables the clock at clkout pin. the following formula can be used to calculate the output frequency: fig 26. quartz connection table 35. crystal requirements recommendations symbol parameter conditions min typ max unit f xtal crystal frequency - 27.12 - mhz ? f xtal /f xtal relative crystal frequency variation ? 250 - +250 ppm esr equivalent series resistance -50100 ? c l load capacitance - 10 - pf p xtal crystal power dissipation -50100 ? w 001aam308 27.12 mhz xtal1 xtal2 reader ic
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 46 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution f out = 13.56 mhz ? plldiv_fb /plldiv_out 8.8.3 low frequency oscillator (lfo) the low-frequency (lfo) is implemented to drive a wake-up counter (wuc). this wakes up the system in regular time intervals and eas es the design of a reader that is regularly polling for card presence or implements a low- power card detection. the lfo is trimmed during production to run at 16 khz. unless a high accuracy of the lfo is required by the application and the device is operated in an environment with changing ambient temperatures, trimming of the lfo is not required. for a typical application making use of the lfo for wake up from power down, the trim value set during production can be used. optional trimming to achieve a higher accuracy of the 16 khz lfo clock is supported by a digital stat e machine which compares lfo-clock to a reference clock. as referenc e clockfrequency the 13.56 mhz crystal clock is available. table 36. divider values for selected frequencies using the integern pll frequency [mhz] 4 6 8 10 12 20 24 1.8432 3.6864 plldiv_fb 2327232823282328 28 plldiv_out 78 61 39 38 26 19 16 206 103 accuracy [%] 0.04 0.03 0.04 0 .08 0.04 0.08 0.04 0.01 0.01
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 47 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.9 power management 8.9.1 supply concept the slrc610 is supplied by v dd (supply voltage), pvdd (pad supply) and tvdd (transmitter power supply). these three voltages are independent from each other. to connect the slrc610 to a microcontroller supplied by 3.3 v, pvdd and v dd shall be at a level of 3.3 v, tvdd can be in a range from 3.3 v to 5.0 v. a higher supply voltage at tvdd will result in a hi gher field strength. independent of the voltage it is recommended to buffer these supplies with blocking capacitances close to the terminals of the package. v dd and pvdd are recommended to be blocked with a capacitor of 100 nf min, tvdd is recommended to be blocked with 2 capacitors, 100 nf parallel to 1.0 ? f avdd and dvdd are not supply input pins. they are output pins and shall be connected to blocking capacitors 470 nf each. 8.9.2 power reduction mode 8.9.2.1 power-down a hard power-down is enabled with high level on pin pdown. this turns off the internal 1.8 v voltage regulators for the analog and digital core supply as well as the oscillator. all digital input buffers are separated from the input pads and clamped internally (except pin pdown itself). the output pins are switched to high impedance. to leave the power- down mode the level at the pin pdow n as to be set to low. this will start the internal start-up sequence. 8.9.2.2 standby mode the standby mode is entered immediately afte r setting the bit powerdown in the register command. all internal cu rrent sinks are switched off exce pt the lfo. voltage references and voltage regulators will be set into stand-by mode. in opposition to the power-down mode, the digital input buffers are not separated by the input pads and keep their functionality. the digital output pins do not change their state. during standby mode, all registers values, the fifo?s content and the configuration itself will keep its current content. to leave the standby mode the bit powerdown in the register command is cleared. this will trigger the internal start-up sequence. the reader ic is in full operation mode again when the internal start-up sequence is finalized (the typical duration is 15 us). alternatively, a value of 55h can be sent to the slrc610 using the rs232 interface to leave the standby mode. then read accesses shall be performed at address 00h until the device returns the content of this address. the return of the content of address 00h indicates that the device is ready to receive further commands and the internal start-up sequence is finalized. 8.9.2.3 modem off mode when the modemoff bit in the register cont rol is set the antenna transmitter and the receiver are switched off.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 48 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution to leave the modem off mode clears t he modemoff bit in the register control. 8.9.3 low-power card detection (lpcd) the low-power card detection is an energy sa ving mode in which the slrc610 is not fully powered permanently. the lpcd works in two phases. first the standby phase is controlled by the wake-up counter (wuc), which defines the duration of the standby of the slrc610. second phase is the detection-phase. in this phase the valu es of the i and q channel are detected and stored in the register map. (lpcd_i_result, lpcd_q_result).this time period can be handled with timer3. the value is compared with the min/max values in the registers (lpcd_imin, lpcd_imax; lpcd_qmin, lpcd_qma x). if it exceeds the limits, a lpcdirq is raised. after the command lpcd the standby of the slrc610 is activated, if selected. the wake-up timer4 can activate the system after a given time. for the lpcd it is recommended to set t4autowakeup and t4autorestart, to start the timer and then go to standby. if a card is detected the timer stop s and the communication can be started. if t4autowakeup is not set, the ic will not enter st andby mode in case no card is detected. 8.9.4 reset and start-up time a 10 ? s constant high level at the pdown pin starts the internal reset procedure. the following figure shows the internal voltage regulator: when the slrc610 has finished the reset phase and the oscillator has entered a stable working condition the ic is ready to be used. fig 27. internal pdown to voltage regulator logic 001aan360 pvdd pdown v ss glitch filter internal voltage regulator v dd v ss 1.8 v 1.8 v avdd dvdd
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 49 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.10 command set 8.10.1 general the behavior is determined by a state machine capable to perform a certain set of commands. by writing the according command-code to register command the command is executed. arguments and/or data necessary to process a command, are exchanged via the fifo buffer. ? a data transmission of the txencoder can be started by a command. when started, the communication is executed as defined in the txframecon register. therefore a communication frame can consist of a star t-symbol, a data-stream, and followed by an end-symbol. ? each command that needs a certain number of arguments will start processing only when it has received the correct number of arguments via the fifo buffer. ? the fifo buffer is not cleared automatically at command start. therefore, it is recommended to write the command arguments and/or the data bytes into the fifo buffer and start the command afterwards. ? each command may be interrupted by the host by writing a new command code into register command e.g.: the idle-command. 8.10.2 command set overview table 37. command set command no. parameter (bytes) short description idle 00h - no action, cancels current command execution lpcd 01h - low-power card detection ackreq 04h - performs a query, an ack and a req-rn for iso/iec 18000-3 mode 3/ epc class-1 hf receive 05h - activates the receive circuit transmit 06h - transmits data from the fifo buffer transceive 07h - transmits data from the fifo buffer and automatically activates the receiver after transmission finished writee2 08h addressl, addressh, data; gets one byte from fifo buffer and writes it to the internal eeprom, valid address range are the addresses of the mifare key area writee2page 09h (page address), data0, [data1 ..data63]; gets up to 64 bytes (one eeprom page) from the fifo buffer and writes it to t he eeprom, valid page address range are the pages of the mifare key area reade2 0ah addressl, address h, length; reads data from the eeprom and copies it into the fifo buffer, valid address range are the addresses of the mifare key area loadreg 0ch (eeprom addressl), (eeprom addressh), regadr, (number of register to be copied); reads data from the internal eeprom and initializes the slrc610 registers. eeprom address needs to be within eeprom sector 2
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 50 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.10.3 command functionality 8.10.3.1 idle command command (00h); this command indicates that th e slrc610 is in idle mode. th is command is also used to terminate the actual command. 8.10.3.2 lpcd command command (01h); this command performs a low-power card detec tion and or an automatic trimming of the lfo. the values of the sampled i and q channel are stored in the register map. the value is compared with the min/max values in the register. if it exceeds the limits, an lpcd_irq will be raised. after the command the st andby is activated if selected. 8.10.3.3 ackreq command command (04h); performs a query (full command must be wr itten into the fifo); a ack and a reqrn command. all answers to the command will be written into the fifo. the error flag is copied after the answer into the fifo. this command terminates automatically when finished and the active command is idle. 8.10.3.4 receive command command (05h); the slrc610 activates the receiver path, waits for any data stream to be received, according to its register settings, which shall be set before starting this command according the used protocol and antenna configuration. the correct settings have to be chosen before starting this command. this command terminates automatically when the received data stream ends. this is indicated either by the end of frame patter n or by the length byte depending on the selected framing and speed. remark: if the bit rxmultiple in the rxmodereg register is set to logic 1, the receive command does not terminate automatically. it has to be terminated by activating any other command in the commandreg register (see section 0.2.6 ? rxmod ? ). 8.10.3.5 transmit command command (06h); loadprotocol 0dh (protocol umber rx), (protocol number tx); reads data from the internal eeprom and initializes the slrc610 registers needed for a protocol change readrnr 1ch - copies bytes from the random number generator into the fifo until the fifo is full soft reset 1fh - resets the slrc610 table 37. command set ?continued command no. parameter (bytes) short description
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 51 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution the content of the fifo is transmitted immediately after starting the command. before transmitting the fifo content all relevant re gister have to be se t to transmit data. this command terminates automatically when t he fifo gets empty. it can be terminated by any other command written to the command register. 8.10.3.6 transceive command command (07h); this command transmits data from the fifo and receives data from the rf field at once. the first action is transmitting and afte r a transmission the command is changed to receive a data stream. each transmission process starts by writing the command into commandreg. remark: if the bit rxmultiple in register rx modereg is set to logic 1, this command will never leave the receiving stat e, because the receiving will not be cancelled automatically. 8.10.3.7 writee2 command command (08h), parameter1 (addressl), parameter2 (addressh), parameter3 (data); this command writes one byte into the eeprom. if the fifo contains no data, the command will wait until th e data is available. abort condition: insufficient parameter in fifo; address-parameter outside of range. 8.10.3.8 writee2page command command (09h), parameter1 (page address), parameter2 (data0), parameter3...65 [data1 ..data63]; this command writes up to 64 bytes into the eeprom. abort condition: insufficient parameters in fifo; page address parameter outside of range. 8.10.3.9 reade2 command command (0ah), parameter1 (addressl), parameter2 (addressh), parameter3 (length); reads up to 256 bytes from the eeprom to the fifo. if a read operation exceeds the address 1fffh, the read operation continues from address 0000h. abort condition: insufficient parameter in fifo; address parameter outside of range. 8.10.3.10 loadreg command command (0ch), parameter1 (eeprom addressl),parame ter2 (eeprom addressh), parameter3 (regadr), parameter4 (number); read a defined number of bytes from the eeprom and copies the valu e into the register set, beginning at the given address regadr. abort condition: insufficient parameter in fifo; address parameter outside of range. 8.10.3.11 loadprotocol command command (0dh), parameter1 (protocol number rx), parameter2 (protocol number tx);
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 52 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution reads out the eeprom register set protocol area and overwrites the content of the rx- and tx- related registers. these register s are important for a protocol selection. abort condition: insuffic ient parameter in fifo [1] for more protocol details please refer to section 8 ? functional description ? . [1] for more protocol details please refer to section 8 ? functional description ? . 8.10.3.12 getrnr command command (1ch); this command is reading random numbers from the random number generator of the slrc610. the random numbers are copied to the fifo until the fifo is full. 8.10.3.13 softreset command command (1fh); table 38. predefined protocol overview rx [1] protocol number (decimal) protocol receiver speed [kbits/s] receiver coding 00 iso/iec15693 26 ssc 01 iso/iec15693 52 ssc 02 iso/iec15693 26 dsc 03 epc/uid 26 ssc 04 iso/iec 18000-3 mode 3/ epc class-1 hf 2/424 05 iso/iec 18000-3 mode 3/ epc class-1 hf 4/424 06 iso/iec 18000-3 mode 3/ epc class-1 hf 2/848 07 iso/iec 18000-3 mode 3/ epc class-1 hf 4/848 table 39. predefined protocol overview tx [1] protocol number (decimal) protocol transmitter speed [kbits/s] transmitter coding 00 iso/iec15693 26 1/4 01 iso/iec15693 26 1/4 02 iso/iec15693 1,66 1/256 03 epc/uid 53 unitray 04 iso/iec 18000-3 mode 3/ epc class-1 hf tari, ask, pie 05 iso/iec 18000-3 mode 3/ epc class-1 hf tari, ask, pie 06 iso/iec 18000-3 mode 3/ epc class-1 hf tari, ask, pie 07 iso/iec 18000-3 mode 3/ epc class-1 hf tari, ask, pie
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 53 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution this command is performing a soft reset. tri ggered by this command all the default values for the register sett ing will be read from the eeprom and copied into the register set.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 54 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9. slrc610 registers 9.1 register bit behavior depending on the functionality of a register, the access conditions to the register can vary. in principle, bits with same behavior are grouped in common registers. the access conditions are described in ta b l e 4 0 . table 40. behavior of register bits and their designation abbreviation behavior description r/w read and write these bits can be writte n and read via the host interface. since they are used only for contro l purposes, the content is not influenced by the state machines but can be read by internal state machines. dy dynamic these bits can be written and re ad via the host interface. they can also be written automatically by internal state machines, for example command register changes its value automatically after the execution of the command. r read only these register bits indicates hold values which are determined by internal states only. w write only reading these register bits always returns zero. rfu - these bits are reserved for future use and must not be changed. in case of a required write access, it is recommended to write a logic 0. table 41. slrc610 registers overview address register name function 00h command starts and stops command execution 01h hostctrl host control register 02h fifocontrol control register of the fifo 03h waterlevel level of the fifo underflow and overflow warning 04h fifolength length of the fifo 05h fifodata data in/out exchange register of fifo buffer 06h irq0 interrupt register 0 07h irq1 interrupt register 1 08h irq0en interrupt enable register 0 09h irq1en interrupt enable register 1 0ah error error bits showing the error status of the last command execution 0bh status contains status of the communication 0ch rxbitctrl control register for anticollisio n adjustments for bit oriented protocols 0dh rxcoll collision position register 0eh tcontrol control of timer 0..3 0fh t0control control of timer0 10h t0reloadhi high register of the reload value of timer0 11h t0reloadlo low register of the reload value of timer0 12h t0countervalhi counter value high register of timer0 13h t0countervallo counter value low register of timer0
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 55 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 14h t1control control of timer1 15h t1reloadhi high register of the reload value of timer1 16h t1reloadlo low register of the reload value of timer1 17h t1countervalhi counter value high register of timer1 18h t1countervallo counter value low register of timer1 19h t2control control of timer2 1ah t2reloadhi high byte of the reload value of timer2 1bh t2reloadlo low byte of the reload value of timer2 1ch t2countervalhi counter value high byte of timer2 1dh t2countervallo counter value low byte of timer2 1eh t3control control of timer3 1fh t3reloadhi high byte of the reload value of timer3 20h t3reloadlo low byte of the reload value of timer3 21h t3countervalhi counter value high byte of timer3 22h t3countervallo counter value low byte of timer3 23h t4control control of timer4 24h t4reloadhi high byte of the reload value of timer4 25h t4reloadlo low byte of the reload value of timer4 26h t4countervalhi counter value high byte of timer4 27h t4countervallo counter value low byte of timer4 28h drvmod driver mode register 29h txamp transmitter amplifier register 2ah drvcon driver configuration register 2bh txl transmitter register 2ch txcrcpreset transmitter crc control register, preset value 2dh rxcrcpreset receiver crc control register, preset value 2eh txdatanum transmitter data number register 2fh txmodwidth transmitter modulation width register 30h txsym10burstlen transmitter symbol 1 + symbol 0 burst length register 31h txwaitctrl transmitter wait control 32h txwaitlo transmitter wait low 33h framecon transmitter frame control 34h rxsofd receiver start of frame detection 35h rxctrl receiver control register 36h rxwait receiver wait register 37h rxthreshold receiver threshold register 38h rcv receiver register 39h rxana receiver analog register 3ah rfu - 3bh serialspeed serial speed register 3ch lfo_trimm low-power oscillator trimming register table 41. slrc610 registers overview ?continued address register name function
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 56 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 3dh pll_ctrl integern pll control register, for microcontroller clock output adjustment 3eh pll_divout integern pll control register, for microcontroller clock output adjustment 3fh lpcd_qmin low-power card detection q channel minimum threshold 40h lpcd_qmax low-power card detection q channel maximum threshold 41h lpcd_imin low-power card detection i channel minimum threshold 42h lpcd_i_result low-power card detection i channel result register 43h lpcd_q_result low-power card detection q channel result register 44h paden pin enable register 45h padout pin out register 46h padin pin in register 47h sigout enables and controls the sigout pin 48h-5fh rfu - 7fh version version and subversion register table 41. slrc610 registers overview ?continued address register name function
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 57 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.2 command configuration 9.2.1 command starts and stops command execution. 9.3 sam configuration register 9.3.1 hostctrl via the hostctrl register the interface access right can be controlled table 42. command register (address 00h) bit 7 6 5 4 3 2 1 0 symbol standby modem off rfu command access rights dy r/w - dy table 43. command bits bit symbol description 7 standby set to 1, the ic is entering power-down mode. 6 modemoff set to logic 1, the receiver and the transmitter circuit is powering down. 5rfu - 4 to 0 command defines the actual command for the slrc610. table 44. hostctrl regi ster (address 01h); bit 7 6 5 4 3 2 1 0 symbol regen bushost bussam rfu sam interface saminterface rfu rfu access rights dy r/w r/w - r/w r/w - - table 45. hostctrl bits bit symbol description 7 regen if this bit is set to logic 1, the register can be changed at the next register access. the next write acce ss clears this bit automatically. 6 bushost set to logic 1, the bus control enables the host interface. this bit cannot be set together with bussam. this bit can only be set if the bit regen is previously set. 5 bussam set to logic 1, the bus control enables the sam interface. this bit cannot be set together with bushost. th is bit can only be set if the bit regen is previously set. 4rfu - 3 to 2 saminterface 0h:interface switched off 1h:interface spi active 2h:interface i 2 cl active 3h:interface i 2 c 1 to 0 rfu -
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 58 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.4 fifo configuration register 9.4.1 fifocontrol fifocontrol defines the characteristics of the fifo 9.4.2 waterlevel defines the level for fifo under- and overflow warning levels.this register is extended by 1 bit in fifocontrol in case the 512-byte fifo mode is activated by setting bit fifocontrol.fifosize. table 46. fifocontrol register (address 02h); bit 7 6 5 4 3 2 1 0 symbol fifosize hialert loalert fifo flush rfu waterlevel fifolength access rights r/w r r w - r/w r table 47. fifocontrol bits bit symbol description 7 fifosize set to logic 1, fifo size is 255 bytes; set to logic 0, fifo size is 512 bytes. it is recommended to change the fifo size only, when the fifo content had been cleared. 6 hialert set to logic 1, when the number of bytes stored in the fifo buffer fulfils the following equation: hialert = (fifosize - fifolength) <= waterlevel 5 loalert set to logic 1, when the number of bytes stored in the fifo buffer fulfils the following conditions: loalert =1 if fifolength <= waterlevel 4 fifoflush set to logic 1 empties the fifo buffer. reading this bit will always return 0 3rfu - 2 waterlevel defines the bit 8 (msb) for t he waterlevel (extension of waterlevel). this bit is only evaluated in the 512-byte fifo mode. bits 7..0 are defined in waterlevel. 1 to 0 fifolength defines the bit9 (msb) and bit8 for the fifo length (extension of fifolength). these two bits are only evaluated in the 512-byte fifo mode, the bits 7..0 ar e defined in fifolength. table 48. waterlevel register (address 03h); bit 7 6 5 4 3 2 1 0 symbol waterlevel access rights r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 59 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution table 49. waterlevel bits bit symbol description 7 to 0 waterlevel sets a level to indicate a fifo-buffer state which can be read from bits highalert and lowalert in the fifocontrol. in 512-byte fifo mode, the register is extended by bit waterlevel in the fifocontrol. this functionality can be used to avoid a fifo buffer overflow or underflow: the bit hialert bit in fifo control is read logic 1, if the number of bytes in the fifo-buffer is equal or less than the number defined by waterlevel. the bit loalert bit in fifo control is read logic 1, if the number of bytes in the fifo buffer is equal or le ss than the number defined by waterlevel. note: for the calculation of hialert and loalert see register description of these bits ( section 9.4.1 ? fifocontrol ? ).
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 60 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.4.3 fifolength number of bytes in the fifo buffer. in 512-byte mode this register is extended by fifocontrol.fifolength. 9.4.4 fifodata in- and output of fifo buffer. contrary to any read/write access to other addresses, reading or writing to the fifo address does not increment the address pointer. resulting in an efficient data transfer from and to the fifo buffer. writing to the fifodata register increments, reading decrements the number of bytes present in the fifo. 9.5 interrupt configuration registers the registers irq0 register and irq1 register implement a special f unctionality to avoid the not intended modification of bits. the mechanism of changing register conten ts requires the following consideration: irq(x). set indicates, if a set bit on position 0 to 6 shall be cleared or set. depending on the content of irq(x).set, a write of a logical 1 to positions 0 to 6 either clears or sets the corresponding bit. with this register the app lication can modify the interrupt status which is maintained by the slrc610. bit 7 indicates, if the intended modification is a setting or clearance of a bit. any 1 written to a bit position 6...0 will trigge r the setting or clearance of th is bit as defined by bit 7. example: writing ffh sets all bits 6..0, writin g 7fh clears all bits 6..0 of the interrupt request register table 50. fifolength register (address 04h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol fifolength access rights dy table 51. fifolength bits bit symbol description 7 to 0 fifolength indicates the number of bytes in the fifo buffer. in 512-byte mode this register is extended by the bits fifolength in the fifocontrol register. writing to the fifodata register increments, reading decrements the number of available bytes in the fifo. table 52. fifodata register (address 05h); bit 7 6 5 4 3 2 1 0 symbol fifodata access rights dy table 53. fifodata bits bit symbol description 7 to 0 fifodata data input and output port for the internal fifo buffer. refer to section 8.5 ? b uffer ? .
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 61 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.5.1 irq0 register interrupt re quest register 0. 9.5.2 irq1 register interrupt request register 1. table 54. irq0 register (address 06h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol set hi alertirq lo alerti rq idleirq txirq rxirq errirq rxsof irq access rights wdydydy dy dy dy dy table 55. irq0 bits bit symbol description 7 set 1: writing a 1 to a bit position 6..0 sets the interrupt request 0: writing a 1 to a bit position 6..0 clears the interrupt request 6 hialerirq set, when bit hialert in register status1reg is set. in opposition to hialert, hialertirq stores this event and can only be reset if set is cleared. 5 loalertirq set, when bit loalert in register status1 is set. in opposition to loalert, loalertirq stores this event and can only be reset if set is cleared 4 idleirq set, when a command terminates by itself e.g. when the command changes its value from any command to the idle command. if an unknown command is started, the command changes its content to the idle state and the bit idleirq is set. starting the idle command by the controller does not set bit idleirq. can only be reset if set is cleared. 3 txirq set, when data transmission is completed, which is immediately after the last bit is sent. can only be reset if set is cleared. 2 rxirq set, when the receiver det ects the end of a data stream. note: this flag is no indication that the received data stream is correct. the error flags have to be evaluated to get the status of the reception. can only be reset if set is cleared. 1 errirq set, when the one of the following errors is set: fifowrerr, fifoovl, proterr, nodataerr, integerr. can only be reset if set is cleared. 0 rxsoflrq set, when a sof or a subcarrier is detected. can only be reset if set is cleared. table 56. irq1 register (address 07h) bit 7 6 5 4 3 2 1 0 symbol set globalirq lpcd_irq timer4irq t imer3irq timer2irq timer1irq timer0irq access rights wdydydy dy dy dy dy
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 62 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.5.3 irq0en register interrupt request enable register for irq0. this register allows to define if an interrupt request is processed by the slrc610. 9.5.4 irq1en interrupt request enabl e register for irq1. table 57. irq1 bits bit symbol description 7 set 1: writing a 1 to a bit position 5..0 sets the interrupt request 0: writing a 1 to a bit position 5..0 clears the interrupt request 6 globalirq set, if an enabled irq occurs. 5 lpcd_irq set if a card is detected in low-power card detection sequence. 4 timer4irq set to logic 1 when timer4 has an underflow. 3 timer3irq set to logic 1 when timer3 has an underflow. 2 timer2irq set to logic 1 when timer2 has an underflow. 1 timer1irq set to logic 1 when timer1 has an underflow. 0 timer0irq set to logic 1 when timer0 has an underflow. table 58. irq0en register (address 08h) bit 7 6 5 4 3 2 1 0 symbol irq_inv hi alertirqen loalertirqen idl eirqen txirqen rxirqen errirqen rxsofirqen access rights r/w r/w r/w r/w r/w r/w r/w r/w table 59. irq0en bits bit symbol description 7 irq_inv set to one the signal of the irq pin is inverted 6 hi alerirqen set to logic 1, it allows the high alert interrupt request (indicated by the bit hialertirq) to be propagated to the globalirq 5 lo alertirqen set to logic 1, it allows the low alert interrupt request (indicated by the bit loalertirq) to be propagated to the globalirq 4 idleirqen set to logic 1, it allows the idle interrupt request (indicated by the bit idleirq) to be propagated to the globalirq 3 txirqen set to logic 1, it allows the tr ansmitter interrupt request (indicated by the bit txtirq) to be propagated to the globalirq 2 rxirqen set to logic 1, it allows the receiver interrupt request (indicated by the bit rxirq) to be propagated to the globalirq 1 errirqen set to logic 1, it allows the e rror interrupt request (indicated by the bit errorirq) to be propagated to the globalirq 0 rxsofirqen set to logic 1, it allows the rx sof interrupt request (indicated by the bit rxsofirq) to be propagated to the globalirq
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 63 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.6 contactless interface c onfiguration registers 9.6.1 error error register. table 60. irq1en register (address 09h); bit 7 6 5 4 3 2 1 0 symbol irqpushpull irqpinen lpcd_irqen timer4irqen timer3irqen timer2irqe n timer1irqen timer0irqen access rights r/w r/w r/w r/w r/w r/w r/w r/w table 61. irq1en bits bit symbol description 7 irqpushpull set to 1 the irq-pin acts as pushpull pin, otherwise it acts as opendrain pin 6 irqpinen set to logic 1, it allows the glo bal interrupt request (indicated by the bit globalirq) to be propagated to the interrupt pin 5 lpcd_irqen set to logic 1, it allows the lpcdinterrupt request (indicated by the bit lpcdirq) to be propagated to the globalirq 4 timer4irqen set to logic 1, it allows the timer4 interrupt request (indicated by the bit timer4irq) to be propagated to the globalirq 3 timer3irqen set to logic 1, it allows the timer3 interrupt request (indicated by the bit timer3tirq) to be propagated to the globalirq 2 timer2irqen set to logic 1, it allows the timer2 interrupt request (indicated by the bit timer2irq) to be propagated to the globalirq 1 timer1irqen set to logic 1, it allows the timer1 interrupt request (indicated by the bit timer1irq) to be propagated to the globalirq 0 timer0irqen set to logic 1, it allows the timer0 interrupt request (indicated by the bit timer0irq) to be propagated to the globalirq table 62. error register (address 0ah) bit 7 6 5 4 3 2 1 0 symbol ee_err fifowrerr fifoovl minframee rr nodataerr colldet proterr integerr access rights dy dy dy dy dy dy dy dy
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 64 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.6.2 status status register. table 63. error bits bit symbol description 7 ee_err an error appeared during t he last eeprom command. for details see the descriptions of the eeprom commands 6 fifowrerr data was written into the fifo , during a transmission of a possible crc, during "rxwait", "wait for data" or "receiving" state, or during an authentication command. the flag is cleared when a new cl command is started. if rxmultiple is active, the flag is cleared after the error flags have been written to the fifo. 5 fifoovl data is written into the fifo when it is already full. the data that is already in the fifo will remain untouched. all data th at is written to the fifo after this flag is set to 1 will be ignored. 4min frameerr a valid sof was received, but afterwards less then 4 bits of data were received. note: frames with less than 4 bits of da ta are automatically discarded and the rxdecoder stays enabled. furthermore no rxirq is set. the same is valid for less than 3 bytes if the emd suppression is activated note: minframeerr is automatically cl eared at the start of a receive or transceive command. in case of a transceive command, it is cleared at the start of the receiving phase ("wait for data" state) 3 nodataerr data should be sent, but no data is in fifo 2 colldet a collision has occurred. the positio n of the first collision is shown in the register rxcoll. note: colldet is automatically cleared at the start of a receive or transceive command. in case of a transceive command , it is cleared at the start of the receiving phase (?wait for data? state). note: if a collision is part of the defi ned eof symbol, colldet is not set to 1. 1 proterr a protocol error has occurred. a protocol error can be a wrong stop bit or sof or a wrong number of received data byte s. when a protocol error is detected, data reception is stopped. note: proterr is automatically cleared at start of a receive or transceive command. in case of a transceive command , it is cleared at the start of the receiving phase (?wait for data? state). note: when a protocol error occurs the last received data byte is not written into the fifo. 0 integerr a data integrity error has been detected. possible cause can be a wrong parity or a wrong crc. in case of a data integrity error the reception is continued. note: integerr is automatically cleared at start of a receive or transceive command. in case of a transceive command, it is cleared at the start of the receiving phase (?wait for data? state). note: if the nocoll bit is set, also a collision is setting the integerr.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 65 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.6.3 rxbitctrl receiver control register. table 64. status register (address 0bh) bit 7 6 5 4 3 2 1 0 symbol----- comstate access rights rfu rfu rfu rfu rfu r table 65. status bits bit symbol description 7to3 - rfu 2 to 0 comstate comstate shows the status of the transmitter and receiver state machine: 000b ... idle 001b ... txwait 011b ... transmitting 101b ... rxwait 110b ... wait for data 111b ... receiving 100b ... not used table 66. rxbitctrl register (address 0ch); bit 7 6 5 4 3 2 1 0 symbol valuesaftercoll rxalign nocoll rxlastbits access rights r/w r/w r/w w table 67. rxbitctrl bits bit symbol description 7 valuesafter coll if cleared, every received bit after a collision is replaced by a zero. this function is needed for iso/iec14443 anticollision
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 66 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 6 to 4 rxalign used for reception of bit oriented frames: rxalign defines the bit position length for the first bit received to be stored. further received bits are stored at the following bit positions. example: rxalign = 0h - the lsb of the received bit is stored at bit 0, the second received bit is stored at bit position 1. rxalign = 1h - the lsb of the received bit is stored at bit 1, the second received bit is stored at bit position 2. rxalign = 7h - the lsb of the received bit is stored at bit 7, the second received bit is stored in the following byte at position 0. note: if rxalign = 0, data is received byte-oriented, otherwise bit-oriented. 3 nocoll if this bit is set, a collision will result in an integerr 2 to 0 rxlastbits defines the number of valid bits of the last data byte received in bit-oriented communications. if zero the whole byte is valid. note: these bits are set by the rxdecoder in a bit-oriented communication at the end of the communication. they are reset at start of reception. table 67. rxbitctrl bits bit symbol description
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 67 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.6.4 rxcoll receiver collision register. table 68. rxcoll register (address 0dh); bit 7 6 5 4 3 2 1 0 symbol collposvalid collpos access rights rr table 69. rxcoll bits bit symbol description 7 collpos valid if set to 1, the value of collpos is va lid. otherwise no col lision is detected or the position of the collision is ou t of the range of bits collpos. 6 to 0 collpos these bits show the bit position of the first detected collision in a received frame (only data bits are interpreted). collpos can only be displayed for the first 8 bytes of a data stream. example: 00h indicates a bit collision in the 1st bit 01h indicates a bit collision in the 2nd bit 08h indicates a bit collision in the 9th bit (1st bit of 2nd byte) 3fh indicates a bit collision in the 64th bit (8th bit of the 8th byte) these bits shall only be interpreted in iso/iec 15693/icode sli read/write mode if bit collposvalid is set. note: if rxbitctrl.rxalign is set to a value different to 0, this value is included in the collpos. example: rxalign = 4h, a collision occurs in the 4th received bit (which is the last bit of that uid byte). the collpos = 7h in this case.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 68 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7 timer configuration registers 9.7.1 tcontrol control register of the timer section. the tcontrol implements a special functionalit y to avoid the not intended modification of bits. bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified. example: writing ffh sets all bits 7..4, writing f0h does not change any of the bits 7..4 9.7.2 t0control control register of the timer0. table 70. tcontrol register (address 0eh) bit 7 6 5 4 3 2 1 0 symbol t3running t2running t1running t0running t3start stopnow t2start stopnow t1start stopnow t0start stopnow access rights dy dy dy dy w w w w table 71. tcontrol bits bit symbol description 7 t3running indicates timer3 is running.if the bit t3startstopnow is set/reset, this bit and the timer can be started/stopped 6 t2running indicates timer2 is running. if the bit t2startstopnow is set/reset, this bit and the timer can be started/stopped 5 t1running indicates ttmer1 is running. if the bit t1startstopnow is set/reset, this bit and the timer can be started/stopped 4 t0running indicates timer0 is running. if the bit t0startstopnow is set/reset, this bit and the timer can be started/stopped 3t3startstop now the bit 7 of tcontrol t3running can be modified if set 2t2startstop now the bit 6of tcontrol t2running can be modified if set 1t1startstop now the bit 5of tcontrol t1running can be modified if set 0t0startstop now the bit 4 of tcontrol t0running can be modified if set table 72. t0control register (address 0fh); bit 7 6 5 4 3 2 1 0 symbol t0stoprx - t0start t0autorestart - t0clk access rights r/w rfu r/w r/w rfu r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 69 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.1 t0reloadhi high byte reload value of the timer0. 9.7.2.2 t0reloadlo low byte reload value of the timer0. table 73. t0control bits bit symbol description 7 t0stoprx if set, the timer stops immediately after receiving the first 4 bits. if cleared the timer does not stop automatically. note: if lfo trimming is selected by t0start, this bit has no effect. 6- rfu 5 to 4 t0start 00b: the timer is not started automatically 01b: the timer starts automatically at the end of the transmission 10b: timer is used for lfo trimming without underflow (start/stop on posedge) 11b: timer is used for lfo trimming with underflow (start/stop on posedge) 3 t0autorestart 1: the timer automatically re starts its count-down from t0reloadvalue, after the counter value has reached the value zero. 0: the timer decrements to zero and stops. the bit timer1irq is set to logic 1 when the timer underflows. 2- rfu 1 to 0 t0clk 00b: the timer input clock is 13.56 mhz. 01b: the timer input clock is 211,875 khz. 10b: the timer input clock is an underflow of timer2. 11b: the timer input clock is an underflow of timer1. table 74. t0reloadhi register (address 10h); bit 7 6 5 4 3 2 1 0 symbol t0reload hi access rights r/w table 75. t0reloadhi bits bit symbol description 7 to 0 t0reloadhi defines the high byte of the reload value of the timer. with the start event the timer loads the value of the registers t0reloadvalhi, t0reloadvallo. changing this register affects the timer only at the next start event. table 76. t0reloadlo register (address 11h); bit 7 6 5 4 3 2 1 0 symbol t0reloadlo access rights r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 70 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.3 t0countervalhi high byte of the counter value of timer0. 9.7.2.4 t0countervallo low byte of the counter value of timer0. 9.7.2.5 t1control control register of the timer1. table 77. t0reloadlo bits bit symbol description 7 to0 t0reloadlo defines the low byte of the reload value of the timer. with the start event the timer loads the value of the t0reloadvalhi, t0reloadvallo. changing this register affects the timer only at the next start event. table 78. t0countervalhi register (address 12h) bit 7 6 5 4 3 2 1 0 symbol t0countervalhi access rights dy table 79. t0countervalhi bits bit symbol description 7to0 t0counter valhi high byte value of the timer0. this value shall not be read out during reception. table 80. t0countervallo register (address 13h) bit 7 6 5 4 3 2 1 0 symbol t0countervallo access rights dy table 81. t0countervallo bits bit symbol description 7 to 0 t0countervallo low byte value of the timer0. this value shall not be read out during reception. table 82. t1control register (address 14h); bit 7 6 5 4 3 2 1 0 symbol t1stoprx - t1start t1autorestart - t1clk access rights r/w rfu r/w r/w rfu r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 71 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.6 t1reloadhi high byte (msb) reload value of the timer1. 9.7.2.7 t1reloadlo low byte (lsb) reload value of the timer1. table 83. t1control bits bit symbol description 7 t1stoprx if set, the timer stops after receiving the first 4 bits. if cleared, the timer is not stopped automatically. note: if lfo trimming is selected by t1start, this bit has no effect. 6- rfu 5 to 4 t1start 00b: the timer is not started automatically 01b: the timer starts automatically at the end of the transmission 10b: timer is used for lfo trimming without underflow (start/stop on posedge) 11b: timer is used for lfo trimming with underflow (start/stop on posedge) 3 t1autorestart set to logic 1, the timer automatically restarts its countdown from t1reloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer1irq is set to logic 1 when the timer underflows. 2- rfu 1 to 0 t1clk 00b: the timer input clock is 13.56 mhz 01b: the timer input clock is 211,875 khz. 10b: the timer input clock is an underflow of timer0 11b: the timer input clock is an underflow of timer2 table 84. t0reloadhi register (address 15h) bit 7 6 5 4 3 2 1 0 symbol t1reloadhi access rights r/w table 85. t1reloadhi bits bit symbol description 7 to 0 t1reloadhi defines the high byte reload value of the timer 1. with the start event the timer loads the value of the t1reloadvalhi and t1reloadvallo. changing this register affects the timer only at the next start event. table 86. t1reloadlo register (address 16h) bit 7 6 5 4 3 2 1 0 symbol t1reloadlo access rights r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 72 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.8 t1countervalhi high byte (msb) of the counter value of byte timer1. 9.7.2.9 t1countervallo low byte (lsb) of the counter value of byte timer1. 9.7.2.10 t2control control register of the timer2. table 87. t1reloadvallo bits bit symbol description 7 to 0 t1reloadlo defines the low byte of the reload value of the timer1. changing this register affects the timer on ly at the next start event. table 88. t1countervalhi register (address 17h) bit 7 6 5 4 3 2 1 0 symbol t1countervalhi access rights dy table 89. t1countervalhi bits bit symbol description 7 to 0 t1counter valhi high byte of the current value of the timer1. this value shall not be read out during reception. table 90. t1countervallo register (address 18h) bit 7 6 5 4 3 2 1 0 symbol t1countervallo access rights dy table 91. t1countervallo bits bit symbol description 7 to 0 t1counter vallo low byte of the current value of the counter 1. this value shall not be read out during reception. table 92. t2control register (address 19h) bit 7 6 5 4 3 2 1 0 symbol t2stoprx - t2start t2autorestart - t2clk access rights r/w rfu r/w r/w rfu r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 73 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.11 t2reloadhi high byte of the reload value of timer2. 9.7.2.12 t2reloadlo low byte of the reload value of timer2. table 93. t2control bits bit symbol description 7 t2stoprx if set the timer stops immediately after receiving the first 4 bits. if cleared indicates, that the timer is not stopped automatically. note: if lfo trimming is selected by t2start, this bit has no effect. 6- rfu 5 to 4 t2start 00b: the timer is not started automatically. 01b: the timer starts automatically at the end of the transmission. 10b: timer is used for lfo trimming without underflow (start/stop on posedge). 11b: timer is used for lfo trimming with underflow (start/stop on posedge). 3 t2autorestart set to logic 1, the timer automatically restarts its countdown from t2reloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer2irq is set to logic 1 when the timer underflows 2- rfu 1 to 0 t2clk 00b: the timer input clock is 13.56 mhz. 01b: the timer input clock is 212 khz. 10b: the timer input clock is an underflow of timer0 11b: the timer input clock is an underflow of timer1 table 94. t2reloadhi register (address 1ah) bit 7 6 5 4 3 2 1 0 symbol t2reloadhi access rights r/w table 95. t2reload bits bit symbol description 7 to 0 t2reloadhi defines the high byte of the reload value of the timer2. with the start event the timer load the value of the t2reloadvalhi and t2reloadvallo. changing this register affects the timer only at the next start event. table 96. t2reloadlo register (address 1bh) bit 7 6 5 4 3 2 1 0 symbol t2reloadlo access rights r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 74 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.13 t2countervalhi high byte of the counter register of timer2. 9.7.2.14 t2countervalloreg low byte of the current value of timer 2. 9.7.2.15 t3control control register of the timer 3. table 97. t2reloadlo bits bit symbol description 7 to 0 t2reloadlo defines the low byte of the reload value of the timer2. with the start event the timer load the value of the t2reloadvalhi and t2relaodvalo. changing this register affects the timer only at the next start event. table 98. t2countervalhi register (address 1ch) bit 7 6 5 4 3 2 1 0 symbol t2countervalhi access rights dy table 99. t2countervalhi bits bit symbol description 7 to 0 t2counter valhi high byte current counter value of timer2. this value shall not be read out during reception. table 100. t2countervallo register (address 1dh) bit 7 6 5 4 3 2 1 0 symbol t2countervallo access rights dy table 101. t2countervallo bits bit symbol description 7to0 t2counter vallo low byte of the current counter value of timer1timer2. this value shall not be read out during reception. table 102. t3control register (address 1eh) bit 7 6 5 4 3 2 1 0 symbol t3stoprx - t3start t3autorestart - t3clk access rights r/w rfu r/w r/w rfu r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 75 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.16 t3reloadhi high byte of the reload value of timer3. 9.7.2.17 t3reloadlo low byte of the reload value of timer3. table 103. t3control bits bit symbol description 7 t3stoprx if set, the timer stops immediately after receiving the first 4 bits. if cleared, indicates that the timer is not stopped automatically. note: if lfo trimming is selected by t3start, this bit has no effect. 6- rfu 5 to 4 t3start 00b - timer is not started automatically 01b - timer starts automatically at the end of the transmission 10b - timer is used for lfo trimmi ng without underflow (start/stop on posedge) 11b - timer is used for lfo trimming with underflow (start/stop on posedge). 3 t3autorestart set to logic 1, the timer automatically restarts its countdown from t3reloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer1irq is set to logic 1 when the timer underflows. 2- rfu 1 to 0 t3clk 00b - the timer input clock is 13.56 mhz. 01b - the timer input clock is 211,875 khz. 10b - the timer input clock is an underflow of timer0 11b - the timer input clock is an underflow of timer1 table 104. t3reloadhi register (address 1fh); bit 7 6 5 4 3 2 1 0 symbol t3reloadhi access rights r/w table 105. t3reloadhi bits bit symbol description 7 to 0 t3reloadhi defines the high byte of the reload value of the timer3. with the start event the timer load the value of the t3reloadvalhi and t3reloadvallo. changing this register affects the timer only at the next start event. table 106. t3reloadlo register (address 20h) bit 7 6 5 4 3 2 1 0 symbol t3reloadlo access rights r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 76 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.18 t3countervalhi high byte of the current counter value the 16-bit timer3. 9.7.2.19 t3countervallo low byte of the current counter value the 16-bit timer3. 9.7.2.20 t4control the wake-up timer t4 activates the system after a given time. if enabled, it can start the low power card detection function. table 107. t3reloadlo bits bit symbol description 7 to 0 t3reloadlo defines the low byte of the reload value of timer3. with the start event the timer load the value of the t3reloadvalhi and t3relaodvallo. changing this register affects the timer only at the next start event. table 108. t3countervalhi register (address 21h) bit 7 6 5 4 3 2 1 0 symbol t3countervalhi access rights dy table 109. t3countervalhi bits bit symbol description 7 to 0 t3counter valhi high byte of the current counter value of timer3. this value shall not be read out during reception. table 110. t3countervallo register (address 22h) bit 7 6 5 4 3 2 1 0 symbol t3countervallo access rights dy table 111. t3countervallo bits bit symbol description 7 to 0 t3counter vallo low byte current counter value of timer3. this value shall not be read out during reception. table 112. t4control register (address 23h) bit 7 6 5 4 3 2 1 0 symbol t4running t4start stopnow t4auto trimm t4auto lpcd t4auto restart t4autowakeup t4clk access rights dy w r/w r/w r/w r/w r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 77 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.21 t4reloadhi high byte of the reload value of the 16-bit timer 4. 9.7.2.22 t4reloadlo low byte of the reload value of the 16-bit timer 4. table 113. t4control bits bit symbol description 7 t4running shows if the timer t4 is running. if the bit t4startstopnow is set, this bit and the timer t4 can be started/stopped. 6t4start stopnow if set, the bit t4running can be changed. 5 t4autotrimm if set to one, the timer ac tivates an lfo trimming procedure when it underflows. for the t4autotrimm function, at least one timer (t0 to t3) has to be configured properly fo r trimming (t3 is not allowed if t4autolpcd is set in parallel). 4 t4autolpcd if set to one, the timer activates a low-power card detection sequence. if a card is detected an interrupt request is raised and the system remains active if enabled. if no card is detected the slrc610 enters the power down mode if enabled. the timer is automatically restarted (no gap). timer 3 is used to specify the time where the rf field is enabled to check if a card is present. therefor you may not use timer 3 for t4autotrimm in parallel. 3 t4autorestart set to logic 1, the timer automatically restarts its countdown from t4reloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer4irq is set to logic 1 at timer underflow. 2 t4autowakeup if set, the slrc610 wakes up automatically, when the timer t4 has an underflow. this bit has to be set if the ic should enter the power down mode after t4autotrimm and/or t4autolpcd is finished and no card has been detected. if the ic should stay active after one of these procedures this bit has to be set to 0. 1 to 0 t4clk 00b - the timer input clock is the lfo clock 01b - the timer input clock is the lfo clock/8 10b - the timer input clock is the lfo clock/16 11b - the timer input clock is the lfo clock/32 table 114. t4reloadhi register (address 24h) bit 7 6 5 4 3 2 1 0 symbol t4reloadhi access rights r/w table 115. t4reloadhi bits bit symbol description 7 to 0 t4reloadhi defines high byte of the for the reload value of timer 4. with the start event the timer 4 loads the t4reloadval. changing this register affects the timer only at the next start event.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 78 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.7.2.23 t4countervalhi high byte of the counter value of the 16-bit timer 4. 9.7.2.24 t4countervallo low byte of the counter value of the 16-bit timer 4. 9.8 transmitter configuration registers 9.8.1 txmode table 116. t4reloadlo register (address 25h) bit 7 6 5 4 3 2 1 0 symbol t4reloadlo access rights r/w table 117. t4reloadlo bits bit symbol description 7 to 0 t4reloadlo defines the low byte of the reload value of the timer 4. with the start event the timer loads the value of the t4reloadval. changing this register affects the timer on ly at the next start event. table 118. t4countervalhi register (address 26h) bit 7 6 5 4 3 2 1 0 symbol t4countervalhi access rights dy table 119. t4countervalhi bits bit symbol description 7 to 0 t4countervalhi high byte of the current counter value of timer 4. table 120. t4countervallo register (address 27h) bit 7 6 5 4 3 2 1 0 symbol t4countervallo access rights dy table 121. t4countervallo bits bit symbol description 7 to 0 t4countervallo low byte of the current counter value of the timer 4. table 122. drvmode register (address 28h) bit 7 6 5 4 3 2 1 0 symbol tx2inv tx1inv - - txen txclk mode access rights r/w r/w rfu rfu r/w r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 79 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.8.2 txamp with the set_cw_amplitude register output power can be traded off against power supply rejection. spending more headroom leads to better power supply rejection ration and better accuracy of the modulation degree. with cwmax set, the voltage of tx1 will be pulled to the maxi mum possible. this register overrides the settings made by set_cw_amplitude. 9.8.3 txcon table 123. drvmode bits bit symbol description 7 tx2inv inverts transmitter 2 at tx2 pin 6 tx1inv inverts transmitter 1 at tx1 pin 5rfu 4- rfu 3 txen if set to 1 both transmitter pins are enabled 2 to 0 txclkmode transmitter clock setti ngs (see 8.6.2. table 27). codes 011b and 0b110 are not supported. this regi ster defines, if the output is operated in open drain, push-pull, at high impedance or pulled to a fix high or low level. table 124. txamp register (address 29h) bit 7 6 5 4 3 2 1 0 symbol set_cw_amplitude - set_residual_carrier access rights r/w rfu r/w table 125. txamp bits bit symbol description 7 to 6 set_cw_amplitude allows to reduce the ou tput amplitude of the transmitter by a fix value. four different preset values that are subtracted from tvdd can be selected: 0: tvdd -100 mv 1: tvdd -250 mv 2: tvdd -500 mv 3: t vdd -1000 mv 5rfu - 4 to 0 set_residual_ carrier set the residual carrier percentage. refer to section 8.6.2 table 126. txcon register (address 2ah) bit 7 6 5 4 3 2 1 0 symbol overshoott2 cwmax txinv txsel access rights r/w r/w r/w r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 80 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.8.4 txl 9.9 crc configuration registers 9.9.1 txcrcpreset table 127. txcon bits bit symbol description 7 to 4 overshoott2 specifies the length (number of carrier clocks) of the additional modulation for overshoot prevention. refer to section 8.6.2.1 ? overshoot protection ? 3 cwmax set amplitude of continuous wave carrier to the maximum. if set, set_cw_amplitude in regist er txamp has no influence on the continuous amplitude. 2 txinv if set, the resulting modulation signal defined by txsel is inverted 1 to 0 txsel defines which signal is used as source for modulation 00b ... no modulation 01b ... txenvelope 10b ... sigin 11b ... rfu table 128. txl register (address 2bh) bit 7 6 5 4 3 2 1 0 symbol overshoott1 tx_set_iload access rights r/w r/w table 129. txl bits bit symbol description 7 to 4 overshoott1 overshoot value for timer1. refer to section 8.6.2.1 ? overshoot protection ? 3 to 0 tx_set_iload factory trim value, sets the expected tx load current. this value is used to control the modulation index in an optimized way dependent on the expected tx load current. table 130. txcrcpreset register (address 2ch) bit 7 6 5 4 3 2 1 0 symbol rfu txpresetval tx crctype txcrcinvert txcrcen access rights - r/w r/w r/w r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 81 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution remark: user defined crc preset values can be configured by eeprom (see section 8.7.2.1 , table 29 ? configuration area (page 0) ? ). 9.9.2 rxcrccon table 131. txcrcpreset bits bit symbol description 7rfu - 6 to 4 txpresetval specifies the crc preset value for transmission (see table 132 ). 3 to 2 txcrctype defines which type of crc (crc8/crc16/crc5) is calculated: ? 00h -- crc5 ? 01h -- crc8 ? 02h -- crc16 ? 03h -- rfu 1 txcrcinvert if set, the resulting crc is in verted and attached to the data frame (iso/iec 3309) 0 txcrcen if set, a crc is appended to the data stream table 132. transmitter crc preset value configuration txpresetval[6...4] crc16 crc8 crc5 0h 0000h 00h 00h 1h 6363h 12h 12h 2h a671h bfh - 3h fffeh fdh - 4h--- 5h--- 6h user defined user defined user defined 7h ffffh ffh 1fh table 133. rxcrccon register (address 2dh) bit 7 6 5 4 3 2 1 0 symbol rxforcecrcwrite rxpresetval rxcrctype rxcrcinvert rxcrcen access rights r/w r/w r/w r/w r/w table 134. rxcrccon bits bit symbol description 7 rxforcecrc write if set, the received crc byte(s) are copied to the fifo. if cleared crc bytes are only checked, but not copied to the fifo. this bit has to be always set in case of a not byte aligned crc (e.g. iso/iec 18000-3 mode 3/ epc class-1hf) 6 to 4 rxpresetval defines the crc preset value (hex.) for transmission. (see table 135 ).
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 82 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.10 transmitter configuration registers 9.10.1 txdatanum 3 to 2 rxcrctype defines which type of crc (crc8/crc16/crc5) is calculated: ? 00h -- crc5 ? 01h -- crc8 ? 02h -- crc16 ? 03h -- rfu 1 rxcrcinvert if set, the crc check is done for the inverted crc. 0 rxcrcen if set, the crc is checked and in case of a wrong crc an error flag is set. otherwise the crc is calculated but the error flag is not modified. table 135. receiver crc pres et value configuration rxpresetval[6...4] crc16 crc8 crc5 0h 0000h 00h 00h 1h 6363h 12h 12h 2h a671h bfh - 3h fffeh fdh - 4h--- 5h--- 6h user defined user defined user defined 7h ffffh ffh 1fh table 134. rxcrccon bits bit symbol description table 136. txdatanum register (address 2eh) bit 7 6 5 4 3 2 1 0 symbol rfu rfu- rfu- keepbitgrid dataen txlastbits access rights r/w r/w r/w table 137. txdatanum bits bit symbol description 7to5 rfu - 4 keepbitgrid if set, the time between consecutive transmissions starts is a multiple of one etu. if cleared, consecut ive transmissions can even start within one etu 3 dataen if cleared - it is possible to send a single symbol pattern. if set - data is sent. 2 to 0 txlastbits defines how many bits of the la st data byte to be sent. if set to 000b all bits of the last data byte are sent. note - bits are skipped at the end of the byte. example - data byte b2h (sent lsb first). txlastbits = 011b (3h) => 010b (lsb first) is sent txlastbits = 110b (6h) => 010011b (lsb first) is sent
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 83 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.10.2 txsym10burstlen if a protocol requires a burst (an unmodulated subcarrier) the length can be defined with this txsymburstlen, the value high or low can be defined by txsym10burstctrl. 9.10.3 txwaitctrl table 138. txsym10burstlen register (address 30h) bit 7 6 5 4 3 2 1 0 symbol rfu sym1burst len rfu rfu access rights -r/w -- table 139. txsym10burstlen bits bit symbol description 7rfu - 6 to 4 sym1burstlen specifies the number of bi ts issued for symbol 1 burst. the 3 bits encodes a range from 8 to 256 bit: 00h - 8bit 01h - 16bit 02h - 32bit 04h - 48bit 05h - 64bit 06h - 96bit 07h - 128bit 08h - 256bit 3 to 0 rfu - table 140. txwaitctrl register (address 31h); reset value: c0h bit 7 6 5 4 3 2 1 0 symbol txwaitstart txwaitetu txwait high rfu access rights r/w r/w r/w - table 141. txwaitctrl bits bit symbol description 7 txwaitstart if cleared, the txwait time is starting at the end of the send data (tx). if set, the txwait time is starting at the end of the received data (rx).
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 84 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 6 txwaitetu if cleared, the txwait time is txwait ? 16/13.56 mhz. if set, the txwait time is txwait ? 0.5 / dbfreq (dbfreq is the frequency of the bit stream as defined by txdatacon). 5 to 3 txwait high bit extension of txwaitlo. txwaitctrl bit 5 is msb. 2 to 0 txstopbitlength defines stop-bits and egt (= stop-bit + extra guard time egt) to be send: 0h: no stop-bit, no egt 1h: 1 stop-bit, no egt 2h: 1 stop-bit + 1 egt 3h: 1 stop-bit + 2 egt 4h: 1 stop-bit + 3 egt 5h: 1 stop-bit + 4 egt 6h: 1 stop-bit + 5 egt 7h: 1 stop-bit + 6 egt note: this is only valid for iso/iec14443 type b table 141. txwaitctrl bits bit symbol description
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 85 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.10.4 txwaitlo 9.11 framecon table 142. txwaitlo register (address 32h) bit 7 6 5 4 3 2 1 0 symbol txwaitlo access rights r/w table 143. txwaitlo bits bit symbol description 7 to 0 txwaitlo defines the minimum time between receive and send or between two send data streams note: txwait is a 11bit register (additional 3 bits are in the txwaitctrl register)! see also txwaitetu and txwaitstart. table 144. framecon register (address 33h) bit 7 6 5 4 3 2 1 0 symbol txparityen rxparityen - - stopsym startsym access rights r/w r/w rfu rfu r/w r/w table 145. framecon bits bit symbol description 7 txparityen if set, a parity bit is calculated and appended to each byte transmitted. 6 rxparityen if set, the parity calculation is enabled. the parity is not transferred to the fifo. 5 to 4 - rfu 3 to 2 stopsym defines which sy mbol is sent as stop-symbol: ? 0h: no symbol is sent ? 1h: symbol0 is sent ? 2h symbol1 is sent ? 3h symbol2 is sent 1 to 0 startsym defines which symbol is sent as start-symbol: ? 0h: no symbol is sent ? 1h: symbol0 is sent ? 2h: symbol1 is sent ? 3h: symbol2 is sent
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 86 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.12 receiver configuration registers 9.12.1 rxsofd 9.12.2 rxctrl table 146. rxsofd register (address 34h) bit 7 6 5 4 3 2 1 0 symbol rfu sof_en sofdetected rfu subc_en subc_detected subc_present access rights - r/w dy - r/w dy r table 147. rxsofd bits bit symbol description 7 to 6 rfu - 5 sof_en if set and a sof is detec ted an rxsofirq is raised. 4 sof_detected shows that a sof is or was detected. can be cleared by sw. 3rfu - 2 subc_en if set and a subcarrier is detected an rxsofirq is raised. 1 subc_detected shows that a subcarrier is or was detected. can be cleared by sw. 0 subc_present shows that a subcarrier is currently detected. table 148. rxctrl register (address 35h) bit 7 6 5 4 3 2 1 0 symbol rxallowbits rxmultiple rfu rfu emd_sup baudrate access rights r/w r/w - - r/w r/w table 149. rxctrl bits bit symbol description 7 rxallowbits if set, data is written into fifo even if crc is enabled, and no complete byte has been received. 6 rxmultiple if set, rxmultiple is activated and the receiver will not terminate automatically (refer section 8.10.3.4 ? receive command ? ). if set to logic 1, at the end of a received data stream an error byte is added to the fifo. the error byte is a copy of the error register. 5 to 4 rfu - 3 emd_sup enables the emd suppression a ccording iso/iec14443. if an error occurs within the first three bytes, these three bytes are assumed to be emd, ignored and the fifo is reset. a collision is treated as an error as well if a valid sof was received, the emd_sup is set and a frame of less than 3 bytes had been receiv ed. rx_irq is not set in this emd error cases. if rxforcecrcwrite is set, the fifo should not be read out before three bytes are written into. 2 to 0 baudrate defines the baud rate of the receiving signal. 2h: 26 kbd 3h: 52 kbd all remaining values are rfu
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 87 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.12.3 rxwait selects internal re ceiver settings. 9.12.4 rxthreshold selects minimum threshold level for the bit decoder. 9.12.5 rcv table 150. rxwait register (address 36h) bit 7 6 5 4 3 2 1 0 symbol rxwaitetu rxwait access rights r/w r/w table 151. rxwait bits bit symbol description 7 rxwaitetu if set to 0, the rxwait time is rxwait ? 16/13.56 mhz. if set to 1, the rxwait time is rxwait ? (0.5/dbfreq). 6 to 0 rxwait defines the time after sending, where every input is ignored. table 152. rxthreshold register (address 37h) bit 7 6 5 4 3 2 1 0 symbol minlevel minlevelp access rights r/w r/w table 153. rxthreshold bits bit symbol description 7 to 4 minlevel defines the minlevel of the reception. note: the minlevel should be higher than the noise level in the system. 3 to 0 minlevelp defines the minlevel of the phase shift detector unit. table 154. rcv register (address 38h) bit 7 6 5 4 3 2 1 0 symbol rcv_rx_single rx_adcmode siginsel rfu colllevel access rights r/w r/w r/w - r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 88 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.12.6 rxana this register allows to set the gain (r cv_gain) and high pass corner frequencies (rcv_hpcf). table 155. rcv bits bit symbol description 7 rcv_rx_single single rxp input pin mode; 0: fully differential 1: quasi-differential 6 rx_adcmode defines the operation mode of the analog digital converter (adc) 0: normal reception mode for adc 1: lpcd mode for adc 5 to 4 siginsel defines input for the signal processing unit: 0h - idle 1h - internal analog block (rx) 2h - signal in over envelope (iso/iec14443a) 3h - signal in over s3c-generic 3 to 2 rfu - 1 to 0 colllevel defines the strength of a signal to be interpreted as a collision: 0h - collision has at least 1/8 of signal strength 1h - collision has at least 1/4 of signal strength 2h - collision has at least 1/2 of signal strength 3h - collision detection is switched off table 156. rxana register (address 39h) bit 7 6 5 4 3 2 1 0 symbol vmid_r_sel rfu rcv_hpcf rcv_gain access rights r/w - r/w r/w table 157. rxana bits bit symbol description 7, 6 vmid_r_sel factory trim value, needs to be 0. 5, 4 rfu 3, 2 rcv_hpcf the rcv_hpcf [1:0] signals allow 4 different settings of the base band amplifier lower cut-off frequen cy from ~40 khz to ~300 khz. 1 to 0 rcv_gain with rcv_gain[1:0] four differ ent gain settings from 30 db and 60 db can be configured (differential output voltage/differential input voltage).
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 89 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.13 clock configuration 9.13.1 serialspeed this register allows to set speed of the rs 232 interface. the default speed is set to 9,6kbit/s. the transmission speed of the interface can be changed by modifying the entries for br_t0 and br_t1. the transfer speed can be calculated by using the following formulas: br_t0 = 0: transfer speed = 27.12 mhz / (br_t1 + 1) br_t0 > 0: transfer speed = 27.12 mhz / (br_t1 + 33) / 2^(br_t0 ? 1) the framing is implemented with 1 startbit, 8 databits and 1 stop bit. a parity bit is not used. transfer speeds above 1228,8 kbit/s are not supported. table 158. effect of gain and highpass corner register settings rcv_gain (hex.) rcv_hpcf (hex.) fl (khz) fu (mhz) gain (db20) bandwith (mhz) 03 00 38 2,3 60 2,3 03 01 79 2,4 59 2,3 03 02 150 2,6 58 2,5 03 03 264 2,9 55 2,6 02 00 41 2,3 51 2,3 02 01 83 2,4 50 2,3 02 02 157 2,6 49 2,4 02 03 272 3,0 41 2,7 01 00 42 2,6 43 2,6 01 01 84 2,7 42 2,6 01 02 157 2,9 41 2,7 01 03 273 3,3 39 3,0 00 00 43 2,6 35 2,6 00 01 85 2,7 34 2,6 00 02 159 2,9 33 2,7 00 03 276 3,4 30 3,1 table 159. serialspeed register (address3bh); reset value: 7ah bit 7 6 5 4 3 2 1 0 symbol br_t0 br_t1 access rights r/w r/w table 160. serialspeed bits bit symbol description 7 to 5 br_t0 br_t0 = 0: transfer speed = 27.12 mhz / (br_t1 + 1) br_t0 > 0: transfer speed = 27. 12 mhz / (br_t1 + 33) / 2^(br_t0 ? 1) 4 to 0 br_t1 br_t0 = 0: transfer speed = 27.12 mhz / (br_t1 + 1) br_t0 > 0: transfer speed = 27. 12 mhz / (br_t1 + 33) / 2^(br_t0 ? 1)
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 90 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.13.2 lfo_trimm 9.13.3 pll_ctrl register the pll_ctrl register implements the control register for the integern pll. two stages exist to create the clkout signal from the 27, 12mhz input. in the firs t stage the 27,12mhz input signal is multiplied by the value define d in plldiv_fb and divided by two, and the second stage divides this frequency by the value defined by plldiv_out. table 161. rs232 speed settings transfer speed (kbit/s) serialspeed register content (hex.) 7,2 fa 9,6 eb 14,4 da 19,2 cb 38,4 ab 57,6 9a 115,2 7a 128,0 74 230,4 5a 460,8 3a 921,6 1c 1228,8 15 table 162. lfo_trim register (address 3ch) bit 7 6 5 4 3 2 1 0 symbol lfo_trimm access rights r/w table 163. lfo_trim bits bit symbol description 7 to 0 lfo_trimm trimm value. refer to section 8.8.3 ? low frequency oscillator (lfo) ? note: if the trimm value is increased , the frequency of the oscillator decreases. table 164. pll_ctrl register (address3dh) bit 7 6 5 4 3 2 1 0 symbol clkoutsel clkout_en pll_pd plldiv_fb access rights r/w r/w r/w r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 91 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.13.4 plldiv_out table 165. pll_ctrl register bits bit symbol description 7 to 4 clkoutsel ? 0h - pin clkout is used as i/o ? 1h - pin clkout shows the output of the analog pll ? 2h - pin clkout is hold on 0 ? 3h - pin clkout is hold on 1 ? 4h - pin clkout shows 27.12 mhz from the crystal ? 5h - pin clkout shows 13.56 mhz derived from the crystal ? 6h - pin clkout shows 6.78 mhz derived from the crystal ? 7h - pin clkout shows 3.39 mhz derived from the crystal ? 8h - pin clkout is toggled by the timer0 overflow ? 9h - pin clkout is toggled by the timer1 overflow ? ah - pin clkout is toggled by the timer2 overflow ? bh - pin clkout is toggled by the timer3 overflow ? ch...fh - rfu 3 clkout_en enables the clock at pin clkout 2 pll_pd pll power down 1-0 plldiv_fb pll feedback divider (see table 174) table 166. setting of feedback divider plldiv_fb [1:0] bit 1 bit 0 division 0 0 23 (vco frequency 312mhz) 0 1 27 (vco frequency 366mhz) 1 0 28 (vco frequency 380mhz) 1 1 23 (vco frequency 312mhz) table 167. plldiv_out re gister (address 3eh) bit 7 6 5 4 3 2 1 0 symbol plldiv_out access rights r/w table 168. plldiv_out bits bit symbol description 7 to 0 plldiv_out pll output divider factor; refer to section 8.8.2 table 169. setting for the output divider ratio plldiv_out [7:0] value division 0rfu 1rfu 2rfu 3rfu 4rfu
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 92 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.14 low-power card detecti on configuration registers the lpcd registers contain the settings for the low-power card detection. the setting for lpcd_imax (6 bits) is done by the two hig hest bits (bit 7, bit 6) of the registers lpcd_qmin, lpcd_qmax and lpcd_imin each. 9.14.1 lpcd_qmin 9.14.2 lpcd_qmax 5r f u 6r f u 7r f u 88 99 10 10 ... ... 253 253 254 254 table 169. setting for the output divider ratio plldiv_out [7:0] value division table 170. lpcd_qmin register (address 3fh) bit 7 6 5 4 3 2 1 0 symbol lpcd_imax.5 lpcd_imax.4 lpcd_qmin access rights r/w r/w r/w table 171. lpcd_qmin bits bit symbol description 7, 6 lpcd_imax defines the highest two bits of the higher border for the lpcd. if the measurement value of the i channe l is higher than lpcd_imax, a lpcd interrupt request is indicated by bit irq0.lpcdirq. 5 to 0 lpcd_qmin defines the lower border for the lpcd. if the measurement value of the q channel is higher than lpcd_qmin, a lpcdinterrupt request is indicated by bit irq0.lpcdirq. table 172. lpcd_qmax register (address 40h) bit 7 6 5 4 3 2 1 0 symbol lpcd_imax.3 lpcd_imax.2 lpcd_qmax access rights r/w r/w r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 93 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.14.3 lpcd_imin 9.14.4 lpcd_result_i 9.14.5 lpcd_result_q table 173. lpcd_qmax bits bit symbol description 7 lpcd_imax.3 defines the bit 3 of the high border for the lpcd. if the measurement value of the i channel is higher than lpcd imax, a lpcd irq is raised. 6 lpcd_imax.2 defines the bit 2 of the high border for the lpcd. if the measurement value of the i channel is higher than lpcd imax, a lpcd irq is raised. 5 to 0 lpcd_qmax defines the high border fo r the lpcd. if the measurement value of the q channel is higher than lpcd qmax, a lpcd irq is raised. table 174. lpcd_imin register (address 41h) bit 7 6 5 4 3 2 1 0 symbol lpcd_imax.1 lpcd_imax.0 lpcd_imin access rights r/w r/w r/w table 175. lpcd_imin bits bit symbol description 7 to 6 lpcd_imax defines lowest two bits of the higher border for the low-power card detection (lpcd). if the measurement value of the i channel is higher than lpcd imax, a lpcd irq is raised. 5 to 0 lpcd_imin defines the lower border for the ow power card detection. if the measurement value of the i channel is lower than lpcd imin, a lpcd irq is raised. table 176. lpcd_result_i register (address 42h) bit 7 6 5 4 3 2 1 0 symbol rfu- rfu- lpcd_result_i access rights -- r table 177. lpcd_i_result bits bit symbol description 7 to 6 rfu - 5 to 0 lpcd_result_i shows the result of t he last low-power card detection (i-channel). table 178. lpcd_result_q register (address 43h) bit 7 6 5 4 3 2 1 0 symbol rfu lpcd_irq_clr lpcd_reslult_q access rights r/w r
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 94 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.15 pin configuration 9.15.1 pinen 9.15.2 pinout table 179. lpcd_q_result bits bit symbol description 7rfu - 6 lpcd_irq_clr if set no lpcd irq is raised any more until the next low-power card detection procedure. can be used by software to clear the interrupt source. 5 to 0 lpcd_result_q shows the result of th e last ow power card detection (q-channel). table 180. pinen register (address 44h) bit 7 6 5 4 3 2 1 0 symbol sigin_en clkout_e n ifsel1_en ifsel0_en tck_ en tms_en tdi_en tmdo_en access rights r/w r/w r/w r/w r/w r/w r/w r/w table 181. pinen bits bit symbol description 7 sigin_en enables the output functionality on sigin (pin 5). the pin is then used as i/o. 6 clkout_en enables the output functionalit y of the clkout (pin 22). the pin is then used as i/o. the clkout function is switched off. 5 ifsel1_en enables the output functionality of the ifsel1 (pin 27). the pin is then used as i/o. 4 ifsel0_en enables the output functionality of the ifsel0 (pin 26). the pin is then used as i/o. 3 tck_en enables the output functionality of the tck (pin 4) of the boundary scan interface. the pin is then used as i/o. if the boundary scan is activated in eeprom, this bit has no function. 2 tms_en enables the output functionality of the tms (pin 2) of the boundary scan interface. the pin is then used as i/o. if the boundary scan is activated in eeprom, this bit has no function. 1 tdi_en enables the output functionality of the tdi (pin 1) of the boundary scan interface. the pin is then used as i/o. if the boundary scan is activated in eeprom, this bit has no function. 0 tdo_en enables the output functionalit y of the tdo(pin 3) of the boundary scan interface. the pin is then used as i/o. if the boundary scan is activated in eeprom, this bit has no function. table 182. pinout register (address 45h) bit 7 6 5 4 3 2 1 0 symbol sigin_out clkout_out ifsel1_out ifsel0_out tck_ou t tms_ou t tdi_out tdo_out access rights r/w r/w r/w r/w r/w r/w r/w r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 95 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.15.3 pinin 9.15.4 sigout table 183. pinout bits bit symbol description 7 sigin_out output buffer of the sigin pin 6 clkout_out output buffer of the clkout pin 5 ifsel1_out output buffer of the ifsel1 pin 4 ifsel0_out output buffer of the ifsel0 pin 3 tck_out output buffer of the tck pin 2 tms_out output buffer of the tms pin 1 tdi_out output buffer of the tdi pin 0 tdo_out output buffer of the tdo pin table 184. pinin register (address 46h) bit 7 6 5 4 3 2 1 0 symbol sigin_in clkout_in ifsel1_in if sel0_in tck_in tms_in tdi_in tdo_in access rights rrrrrrrr table 185. pinin bits bit symbol description 7 sigin_in input buffer of the sigin pin 6 clkout_in input buffer of the clkout pin 5 ifsel1_in input buffer of the ifsel1 pin 4 ifsel0_in input buffer of the ifsel0 pin 3 tck_in input buffer of the tck pin 2 tms_in input buffer of the tms pin 1 tdi_in input buffer of the tdi pin 0 tdo_in input buffer of the tdo pin table 186. sigout register (address 47h) bit 7 6 5 4 3 2 1 0 symbol pad speed rfu sigoutsel access rights r/w - r/w
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 96 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 9.16 version register 9.16.1 version table 187. sigout bits bit symbol description 7 padspeed if set, the i/o pins are supporting a fast switching mode.the fast mode for the i/o?s will increase the peak current consumption of the device, especially if multiple i/os are switching at the same time. the power supply needs to be designed to deliver this peak currents. 6 to 4 rfu - 3 to 0 sigoutsel 0h, 1h - the pin sigout is 3-state 2h - the pin sigout is 0 3h - the pin sigout is 1 4h - the pin sigout shows the tx-envelope 5h - the pin sigout shows the tx-active signal 6h - the pin sigout shows the s3c (generic) signal 7h - the pin sigout shows the rx-envelope (only valid for iso/iec 14443a, 106 kbd) 8h - the pin sigout shows the rx-active signal 9h - the pin sigout shows the rx-bit signal table 188. version register (address 7fh) bit 7 6 5 4 3 2 1 0 symbol version subversion access rights rr table 189. version bits bit symbol description 7 to 4 version includes the version of the slrc610 silicon. 3 to 0 subversion includes the subversion of the slrc610 silicon.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 97 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 10. limiting values 11. recommended operating conditions [1] v dd(pvdd) must always be the same or lower than v dd . 12. thermal characteristics 13. characteristics table 190. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +5.5 v v dd(pvdd) pvdd supply voltage ? 0.5 +5.5 v v dd(tvdd) tvdd supply voltage ? 0.5 +5.5 v v i(rxp) input voltage on pin rxp -0.5 +2.0 v v i(rxn) input voltage on pin rxn ? 0.5 +2.0 v p tot total power dissipation per package - 1125 mw v esd (hbm) electrostatic discharge voltage human body model (hbm); 1500 ? , 100 pf; jesd22-a114-b - 2000 v v esd( cdm ) electrostatic discharge voltage charge device model (cdm); - 500 v t j(max) maximum junction temperature - 150 c table 191. operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3 5 5.5 v v dd(tvdd) tvdd supply voltage [1] 355.5v v dd(pvdd) pvdd supply voltage 3 5 5.5 v t amb ambient temperature ? 25 - +85 ?c table 192. thermal characteristics symbol parameter conditions package typ unit r th(j-a) thermal resistance from junction to ambient in still air with exposed pin soldered on a 4 layer jedec pcb hvqfn32 40 k/w table 193. characteristics symbol parameter conditions min typ max unit input characteristics i/o pin characteristics if3-sda in i 2 c configuration i li input leakage current output disabled - 2 100 na v il low-level input voltage ? 0.5 - +0.3v dd(pvdd) v v ih high-level input voltage 0.7v dd(pvdd) -v dd(pvdd) + 0.5 v v ol low-level output voltage i ol = 3 ma - - 0.3 v
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 98 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution i ol low-level output current v ol = 0.4 v; standard mode, fast mode 4-- ma v ol = 0.6 v; standard mode, fast mode 6-- ma t f(o) output fall time standard mode, fast mode, c l < 400 pf --250ns fast mode +; c l < 550 pf - - 120 ns t sp pulse width of spikes that must be suppressed by the input filter 0-50 ns c i input capacitance - 3.5 5 pf c l load capacitance standard mode - - 400 pf fast mode - - 550 pf t eer eeprom data retention time t amb = +55 c1 0- -y e a r n eec eeprom endurance (number of programming cycles) under all operating conditions 5 x 10 5 - - cycle analog and digital supply avdd,dvdd v dda analog supply voltage - 1.8 - v v ddd digital supply voltage - 1.8 - v c l load capacitance avdd 220 470 - nf c l load capacitance dvdd 220 470 - nf current consumption i stb standby current standby bit = 1 - 3 6 ? a i dd supply current modem on - 17 20 ma modem off - 0.45 0.5 ma i dd(tvdd) tvdd supply current - 100 200 ma i/o pin characteristics sigin, sigout, clkout, ifsel0, ifsel1, tck, tms, tdi, tdo, irq, if0, if1, if2, scl2, sda2 i li input leakage current output disabled - 50 500 na v il low-level input voltage ? 0.5 - 0.3v dd(pvdd) v v ih high-level input voltage 0.7v dd(pvdd) -v dd(pvdd) + 0.5 v v ol low-level output voltage i ol = 4 ma, v dd(pvdd) =5.0v --0.4v i ol = 4 ma, v dd(pvdd) =3.3v --0.4v v oh high-level output voltage i ol = 4 ma, v dd(pvdd) =5.0v 4.6 - - v i ol = 4 ma, v dd(pvdd) =3.3v 2.9 - - v c i input capacitance - 2.5 4.5 pf pull-up resistance for tck, tms, tdi, if2 r pu pull-up resistance 50 72 120 k ? table 193. characteristics ?continued symbol parameter conditions min typ max unit
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 99 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution [1] i pd is the total current for all supplies. [2] i dd(pvdd) depends on the overall load at the digital pins. [3] i dd(tvdd) depends on v dd(tvdd) and the external circuit c onnected to pins tx1 and tx2. [4] during typical circuit operation, the overall current is below 100 ma. [5] typical value using a complementary driv er configuration and an antenna matched to 40 ? between pins tx1 and tx2 at 13.56 mhz. pin characteristics aux 1, aux 2 v o output voltage 0 - 1.8 v c l load capacitance - - 400 pf pin characteristics rxp, rxn v i input voltage 0 - 1.8 v c i input capacitance 2 3.5 5 pf v mod(pp) modulation voltage v mod(pp) =v i(pp)(max) ? v i(pp) (min) -2 . 5- m v v pp signal on rxp, rxn - - 1.65 v pins tx1 and tx2 v o output voltage v ss(tvss) -v dd(tvdd) v r o output resistance - 1.5 - ? current consumption i pd power-down current ambient temp = 25c - 8 40 na ambient temp = 85c - 200 400 na i stby standby current ambient temp = 25c [1] -36 ? a i lpcd lpcd sleep current [1] -36 ? a i dd supply current - 17 20 ma modem off; transceiver off - 0.45 0.5 ma i dd(pvdd) pvdd supply current no load on digital pin [2] --1 0 ? a i dd(tvdd) tvdd supply current [3] [4] [5] - 100 200 ma clock frequency pin clkout f clk clock frequency configured to 27.12 mhz - 27.12 - mhz ? clk clock duty cycle - 50 - % crystal oscillator v o(p-p) peak-to-peak output voltage pin xtal1 - 1 - v v i input voltage pin xtal1 0 - 1.8 v c i input capacitance pin xtal1 - 3 - pf typical input requirements f xtal crystal frequency - 27.12 - mhz esr equivalent series resistance -5 01 0 0 ? c l load capacitance - 10 - pf p xtal crystal power dissipation - 50 100 ? w table 193. characteristics ?continued symbol parameter conditions min typ max unit
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 100 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 13.1 timing characteristics remark: to send more bytes in one data stream the nss signal must be low during the send process. to send more than one data stream the nss signal must be high between each data stream. fig 28. pin rx input voltage 001aak012 vmid 0 v v mod v i(p-p)(max) v i(p-p)(min) 13.56 mhz carrier table 194. spi timing characteristics symbol parameter conditions min typ max unit t sckl sck low time 50 - - ns t sckh sck high time 50 - - ns t h(sckh-d) sck high to data input hold time sck to changing mosi 25 - - ns t su(d-sckh) data input to sck high set-up time changing mosi to sck 25 - - ns t h(sckl-q) sck low to data output hold time sck to changing miso - - 25 ns t (sckl-nssh) sck low to nss high time 0--ns t nssh nss high time before communication 50 - - ns table 195. i 2 c-bus timing in fast mode and fast mode plus symbol parameter conditions fast mode fast mode plus unit min max min max f scl scl clock frequency 0 400 0 1000 khz t hd;sta hold time (repeated) start condition after this period, the first clock pulse is generated 600 - 260 - ns t su;sta set-up time for a repeated start condition 600 - 260 - ns t su;sto set-up time for stop condition 600 - 260 - ns t low low period of the scl clock 1300 - 500 - ns t high high period of the scl clock 600 - 260 - ns t hd;dat data hold time 0 900 - 450 ns
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 101 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution t su;dat data set-up time 100 - - - ns t r rise time scl signal 20 300 - 120 ns t f fall time scl signal 20 300 - 120 ns t r rise time sda and scl signals 20 300 - 120 ns t f fall time sda and scl signals 20 300 - 120 ns t buf bus free time between a stop and start condition 1.3 - 0.5 - ? s fig 29. timing for fast and standard mode devices on the i 2 c-bus table 195. i 2 c-bus timing in fast mode and fast mode plus ?continued symbol parameter conditions fast mode fast mode plus unit min max min max 001aaj635 sda t f scl t low t f t sp t r t hd;sta t hd;dat t hd;sta t r t high t su;dat ss r p s t su;sta t su;sto t buf
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 102 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 14. application information a typical application diagram using a comple mentary antenna connection to the slrc610 is shown in figure 30 . the antenna tuning and rf part matching is described in the application note ref. 1 and ref. 2 . 14.1 antenna design description the matching circuit for the antenna consists of an emc low pass filter (l0 and c0), a matching circuitry (c1 and c2), and a receiving circuits (r1 = r3, r2 = r4, c3 = c5 and c4 = c6;), and the antenna itself. the receiving circuit component values needs to be designed for operation with the slrc610. a reus e of dedicated antenna designs done for other products without adap tation of component values will result in degraded performance. for a more detailed information about designing and tuning the antenna, please refer to the relevant application notes: ? micore reader ic family; directly matched antenna design, ref. 1 and ? mifare (14443a) 13.56 mhz rfid proximity antennas, ref. 2 . 14.1.1 emc low pass filter the mifare system operates at a frequency of 13.56 mhz. this frequency is derived from a quartz oscillato r to clock the slrc610 and is also the basis for driving the antenna with the 13.56 mhz energy carrier. this will not only cause emitted power at 13.56 mhz fig 30. typical applicatio n antenna circuit diagram 001aam269 vdd pvdd micro- processor host interface tvdd xtal1 xtal2 rxn vmid tx1 tvss tx2 9 82518 19 vss 33 20 13 14 17 16 15 14 21 28-31 32 pdown irq 7 dvdd avdd 12 rxp reader ic r1 l0 c1 ra ra c1 l0 r2 r4 c0 c0 c2 c2 c rxn c rxp c vmid r3 27.12 mhz antenna lant
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 103 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution but will also emit power at higher harmonics. the international emc regulations define the amplitude of the emitted power in a broad fre quency range. thus, an appropriate filtering of the output signal is necessa ry to fulfil these regulations. remark: the pcb layout has a major influence on the overall performance of the filter. 14.1.2 antenna matching due to the impedance transformation of the given low pass filter, the antenna coil has to be matched to a certain impedance. the matching elements c1 and c2 can be estimated and have to be fine tuned dependi ng on the design of the antenna coil. the correct impedance matching is important to provide the optimum performance. the overall quality factor has to be considered to guarantee a proper iso/iec 14443 communication scheme. environmental influences have to be considered as well as common emc design rules. for details refer to the nxp application notes. 14.1.3 receiving circuit the internal receiving concept of the slrc610 makes use both side-bands of the sub-carrier load modulation of the card response via a differential receiving concept (rxp, rxn). no external filtering is required. it is recommended to use the internally generated vmid potential as the input potential of pin rx. this dc voltage level of vmid has to be coupled to the rx-pins via r2 and r4. to provide a stable dc reference voltage capacitances c4, c6 has to be connected between vmid and ground. refer to figure 30 considering the (ac) voltage limits at the rx-pins the ac voltage divider of r1 + c3 and r2 as well as r3 + c5 and r4 has to be designed. depending on the antenna coil design and the impedance matching the voltage at the antenna coil varies from antenna design to antenna design. therefore the recommended way to design the receiving circuit is to use the given values for r1(= r3), r2 (= r4), and c3 (= c5) from the above mentioned application note, and adjust the voltage at the rx-pins by varying r1(= r3) within the given limits. remark: r2 and r4 are ac-wise connected to ground (via c4 and c6).
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 104 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 14.1.4 antenna coil the precise calculation of the antenna coils ? inductance is not practicable but the inductance can be estimated using the following formula. we recommend designing an antenna either with a circular or rectangular shape. (4) ? i 1 - length in cm of one turn of the conductor loop ? d 1 - diameter of the wire or width of the pcb conductor respectively ? k - antenna shape factor (k = 1,07 for circular antennas and k = 1,47 for square antennas) ? l 1 - inductance in nh ? n 1 - number of turns ? ln: natural logarithm function the actual values of the antenna inductance, resistance, and capacitance at 13.56 mhz depend on various parameters such as: ? antenna construction (type of pcb) ? thickness of conductor ? distance between the windings ? shielding layer ? metal or ferrite in the near environment therefore a measurement of those parameters under real life conditions, or at least a rough measurement and a tuning procedure is highly recommended to guarantee a reasonable performance. for details refer to the above mentioned application notes. l 1 2 = i 1 i 1 d 1 ------ ?? ln k ? ?? ?? n 1 18 ? ??
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 105 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 15. package outline fig 31. package outline sot617-1 (hvqfn32) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617-1 hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 106 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution detailed package information can be found at http://www.nxp.com/package/sot617-1.html. 16. handling information moisture sensitivity level (msl) evaluation has been performed according to snw-fq-225b rev.04/07/07 (jedec j-std-020c) . msl for this package is level 2 which means 260 ? c convection reflow temperature. for msl2: ? dry pack is required. ? 1 year out-of-pack floor life at maximum ambient temperature 30 ? c/ 85 % rh. for msl1: ? no dry pack is required. ? no out-of-pack floor live spec. required. 17. packing information fig 32. packing information 1 tray 001aaj740 strap 46 mm from corner tray chamfer pin 1 chamfer pin 1 printed plano box esd warning preprinted barcode label (permanent) barcode label (peel-off) qa seal hyatt patent preprinted the straps around the package of stacked trays inside the plano-box have sufficient pre-tension to avoid loosening of the trays. in the traystack (2 trays) only one tray type* allowed *one supplier and one revision number.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 107 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution fig 33. packing information 5 tray aaa-004952 pq-label (permanent) bag strap 46 mm from the corner dry-agent esd warning preprinted pq-label (permanent) dry-pack id preprinted strap qa seal relative humidity indicator tray preprinted: recycling symbol moisture caution label esd warning manufacturer bag info chamfer chamfer chamfer printed plano box pin 1 pin 1 pin 1 plcc52
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 108 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution fig 34. tray details bc bc ak ak 1.55 3.00 (0.30) 16.600.08+7/s sq. 1.20 0.56 3.32 (14.40+5/s sq.) (1.45) 1.10 2.50 (0.64) 0.35 an an aaa-004949 bb bd ba bd aj ar aj al al am am ar ba bb section bc-bc scale 4:1 vacuum cell section bd-bd scale 4:1 section ba-ba scale 4:1 detail ac scale 20:1 section aj-aj scale 2:1 section ar-ar scale 2:1 section al-al scale 5:1 section ak-ak scale 5:1 section am-am scale 4:1 section an-an scale 4:1 end lock side lock 12.80-5/s sq. 14.200.08+10/s sq. 13.850.08+12/s sq. ba c 0.50 ba c 0.50
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 109 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution fig 35. packing information reel aaa-004950 tape guard band circular sprocket holes opposite the label side of reel cover tape carrier tape enlongated circular enlongated pin1 has to be in quadrant 1 qa seal preprinted esd warning pq-label dry-pack id preprinted (permanent) product orientation in carrier tape product orientation only for turned products with 12nc ending 128 how to secure leader end to the guard band, how to secure guard band unreeling direction (see: how to secure) (see: how to secure) pin1 pin1 pin1 pin1 bga bare die bga bare die for sot505-2 ending 125 for sot765 ending 125 pin1 pin1 pin1 pin1 pin1 qfp qfp plcc so so 12 34 (hv)qfn (hv)son (h)bcc (hv)qfn (hv)son (h)bcc 12 34 see: assy reel + labels assy reel + labels label side embossed esd logo embossed esd logo tape printed plano-box ? 330x12/16/24/32 (hub 7) ? 330x16/24/32/44 (hub 4) ? 330x44 (hub 6) ? 180x12/16/24 tapeslot label side trailer leader leader : lenght of trailer shall be 400 mm min. and covered with cover tape circular sprocket hole side guard band trailer : lenght of trailer shall be 160 mm min. and covered with cover tape tape (with pull tabs on both ends) guard band lape double-backed onto itself on both ends
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 110 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 18. abbreviations table 196. abbreviations acronym description adc analog-to-digital converter bpsk binary phase shift keying crc cyclic redundancy check cw continuous wave egt extra guard time emc electro magnetic compatibility emd electro magnetic disturbance eof end of frame epc electronic product code etu elementary time unit gpio general purpose input/output hbm human body model i 2 c inter-integrated circuit lfo low frequency oscillator lpcd low-power card detection lsb least significant bit miso master in slave out mosi master out slave in msb most significant bit nrz not return to zero nss not slave select pcd proximity coupling device pll phase-locked loop rz return to zero rx receiver sam secure access module sof start of frame spi serial peripheral interface sw software ttimer timing of the clk period tx transmitter uart universal asynchronous receiver transmitter uid unique identification vco voltage controlled oscillator
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 111 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 19. references [1] application note ? mfrc52x reader ic family directly matched antenna design [2] application note ? mifare (iso/iec 14443 a) 13.56 mhz rfid proximity antennas [3] bsdl file ? boundary scan description language file of the slrc610
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 112 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 20. revision history table 197. revision history document id release date data sheet status change notice supersedes slrc610 v.3.4 20140206 product data sheet - slrc610 v.3.3 modifications: ? typo corrected slrc610 v.3.3 20140204 product data sheet - slrc610 v.3.2 modifications: ? pvdd, tvdd data updated ? information on fifo size corrected ? typing error corrected in description for lpcd ? waterlevel and fifolength updated in register overview description ? waterlevel and fifolength updated in register fifocontrol ? waterlevel register updated ? fifolength register updated ? section 9.15.2 ? pinout ? : pin out register de scription corrected slrc610 v.3.2 20130910 product data sheet - slrc610 v.3.1 modifications: ? update of eeprom content ? descriptive title changed ? table 182 ? pinout register (address 45h) ? : corrected slrc610 v.3.1 20120906 product data sheet - -
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 113 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 21.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 21.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 114 of 117 nxp semiconductors slrc610 high performance iso/iec 15693 reader solution quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 21.4 licenses 21.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. icode and i-code ? are trademarks of nxp b.v. 22. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with nfc technology purchase of an nxp semiconductors ic that complies with one of the near field communication (nfc) standards iso/iec 18092 and iso/iec 21481 does not convey an implied license unde r any patent right infringed by implementation of any of those standards.
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 115 of 117 continued >> nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 23. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general description . . . . . . . . . . . . . . . . . . . . . . 1 3 features and benefits . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 interrupt controller . . . . . . . . . . . . . . . . . . . . . . 6 8.2 timer module . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.1 timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1.1 time-out- and watch-dog- counter . . . . . . . . . 9 8.2.1.2 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1.3 stop watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1.4 programmable one-shot timer . . . . . . . . . . . . . 9 8.2.1.5 periodical trigger. . . . . . . . . . . . . . . . . . . . . . . . 9 8.3 contactless interface unit . . . . . . . . . . . . . . . 10 8.3.1 iso/iec15693 functionality . . . . . . . . . . . . . . 10 8.3.2 epc-uid/uid-otp functionality . . . . . . . . . . . 12 8.3.3 iso/iec 18000-3 mode 3/ epc class-1 hf functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3.4 epc class-1 hf and icode . . . . . . . . . . . . . 12 8.3.4.1 data encoding icode . . . . . . . . . . . . . . . . . . 12 8.4 host interfaces . . . . . . . . . . . . . . . . . . . . . . . . 12 8.4.1 host interface configuration . . . . . . . . . . . . . . 12 8.4.2 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4.2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4.2.2 read data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4.2.3 write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.4.2.4 address byte. . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.4.2.5 timing specification spi . . . . . . . . . . . . . . . . . 14 8.4.3 rs232 interface . . . . . . . . . . . . . . . . . . . . . . . 15 8.4.3.1 selection of the transfer speeds . . . . . . . . . . . 15 8.4.3.2 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.4.4 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 18 8.4.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.4.4.2 i 2 c data validity . . . . . . . . . . . . . . . . . . . . . . . 18 8.4.4.3 i 2 c start and stop conditions . . . . . . . . . . 19 8.4.4.4 i 2 c byte format . . . . . . . . . . . . . . . . . . . . . . . . 19 8.4.4.5 i 2 c acknowledge . . . . . . . . . . . . . . . . . . . . . . 20 8.4.4.6 i 2 c 7-bit addressing . . . . . . . . . . . . . . . . . . . . 20 8.4.4.7 i 2 c-register write access . . . . . . . . . . . . . . . . 21 8.4.4.8 i 2 c-register read access . . . . . . . . . . . . . . . . . 21 8.4.4.9 i 2 cl-bus interface. . . . . . . . . . . . . . . . . . . . . . 22 8.4.5 sam interface i 2 c . . . . . . . . . . . . . . . . . . . . . . 23 8.4.5.1 sam functionality . . . . . . . . . . . . . . . . . . . . . . 23 8.4.5.2 sam connection. . . . . . . . . . . . . . . . . . . . . . . 24 8.4.6 boundary scan interface . . . . . . . . . . . . . . . . 24 8.4.6.1 interface signals. . . . . . . . . . . . . . . . . . . . . . . 25 8.4.6.2 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . 25 8.4.6.3 test mode select (tms) . . . . . . . . . . . . . . . . 25 8.4.6.4 test data input (tdi) . . . . . . . . . . . . . . . . . . . 25 8.4.6.5 test data output (tdo) . . . . . . . . . . . . . . . . . 25 8.4.6.6 data register . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4.6.7 boundary scan cell. . . . . . . . . . . . . . . . . . . . . 26 8.4.6.8 boundary scan path . . . . . . . . . . . . . . . . . . . . 26 8.4.6.9 boundary scan description language (bsdl) 27 8.4.6.10 non-ieee1149.1 commands . . . . . . . . . . . . . 28 8.5 buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5.2 accessing the fifo buffer . . . . . . . . . . . . . . . 29 8.5.3 controlling the fifo buffer . . . . . . . . . . . . . . 29 8.5.4 status information about the fifo buffer. . . . 29 8.6 analog interface and contactless uart . . . . 31 8.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6.2 tx transmitter . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6.2.1 overshoot protection . . . . . . . . . . . . . . . . . . . 33 8.6.2.2 bit generator . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6.3 receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 34 8.6.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6.3.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . 35 8.6.4 active antenna concept . . . . . . . . . . . . . . . . . 36 8.6.5 symbol generator. . . . . . . . . . . . . . . . . . . . . . 39 8.7 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.7.1 memory overview. . . . . . . . . . . . . . . . . . . . . . 39 8.7.2 eeprom memory organization. . . . . . . . . . . 40 8.7.2.1 product information and configuration - page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.7.3 eeprom initialization content loadprotocol. 43 8.8 clock generation . . . . . . . . . . . . . . . . . . . . . . 45 8.8.1 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 45 8.8.2 integern pll clock line . . . . . . . . . . . . . . . . . 45 8.8.3 low frequency oscillator (lfo) . . . . . . . . . . 46 8.9 power management. . . . . . . . . . . . . . . . . . . . 47 8.9.1 supply concept . . . . . . . . . . . . . . . . . . . . . . . 47 8.9.2 power reduction mode . . . . . . . . . . . . . . . . . . 47 8.9.2.1 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.9.2.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . 47 8.9.2.3 modem off mode . . . . . . . . . . . . . . . . . . . . . . 47 8.9.3 low-power card detection (lpcd) . . . . . . . . 48 8.9.4 reset and start-up time . . . . . . . . . . . . . . . . . 48 8.10 command set. . . . . . . . . . . . . . . . . . . . . . . . . 49 8.10.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.10.2 command set overview . . . . . . . . . . . . . . . . . 49
slrc610 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet company public rev. 3.4 ? 6 february 2014 227634 116 of 117 continued >> nxp semiconductors slrc610 high performance iso/iec 15693 reader solution 8.10.3 command functionality . . . . . . . . . . . . . . . . . . 50 8.10.3.1 idle command . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.10.3.2 lpcd command . . . . . . . . . . . . . . . . . . . . . . . 50 8.10.3.3 ackreq command . . . . . . . . . . . . . . . . . . . . . 50 8.10.3.4 receive command . . . . . . . . . . . . . . . . . . . . . 50 8.10.3.5 transmit command . . . . . . . . . . . . . . . . . . . . . 50 8.10.3.6 transceive command . . . . . . . . . . . . . . . . . . . 51 8.10.3.7 writee2 command . . . . . . . . . . . . . . . . . . . . . 51 8.10.3.8 writee2page command . . . . . . . . . . . . . . . . 51 8.10.3.9 reade2 command . . . . . . . . . . . . . . . . . . . . . 51 8.10.3.10 loadreg command . . . . . . . . . . . . . . . . . . . . 51 8.10.3.11 loadprotocol command . . . . . . . . . . . . . . . . . 51 8.10.3.12 getrnr command . . . . . . . . . . . . . . . . . . . . . 52 8.10.3.13 softreset command . . . . . . . . . . . . . . . . . . . . 52 9 slrc610 registers . . . . . . . . . . . . . . . . . . . . . . 54 9.1 register bit behavior. . . . . . . . . . . . . . . . . . . . 54 9.2 command configuration . . . . . . . . . . . . . . . . . 57 9.2.1 command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3 sam configuration register . . . . . . . . . . . . . . . 57 9.3.1 hostctrl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.4 fifo configuration register . . . . . . . . . . . . . . . 58 9.4.1 fifocontrol . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.4.2 waterlevel . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.4.3 fifolength . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4.4 fifodata . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.5 interrupt configuration registers . . . . . . . . . . . 60 9.5.1 irq0 register . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.5.2 irq1 register . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.5.3 irq0en register . . . . . . . . . . . . . . . . . . . . . . . 62 9.5.4 irq1en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.6 contactless interface configuration registers . 63 9.6.1 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.6.2 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.6.3 rxbitctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.6.4 rxcoll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.7 timer configuration registers . . . . . . . . . . . . . 68 9.7.1 tcontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.7.2 t0control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.7.2.1 t0reloadhi. . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.7.2.2 t0reloadlo . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.7.2.3 t0countervalhi . . . . . . . . . . . . . . . . . . . . . . . 70 9.7.2.4 t0countervallo . . . . . . . . . . . . . . . . . . . . . . . 70 9.7.2.5 t1control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.7.2.6 t1reloadhi. . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.7.2.7 t1reloadlo . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.7.2.8 t1countervalhi . . . . . . . . . . . . . . . . . . . . . . . 72 9.7.2.9 t1countervallo . . . . . . . . . . . . . . . . . . . . . . . 72 9.7.2.10 t2control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.7.2.11 t2reloadhi. . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.7.2.12 t2reloadlo . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.7.2.13 t2countervalhi . . . . . . . . . . . . . . . . . . . . . . . 74 9.7.2.14 t2countervalloreg . . . . . . . . . . . . . . . . . . . 74 9.7.2.15 t3control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.7.2.16 t3reloadhi . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.7.2.17 t3reloadlo . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.7.2.18 t3countervalhi . . . . . . . . . . . . . . . . . . . . . . . 76 9.7.2.19 t3countervallo . . . . . . . . . . . . . . . . . . . . . . . 76 9.7.2.20 t4control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.7.2.21 t4reloadhi . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.7.2.22 t4reloadlo . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.7.2.23 t4countervalhi . . . . . . . . . . . . . . . . . . . . . . . 78 9.7.2.24 t4countervallo . . . . . . . . . . . . . . . . . . . . . . . 78 9.8 transmitter configuration registers. . . . . . . . . 78 9.8.1 txmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.8.2 txamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.8.3 txcon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.8.4 txl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.9 crc configuration registers. . . . . . . . . . . . . . 80 9.9.1 txcrcpreset . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.9.2 rxcrccon . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.10 transmitter configuration registers. . . . . . . . . 82 9.10.1 txdatanum . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.10.2 txsym10burstlen . . . . . . . . . . . . . . . . . . . . . 83 9.10.3 txwaitctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.10.4 txwaitlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.11 framecon . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.12 receiver configuration registers . . . . . . . . . . 86 9.12.1 rxsofd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.12.2 rxctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.12.3 rxwait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.12.4 rxthreshold. . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.12.5 rcv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.12.6 rxana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.13 clock configuration . . . . . . . . . . . . . . . . . . . . 89 9.13.1 serialspeed . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.13.2 lfo_trimm . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.13.3 pll_ctrl register. . . . . . . . . . . . . . . . . . . . . . 90 9.13.4 plldiv_out . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.14 low-power card detection configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.14.1 lpcd_qmin. . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.14.2 lpcd_qmax . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.14.3 lpcd_imin. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.14.4 lpcd_result_i . . . . . . . . . . . . . . . . . . . . . . . 93 9.14.5 lpcd_result_q . . . . . . . . . . . . . . . . . . . . . . 93 9.15 pin configuration . . . . . . . . . . . . . . . . . . . . . . 94 9.15.1 pinen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.15.2 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.15.3 pinin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.15.4 sigout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.16 version register . . . . . . . . . . . . . . . . . . . . . . . 96
nxp semiconductors slrc610 high performance iso/iec 15693 reader solution ? nxp b.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 6 february 2014 227634 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 9.16.1 version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 97 11 recommended operating conditions. . . . . . . 97 12 thermal characteristics . . . . . . . . . . . . . . . . . 97 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 97 13.1 timing characteristics . . . . . . . . . . . . . . . . . . 100 14 application information. . . . . . . . . . . . . . . . . 102 14.1 antenna design description . . . . . . . . . . . . . 102 14.1.1 emc low pass filter . . . . . . . . . . . . . . . . . . . . 102 14.1.2 antenna matching. . . . . . . . . . . . . . . . . . . . . 103 14.1.3 receiving circuit . . . . . . . . . . . . . . . . . . . . . . 103 14.1.4 antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . 104 15 package outline . . . . . . . . . . . . . . . . . . . . . . . 105 16 handling information. . . . . . . . . . . . . . . . . . . 106 17 packing information . . . . . . . . . . . . . . . . . . . 106 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 110 19 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 112 21 legal information. . . . . . . . . . . . . . . . . . . . . . 113 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 113 21.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 113 21.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 21.5 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 114 22 contact information. . . . . . . . . . . . . . . . . . . . 114 23 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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