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| austriamicrosystems ag is now ams ag the technical content of this austriamicrosystems datasheet is still valid. contact information: headquarters: ams ag tobelbaderstrasse 30 8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 e - mail: ams_sales @ams.com please visit our website at www.ams.com
as3675 flexible lighting management unit (charge pump, dcdc, 13 current sinks, adc, led test, ldo, audio controlled light) www.austriamicrosystems.com/as3675 1v3 1 - 80 (ptr) datasheet 1 general description the as3675 is a highly-integrated cmos power and lighting management unit for mobile telephones, and other 1-cell li+ or 3-cell nimh powered devices. the as3675 incorporates one step up dc/dc con- verter for white backlight leds, one high-power charge pump, one analog-to-digital converter, 13 current sinks, the rgb and white leds can be controlled by an audio input, led in-circuit function test, a two wire serial inter- face, and control logic all onto a single device. output voltages and output currents are fully programmable. the as3675 is part of to the austriamicrosystems as3676, as3687/87xm and as3689 lighting mange- ment units family. it is software compatible to as3687/ 87xm and as3689 and pin and software compatible to as3676. 2 key features high-efficiency step up dc/dc converter - up to 16v/55ma (or 25v/35ma) for white leds - programmable output volt age with external resis- tors and serial interface - over voltage protection high-efficiency high-power charge pump - 1:1, 1:1.5, and 1:2 mode - automatic up switching (can be disabled and 1:2 mode can be blocked) - output current up to 300ma/500ma pulsed - efficiency up to 95% - very low effective resistance (2.5 typ. in 1:1.5) - only 4 external capacitors required: 2 x 1f flying capacitors, 2 x 2.2f input/output capacitors - supports lcd white backlight leds, or rgb leds 13 current sinks - all 13 current sinks fully programmable (8-bit) from: 0.15ma to 38.5ma (up to 75.6ma for curr30...curr33) - three current sinks are high voltage capable (curr1, curr2, curr6) - programmable hardware control (strobe, and pre- view or pwm) - selectively enable/disable current sinks internal pwm generation - 8 bit resolution - autonomous logarithmic up/down dimming led pattern generator - autonomous driving for fun rgb leds - support indicator leds 10-bit successive approximation adc - 27s conversion time - selectable inputs: gpio, all current sources, vbat, cpout, dcdc_fb - internal temp. measurement - light sensor input support for automatic led testing (open and shorted leds can be identified) support for external temperature sensor for high current led protection (curr3x) strobe timeout protection - up to 1600ms - three different timing modes two general purpose inputs/output - vana/gpi input, gpio input/output - digital input, digital output using vana/gpi sup- ply and tristate - vana/gpi internal pull down - gpio programmable pull-up/down programmable ldo - 1.85 to 3.4v, 150ma - programmable via serial interface standby ldo always on - regulated 2.5v max. output 10ma - 3a quiescent current audio can be used to drive rgb led or up to four white leds - rgb color and brightness is dependent on audio input amplitude or frequency white leds can be controlled by amplitude or fre- quency (different modes like bar-type or two and two leds driven by frequency filters) wide battery supply range: 3.0 to 5.5v two wire serial interface control over current and thermal protection wl-csp30 3x2.5mm, 0.5mm pitch package 3 applications power- and lighting-management for mobile telephones and other 1-cell li+ or 3-cell nimh powered devices. ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 2 - 80 as3675 datasheet - applications figure 1. block diagram ams ag technical content still valid www.austriamicrosystems.com/as3675 1v3 3 - 80 as3675 datasheet - applications contents 1 general description ......................................................................................................... ................... 1 2 key features ................................................................................................................ ....................... 1 3 applications ................................................................................................................ ........................ 1 4 pinout ...................................................................................................................... ............................. 4 4.1 pin definitions ..............................................................................................................................................5 5 absolute maximum ratings ... ............................................................................................................ 6 6 electrical characteristics .................................................................................................. ................. 6 7 typical operating characteristics ........................................................................................... .......... 7 8 detailed description ........................................................................................................ ................... 9 8.1 analog ldo ..................................................................................................................................................9 8.2 step up dc/dc converter .........................................................................................................................11 8.3 charge pump ............................................................................................................................... ..............16 8.4 current sinks ............................................................................................................................... ..............24 8.5 general purpose input / output .................................................................................................................46 8.6 led test ............................................................................................................................... ......................51 8.7 analog-to-digital converter ........................................................................................................................53 8.8 audio controlled leds ............................................................................................................................... .56 8.9 power-on reset ............................................................................................................................... ..........65 8.10 temperature supervision ...........................................................................................................................67 8.11 serial interface ............................................................................................................................... ............67 8.12 operating modes ............................................................................................................................... ........70 9 register map ................................................................................................................ ..................... 71 10 external components .............................. .......................................................................... ............. 74 11 package drawings and mark ings .............................................................................................. .... 75 11.1 tape & reel information .............................................................................................................................76 12 ordering information ....................................................................................................... ............... 77 ams ag technical content still valid www.austriamicrosystems.com/as3675 1v3 4 - 80 as3675 datasheet - pinout 4 pinout table 1. pin description for as3675 pin number pin name type description a1 gpio aio general purpose input output a2 vana/gpi aio ldo output /general purpose input a3 c2_n aio charge pump flying capacitor; connect a ceramic capacitor of 500nf to this pin. a4 c1_p aio charge pump flying capacitor; connect a ceramic capacitor of 500nf to this pin. a5 cpout ao output voltage of the charge pump; connect a ceramic capacitor of 1f (20%). a6 data dio serial interface data input/output. b1 audio_in ai audio input b2 vss_cp gnd ground pad for charge pump b3 c1_n aio charge pump flying capacitor; connect a ceramic capacitor of 500nf to this pin. b4 c2_p aio charge pump flying capacitor; connect a ceramic capacitor of 500nf to this pin. b5 dcdc_gate ao dcdc gate driver. b6 clk di clock input for serial interface. c1 curr41 ai analog current sink input c2 rgb3 ai analog current sink input c3 vss gnd ground pad c4 vbat s supply pad. connect to battery. c5 curr30 ai analog current sink input, intended for activity icon led c6 dcdc_sns ai sense input of shunt resistor for step up dc/dc converter. d1 curr43 ai analog current sink input d2 rgb1 ai analog current sink input d3 curr33 ai analog current sink input, intended for activity icon led d4 curr31 ai analog current sink input, intended for activity icon led d5 curr2 ai_hv analog current sink input (intended for keyboard backlight) d6 dcdc_fb ai dcdc feedback. connect to resistor string. e1 curr42 ai analog current sink input e2 rgb2 ai analog current sink input e3 curr32 ai analog current sink input, intended for activity icon led e4 curr6 ai_hv analog current sink input (intended for keyboard backlight) e5 curr1 ai_hv analog current sink input (intended for keyboard backlight) e6 v2_5 ao3 output voltage of the low-power ldo; always connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%). do not load this pin during device startup. ams ag technical content still valid www.austriamicrosystems.com/as3675 1v3 5 - 80 as3675 datasheet - pinout 4.1 pin definitions table 2. pin type definitions type description di digital input do digital output dio digital input/output aio analog pad ai analog input ai_hv high-voltage (15v) pin ao3 analog output (3.3v) s supply pad gnd ground pad ams ag technical content still valid www.austriamicrosystems.com/as3675 1v3 6 - 80 as3675 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other cond itions beyond those indicated in table 4, ?operating conditions,? on page 6 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6 electrical characteristics table 3. absolute maximum ratings symbol parameter min max units comments v in_hv 15v pins -0.3 17 v applicable for high-voltage current sink pins curr1, curr2, curr6 v in_mv 5v pins -0.3 7.0 v applicable for 5v pins vbat, curr30-33, curr41-43, rgb1-3, c1_n, c2_n, c1_p, c2_p, cpout, dcdc_fb, dcdc_gate, clk, data; v in_lv 3.3v pins -0.3 5.0 v applicable for 3.3v pins v2_5; dcdc_sns, gpio, vana/gpi, audio_in input pin current -25 +25 ma at 25oc, norm: jedec 17 t strg storage temperature range -55 125 oc i in humidity 5 85 % non-condensing v esd electrostatic discharge -2000 2000 v norm: mil 883 e method 3015 pt total power dissipation 0.75 w ta = 70 oc, tjunc_max = 125oc t body peak body temperature 260 oc t = 20 to 40s, in accordance with ipc/jedec j-std 020. table 4. operating conditions symbol parameter condition min typ max unit general operating conditions v hv high voltage applicable for high-voltage current sink pins curr 1 , curr2 and curr6. 0.0 15.0 v v bat battery voltage pin vbat 3.0 3.6 5.5 v v peri periphery supply voltage for serial interface pins. 1.5 5.5 v v 2_5 voltage on pin v2_5 internally generated 2.4 2.5 2.6 v t amb operating temperature range -30 25 85 oc i active battery current normal operating current (see operating modes on page 71) 35 a i standby standby mode current current consumption in standby mode. only 2.5v regulator on, interface active 813a i shutdown shutdown mode current interface inactive (clkand data set to 0v) 0.1 3 a ams ag technical content still valid www.austriamicrosystems.com/as3675 1v3 7 - 80 as3675 datasheet - typical operating characteristics 7 typical operating characteristics figure 2. dcdc step up converter: efficiency of +15v, figure 3. charge pump: efficiency vs. vbat step up to 15v vs. load current at vbat =3.8v figure 4. charge pump: battery current vs. vbat figure 5. current sink curr1 vs. v(currx) figure 6. current sink curr1 protection current figure 7. current sink curr3x vs. vbat 65 70 75 80 85 90 0 0.010.020.030.040.050.06 load current [a] efficiency o f d cdc [%] vout=14.2v vout=17.2v vout=22v vout=14.2v fclk=550khz 0 10 20 30 40 50 60 70 80 90 10 0 2.8 3 3.2 3.4 3.6 3.8 4 4.2 v bat [v] efficiency of cp [%] i load =305ma i load =150ma i load =80ma i load =40ma 0 10 0 20 0 30 0 40 0 50 0 60 0 2.8 3 3. 2 3.4 3.6 3.8 4 4.2 vbat[v] iba t[m a] i loa d =305ma i loa d =150ma i loa d =80ma i loa d =40ma 0.0 5.0 10 .0 15 .0 20 .0 25 .0 30 .0 35 .0 40 .0 0 . 00 . 51 . 01 . 52 . 0 v curr1 [v ] i curr1 [ma] i curr1 =2.4ma i curr1 =19.2mam i curr1 =38.25ma 0,0 0,5 1,0 1,5 2,0 2,5 3,0 0,0 5 ,0 1 0,0 15 ,0 2 0,0 v(curr1) [v] c urrent [ma] curr_prot1_on=0 curr _prot1_ on=1 4. 5ua 0.0 5.0 10 .0 15 .0 20 .0 25 .0 30 .0 35 .0 40 .0 0 .0 0 .5 1. 0 1. 5 2. 0 v curr30 [v] i curr30 [ma] i curr30 =2.4ma i curr30 =1 9 .2 ma m i curr30 =38.25ma ams ag technical content still valid www.austriamicrosystems.com/as3675 1v3 8 - 80 as3675 datasheet - typical operating characteristics figure 8. charge pump input and output ripple f igure 9. charge pump input and output ripple 1:1.5 mode, 100ma l oad 1:2 mode, 100ma load figure 10. characteristics frequency mode, bp filter 512/2048hz vbat = 3.6v, t a = +25oc (unless otherwise specified). ! ! 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"# $ %& 0 0. 00 5 0.01 0. 01 5 0.02 0. 02 5 0.03 0. 03 5 0.04 10 100 1000 10000 100000 f requency[hz ] cu rrent[a ] bp gain +6/+4/+2/0/-2/-4/-6db ams ag technical content still valid www.austriamicrosystems.com/as3675 1v3 9 - 80 as3675 datasheet - detailed description 8 detailed description 8.1 analog ldo the ldo is a general purpose ldo and the output pin is shared with the general purpos e input (gpi) connected to vana/gpi. the design is optimized to deliver the best co mpromise between quiescent current and regulator perfor- mance for battery powered devices. stability is guaranteed with ceramic output capacitors (of 1f 20% (x5r) or 2.2f +100/-50%(z5u). the low esr of these capacitors ensures low output impedance at high frequencies. the low impedanc e of the power transistor enables the device to deliver up to 150ma even at near ly discharged batteries without any decrease in performance. the ldo is off by default after start-up. figure 11. analog ldo block diagram table 5. electrical characteristics symbol parameter condition min typ max unit v bat supply voltage range 3.0 5.5 v r on on resistance @150ma, full o perating temperature range 1.0 v dropout dropout voltage @150ma, ldo_ana_lpo (see page 10) = 0 150 mv @50ma, ldo_ana_lpo = 0 50 mv @5ma, ldo_ana_lpo = 1 500 mv i on supply current without load 50 a without load, ldo_ana_lpo = 1 ldo_ana only 3 with 150ma load 150 i off shutdown current without load 100 na t start start-up time 200 s v out_tol output voltage tolerance -3 +3 % v out output voltage v bat > 3.0v and i out =150ma 1.8 2.85 v full programmable range 1.8 3.35 v i limit 1 ldo current limit ldo_ana_lpo = 0 pin vana. ldo acts as current source if the output current exceeds i limit . 300 450 2 ma ldo current limit ldo_ana_lpo = 1 v bat -vana 0.2v 4 8 ma as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 10 - 80 as3675 datasheet - detailed description 8.1.1 ldo registers 1. not production tested ? guaranteed by design and laboratory verification 2. during startup of the ldo the curr ent limit is half the value of i limit table 6. reg. control register addr: 00 reg. control this register enables/disables the ldos, charge pumps, charge pump leds, current sinks, the step up dc/dc converter, and low-power mode. bit bit name default access description 0 ldo_ana_on 0r/w 0 analog ldo is switched off 1 analog ldo is switched on 7 ldo_ana_lpo 0r/w 0 normal operation 1 low-power mode; current consumption is reduced by about 75a. reduced performance of ldo: max 5ma load, internal oscillator is switched off. the device will exit low-power mode automatically, if blocks requiring the oscillator are enabled. table 7. ldo ana1 voltage register addr: 07h ldo ana1 voltage this register sets the output voltage (vana) for the ldo. bit bit name default access description 4:0 ldo_ana_voltage 00000b r/w controls ldo voltage selection. 00000b 1.85v ... lsb=50mv 11111b 3.4v ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 11 - 80 as3675 datasheet - detailed description 8.2 step up dc/dc converter the step up dc/dc converter is a high-efficiency current mode pwm regulator, providing output voltage up to e.g. 25v/35ma or e.g. 16v/55ma. a constant switching-frequency results in a low noise on the supply and output voltages. figure 12. step up dcdc converter block diagram opti on: current feedback with over voltage protection table 8. step up dc/dc converter parameters symbol parameter condition min typ max unit i vdd quiescent current pulse skipping mode. 140 a v fb1 feedback voltage for external resistor divider for constant voltage control. step_up_res = 1 1.20 1.25 1.30 v v fb2 feedback voltage for current sink regulation on curr1, curr2 or curr6 in regulation. step_up_res = 0 0.4 0.5 0.6 v i dcdc_fb additional tuning current at pin dcdc_fb and over voltage protection adjustable by software using register dcdc control1 1a step size (0-31a) v protect = 1.25v + i dcdc_fb * r 2 03 1 a accuracy of feedback current at full scale -6 6 % ! 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" as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 12 - 80 as3675 datasheet - detailed description to ensure soft startup of the dcdc converter, the over curre nt limits are reduced for a fixed time after enabling the dcdc converter. the total startup time for an output voltage of e.g. 25v is less than 2ms. 8.2.1 feedback selection register dcdc control1 and dcdc control2 selects the type of feedback for the step up dc/dc converter. the feedback for the dc/dc converter can be selected either by current sinks (curr1, curr2, curr6) or by a volt- age feedback at pin dcdc_fb. if the register bit step_up_fb_auto is set, the feedback path is automatically selected between curr1, curr2 and curr6 (the lowest voltage of these current sinks is used). setting step_up_fb enables feedback on the pins curr1, curr2 or curr6. the step up dc/dc converter is regu- lated such that the required current at the feedback path can be supported. (bit step_up_res should be set to 0 in this configuration) note: always choose the path with the highest voltage drop as feedback to guarantee adequate supply for the other (unregulated) paths or enable the register bit step_up_fb_auto . 8.2.2 over voltage protection in current feedback mode the over voltage protection in current feedback mode ( step_up_fb = 01, 10 or 11 or step_up_fb_auto = 1) works as fol- lows: only resistor r2 and c7/c8 is soldered and r3 is omitte d. an internal current source (sink) is used to generate a voltage drop across the resistor r2. if then the voltage on dcdc_fb is above 1.25v, the dcdc is momentarily dis- abled to avoid too high voltages on the output of the dcdc converter. the protection voltage can be calculated according to the following formula: v protect = 1.25v + i dcdc_fb * r 2 (eq 1) note: the voltage on the pin dcdc_fb is limited by an internal protection diode to vbat + one diode forward volt- age (typ. 0.6v). if the over voltage protection is not used in cu rrent feedback mode, connect dcdc_fb to ground. v rsense_max current limit voltage at r1 e.g., 0.66a for 0.1 sense resistor. 46 66 85 mv for fixed startup time of 500us 25 33 43 if step up_lowcur = 1 30 43 57 r sw switch resistance on-resistance of external switching transistor. 1 i load load current at 16v output voltage 0 55 ma at 25v output voltage 0 35 f in switching frequency internally trimmed 0.9 1 1.1 mhz c out output capacitor ceramic, 20%. use nominal 4.7f capacitors to obtain at least 0.7f under all conditions (voltage dependence of capacitors) 0.7 4.7 f l inductor use inductors with small c parasitic (<100pf) to get high efficiency. 71013h t min_on minimum on time 90 140 190 ns mdc maximum duty cycle 88 91 % vripple voltage ripple >20khz cout=4.7f,iout=0.. 45ma, vbat=3.0...4.2v 160 mv voltage ripple <20khz 40 mv efficiency efficiency iout=20ma,vout=17v,vbat=3.8v 85 % table 8. step up dc/dc converter parameters symbol parameter condition min typ max unit ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 13 - 80 as3675 datasheet - detailed description figure 13. step up dc/dc converter detail diagram; option: regulated output current, feedback is automatically selected between curr1, curr2, curr6 ( step_up_fb_auto =1); over voltage protection is enabled ( step_up_prot =1); 1mhz clock frequency ( step_up_frequ =0) 8.2.3 voltage feedback setting bit step_up_fb (see page 15) = 00 enables voltage feedback at pin dcdc_fb. the output voltage is regulated to a constant value, given by (bit step_up_res should be set to 1 in this configuration) u step up_out = (r 2 +r 3 )/r 3 *1.25 + i dcdc_fb * r 2 (eq 2) if r4 is not used, the out put voltage is by (bit step_up_res should be set to 0 in this configuration) u step up_out = 1.25 + i dcdc_fb * r 2 (eq 3) where: u step up_out = step up dc/dc converter output voltage r 2 = feedback resistor r2 r 3 = feedback resistor r3 2 !" # $% % % # & ' 2 ( ( ) * ( ( ( + ( ( 34 ( 5 $ '+* ) 6 ( ( 3 7 $ 8 8 9 +) +) )+ 9 * + 3 :4 9 ; << = ( ( 34 + > + : > + ( ? +) ++ + ( + + +) ++ ( 9 ( as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 14 - 80 as3675 datasheet - detailed description i dcdc_fb = tuning current at ball dcdc_fb; 0 to 31a note: the voltage on curr1, curr2 and curr6 must not exceed 15v (see page 25) 8.2.4 pcb layout hints to ensure good emc performance of the dcdc converter, keep its external power components c6, r1, l1, q1, d1 and c9 close together. connect the grou nd of c6, r1 and c9 locally together and connect this with a short path to as3675 vss. this ensures that local high-frequency currents will not flow to the battery. 8.2.5 step up registers table 9. voltage feedback example values i dcdc_fb u step up_out u step up_out a r2 = 1m , r3 not used r2 = 500k , r3 = 50k 0-1 3 . 7 5 1-1 4 . 2 5 2-1 4 . 7 5 3-1 5 . 2 5 4-1 5 . 7 5 5 6.25 16.25 6 7.25 16.75 7 8.25 17.25 8 9.25 17.75 9 10.25 18.25 10 11.25 18.75 11 12.25 19.25 12 13.25 19.75 13 14.25 20.25 14 15.25 20.75 15 16.25 21.25 ??? 30 31.25 28.75 31 32.25 29.25 table 10. reg. control register addr: 00 reg. control this register enables/disables t he charge pump and the step up dc/dc converter. bit bit name default access description 3 step_up_on 0r/w enable the step up converter 0b disable the step up dc/dc converter 1b enable the step up dc/dc converter ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 15 - 80 as3675 datasheet - detailed description table 11. dcdc control1 register addr: 21h dcdc control1 this register controls the step up dc/dc converter. bit bit name default access description 0 step_up_frequ 0 r/w defines the clock frequency of the step up dc/dc converter. 01mhz 1 500khz 2:1 step_up_fb 00 r/w controls the feedback source if step_up_fb_auto = 0 00 dcdc_fb enabled (external resistor divider). set step_up_fb=00 (dcdc_fb) 01 curr1 feedback enabled (feedback via leds) 10 curr2 feedback enabled (feedback via leds) 11 curr6 feedback enabled (feedback via leds) 7:3 step_up_vtuning 00000 r/w defines the tuning current at pin dcdc_fb. 00000 0 a 00001 1 a 00010 2 a .... 10000 15 a ..... 11111 31 a table 12. dcdc control2 register addr: 22h dcdc control2 this register controls the step up dc/dc converter and low-voltage current sinks curr3x. bit bit name default access description 0 step_up_res 0r/w gain selection for step up dc/dc converter 0 select 0 if step up dc/dc converter is used with current feedback (curr1, curr2, curr6) or if dcdc_fb is used with current feedback only ? r2, c7, c8 connected, r3 not used 1 select 1 if dcdc_fb is used with external resistor divider using 2 resistors: r2 and r3 1 skip_fast 0r/w step up dc/dc converter output voltage at low loads, when pulse skipping is active 0 accurate output voltage, more ripple 1 elevated output voltage, less ripple 2 step_up_prot 1r/w step up dc/dc converter protection 0 no over voltage protection 1 over voltage protection on pin dcdc_fb enabled voltage limitation =1.25v on dcdc_fb ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 16 - 80 as3675 datasheet - detailed description 8.3 charge pump the charge pump uses two external flying capacitors c3, c4 to generate output voltages higher than the battery volt- age. there are three different operat ing modes of the charge pump itself: 1:1 bypass mode - battery input and output are connected by a low-impedance switch - battery current = output current. 1:1.5 mode - the output voltage is up to 1.5 times the battery voltage (without load), but is limit ed to vcpoutmax all the time - battery current = 1.5 times output current. 1:2 mode - the output voltage is up to 2 times the battery voltage (w ithout load), but is limit ed to vcpoutmax all the time - battery current = 2 times output current as the battery voltage decreases, the charge pump must be switched from 1:1 mode to 1:1.5 mode and eventually in 1:2 mode in order to provide enough supply for the current sinks. depending on the actual current the mode with best overall efficiency can be automatically or manually selected: examples: battery voltage = 3.7v, led dropout vo ltage = 3.5v. the 1:1 mode will be sele cted and there is 200mv drop on the current sink and on the charge pump switch. efficiency 95%. battery voltage = 3.5v, led dropout voltage = 3.5v. the 1:1. 5 mode will be selected and there is 1.5v drop on the current sink and 250mv on the charge pump. efficiency 66%. battery voltage = 3.8v, led dropout voltage = 4.5v (camer a flash). the 1:2 mode can be selected and there is 600mv drop on the current sink and 2. 5v on the charge pump. efficiency 60%. the efficiency is dependent on the led forward voltage given by: eff=(v_led*iout)/(uin*iin) (eq 4) the charge pump mode switching can be done manually or aut omatically with the following possible software settings: automatic up all modes allowed (1:1, 1:1.5, 1:2) - start with 1:1 mode - switch up automatically 1:1 to 1:1.5 to 1:2 automatic up, but only 1:1 and 1:1.5 allowed - start with 1:1 mode - switch up automatically only from 1:1 to 1:1.5 mode; 1:2 mode is not used manual - set modes 1:1, 1:1.5, 1:2 by software 3 step up_lowcur 1r/w step up dc/dc converter coil current limit 0 normal current limit 1 current limit reduced by approx. 33% 7 step_up_fb_auto 0r/w 0 step_up_fb select the feedback of the dcdc converter 1 the feedback is automatically chosen within the current sinks curr1, curr2 and curr6 (never dcdc_fb). only t hose are used for this selection, which are enabled (currx_mode must not be 00) and not connected to the charge pump (currx_on_cp must be 0). table 12. dcdc control2 register addr: 22h dcdc control2 this register controls the step up dc/dc converter and low-voltage current sinks curr3x. bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 17 - 80 as3675 datasheet - detailed description figure 14. charge pump pin connections the charge pump requires the external components listed in the following table: note: the connections of the external capacitors c2, c3, c4 and c5 should be kept as short as possible. the maximum voltage on the flying capacitors c3 and c4 is vbat. table 13. charge pump external components symbol parameter condition min typ max unit c 2 external decoupling capacitor ceramic low-esr capacitor between pins vbat and vss. 1.0 f c 3 , c 4 external flying capacitor (2x) ceramic low-esr capacitor between pins c1_p and c1_n, between pins c2_p and c2_n and between vbat and vss 1.0 f c 5 external storage capacitor ceramic low-esr capacitor between pins cpout and vss, pins cpout and vss. use nominal 2.2f capacitors (size 0603) 2.2 f table 14. charge pump characteristics symbol parameter condition min typ max unit icpout output current continuous depending on pcb layout 0.0 300 ma output current pulsed max. 200ms v cpout = vbat * cp mode ? i load * r cp 0.0 500 ma vcpoutmax output voltage internally limited, including output ripple 5.6 v efficiency including current sink loss; icpout < 100ma. 60 90 % icp1_1.5 power consumption without load fclk = 1 mhz 1:1.5 mode 3.4 ma icp1_2 1:2 mode 3.8 rcp1_1 effective charge pump output resistance (open loop, fclk = 1mhz) 1:1 mode; vbat 3.5v 0.57 rcp1_1.5 1:1.5 mode; vbat 3.3v 2.65 rcp1_2 1:1.2 mode; vbat 3.1v 3.25 fclk accuracy accuracy of clock frequency -10 10 % ! as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 18 - 80 as3675 datasheet - detailed description 8.3.1 charge pump mode switching if automatic mode switching is enabled ( cp_mode_switching (see page 20) = 00 or cp_mode_switching = 01) the charge pump monitors the current sinks, which are connected via a led to the output cpout. to identify these current sources (sinks), the registers cp mode switch1 and cp mode switch2 (register bits curr30_on_cp (see page 21) ? curr33_on_cp , rgb1_on_cp ? rgb3_on_cp , curr1_on_cp , curr2_on_cp , curr41_on_cp ? curr43_on_cp and curr6_on_cp ) should be setup before starting the charge pump ( cp_on (see page 20) = 1). if any of the voltage on these current sources drops below the threshold (currlv_swit ch, currhv_switch), the next higher mode is selected after the debounce time. to avoid switching into 1:2 mode (battery current = 2 times output current), set cp_mode_switching = 01. if the currx_on_cp=0 and the according current sink is conne cted to the charge pump, the current sink will be func- tional, but there is no up switching of the charge pump, if the voltage compliance is too low for the current sink to sup- ply the specified current. currhv_switch curr1, 2, 6 minimum voltage if the voltage drops below this threshold, the charge pump will use the next available mode (1:1 -> 1:1.5 or 1:1.5 -> 1:2) 0.45 v currlv_switch curr30-33, rgb1- 3, curr41-3 minimum voltage 0.2 v curr30-33 0-75.6ma range for strobe if curr3x_strobe_high = 1 0.4 v t deb cp automatic up- switching debounce time cp_start_debounce =0 240 sec after switching on cp (cp_on set to 1), if cp_start_debounce =1 2000 sec table 14. charge pump characteristics symbol parameter condition min typ max unit ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 19 - 80 as3675 datasheet - detailed description figure 15. automatic mode switching 8.3.2 soft start an implemented soft start mechanism reduces the inrush current. battery current is smoothed when switching the charge pump on and also at each switch ing condition. this precaution reduces el ectromagnetic radiation significantly. ! "##$ $ "##% "##% % % "##% % & ' ( )* + + * , * % , & * -) . &-/0 * #1- #1- #1- as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 20 - 80 as3675 datasheet - detailed description 8.3.3 charge pump registers table 15. reg. control register addr: 00h reg. control this register controls the charge pump. bit bit name default access description 2 cp_on 0r/w 0 set charge pump into 1:1 mode (off state) unless cp_auto_on is set 1 enable manual or automatic mode switching table 16. cp control register addr: 23h cp control this register enables/disables t he charge pump and the step up dc/dc converter. bit bit name default access description 0 cp_clk 0r/w clock frequency selection. 01 mhz 1 500 khz 2:1 cp_mode 00b r/w charge pump mode (in manual mode sets this mode, in automatic mode reports th e actual mode used) 1 1. direct switching from 1:1.5 mode into 1:2 in manual mode and vice versa is not allowed. always switch over 1:1 mode. 00 1:1 mode 01 1:1.5 mode 10 1:2 mode 11 na 4:3 cp_mode_switching 00b r/w set the mode switching algorithm 00 automatic mode switching; 1:1, 1:1.5 and 1:2 allowed 01 automatic mode switching; only 1:1 and 1:1.5 allowed 10 manual mode switching; register cp_mode defines the actual charge pump mode used 11 reserved 5 cp_start_debounce 0r/w 0 mode switching debounce timer is always 240s 1 upon startup ( cp_on set to 1) the mode switching debounce time is first started with 2ms then reduced to 240s 6 cp_auto_on 0r/w 0 charge pump is switched on/off with cp_on 1 charge pump is automatically switched on if a current sink, which is connected to the charge pump (defined by registers cp mode switch 1 & 2) is switched on ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 21 - 80 as3675 datasheet - detailed description table 17. cp mode switch1 register addr: 24h cp mode switch1 setup which current sinks are connected (via leds) to the charge pump; if set to ?1? the correspond current source (sink) is used for automatic mode selection of the charge pump bit bit name default access description 0 curr30_on_cp 0r/w 0 current sink curr30 is not connected to charge pump 1 current sink curr30 is connected to charge pump 1 curr31_on_cp 0r/w 0 current sink curr31 is not connected to charge pump 1 current sink curr31 is connected to charge pump 2 curr32_on_cp 0r/w 0 current sink curr32 is not connected to charge pump 1 current sink curr32 is connected to charge pump 3 curr33_on_cp 0r/w 0 current sink curr33 is not connected to charge pump 1 current sink curr33 is connected to charge pump 4 rgb1_on_cp 0r/w 0 current sink rgb1 is not connected to charge pump 1 current sink rgb1 is connected to charge pump 5 rgb2_on_cp 0r/w 0 current sink rgb2 is not connected to charge pump 1 current sink rgb2 is connected to charge pump 6 rgb3_on_cp 0r/w 0 current sink rgb3 is not connected to charge pump 1 current sink rgb3 is connected to charge pump table 18. cp mode switch2 register addr: 25h cp mode switch2 setup which current sinks are connected (via leds) to the charge pump; if set to ?1? the correspond current source (sink) is used for automatic mode selection of the charge pump bit bit name default access description 0 curr1_on_cp 0r/w 0 current sink curr1is not connected to charge pump 1 current sink curr1 is connected to charge pump 1 curr2_on_cp 0r/w 0 current sink curr2 is not connected to charge pump 1 current sink curr2 is connected to charge pump 2 curr41_on_cp 0r/w 0 current sink curr41 is not connected to charge pump 1 current sink curr41 is connected to charge pump 3 curr42_on_cp 0r/w 0 current sink curr42 is not connected to charge pump 1 current sink curr42 is connected to charge pump ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 22 - 80 as3675 datasheet - detailed description 4 curr43_on_cp 0r/w 0 current sink curr43 is not connected to charge pump 1 current sink curr43 is connected to charge pump 7 curr6_on_cp 0r/w 0 current sink curr6 is not connected to charge pump 1 current sink curr6 is connected to charge pump table 19. curr low voltage status1 register addr: 2ah curr low voltage status1 indicates the low voltage status of the current sinks. if the currx_low_v bit is set, the voltage on the current sink is too low, to drive the selected output current bit bit name default access description 0 curr30_low_v na r 0 voltage of current sink curr30 >currlv_switch 1 voltage of current sink curr30 www.austriamicrosystems. com/as3675 1v3 25 - 80 as3675 datasheet - detailed description 8.4.1 high voltage current sinks curr1, curr2, curr6 the high voltage current sinks have a resolution of 8 bits. addi tionally an internal protection circuit monitors with a volt- age divider (max 3a @ 15v) the voltage on curr1, curr2 and curr6 and increases the current in off state in case of over voltage. high voltage current sinks curr1, curr2, curr6 registers table 22. hv current sinks characteristics symbol parameter condition min typ max unit i bit7 current sink if bit7 = 1 for v(currx) > 0.45v 19.2 ma i bit6 current sink if bit6 = 1 9.6 i bit5 current sink if bit5 = 1 4.8 i bit4 current sink if bit4 = 1 2.4 i bit3 current sink if bit3 = 1 1.2 i bit2 current sink if bit2 = 1 0.6 i bit1 current sink if bit1 = 1 0.3 i bit0 current sink if bit0 = 1 0.15 m matching accuracy curr1,curr2,curr6 -10 +10 % absolute accuracy -15 +15 % v curr1,2,6x voltage compliance 0.45 15 v ov_prot_13v over voltage protection of current sink curr1,2,6 at 13v, independent of curr1_prot_on , curr2_prot_on or curr6_prot_on 3.0 a ov_prot_15v over voltage protection of current sink curr1,2,6 at 15v, step_up_on=1, curr1_prot_on =1 for curr1, curr2_prot_on =1 for curr2, curr6_prot_on =1 for curr6 0.8 4.0 ma table 23. curr1 current register addr: 09h curr1 current this register controls the hig h voltage current sink current. bit bit name default access description 7:0 curr1_current 0r/w defines current into current sink curr1 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 26 - 80 as3675 datasheet - detailed description table 24. curr2 current register addr: 0ah curr2 current this register controls the hig h voltage current sink current. bit bit name default access description 7:0 curr2_current 0r/w defines current into current sink curr2 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 25. curr6 current register addr: 2fh curr6 current this register controls the hig h voltage current sink current. bit bit name default access description 7:0 curr6_current 0r/w defines current into current sink curr6 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 26. curr12 control register addr: 01h curr12 control this register select the mode of the cu rrent sinks controls high voltage current sink current. bit bit name default access description 1:0 curr1_mode 0r/w select the mode of the current sink curr1 00b off 01b on 10b pwm controlled 11b led pattern controlled 3:2 curr2_mode 0r/w select the mode of the current sink curr2 00b off 01b on 10b pwm controlled 11b led pattern controlled ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 27 - 80 as3675 datasheet - detailed description 8.4.2 current sinks curr30, curr31, curr32, curr33 these current sinks have a resolution of 8 bits and can sink up to 38.25ma. the current values can be controlled indi- vidually with curr30_current ? curr33_current or common with curr3x_strobe or curr3x_preview. table 27. curr rgb control register addr: 02h curr rgb control this register select the mode of the current sinks curr6. bit bit name default access description 7:6 curr6_mode 0r/w select the mode of the current sink curr6 00b off 01b on 10b pwm controlled 11b led pattern controlled table 28. dcdc control2 register addr: 22h dcdc control2 this register controls the step up dc/dc converter and low-voltage current sinks curr3x. bit bit name default access description 4 curr1_prot_on 0r/w 0 no over voltage protection 1 pull down current on curr1 switched on, if voltage on curr1 exceeds 13.75v, and step_up_on=1 5 curr2_prot_on 0r/w 0 no over voltage protection 1 pull down current on curr2 switched on, if voltage exceeds on curr2 13.75v, and step_up_on=1 6 curr6_prot_on 0r/w 0 no over voltage protection 1 pull down current on curr6 switched on, if voltage on curr6 exceeds 13.75v, and step_up_on=1 table 29. current sinks curr30,31,32,33 parameters symbol parameter condition min typ max unit i bit7 current sink if bit7 = 1 for v(curr3x) > 0.2v 19.2 ma i bit6 current sink if bit6 = 1 9.6 i bit5 current sink if bit5 = 1 4.8 i bit4 current sink if bit4 = 1 2.4 i bit3 current sink if bit3 = 1 1.2 i bit2 current sink if bit2 = 1 0.6 i bit1 current sink if bit1 = 1 0.3 i bit0 current sink if bit0 = 1 0.15 m matching accuracy curr30-33 -10 +10 % absolute accuracy -15 +15 % v curr3x voltage compliance 0.2 cpo ut v curr3x_strobe_high =1 and strobe function 0.4 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 28 - 80 as3675 datasheet - detailed description current sinks c urr3x registers table 30. curr3 control2 register addr: 12h curr3 control2 this register selects the modes of the current sinks30..33 current. bit bit name default access description 0 preview_off_after strobe 0b r/w select the switch off mode after strobe pulse 0 normal preview/strobe mode 1 switch off preview after strobe duration has expired. to reinitiate the torch mode the preview_ctrl has to be set off and on again 2:1 preview_ctrl 00b r/w preview is triggered by 00b off 01b software trigger (setting this bit automatically triggers preview) 10b curr2 active high; set gpi_curr2_en =1 11b curr2 active low; set gpi_curr2_en =1 5 curr3x_strobe_high 0b r/w double current on curr30...curr33 during strobe function 0 normal strobe current (0-37.8ma) 1 double strobe current (0-75.6ma) 7 strobe_pin 0r/w select strobe input pin and current sink outputs (only if strobe_ctrl =10 or 11) 0 curr1 is strobe input; curr30...curr33 flash output; set gpi_curr1_en =1 1 curr30 is strobe input; curr1, curr2, curr6 flash output; set gpi_curr30_en =1 table 31. curr3 strobe control register addr: 11h curr3 strobe control this register selects the modes of the current sinks30..33 current. bit bit name default access description 1:0 strobe_ctrl 00b r/w strobe is triggered by 00b off 01b software trigger (setting this bit automatically triggers strobe) 10b curr1 (or curr30 see strobe_pin ) active high 11b curr1 (or curr30 see strobe_pin ) active low 3:2 strobe_mode 00b r/w selects strobe mode 00b mode1 (tstrobe=ts; strobe trigger signal 10s) 01b mode 2 (tstrobe=max ts) 10b mode 3 (tstrobe = strobe signal) 11b not used ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 29 - 80 as3675 datasheet - detailed description 7:4 strobe_timing 0000b r/w selects strobe time (ts) 0000b 100 msec 0001b 200 msec 0010b 300 msec 0011b 400 msec 0100b 500 msec 0101b 600 msec 0110b 700 msec 0111b 800 msec 1000b 900 msec 1001b 1000 msec 1010b 1100 msec 1011b 1200 msec 1100b 1300 msec 1101b 1400 msec 1110b 1500 msec 1111b 1600 msec table 32. curr3x strobe register addr: 0eh curr3x strobe this register selects the strobe current of the current sinks30..33 bit bit name default access description 5:0 curr3x_strobe 00 r/w defines strobe current of current sinks curr30-33 00h 0 ma 01h 0.6 ma (1.2ma if curr3x_strobe_high =1) .... .... 3fh 37.8 ma (75.6ma if curr3x_strobe_high =1) table 33. curr3x preview register addr: 0fh curr3x preview this register selects the preview current of the current sinks30..33 bit bit name default access description 5:0 curr3x_preview 00 r/w defines preview current of current sinks curr30-33 00h 0 ma 01h 0.6 ma .... .... 3fh 37.8 ma table 31. curr3 strobe control register (continued) addr: 11h curr3 strobe control this register selects the modes of the current sinks30..33 current. bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 30 - 80 as3675 datasheet - detailed description table 34. curr3x other register addr: 10h curr3x other this register selects the current of the current sinks30..33 bit bit name default access description 5:0 curr3x_other 00 r/w selects curr30 current, if curr30 is not used for strobe/ preview (curr30_mode=11b) 00h 0 ma 01h 0.6 ma .... .... 3fh 37.8 ma table 35. curr30 current register addr: 40h curr30 current this register selects the current of the current sink30 bit bit name default access description 7:0 curr30_current 00 r/w selects curr30 current, if curr30 is not used for strobe/ preview ( curr30_mode =11b) 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 36. curr31 current register addr: 41h curr31 current this register selects the current of the current sink31 bit bit name default access description 7:0 curr31_current 00 r/w selects curr30 current, if curr30 is not used for strobe/ preview ( curr31_mode =11b) 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 37. curr32 current register addr: 42h curr32 current this register selects the current of the current sink32 bit bit name default access description 7:0 curr32_current 00 r/w selects curr32 current, if curr32 is not used for strobe/ preview ( curr32_mode =11b) 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 31 - 80 as3675 datasheet - detailed description table 38. curr33 current register addr: 43h curr33 current this register selects the current of the current sink33 bit bit name default access description 7:0 curr33_current 00 r/w selects curr33 current, if curr33 is not used for strobe/ preview ( curr33_mode =11b) 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 39. curr3 control1 register addr: 03h curr3 control1 this register select the mode of the current sinks30 - 33 bit bit name default access description 1:0 curr30_mode 0r/w select the mode of the current sink curr30 00b off 01b strobe/preview 10b curr30_current or curr3x_other pwm controlled 11b curr30_current or curr3x_other - don?t use curr3x_other if softdim_pattern =1, use curr30_current instead 3:2 curr31_mode 0r/w select the mode of the current sink curr31 00b off 01b strobe/preview 10b curr31_current or curr3x_other pwm controlled 11b curr31_current - don?t use curr3x_other if softdim_pattern =1, use curr31_current instead 5:4 curr32_mode 0r/w select the mode of the current sink curr32 00b off 01b strobe/preview 10b curr32_current or curr3x_other pwm controlled 11b curr32_current or curr3x_other - don?t use curr3x_other if softdim_pattern =1, use curr32_current instead 7:6 curr33_mode 0r/w select the mode of the current sink curr33 00b off 01b strobe/preview 10b curr33_current or curr3x_other pwm controlled 11b curr33_current or curr3x_other - don?t use curr3x_other if softdim_pattern =1, use curr33_current instead ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 32 - 80 as3675 datasheet - detailed description 8.4.3 current sink s rgb1, rgb2, rgb3 these current sinks have a resolution of 8 bits and can sink up to 38.25ma. table 40. pattern control register addr: 18h pattern control this register controls the led pattern bit bit name default access description 4 curr30_pattern 0b r/w additional curr33 led pattern control bit 0b curr30 controlled according curr30_mode register 1b curr30 controlled by led pattern generator 5 curr31_pattern 0b r/w additional curr33 led pattern control bit 0b curr31 controlled according curr31_mode register 1b curr31 controlled by led pattern generator 6 curr32_pattern 0b r/w additional curr33 led pattern control bit 0b curr32 controlled according curr33_mode register 1b curr32 controlled by led pattern generator 7 curr33_pattern 0b r/w additional curr33 led pattern control bit 0b curr33 controlled according curr33_pattern register 1b curr33 controlled by led pattern generator table 41. current sinks rg b1, rgb2, rgb3 parameters symbol parameter condition min typ max unit i bit7 current sink if bit7 = 1 for v(rgbx) > 0.2v 19.2 ma i bit6 current sink if bit6 = 1 9.6 i bit5 current sink if bit5 = 1 4.8 i bit4 current sink if bit4 = 1 2.4 i bit3 current sink if bit3 = 1 1.2 i bit2 current sink if bit2 = 1 0.6 i bit1 current sink if bit1 = 1 0.3 i bit0 current sink if bit0 = 1 0.15 m matching accuracy rgb1, rgb2, rgb3 -10 +10 % absolute accuracy -15 +15 % v rgbx voltage compliance 0.2 cpo ut v ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 33 - 80 as3675 datasheet - detailed description rgb current sinks registers table 42. curr rgb control register addr: 02h curr rgb control this register select the mode of the current sinks rgb1, rgb2, rgb3 bit bit name default access description 1:0 rgb1_mode 0r/w select the mode of the current sink rgb1 00b off 01b on 10b pwm controlled 11b led pattern controlled 3:2 rgb2_mode 0r/w select the mode of the current sink rgb2 00b off 01b on 10b pwm controlled 11b led pattern controlled 5:4 rgb3_mode 0r/w select the mode of the current sink rgb3 00b off 01b on 10b pwm controlled 11b led pattern controlled table 43. rgb1 current register addr: 0bh rgb1 current this register controls th e rgb current sink current. bit bit name default access description 7:0 rgb1_current 0r/w defines current into current sink rgb1 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 44. rgb2 current register addr: 0ch rgb2 current this register controls th e rgb current sink current. bit bit name default access description 7:0 rgb2_current 0r/w defines current into current sink rgb2 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 34 - 80 as3675 datasheet - detailed description 8.4.4 general purpose current sinks curr4x these low voltage current sinks have a resolu tion of 8 bits and can sink up to 38.25ma. general purpose current sinks curr4x registers table 45. rgb3 current register addr: 0dh rgb3 current this register controls th e rgb current sink current. bit bit name default access description 7:0 rgb3_current 0r/w defines current into current sink rgb3 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 46. curr4x sinks characteristics symbol parameter condition min typ max unit i bit7 current sink if bit7 = 1 for v(currx) > 0.2v 19.2 ma i bit6 current sink if bit6 = 1 9.6 i bit5 current sink if bit5 = 1 4.8 i bit4 current sink if bit4 = 1 2.4 i bit3 current sink if bit3 = 1 1.2 i bit2 current sink if bit2 = 1 0.6 i bit1 current sink if bit1 = 1 0.3 i bit0 current sink if bit0 = 1 0.15 m matching accuracy curr1,curr2 -10 +10 % absolute accuracy -15 +15 % v curr41,42,43x voltage compliance 0.2 cpo ut v table 47. curr4 control register addr: 04h curr4 control this register selects the mode of the current sinks curr41, curr42, curr43 bit bit name default access description 1:0 curr41_mode 0r/w select the mode of the current sink curr41 00b off 01b on 10b pwm controlled 11b led pattern controlled ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 35 - 80 as3675 datasheet - detailed description 3:2 curr42_mode 0r/w select the mode of the current sink curr42 00b off 01b on 10b pwm controlled 11b led pattern controlled 5:4 curr43_mode 0r/w select the mode of the current sink curr43 00b off 01b on 10b pwm controlled 11b led pattern controlled table 48. curr41 current register addr: 13h curr41 current this register controls the curr41 current sink current. bit bit name default access description 7:0 curr41_current 0r/w defines current into current sink curr41 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 49. curr42 current register addr: 14h curr42 current this register controls the curr42 current sink current. bit bit name default access description 7:0 curr42_current 0r/w defines current into current sink curr42 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma table 47. curr4 control register (continued) addr: 04h curr4 control this register selects the mode of the current sinks curr41, curr42, curr43 bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 36 - 80 as3675 datasheet - detailed description 8.4.5 led pattern generator the led pattern generator is capable of producing a patter n with 32 bits length and 1 second duration (31.25ms for each bit). the pattern itself can be started every second, every 2 nd , 3 rd up to 7 th second 1 . with this pattern all current sinks can be controlled. the pattern itself switc hes the configured current sources between 0 and their programmed current. if everything else is switched off, the current consumption in this mode is i active . (excluding current through switched on current source) and the charge pump, if required. the c harge pump can be automatically switched on/off depending on the pattern (set register cp_auto_on on page 20 =1) to reduce the overall current consumption. figure 16. led pattern generator as3675 for pattern_color = 0 to select the different current sinks to be controlled by the led pattern generator, see the ?xxxx?_mode registers (where ?xxxx? stands for the to be controlled current sink , e.g. curr1_mode for curr1 current sink). see also the description of the different current sinks. to allow the generator of a color patterns set the bit pattern_color to ?1?. then the pattern can be connected to currx as follows: figure 17. led pattern generator as3675 for pattern_color = 1 table 50. curr43 current register addr: 15h curr43 current this register controls the curr43 current sink current. bit bit name default access description 7:0 curr43_current 0r/w defines current into current sink curr43 00h 0 ma 01h 0.15 ma .... .... ffh 38.25 ma 1. all times can be extended by a factor of 8 by setting pattern_slow =1 (this result in a delay of up to 56s) 2 ! ! !! ! ! ! ! ! ! "# $ % "" #$ # & '# ( # & )* + 33 " 33 !" # $ # $ % &'(' )*+ & ), )- & .)& ( $ - ' +& ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 37 - 80 as3675 datasheet - detailed description only those current sinks will be co ntrolled, where the ?xxxx?_mode regist er is configured for led pattern. if the register bit pattern_slow is set, all pattern times are increased by a factor of eight. (bit duration: 250ms if pattern_color =0 / 800ms if pattern_color =1, delays between pattern up to 56s). soft dimming for pattern the internal pattern generator can be combined with the internal pwm dimming modulator to obtain as shown in the fol- lowing figure: figure 18. soft dimming architecture for the as3675 (softdim_pattern=1 and pattern_color = 1) with the as3675 smooth fade-in and fade-out effects can be automatically generated. as there is only one dimming ramp generator and one pwm modulator following constraints have to be considered when setting up the pattern (applies only if pattern_color =1): figure 19. soft dimming example waveform for curr30-32 however using the identical dimming waveform for two channels is possible as shown in the following figure: / ! " # $ "$ #$ % $& " # ' (() ( * +, - ./ ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 38 - 80 as3675 datasheet - detailed description figure 20. soft dimming example waveform for curr30-32 led pattern registers table 51. pattern data0 ... pattern data3 registers addr: 19h,1ah,1bh,1ch pattern data0 , pattern data1 , pattern data2 , pattern data3 this registers contains the pattern data for the current sinks. bit bit name default access description 7:0 pattern_data[7:0] 1 1. update any of the pattern register only if none of t he current sources is connected to the pattern generator ('xxxx'_mode must not be 11b). the pa ttern generator is automatically starte d at the same time when any of the current sources is connecte d to the pattern generator 0 r/w pattern data0 7:0 pattern_data[15:8]1111 1 0 r/w pattern data1 7:0 pattern_data[23:16]1111 1 0 r/w pattern data2 7:0 pattern_data[31:24]1111 1 0 r/w pattern data3 table 52. pattern control register addr: 18h pattern control this register controls the led pattern bit bit name default access description 0 pattern_color 0r/w defines the pattern type for the current sinks 0b single 32 bit pattern (also set currx_mode = 11) 1b rgb pattern with each 10 bits (set all currx_mode = 11) 2:1 pattern_delay 00b r/w delay between pattern, details (see table 55) ; together with pattern_delay2 sets the delay time between patterns 3 softdim_pattern 1 1. if softdim_pattern =1, don?t set curr30_mode , curr31_mode , curr32_mode or curr33_mode to 11b. 0b r/w enable the ?soft? dimming feature for the pattern generator 0 pattern generator directly control current sources 1 ?soft dimming? is performed (see page 37) table 53. gpio current register addr: 2ch gpio current bit bit name default access description 4 pattern_delay2 0r/w delay between pattern (see table 55 on page 39) ; together with pattern_delay sets the delay time between patterns ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 39 - 80 as3675 datasheet - detailed description 8.4.6 pwm generator 6 pattern_slow 0r/w pattern timing control 0b normal mode 1b slow mode (all pattern times are increased by a factor of eight) table 54. pattern end register addr: 54h pattern end bit bit name default access description 0 pattern_end 0r pattern_end is toggled from 0 to 1 (or from 1 to 0) at each end of the pattern just before restarting of the internal pattern generator at the fi rst bit of the pattern data (can be used to synchronize the baseband software to the pattern generator) 1 1. pattern_end toggles whenever the as3675 is in active mode (see section 8.12 operating modes on page 71 ) even if no pattern data has been setup. table 55. led pattern timing pattern_slow pattern_delay2 pattern_delay [1..0] bit duration [ms] delay [s] between patterns pattern duration [s] (total cycle time: pattern + delay) delay between patterns pattern_color =0 pattern_color =1 0 0 00 31 100 0 1 1 0 0 01 31 100 1 2 0 0 10 31 100 2 3 00 11 3110034 0 1 00 31 100 4 5 0 1 01 31 100 5 6 0 1 10 31 100 6 7 01 1 1 3 11 0 078 1 0 00 250 800 0 8 1 0 01 250 800 8 16 1 0 10 250 800 16 24 1 0 11 250 800 24 32 1 1 00 250 800 32 40 1 1 01 250 800 40 48 1 1 10 250 800 48 56 1 1 11 250 800 56 64 1. even by setting 000 for pattern delay, there is a small delay before the new patterns starts. table 53. gpio current register (continued) addr: 2ch gpio current bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 40 - 80 as3675 datasheet - detailed description the pwm generator can be used for any current sink. the sett ing applies for all current sinks, which are controlled by the pwm generator (e.g. curr1 is pwm controlled if curr1_mode = 10). the pwm modulated signal can switch on/off the current sinks and therefore depending on its duty cycle change the brightness of an attached led. internal pwm generator the internal pwm generator uses the 2mhz internal clock as input frequency and its dimming range is 6 bits digital (2mhz / 2^6 = 31.3khz pwm frequency) and 2 bits anal og. depending on the actual code in the register pwm_code the following algorithm is used: if pwm_code bit 7 = 1 then the upper 6 bits (bits 7:2) of pwm_code are used for the 6 bits pwm generatio n, which controls the selected cur- rents sinks directly if pwm_code bit 7 =0 and bit 6 = 1 then bits 6:1 of pwm_code are used for the 6 bits pwm generation. this si gnal controls the selected current sinks, but the analog current of these sinks is divided by 2 if pwm_code bit 7 and bit 6 = 0 then bits 5:0 of pwm_code are used for the 6 bits pwm generation. this si gnal controls the selected current sinks, but the analog current of these sinks is divided by 4 figure 21. pwm control automatic up/down dimming if the register pwm_dim_mode is set to 01 (up dimming) or 10 (dow n dimming) the value within the register pwm_code is increased (up dimming) or decreased (dow n dimming) every time and amount (either 1/4 th or 1/8 th ) defined by the register pwm_dim_speed . the maximum value of 255 (completely on) and the minimum value of 0 (off) is never exceeded. it is used to smoothly and automatically dim the brightness of the leds connected to any of the current sinks. the pwm code is readable all the time (also during up and down dimming). the waveform for up dimming looks as fo llows (cycles omitted for simplicity): figure 22. pwm dimming waveform for up dimming ( pwm_dim_mode = 01); currx_mode = pwm controlled (not all steps shown) the internal pwm modulator circuit controls the current sinks as shown in the following figure: ! " # ! " # $ ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 41 - 80 as3675 datasheet - detailed description figure 23. pwm control circuit (currx_mode = 10b (pwm controlled)); x = any current sink the adder logic (available for all current sinks) is intended to allow dimming not only from 0% to 100% (or 100% to 0%) of currx_current, but also e.g. from 10% to 110% (or 110% to 10%) of currx_current. the starting current for up dim- ming is defined by 0 + currx_adder and the end current is defined by currx_current + currx_adder. an overflow of the internal bus (8 bits wide to the idac) has to be avoided by the register settings (currx_current + currx_adder must not exceed 255). if the register subx_en is se t, the result from the pwm modulator is inve rted logically. that means for up dimming the starting current is defined by currx_adder - 1 and the end cu rrent is defined by currx_adder - currx_current - 1. an overflow of the internal bus (8 bits wide to the idac) has to be avoided by the register settings (currx_adder - currx_current - 1 must not be below zero). its purpose is to dim one channel e.g. curr30 from e.g. 110% to 10% of curr30_current and at the same time dim another channel e.g. curr31 from 20% to 120% of curr31_current. note: the adder logic operates independent of the currx_mode sett ing, but its main purpose is to work together with the pwm modulator (improved up/down dimming) if the adder logic is not used anymore, set the bit currx_ adder to 0. (setting adder_currentx to 0 is not suffi- cient) at the end of up/down dimming, the pwm_code register keeps its final value (for up-dimming 255 and for down- dimming 0). this can be used to identify the exact time, when up/down dimming is finished. table 56. pwm dimming table decrease by 1/4th every step decrease by 1/8th every step seconds seconds seconds seconds step %dimming pwm %dimming pwm 50msec/ step 25msec/ step 5msec/ step 2.5msec/ step 1 100,0 255 100,0 255 0,00s 0,00s 0,000s 0,000s 2 75,3 192 87,8 224 0,05 s 0,03s 0,005s 0,003s 3 56,5 144 76,9 196 0,10 s 0,05s 0,010s 0,005s 4 42,4 108 67,5 172 0,15 s 0,08s 0,015s 0,008s 5 31,8 81 59,2 151 0,20s 0,10s 0,020s 0,010s 6 23,9 61 52,2 133 0,25s 0,13s 0,025s 0,013s 7 18,0 46 45,9 117 0,30s 0,15s 0,030s 0,015s 8 13,7 35 40,4 103 0,35s 0,18s 0,035s 0,018s 9 10,6 27 35,7 91 0,40s 0,20s 0,040s 0,020s 10 8,2 21 31,4 80 0,45s 0,23s 0,045s 0,023s 11 6,3 16 27,5 70 0,50s 0,25s 0,050s 0,025s ! " # $ % $& % ' ( ( )! as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 42 - 80 as3675 datasheet - detailed description 12 4,7 12 24,3 62 0,55s 0,28s 0,055s 0,028s 13 3,5 9 21,6 55 0,60s 0,30s 0,060s 0,030s 14 2,7 7 19,2 49 0,65s 0,33s 0,065s 0,033s 15 2,4 6 16,9 43 0,70s 0,35s 0,070s 0,035s 16 2,0 5 14,9 38 0,75s 0,38s 0,075s 0,038s 17 1,6 4 13,3 34 0,80s 0,40s 0,080s 0,040s 18 1,2 3 11,8 30 0,85s 0,43s 0,085s 0,043s 19 0,8 2 10,6 27 0,90s 0,45s 0,090s 0,045s 20 0,4 1 9,4 24 0,95s 0,48s 0,095s 0,048s 21 0,0 0 8,2 21 1,00s 0,50s 0,100s 0,050s 22 7,5 19 1,05s 0,53s 0,105s 0,053s 23 6,7 17 1,10s 0,55s 0,110s 0,055s 24 5,9 15 1,15s 0,58s 0,115s 0,058s 25 5,5 14 1,20s 0,60s 0,120s 0,060s 26 5,1 13 1,25s 0,63s 0,125s 0,063s 27 4,7 12 1,30s 0,65s 0,130s 0,065s 28 4,3 11 1,35s 0,68s 0,135s 0,068s 29 3,9 10 1,40s 0,70s 0,140s 0,070s 30 3,5 9 1,45s 0,73s 0,145s 0,073s 31 3,1 8 1,50s 0,75s 0,150s 0,075s 32 2,7 7 1,55s 0,78s 0,155s 0,078s 33 2,4 6 1,60s 0,80s 0,160s 0,080s 34 2,0 5 1,65s 0,83s 0,165s 0,083s 35 1,6 4 1,70s 0,85s 0,170s 0,085s 36 1,2 3 1,75s 0,88s 0,175s 0,088s 37 0,8 2 1,80s 0,90s 0,180s 0,090s 38 0,4 1 1,85s 0,93s 0,185s 0,093s 39 0,0 0 1,90s 0,95s 0,190s 0,095s table 56. pwm dimming table decrease by 1/4th every step decrease by 1/8th every step seconds seconds seconds seconds step %dimming pwm %dimming pwm 50msec/ step 25msec/ step 5msec/ step 2.5msec/ step ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 43 - 80 as3675 datasheet - detailed description pwm generator registers table 57. pwm control register addr: 16h pwm control this register controls pwm generator bit bit name default access description 2:1 pwm_dim_mode 00b r/w selects the dimming mode 00b no dimming; actual c ontent of register pwm_code is used for pwm generator 01b logarithmic up dimming (codes are increased). start value is actual pwm_code 10b logarithmic down dimming (codes are decreased). start value is actual pwm_code ; switch off the dimmed current source after dimming is finished to avoid unnecessary quiescent current 11b na 5:3 pwm_dim_speed 000b r/w defines dimming speed by increase/decrease pwm_code 000b by 1/4 th every 50 msec (total dim time 1.0s) 001b by 1/8 th every 50 msec (total dim time 1.9s) 010b by 1/4 th every 25 msec (total dim time 0.5s) 011b by 1/8 th every 25 msec (total dim time 0.95s) 100b by 1/4 th every 5 msec (total dim time 100ms) 101b by 1/8 th every 5 msec (total dim time 190ms) 110b by 1/4 th every 2.5 msec (total dim time 50ms) 111b by 1/8 th every 2.5 msec (total dim time 95ms) table 58. pwm code register addr: 17h pwm code this register controls the pwm code. bit bit name default access description 7:0 pwm_code 00b r/w selects the pwm code 00h 0% duty cycle .... .... ffh 100% duty cycle ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 44 - 80 as3675 datasheet - detailed description table 59. adder current 1 register addr: 30h adder current 1 this register defines the current wh ich can be added to curr1, curr30, curr41, rgb1 bit bit name default access description 7:0 adder_current1 00b r/w selects the added current value ? do not exceed together with currx_current the internal 8 bit range (see text) 00h 0 (represents 0ma) .... .... ffh 255 (represents 38.25ma) table 60. adder current 2 register addr: 31h adder current 2 this register defines the current wh ich can be added to curr2, curr31, curr42, rgb2 bit bit name default access description 7:0 adder_current2 00b r/w selects the added current value ? do not exceed together with currx_current the internal 8 bit range (see text) 00h 0 (represents 0ma) .... .... ffh 255 (represents 38.25ma) table 61. adder current 3 register addr: 32h adder current 3 this register defines the current wh ich can be added to curr6, curr32, curr43, rgb3 bit bit name default access description 7:0 adder_current3 00b r/w selects the added current value ? do not exceed together with currx_current the internal 8 bit range (see text) 00h 0 (represents 0ma) .... .... ffh 255 (represents 38.25ma) table 62. adder current 4 register addr: 52h adder current 4 this register defines the current which can be added to curr33 bit bit name default access description 7:0 adder_current4 00b r/w selects the added current value ? do not exceed together with currx_current the internal 8 bit range (see text) 00h 0 (represents 0ma) .... .... ffh 255 (represents 38.25ma) ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 45 - 80 as3675 datasheet - detailed description table 63. adder enable 1 register addr: 33h adder enable 1 enables the adder circuit for the selected current sources bit bit name default access description 0 rgb1_adder 0r/w enables adder circuit for current source rgb1 0 normal operation of the current source 1 adder_current1 gets added to the current source current 1 rgb2_adder 0r/w enables adder circuit for current source rgb2 0 normal operation of the current source 1 adder_current2 gets added to the current source current 2 rgb3_adder 0r/w enables adder circuit for current source rgb3 0 normal operation of the current source 1 adder_current3 gets added to the current source current 3 curr41_adder 0r/w enables adder circuit for current source curr41 0 normal operation of the current source 1 adder_current1 gets added to the current source current 4 curr42_adder 0r/w enables adder circuit for current source curr42 0 normal operation of the current source 1 adder_current2 gets added to the current source current 5 curr43_adder 0r/w enables adder circuit for current source curr43 normal operation of the current source adder_current3 gets added to the current source current table 64. adder enable 2 register addr: 34h adder enable 2 enables the adder circuit for the selected current sources bit bit name default access description 0 curr1_adder 0r/w enables adder circuit for current source curr1 0 normal operation of the current source 1 adder_current1 gets added to the current source current 1 curr2_adder 0r/w enables adder circuit for current source curr2 0 normal operation of the current source 1 adder_current2 gets added to the current source current 2 curr6_adder 0r/w enables adder circuit for current source curr6 0 normal operation of the current source 1 adder_current3 gets added to the current source current ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 46 - 80 as3675 datasheet - detailed description 3 curr30_adder 0r/w enables adder circuit for current source curr30 0 normal operation of the current source 1 adder_current1 gets added to the current source current 4 curr31_adder 0r/w enables adder circuit for current source curr31 0 normal operation of the current source 1 adder_current2 gets added to the current source current 5 curr32_adder 0r/w enables adder circuit for current source curr32 0 normal operation of the current source 1 adder_current3 gets added to the current source current 6 curr33_adder 0r/w enables adder circuit for current source curr33 0 normal operation of the current source 1 adder_current4 gets added to the current source current table 65. subtract enable register addr: 35h subtract enable enable the inversion from the signal from the pwm generator bit bit name default access description 0 sub_en1 0r/w inverts the signal from the pwm generator 0 direct operation (no inversion) 1 the signal from the pwm generator for which the adder is enabled ( curr1_adder = 1, curr30_adder = 1, rgb1_adder = 1, curr41_adder = 1) is inverted 1 sub_en2 0r/w inverts the signal from the pwm generator 0 direct operation (no inversion) 1 the signal from the pwm generator for which the adder is enabled ( curr2_adder = 1, curr31_adder = 1, rgb2_adder = 1, curr42_adder = 1) is inverted 2 sub_en3 0r/w inverts the signal from the pwm generator 0 direct operation (no inversion) 1 the signal from the pwm generator for which the adder is enabled ( curr6_adder = 1, curr32_adder = 1, rgb3_adder = 1, curr43_adder = 1) is inverted table 64. adder enable 2 register (continued) addr: 34h adder enable 2 enables the adder circuit for the selected current sources bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 47 - 80 as3675 datasheet - detailed description 8.5 general purpo se input / output the gpio is a highly-configurable general purpose input/outp ut pin which can be used for the following functionality: digital schmitt trigger input digital output with 4ma driving ca pability at 2.8v supply (vana) tristate output analog input to the adc default mode for gpio and vana/gpi is input (pull-down) figure 24. gpio and vana/gpi blockdiagram 8.5.1 unused gpio pin if the pin gpio is not used, they can be left open (an inte rnal pulldown, which is enabled by default, will pull them to gnd). 3 sub_en4 0r/w inverts the signal from the pwm generator 0 direct operation (no inversion) 1 the signal from the pwm generator for which the adder is enabled ( curr33_adder = 1) is inverted table 66. gpio pin function summary gpio pin configuration additional function gpio digital input, totem-pol e output (push/pull), open drain (pmos or nmos), high-z, pull- down or pull-up resistor adc input vana/gpi digital input adc input, ldo output table 65. subtract enable register (continued) addr: 35h subtract enable enable the inversion from the signal from the pwm generator bit bit name default access description * * !"# $% &&'( )*+ ,,+- ,+"#. $ ,/.0.,1 /.0 /.0.,1 $ /.0 /.0 /.0., /.01 +/.02+1% +/.0.,1 /.01% +/.02+1%% +/.0.,1 23 &0 "# "# 4 /.050 as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 48 - 80 as3675 datasheet - detailed description 8.5.2 gpio characteristics 8.5.3 gpio registers table 67. gpio dc characteristics symbol parameter condition min typ max unit rpull pull up/pull down resistance enabled by gpio_pulls 30 75 k vgpio supply voltage =vana/gpi 1.5 3.4 v v ih high level input voltage 0.7vana min. 1.75v v v il low level input voltage 0.3 vana min. 0.75v v v hys hysteresis 0.1 vana min. 250mv v i leak input leakage current to v2_5 or vana/gpi and vss -5 5 a v oh high level output voltage at iout 0.8vana v v ol low level output voltage at iout 0.2 vana v i out driving capability vana/gpi = 2.8v, gpio_low_curr = 1 4 ma vana/gpi = 2.8v, gpio_low_curr = 0 16 c load capacitive load 50 pf table 68. gpio output 1 register addr: 05h gpio output 1 this register controls gpio outputs. bit bit name default access description 0 gpi_curr1_en 0r/w enables the curr1 input 0 input disabled 1 input enabled 1 gpi_curr2_en 0r/w enables the curr2 input 0 input disabled 1 input enabled 2 gpi_curr6_en 0r/w enables the curr6 input 0 input disabled 1 input enabled 3 not used 4 gpi_curr30_en 0r/w enables the curr30 input 0 input disabled 1 input enabled ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 49 - 80 as3675 datasheet - detailed description 5 gpi_curr31_en 0r/w enables the curr31 input 0 input disabled 1 input enabled 6 gpi_curr32_en 0r/w enables the curr32 input 0 input disabled 1 input enabled 7 gpi_curr33_en 0r/w enables the curr33 input 0 input disabled 1 input enabled table 69. gpio signal 1 register addr: 06h gpio signal 1 this register controls gpio outputs. bit bit name default access description 0 gpi_curr1_in n/a r reads a logic signal from pin curr1; if gpi_curr1_en =1 1 gpi_curr2_in n/a r reads a logic signal from pin curr2; if gpi_curr2_en =1 2 gpi_curr6_in n/a r reads a logic signal from pin curr6; if gpi_curr6_en =1 3 n/a not used 4 gpi_curr30_in n/a r reads a logic signal from pin curr30; if gpi_curr30_en =1 5 gpi_curr31_in n/a r reads a logic signal from pin curr31; if gpi_curr31_en =1 6 gpi_curr32_in n/a r reads a logic signal from pin curr32; if gpi_curr32_en =1 7 gpi_curr33_in n/a r reads a logic signal from pin curr33; if gpi_curr33_en =1 table 70. gpio output 2 register addr: 50h gpio output 2 this register controls gpio outputs. bit bit name default access description 0 gpio_out 0r/w writes a logic signal to pin gpio; this is independent of any other bit setting e.g., gpio_mode table 72 . 1 gpi_en 0r/w enables the vana/gpi input 0 input disabled 1 input enabled 2 gpi_rgb1_en 0r/w enables the rgb1 input 0 input disabled 1 input enabled 3 gpi_rgb2_en 0r/w enables the rgb2 input 0 input disabled 1 input enabled table 68. gpio output 1 register (continued) addr: 05h gpio output 1 this register controls gpio outputs. bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 50 - 80 as3675 datasheet - detailed description 4 gpi_rgb3_en 0r/w enables the rgb3 input 0 input disabled 1 input enabled 5 gpi_curr41_en 0r/w enables the curr41 input 0 input disabled 1 input enabled 6 gpi_curr42_en 0r/w enables the curr42 input 0 input disabled 1 input enabled 7 gpi_curr43_en 0r/w enables the curr43 input 0 input disabled 1 input enabled table 71. gpio signal 2 register addr: 51h gpio signal 2 this register controls gpio outputs. bit bit name default access description 0 gpio _in n/a r reads a logic signal from pin gpio; this is independent of any other setting e.g., table 72 except gpio_pulls =11 1 gpi_ in n/a r reads a logic signal from pin vana/gpi; if gpi_en =1 2 gpi_rgb1_in n/a r reads a logic signal from pin rgb1; if gpi_rgb1_en =1 3 gpi_rgb2_in n/a r reads a logic signal from pin rgb2; if gpi_rgb2_en =1 4 gpi_rgb3_in n/a r reads a logic signal from pin rgb3; if gpi_rgb3_en =1 5 gpi_curr41_in n/a r reads a logic signal from pin curr41; if gpi_curr41_en =1 6 gpi_curr42_in n/a r reads a logic signal from pin curr42; if gpi_curr42_en =1 7 gpi_curr43_in n/a r reads a logic signal from pin curr43; if gpi_curr43_en =1 table 72. gpio control register addr: 1eh gpio control this register controls gpio and gpio1 pin functions. bit bit name default access description 1:0 gpio_mode 00 r/w defines the direction for pin gpio 00 input only 01 output (push and pull) 10 output (open drain, on ly push; only nmos is active) 11 output (open drain, only pull; only pmos is active) table 70. gpio output 2 register (continued) addr: 50h gpio output 2 this register controls gpio outputs. bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 51 - 80 as3675 datasheet - detailed description 3:2 gpio_pulls 01 r/w adds the following pullup/pulldown to pin gpio; this is independent of setting of bits gpio_mode 00 none 01 pulldown 10 pullup 11 adc input ( gpio_mode = xx); recommended for analog signals table 73. gpio driving cap register addr: 20h gpio driving cap this register enables low current mode for gpios. bit bit name default access description 0 gpio_low_curr 0r/w defines the driving capability of pin gpio 0iout 1 iout /4 table 72. gpio control register (continued) addr: 1eh gpio control this register controls gpio and gpio1 pin functions. bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 52 - 80 as3675 datasheet - detailed description 8.6 led test figure 25. led function testing the as3675 supports the verification of the functionality of all the connected leds (open and shorted leds can be detected). this feature is especially useful in production te st to verify the correct assemb ly of the leds, all its connec- tors and cables. it can also be used in the field to verify if any of the leds is dam aged. a damaged led can then be disabled (to avoid unnecessary currents). the current sources, charge pump, dcdc c onverter and the internal adc are used to verify the forward voltage of the leds. if this forward voltage is within the specified limits of the leds, the external circuitry is assumed to operate. 8.6.1 function testing for single le ds connected to the charge pump for any current source connected to the charge pump (curr30-33) where only one led is connected between the charge pump and the current sink (see figure 1) use: table 74. function testing for leds connected to the charge pump step action example code 1 switch on the charge pump and set it into manual 1:2 mode (to avoid automatic mode switching during measurements) reg 23h 14h ( cp_mode = 1:2, manual) reg 00h 04h ( cp_on = 1) 2 switch on the current sink for the led to be tested e.g. for register curr31set to 9ma use reg 10h 0fh ( curr3x_other = 9ma) reg 03h 0ch ( curr31_mode = curr31_other) 3 measure with the adc the voltage on cpout reg 26h 95h ( adc_select =cpout,start adc) fetch the adc result from reg 27h and 28h 4 measure with the adc the voltage on the switched on current sink reg 26h 8bh ( adc_select =curr31,start adc) fetch the adc result from reg 27h and 28h 5 switch off the current sink for the led to be tested reg 03h 00h ( curr31_mode = off) 6 compare the difference between the adc measurements (which is the actual voltage across the tested led) against the specification limits of the tested led calculation performed in baseband uprocessor ! "# $%& $ ''' ( ! ! ) * ''' as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 53 - 80 as3675 datasheet - detailed description 8.6.2 function testing for leds connected to the step up dcdc converter for leds connected to the dcdc converter (usually current sinks curr1,curr2 and curr6) use the following pro- cedure: note: with the above described procedures electrically open and shorted leds can be automatically detected 7 do the same procedure for the next led starting from point 2 jump to 2. if not all the leds have been tested 8 switch off the charge pump set charge pump automatic mode reg 00h 00h ( cp_on = 0) reg 23h 00h table 75. function testing for le ds connected to the dcdc converter step action example code 1 switch on the current sink for the led string to be tested (curr1,2 or 6) e.g. test leds on curr1: reg 01h 01h ( curr1_mode =on) reg 09h 3ch ( curr1_current = 9ma) 2 select the feedback path for the led string to be tested (e.g. step_up_fb = 01 for led string on curr1) reg 21h 02h ( step_up_fb =curr1) 3 set the current for step_up_vtuning exactly above the maximum forward voltage of the tested led string + 0.6v (for the current sink) + 0.25v; add 6% margin (accuracy of step_up_vtuning ); this sets the maximum output voltage limit for the dcdc converter e.g. 4 leds with ufmax = 4.1v gives 17.25v +6% = 18.29v; if r2=1m and r3 = open, then select step_up_vtuning = 18 (reg 21h 92h; results in 19.25v over voltage protection voltage ? table 9 on page 14 ) 4set step_up_prot = 1 reg 22h 04h 5 switch on the dcdc converter reg 00h 08h 6 wait 80ms (dcdc_fb settling time) 7 measure the voltage on dcdc_fb (adc) reg 26h 96h ( adc_select =dcdc_fb, start adc; fetch the adc result from reg 27h and 28h) 8 if the voltage on dcdc_fb is above 1.0v, the tested led string is broken ? then skip the following steps (code >199h) 9 switch off the over voltage protection ( step_up_prot =0) reg 22h 00h 10 reduce step_up_vtuning step by step until the measured voltage on dcdc_fb (adc) is above 1.0v. after changing step_up_vtuning always wait 80ms, before ad-conversion e.g.: reg 21h 62h ( step_up_vtuning =12): adc result=1,602v 11 measure voltage on dcdc_fb e.g. dcdc_fb=1.602v 12 switch off the dcdc converter reg 00h 00h 13 the voltage on the led string can be calculated now as follows (r4 = open): vled string = v(dcdc_fb) + i( step_up_vtuning ) * r2 ? 0.5v (current sinks feedback voltage: v fb2 ). v(dcdc_fb) = adc measurement from point 11 i( step_up_vtuning ) = last setting used for point 10 e.g.: v led = (1.602v + 12v ? 0.5v) / 4 = 3.276v 14 compare the calculated value against the specification limits of the tested leds table 74. function testing for leds connected to the charge pump step action example code ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 54 - 80 as3675 datasheet - detailed description 8.7 analog-to-digital converter the as3675 has a built-in 10-bit successive approximation analog-to-digital converter (adc). it is internally supplied by v2_5, which is also the full-scale input range (0v defines the adc zero-code). for input signals exceeding v2_5 (typ. 2.5v) a resistor divider with a gain of 0.4 (ratioprescaler) is used to scal e the input of the adc converter. conse- quently the resolution is: the junction temperature (t junction ) can be calculated with the following formula (adc temp_code is the adc conver- sion result for channel 04h selected by register adc_select = 000100b): t junction [ c] = adc toffset - adc tc adc temp_code (eq 5) table 76. adc input ranges, compliances and resolution channels (pins) input range v lsb note dcdc_fb, gpio, audio_in, vana/ gpi, audio controlled led buffer output 0v-2.5v 2.44mv v lsb =2.5/1024 adc temp_code -30c to 125c 1 / adc tc junction temperature curr30-33, curr4x, rgbx vbat, cpout 0v-5.5v 6.1mv v lsb =2.5/1024 * 1/0.4; internal resistor divider used curr1, curr2, curr6 0v-1.0v 2.44mv v lsb =2.5/1024 table 77. adc parameters symbol parameter condition min typ max unit resolution 10 bit v in input voltage range v supply = v2_5 vss see ta b l e 76 v dnl differential non- linearity 0.25 lsb inl integral non-linearity 0.5 lsb vos input offset voltage 0.25 lsb rin input impedance 100 m cin input capacitance 9 pf v supply (v2_5) power supply range 2%, internally trimmed. 2.5 v idd power supply current during conversion only. 500 a idd power down current 100 na t tol temperature sensor accuracy @ 25 c-10+10 c adc toffset adc temperature measurement offset value 375 c adc tc code temperature coefficient temperature change per adc lsb 1.293 9 c/ code ratio prescale r ratio of prescaler for all low voltage current sinks, cpout and vbat 0.4 transient paramete rs (2.5v, 25 oc) tc conversion time all signals are internally generated and triggered by start_conversion 27 s fc clock frequency 1.0 mhz ts settling time of s&h 16 s ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 55 - 80 as3675 datasheet - detailed description adc registers table 78. adc_msb result register addr: 27h adc_msb result together with register 27h, this regist er contains the results (msb) of an adc cycle. bit bit name default access description 6:0 d9:d3 n/a r adc results register. 7 result_not_ready n/a r indicates end of adc conversion cycle 0 result is ready 1 conversion is running table 79. adc_lsb result register addr: 28h adc_lsb result together with register 28h, this register contains the results (lsb) of an adc cycle bit bit name default access description 2:0 d2:d0 n/a r adc result register ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 56 - 80 as3675 datasheet - detailed description table 80. adc_control register addr: 26h adc_control this register input source sele ction and initialization of adc bit bit name default access description 5:0 adc_select 1 03h r/w selects input source as adc input 000000 (00h) audio_in 000001 (01h) vana/gpi 000010 (02h) gpio 000011 (03h) audio controlled led buffer output 000100 (04h) reserved 000101 (05h) rgb1 000110 (06h) rgb2 000111 (07h) rgb3 001000 (08h) curr1 001001 (09h) curr2 001010 (0ah) curr30 001011 (0bh) curr31 001100 (0ch) curr32 001101 (0dh) curr33 001110 (0eh) curr41 001111 (0fh) curr42 010000 (10h) curr43 010001 (11h) reserved 010010 (12h) reserved 010011 (13h) curr6 010100 (14h) vbat 010101 (15h) cpout 010110 (16h) dcdc_fb 010111 (17h) adc temp_code (junction temperature) 011xxx, 1xxxxx reserved 6 na 7 start_conversion n/a w writing a 1 into this bit starts one adc conversion cycle. 1. see table table 76 for adc ranges and resultion. ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 57 - 80 as3675 datasheet - detailed description figure 26. adc circuit 8.8 audio controlled leds up to four rgb leds and/or up to 13 leds (number of le ds is fully configurable) can be controlled by an audio source (connected to the pin audio_in). the audio controlled led block can operate in two modes: amplitude mode: the color of the rgb le d(s) or the brightness of the single color led(s) is depending on the input amplitude. for the rgb leds it starts from black transitions to blue, green, cyan, yellow, red and for high amplitudes white is used (internal lookup table if audio_color =000b). frequency mode: three internal fully configurable filters define the brightness of the single color led(s) or the color of the rgb led(s). each of the filters ca n be configured individually in amplitude, frequency response and type (lowpass filter, bandpass filt er, highpass filter). ++++ !"# $%& %& ' '' ( ' ' ) * ** *! +,- .)/0 . ' . . 1' 1 1 2 3.)/ /0/2 *45 66# as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 58 - 80 as3675 datasheet - detailed description figure 27. audio controlled led internal circuit the audio controlled led block is enabled if any of the registers curr30_aud_src[1:0] ... curr33_aud_src[1:0] , curr126_aud_on , rgbx_aud_on or curr4x_aud_on not equal zero. the audio input amplifier (enabled by aud_buf_on =1) is used to allow the attenuation (or amplification of the input sig- nal) and has the following parameters: the signal is converted with the adc (if the audio controlled le d is active, the internal adc is continuously running at a sample frequency of 45.4khz. in this case the adc cannot be used for any other purpose). the digital processing converts this signal into 3 channels (ch1, ch2, ch3): table 81. audio input parameters symbol parameter condition min typ max unit v in input voltage range 0 2.5 v rin_min min. input impedance at max. input gain (30db) 20 k @ ! " ! ! ! #$ #$ #$ ! ! ! %& ' ! ! ! ' ( ( ( ! ! ! (& ) $* $ %+ as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 59 - 80 as3675 datasheet - detailed description figure 28. audio controlled led digital processing internal circuit these three output channels (ch1, ch2, ch3) can be r outed to any of the current sources according to figure 27 . the digital processing can be done in two differ ent operating modes (defined by the register bit freq_mode ): 8.8.1 amplitude mode this mode is selected by freq_mode =0. the input amplitude is mapped into different colors for rgb led(s) or brightness for single color led(s). the mapping is controlled by the register audio_color . if audio_color = 000, then the mapping is done as follows: very low amplitudes are mapped to black, for higher amplitudes, the color smoothly transiti ons from blue, green, cyan, yellow, red and eventually to white (for high input amplitudes). ! " " "! #$% & $' ( & # % % %) % %) # * + +!,%*-+-+ + +-+ + , )) ' % as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 60 - 80 as3675 datasheet - detailed description 8.8.2 frequency mode this mode is selected by freq_mode =1. the input signal is frequency filtered by three digital f ilters. the filters ar e 2nd order biquad iir (infinite impulse response filters). each of these filter s has the following structure (sampling fr equency = 45.4khz / internal clock of 1mhz divided by 22): figure 29. audio controlled led frequency filter the mathematical formula for these filters is: y(n) = a0(x(n) + b1 x(n-1) + b2 x(n-2)) ? a1 y(n-1) ? a2 y(n-2) (eq 6) the internal calculation is preformed using 12bits coefficients (state variables (z -1 ) are rounded to 12bit, the output uses 8bits). all coefficients can be set individually for each of the three filters (f ilter1, filter2, filter3). (see audio con- trolled led registers on page 62) , registers filt_type (70h) and registers 71h to 82h. it is recommended to use austri- amicrosystems ?demoboard software? fo r simple control of the filter cutoff frequencies and filter type. note: do not set filter cutoff frequencies below 500hz. 8.8.3 agc the agc (available in amplitude and frequency mode) is used to ?compress? the input signal and to attenuate very low input amplitude signals (this is perform ed to ensure no light output for low signa ls especially for noisy input signals). the agc monitors the input signal amplitude and filters this amplitude with a filter with a short attack time, but a long decay time (decay time depends on the register agc_ctrl ). this amplitude measurement (represented by an integer value from 0 to 15) is then used to amplify or attenuate th e input signal with one of the following amplification ratios (output to input ratio) ? the curve a, b, or c is selected depending on the register agc_ctrl : ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 61 - 80 as3675 datasheet - detailed description figure 30. agc curve a (x-axis: input amplitude, y-axis: output amplitude; actual val ue: gain between output to input) figure 31. agc curve b (x-axis: input amplitude, y-axis: output amplitude; actual val ue: gain between output to input) figure 32. agc curve c (x-axis: input amplitude, y-axis: ou tput amplitude; actual valu e: gain between output to input) ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 62 - 80 as3675 datasheet - detailed description 8.8.4 audio contro lled led registers table 82. audio control register addr: 46h audio control audio sync mode control bit bit name default access description 0 aud_buf_on 0b r/w audio input buffer enable 0 off; for audio direct input to adc use adc_select = 00h (audio_in) 1 on; set adc_select = 03h (buffer output) 4:2 audio_color 000b r/w audio controlled led color selection (amplitude mode) 000 color scheme defined by lookup table 001-111 single color scheme (b2=r, b1=g, b0=b) 5 freq_mode 0b r/w audio controlled led mode selection 0 amplitude mode 1 frequency mode 7:6 audio_speed 00b r/w audio controlled led persistence time 00 none 01 200ms 10 400ms 11 800ms table 83. audio input register addr: 47h audio input audio sync input control bit bit name default access description 2:0 audio_gain 000b r/w audio input buffer gain control 000 -12db 001 -6db 010 0db 011 +6db 100 +12db 101 +18db 110 +24db 111 +30db ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 63 - 80 as3675 datasheet - detailed description 5:3 agc_ctrl 000b r/w audio input buffer agc function controls agc switching threshold 000 agc off 001 attenuate low amplitude signals otherwise linear response (to remove e.g. noise) 010 agc curve a; slow decay of amplitude detection 011 agc curve a; fast deca y of amplitude detection 100 agc curve b; slow decay of amplitude detection 101 agc curve b; fast deca y of amplitude detection 110 agc curve c; slow decay of amplitude detection 111 agc curve c; fast decay of amplitude detection 6 audio_man_start 1 0b r/w startup control of audio input buffer (used to charge optional external dc blocking capacitor) 0 automatic precharging 300us (if audio_dis_start = 0) 1 continuously precharging (if aud_buf_on = 1) 7 audio_dis_start 2 0b r/w disable startup control of audio input buffer (used to charge optional external dc blocking capacitor) 0 precharging enabled 1 precharging disabled 1. its safe to keep default value 2. its safe to keep default value table 84. audio output register addr: 48h audio output audio sync input control bit bit name default access description 2:0 aud_amplitude 000b r/w led(s) output amplitude cont rol (in percent of selected output current) 000 6.25% 001 12.5% 010 25% 011 50% 100 75% 101 87.5% 110 93.75% 111 100% table 83. audio input register (continued) addr: 47h audio input audio sync input control bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 64 - 80 as3675 datasheet - detailed description 4 curr126_aud_on 0b r/w audio controlled led enable for curr1, curr2, curr6 0off 1 on, audio controlled led is enabled 5 rgbx_aud_on 0b r/w audio controlled led enable for rgb1-rgb3 0o f f 1 on, audio controlled led is enabled 6 curr4x_aud_on 0b r/w audio controlled led enable for curr41-curr43 0o f f 1 on, audio controlled led is enabled table 85. curr3x audio source register addr: 53h curr3x audio source controls curr30,31,32,33 audio outputs and enables audio controlled led bit bit name default access description 1:0 curr30_aud_src[1:0] 00b r/w audio controlled led source for curr30 00 all other modes 01 ch1 connected to curr30, audio controlled led on 10 ch2 connected to curr30, audio controlled led on 11 ch3 connected to curr30, audio controlled led on 3:2 curr31_aud_src[1:0] 00b r/w audio controlled led source for curr31 00 all other modes 01 ch1 connected to curr31, audio controlled led on 10 ch2 connected to curr31, audio controlled led on 11 ch3 connected to curr32, audio controlled led on 5:4 curr32_aud_src[1:0] 00b r/w audio controlled led source for curr32 00 all other modes 01 ch1 connected to curr32, audio controlled led on 10 ch2 connected to curr32, audio controlled led on 11 ch3 connected to curr32, audio controlled led on table 84. audio output register (continued) addr: 48h audio output audio sync input control bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 65 - 80 as3675 datasheet - detailed description registers 71h to 82h define the filter coefficients filt{1,2,3}_ {a0,a1,a2}. each of the coefficients is 12 bits wide and is calculated according to the following formula (2s complement number): - bit11 is used as sign bit 0?positive number, 1?negative number - bit10 is multiplied by 2^0 - bit9 is multiplied by 2^-1 -? - bit 1 is multiplied by 2^-9 7:6 curr33_aud_src[1:0] 00b r/w audio controlled led source for curr33 00 all other modes 01 ch1 connected to curr33, audio controlled led on 10 ch2 connected to curr33, audio controlled led on 11 ch3 connected to curr33, audio controlled led on table 86. filt_type register addr: 70h filt_type define frequency filter types bit bit name default access description 1:0 filt1_type[1:0] 00b r/w defines filter1 (for ch1) characteristics and filter coefficients b1 and b2 00 don?t use 01 low pass filter; filt1_b1=2, filt1_b2=1 10 high pass filter; filt1_b1=-2, filt1_b2=1 11 band pass filter; filt1_b1=0, filt1_b2=-1 3:2 filt2_type[1:0] 00b r/w defines filter2 (for ch2) characteristics and filter coefficients b1 and b2 00 don?t use 01 low pass filter; f ilt2_b1=2, filt2_b2=1 10 high pass filter; filt2_b1=-2, filt2_b2=1 11 band pass filter; filt2_b1=0, filt2_b2=-1 5:4 filt3_type[1:0] 00b r/w defines filter3 (for ch3) characteristics and filter coefficients b1 and b2 00 don?t use 01 low pass filter; f ilt3_b1=2, filt3_b2=1 10 high pass filter; filt3_b1=-2, filt3_b2=1 11 band pass filter; filt3_b1=0, filt3_b2=-1 table 85. curr3x audio source register (continued) addr: 53h curr3x audio source controls curr30,31,32,33 audio outputs and enables audio controlled led bit bit name default access description ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 66 - 80 as3675 datasheet - detailed description - bit 0 is multiplied by 2^-10 8.9 power-on reset the internal reset is controlled by two sources: vbat supply serial interface state (clk, data) the internal reset is forced if vbat is low or if both interface pins (clk, data) are low for more than t por_deb (typ. 100ms) 2 . then device enters shutdown mode. the reset levels control the state of a ll registers. as long as vbat and clk/data are below their reset thresholds, the register contents are set to default. access by serial interface is possible once the reset thresholds are exceeded. table 87. filter definitions register register definition addr default content name b7 b6 b5 b4 b3 b2 b1 b0 filt1_a0_msb 71h 00h filt1_a0[11:8] filt1_a0_lsb 72h 00h filt1_a0[7:0] filt1_a1_msb 73h 00h filt1_a1[11:8] filt1_a1_lsb 74h 00h filt1_a1[7:0] filt1_a2_msb 75h 00h filt1_a2[11:8] filt1_a2_lsb 76h 00h filt1_a2 [7:0] filt2_a0_msb 77h 00h filt2_a0[11:8] filt2_a0_lsb 78h 00h filt2_a0[7:0] filt2_a1_msb 79h 00h filt2_a1[11:8] filt2_a1_lsb 7ah 00h filt2_a1[7:0] filt2_a2_msb 7bh 00h filt2_a2[11:8] filt2_a2_lsb 7ch 00h filt2_a2 [7:0] filt3_a0_msb 7dh 00h filt3_a0[11:8] filt3_a0_lsb 7eh 00h filt3_a0[7:0] filt3_a1_msb 7fh 00h filt3_a1[11:8] filt3_a1_lsb 80h 00h filt3_a1[7:0] filt3_a2_msb 81h 00h filt3_a2[11:8] filt3_a2_lsb 82h 00h filt3_a2[7:0] 2. only if shutdwn_enab =1 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 67 - 80 as3675 datasheet - detailed description figure 33. zero power device wakeup block diagram 8.9.1 reset control register 8.10 temperature supervision an integrated temperature sensor provides over-temperature protection for the as3675. this sensor generates a flag if the device temperature reaches the overtemperature threshold of 140o. the threshold has a hysteresis to prevent oscillation effects. table 88. audio input parameters symbol parameter condition min typ max unit v por_vbat overall power-on reset monitor voltage on v2_5; power-on reset for all internal functions. 1.8 2.15 2.4 1 1. guaranteed by design - min./max. limits not production tested v v por_peri reset level for pins clk, data monitor voltage on pins clk, data 0.29 1.0 1.38 v t por_deb reset debounce time for pins clk, data 80 100 120 ms t start interface startup time 4 6 8 ms table 89. overtemp control register addr: 29h overtemp control this register reads and resets the overtemperature flag. bit bit name default access description 4 shutdwn_enab 0r/w enable shutdown mode and serial interface reset. 0 serial interface reset disabled. device does not enter shutdown mode 1 serial interface reset enabled, device enters shutdown when scl and sda remain low for min. 120ms !"# $ %&" ' '%( '( " ) )% )% # % ' * $ + , * $ , % %&" ' , * $ * $ , as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 68 - 80 as3675 datasheet - detailed description if the device temperature exceeds the t 140 threshold all current sources, the ch arge pump and the dcdc converter is disabled and the ov_temp flag is set. after decreasing the temperature by t hyst operation is resumed. the ov_temp flag can only be reset by first wr iting a 1 and then a 0 to the register bit rst_ov_temp . bit ov_temp_on = 1 activates temperature supervision table 91 . it is recommend to leave this bit set (default state). 8.11 serial interface the as3675 is controlled using serial interface pins clk and data: figure 34. serial interface block diagram table 90. overtemp erature detection symbol parameter condition min typ max unit t 140 ov_temp rising threshold 140 oc t hyst ov_temp hysteresis 5 oc table 91. overtemp control register addr: 29h overtemp control this register reads and resets the overtemperature flag. bit bit name default access description 0 ov_temp_on 1w activates/deactivates devic e temperature supervision. default: off - all other bits are on ly valid if this bit is set to 1 0 temperature supervision is disabled. no reset will be generated if the device temperature exceeds 140oc 1 temperature supervision is enabled 1 ov_temp n/a r 1 indicates that the overtemperature threshold has been reached; this flag is not cleared by an overtemperature reset. it has to be cleared using rst_ov_temp 2 rst_ov_temp 0r/w the ov_temp flag is cleared by first setting this bit to 1, and then setting this bit to 0. - as3675 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 69 - 80 as3675 datasheet - detailed description the clock line clk is never held low by the as3675 (as the as3675 does not use clock stretching of the bus). the as3675 is compatible to the nxp two wire specification http://www.nxp.com/acr obat_download/literature/9398/ 39340011.pdf, version 2.1, january 200 0 for standard and fast mode (no high speed mode) with the following excep- tion: data set-up time for fast mode: t su;dat =250ns (instead of 100ns from table 5, p32) 8.11.1 serial interface features fast mode capability (maximum clock frequency is 400 khz) 7-bit addressing mode write formats - single-byte write - page-write read formats - current-address read - random-read - sequential-read data input delay and clk spike filtering by integrated rc components 8.11.2 device address selection the serial interface address of the as3675 has the following address: 80 h ? write commands 81 h ? read commands figure 35. complete serial data transfer serial data transfer formats table 92. serial interface timing symbol parameter condition min typ max unit v ihi/f high level input voltage pins data and clk 1.38 vbat v v ili/f low level input voltage 0.0 0.52 v v hysti/f hysteresis 0.1 v t rise rise time 0 1000 ns t fall fall time 0 300 ns t clk_filter spike filter on clk 100 ns t data_filter spike filter on data 300 ns s start condition address r/w ack data ack data ack stop condition p data clk 1-7 8 9 1-7 89 1-7 8 9 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 70 - 80 as3675 datasheet - detailed description definitions used in the serial data transfer format diagrams are listed in the following table: figure 36. serial interface byte write figure 37. serial interface page write byte write and page write formats are used to write data to the slave. the transmission begins with the start condition, which is generated by the master when the bus is in idle state (the bus is free). the device-write address is followed by the word address. after the word address any number of data bytes can be sent to the slave. the word address is increm ented internally, in order to write subsequent data bytes on subsequent address locations. for reading data from the slave device, the master has to change the transfer direction. this can be done either with a repeated start condition followed by the device-read address, or simply with a new transmission start followed by the device-read address, when the bus is in idle state. th e device-read address is always followed by the 1st register byte transmitted from the slave. in re ad mode any number of subsequent regist er bytes can be read from the slave. the word address is incremented internally. the following diagrams show the serial read formats supported by the as3675. figure 38. serial interface random read table 93. serial data transfer byte definitions symbol definition r/w (as3675 slave) note s start condition after stop r 1 bit sr repeated start r 1 bit dw device address for write r 10000000b (80 h ). dr device address for read r 10000001b (81 h ) wa word address r 8 bits a acknowledge w 1 bit n not acknowledge r 1 bit reg_data register data/write r 8 bits data (n) register data/read r 1 bit p stop condition r 8 bits wa++ increment word address internally r during acknowledge s dw a wa a reg_data a p write register wa++ as3675 (= slave) receives data as3675 (= slave) transmits data s dw a wa a reg_data 1 a reg_data 2 a ? reg_data n a p write register wa++ write register wa++ write register wa++ as3675 (= slave) receives data as3675 (= slave) transmits data s dw a wa a sr dr a data n p read register wa++ as3675 (= slave) receives data as3675 (= slave) transmits data ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 71 - 80 as3675 datasheet - detailed description random read and sequential read are combined formats. the repeated start condition is used to change the direction after the data transfer from the master. the word address transfer is initiated with a start condition issued by the master while the bus is idle. the start condition is followed by the device-write address and the word address. in order to change the data direction a repeated start cond ition is issued on the 1st clkpulse after the acknowl- edge bit of the word address transfer. after the reception of the device-read address, the slave becomes the transmit- ter. in this state the slave transmits register data locate d by the previous received word address vector. the master responds to the data byte with a not acknowledge, and issues a stop condition on the bus. figure 39. serial interface sequential read sequential read is the extended form of random read, as multiple register-d ata bytes are subsequently transferred. in contrast to the random read, in a sequential read th e transferred register-data bytes are responded by an acknowl- edge from the master. the number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). to terminate the transmission the master has to send a not acknowledge following the last data byte and subsequently generate the stop condition. figure 40. serial interface current address read to keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. the bus is idle and the ma ster issues a start condition followed by the device-read address. analogous to random read, a single byte transfer is te rminated with a not acknowledge after the 1st register byte. analogous to sequential read an unl imited number of data bytes can be tran sferred, where the data bytes must be responded to with an acknowledge from the master. for termination of the transmission the master sends a not acknowledge following the last data byte and a sub- sequent stop condition. 8.12 operating modes if the voltage on clk and data is less than 1v (for > t por_deb ), the as3675 is in shutdown mode and its current con- sumption is minimized (i bat = i shutdown ) and all internal registers are reset to their default values. if the voltage at clk or data rises above 1v, the as3675 serial interface is enabled and the as3675 and the standby mode is selected. the as3675 is switc hed automatically from standby mode (i bat = i stanby ) into normal mode (i bat = i active ) and back, if one of the following blocks are activated: charge pump step up regulator any current sink adc conversion started pwm active pattern mode active. if any of these blocks are already switched on the internal o scillator is running and a write instruction to the registers is directly evaluated within 1 internal clk cycle (typ. 1s) s dw a wa a sr dr a data 1 a data 2 as3675 (= slave) receives data as3675 (= slave) transmits data ... a data n n p read register wa++ s dr a data 1 a data 2 ? a data n n p read register wa++ read register wa++ read register wa++ read register wa++ as3675 (= slave) receives data as3675 (= slave) transmits data ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 72 - 80 as3675 datasheet - detailed description if all these blocks are disabled, a write instruction to enable these blocks is delayed by 64 clk cycles (oscillator will startup, within max 200s). ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 73 - 80 as3675 datasheet - register map 9 register map table 94. registermap register definition addr default content name b7 b6 b5 b4 b3 b2 b1 b0 reg. control 00h 00 ldo_ana _lpo step_up _on cp_on ldo_ana _on curr12 control 01h 00h curr2_mode curr1_mode curr rgb control 02h 00h curr6_mode rgb3_mode rgb2_mode rgb1_mode curr3 control1 03h 00h curr33_mode curr32_mode curr31_mode curr30_mode curr4 control 04h 00h curr43_mode curr42_mode curr41_mode gpio output 1 05h 00h gpi_curr 33_en gpi_curr 32_en gpi_curr 31_en gpi_curr 30_en gpi_curr 6_en gpi_curr 2_en gpi_curr 1_en gpio signal 1 06h 00h gpi_curr 33_in gpi_curr 32_in gpi_curr 31_in gpi_curr 30_in gpi_curr 6_in gpi_curr 2_in gpi_curr 1_in ldo ana1 voltage 07h 00h ldo_ana_voltage curr1 current 09h 00h curr1_current curr2 current 0ah 00h curr2_current rgb1 current 0bh 00h rgb1_current rgb2 current 0ch 00h rgb2_current rgb3 current 0dh 00h rgb3_current curr3x strobe 0eh 00h curr3x_strobe curr3x preview 0fh 00h curr3x_preview curr3x other 10h 00h curr3x_other curr3 strobe control 11h 00h strobe_timing strobe_mode strobe_ctrl curr3 control2 12h 00h strobe_p in curr3x_s trobe_hi gh preview_ctrl preview_ off_after strobe curr41 current 13h 00h curr41_current curr42 current 14h 00h curr42_current curr43 current 15h 00h curr43_current pwm control 16h 00h pwm_dim_speed pwm_dim_mode pwm code 17h 00h pwm_code pattern control 18h 00h curr33_p attern curr32_p attern curr31_p attern curr30_p attern softdim_ pattern p attern_delay pattern_ color pattern data0 19h 00h pattern_data[7:0] pattern data1 1ah 00h pattern_data[15:8]1111 pattern data2 1bh 00h pattern_data[23:16]1111 pattern data3 1ch 00h pattern_data[31:24]1111 gpio control 1eh 44h gpio_pulls gpio_mode gpio driving cap 20h 00h gpio_low _curr ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 74 - 80 as3675 datasheet - register map dcdc control1 21h 00h step_up_vtuning step_up_fb step_up _frequ dcdc control2 22h 04h step_up _fb_auto curr6_pr ot_on curr2_pr ot_on curr1_pr ot_on step up_lowc ur step_up _prot skip_fast step_up _res cp control 23h 00h cp_auto _on cp_start _deboun ce cp_mode_switchin g cp_mode cp_clk cp mode switch1 24h 00h rgb3_on _cp rgb2_on _cp rgb1_on _cp curr33_o n_cp curr32_o n_cp curr31_o n_cp curr30_o n_cp cp mode switch2 25h 00h curr6_on _cp curr43_o n_cp curr42_o n_cp curr41_o n_cp curr2_on _cp curr1_on _cp adc_control 26h 03h start_co nversion adc_on adc_select adc_msb result 27h na result_n ot_ready d9:d3 adc_lsb result 28h na d2:d0 overtemp control 29h 01h shutdwn _enab rst_ov_t emp ov_temp ov_temp _on curr low voltage status1 2ah na curr6_lo w_v rgb3_low _v rgb2_low _v rgb1_low _v curr33_l ow_v curr32_l ow_v curr31_l ow_v curr30_l ow_v curr low voltage status2 2bh na curr43_l ow_v curr42_l ow_v curr41_l ow_v curr2_lo w_v curr1_lo w_v gpio current 2ch 00h pattern_ slow pattern_ delay2 curr6 current 2fh 00h curr6_current adder current 1 30h 00h adder_current1 (can be enabled for curr30, curr1, rgb1, curr41) adder current 2 31h 00h adder_current2 (can be enabled for curr31, curr2, rgb2, curr42) adder current 3 32h 00h adder_current3 (can be enabled for curr32, curr6, rgb3, curr43) adder enable 1 33h 00h curr43_a dder curr42_a dder curr41_a dder rgb3_ad der rgb2_ad der rgb1_ad der adder enable 2 34h 00h curr33_a dder curr32_a dder curr31_a dder curr30_a dder curr6_ad der curr2_ad der curr1_ad der subtract enable 35h 00h sub_en4 sub_en3 sub_en2 sub_en1 asic id1 3eh cbh 1 1 0 0 1 0 1 1 asic id2 3fh 5xh 0 1 0 1 revision curr30 current 40h 00h curr30_current curr31 current 41h 00h curr31_current curr32 current 42h 00h curr32_current curr33 current 43h 00h curr33_current audio control 46h 00h audio_speed freq_mo de audio_color aud_buf _on table 94. registermap register definition addr default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 75 - 80 as3675 datasheet - register map note: if writing to register, write 0 to unused bits write to read only bits will be ignored yellow color = read only audio input 47h 00h audio_di s_start audio_m an_start agc_ctrl audio_gain audio output 48h 00h curr4x_a ud_on rgbx_au d_on curr126_ aud_on aud_amplitude gpio output 2 50h 00h gpi_curr 43_en gpi_curr 42_en gpi_curr 41_en gpi_rgb3 _en gpi_rgb2 _en gpi_rgb1 _en gpi_en gpio_out gpio signal 2 51h 00h gpi_curr 43_in gpi_curr 42_in gpi_curr 41_in gpi_rgb3 _in gpi_rgb2 _in gpi_rgb1 _in gpi_ in gpio _in adder current 4 52h 00h adder_current4 (can be enabled for curr33) curr3x audio source 53h 00h curr33_aud_src[1:0 ] curr32_aud_src[1:0 ] curr31_aud_src[1:0 ] curr30_aud_src[1:0 ] pattern end 54h 00h pattern_ end filt_type 70h 00h filt3_type[1:0] filt2_ty pe[1:0] filt 1_type[1:0] filt1_a0_msb 71h 00h filt1_a0[11:8] filt1_a0_lsb 72h 00h filt1_a0[7:0] filt1_a1_msb 73h 00h filt1_a1[11:8] filt1_a1_lsb 74h 00h filt1_a1[7:0] filt1_a2_msb 75h 00h filt1_a2[11:8] filt1_a2_lsb 76h 00h filt1_a2 [7:0] filt2_a0_msb 77h 00h filt2_a0[11:8] filt2_a0_lsb 78h 00h filt2_a0[7:0] filt2_a1_msb 79h 00h filt2_a1[11:8] filt2_a1_lsb 7ah 00h filt2_a1[7:0] filt2_a2_msb 7bh 00h filt2_a2[11:8] filt2_a2_lsb 7ch 00h filt2_a2 [7:0] filt3_a0_msb 7dh 00h filt3_a0[11:8] filt3_a0_lsb 7eh 00h filt3_a0[7:0] filt3_a1_msb 7fh 00h filt3_a1[11:8] filt3_a1_lsb 80h 00h filt3_a1[7:0] filt3_a2_msb 81h 00h filt3_a2[11:8] filt3_a2_lsb 82h 00h filt3_a2[7:0] table 94. registermap register definition addr default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 76 - 80 as3675 datasheet - external components 10 external components table 95. external components list part number min value typ max tol. (min.) rating (max) notes package (min.) c1 1f 20% 6.3v ceramic, x5r (v2_5 output) (e.g. taiyo yuden jmk105bj105kv-f) 0402 c2 1f 20% 6.3v ceramic, x5r (vbat) (e.g. taiyo yuden jmk105bj105kv- f) 0402 c3 1f 20% 6.3v ceramic, x5r (charge pump) (e.g. taiyo yuden jmk105bj105kv-f) 0402 c4 1f 20% 6.3v ceramic, x5r (charge pump) (e.g. taiyo yuden jmk105bj105kv-f) 0402 c5 2.2f 20% 6.3v ceramic, x5r (charge pump output) (e.g. taiyo yuden jmk107bj225ma-t) 0403 c6 1f 20% 6.3v ceramic, x5r (step up dcdc input) (e.g. taiyo yuden jmk105bj105kv-f) 0402 c7 1.5nf 20% 25v ceramic, x5r (step up dcdc feedback, 150pf for over voltage protection) 0402 c8 15nf 20% 6.3v ceramic, x5r (step up dcdc feedback, 1.5nf for over voltage protection) 0402 c9 4.7f 20% 25v ceramic, x5r, x7r (step up dcdc output) (e.g. taiyo yuden tmk316bj475kg) 3.2x1.6x 1.25mm c10 2.2 f 20% 6.3v ceramic, x5r (vana1 output) (e.g. taiyo yuden jmk107bj225ma-t) only required if ldo is used 0403 r1 100m 5% shunt resistor 0603 r2 1m 1% step up dc/dc converter voltage feedback 0201 r3 100k 1% step up dc/dc converter voltage feedback - not required for over voltage protection 0201 r4 1-10k 1% data pullup resistor ? usually already inside master 0201 r5 clkpullup resistor ? usually already inside master 0201 l1 10h 20% recommended type: murata lqh3npn100nj0, panasonic ellsfg100ma or tdk vlf3012a 3x3x1.2m m q1 (+ d1) fdfma3n109 integrated nmos and schottky diode microfet 2x2mm d2:d14 led as required by application ams ag technical content still valid www.austriamicrosystems. com/as3675 1v3 77 - 80 as3675 datasheet - package drawings and markings 11 package drawings and markings figure 41. wl-csp30 3x2.5mm 6x5 balls package drawing note: line 1: austriamicrosystems logo line 2: 3675 line 3: encode datecode 4 characters figure 42. wl-csp30 3x2.5mm 6x5 balls detail dimensions 3675 |
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