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december 1998 preliminary ml6430/ml6431 * genlocking sync generator with digital audio clock for ntsc, pal & vga 1 general description the ml6430/ml6431 are multi-standard single-chip bicmos video genlock ics for ntsc, pal and vga. they are designed to provide a stable clock from an analog video signal, and to provide timing pulses for clamping, decoding, blanking and processing video signals. the ml6430/ml6431 handle vcr glitches and variations created by head switching, tape dropouts, missing sync pulses, freeze frames, high speed playback and camcorder gyro errors. the ml6430/ml6431 are designed for high noise immunity, insensitivity to varying signal amplitudes, overmodulated color carriers, and sync glitches. advanced analog and digital clock synthesis techniques provide multi-standard and non-standard operation from a single crystal or external asynchronous clock source. pin selectable preset modes allow operation for most video standards in simple stand-alone mode without the necessity of using the serial bus. for more demanding applications, a two wire serial control bus is available for full control of all of the ml6430/ml6431 features. the ml6430/ml6431 are ideal for clock generation in mpeg encoders, high performance display timing, and video editing. features n line locked scalable horizontal pixel clock for an arbitrary number of pixels per line n standard frequencies of 12.27, 13.5, 14.75mhz, or 4fsc n 4 /2 or 2 /1 clock outputs (54 and 27mhz, or 27 and 13.5mhz) and vga clocks n audio clocks: 32, 44.1, or 48khz, locked to video n on-chip sync separator, vco and pulse generator n low clock jitter: short term: <200ps rms locked n line to line: <600ps rms (2.2ns peak-to-peak) locked n fast recovery from vcr head switch, stable for fast shuttle speeds and pause n single crystal or external frequency source n pal, ntsc or vga operation n 2 wire serial control bus, or selectable presets for stand alone operation n rs170a compatible * this part is end of life as of august 1, 2000 block diagram analog pll digital pll pulse and audio clock generator digital phase det. and filtering digital phase mod. crystal osc. xtal in phase detector ? n horiz. pixel counter vert. line counter dyna. state mach. controller v sync c vin/ h sync ? m cv ref v cc sv cc av cc bv cc d c sync locked h reset f reset gnd s gnd a gnd b gnd d sleep /54mhz freerun s clamp b clamp /burst 1x clock/4x clock 2x clock h blank v blank field id audioclk/pherrout* p0 p1 p2/s data p3/s clk nosignal 6 7 8 11 12 3 13 5 10 20 30 16 17 24 25 2 1 32 31 18 19 27 28 22 23 15 29 21 9 4 xtal out signal detect mux sync separator 14 26 ref vco serial control and presets *pherrout is only available in ml6431
ml6430/ml6431 2 pin configuration vblank hreset freset v cc b gnd b 1x clock/4x clock 2x clock field id 1 2 3 4 5 6 7 8 9 10111213141516 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p2/s data p3/s clk sleep /54mhz v cc s gnd s c vin /h sync cv ref v sync v cc a gnd a xtalin xtalout freerun nosignal locked audioclk p1 p0 gnd d v cc d sclamp bclamp/burst c sync hblank top view ml6430 32-pin tqfp (h32-7) vblank hreset freset v cc b gnd b 1x clock/4x clock 2x clock field id 1 2 3 4 5 6 7 8 9 10111213141516 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p2/s data p3/s clk sleep /54mhz v cc s gnd s c vin /h sync cv ref v sync v cc a gnd a xtalin xtalout freerun nosignal locked audioclk/pherrout p1 p0 gnd d v cc d sclamp bclamp/burst c sync hblank top view ml6431 32-pin tqfp (h32-7)
ml6430/ml6431 3 pin name function 1 p2/s data this is a dual function pin. if presets are enabled, refer to table 7. if presets are disabled, serial bus data input. 2 p3/s clk this is a dual function pin. if presets are enabled, refer to table 7. if presets are disabled, serial bus clock input. 3 sleep /54mhz hardware sleep mode: when low, disables entire chip for ultra-low power dissipation. sleep mode can also be enabled/disabled via serial bus (register 8). 54mhz is a clock input. this can be any 4x clock up to 70mhz used for pulse generation. 4v cc s analog supply for sync separator. 5 gnd s analog ground for sync separator. 6cv in /h sync composite video input; video input in typical composite video applications, or y input for yuv applications, or g input for rgb applications with sync on green. for typical vga or other high performance display applica- tions, this input may be supplied with a ttl level h sync signal and the vertical sync input supplied with a ttl level v sync signal. 7cv ref reference voltage for internal sync slicer. the external capacitor is driven by a charge pump to follow the sync tip. 8v sync vertical input for non-composite sources. this input may be supplied with a ttl level v sync signal. for composite inputs this pin is tied high or low. 9v cc a analog supply pin for analog pll. 10 gnd a analog ground for analog pll. 11 xtal in crystal may be parallel tuned 3.58 mhz or 4.43mhz, or may be driven by an external oscillator at these frequencies, or at 4x these frequencies. 12 xtal out crystal drive pin. no connect if using external oscillator or clock. pin name function 13 freerun forces the pll to run at a selected standard without syncing to a video signal. accuracy is 20ppm in freerun with ideal crystal, otherwise locked to video source 14 nosignal indicates video signal activity has not been detected at the composite input. if nosignal = low, this condition does not imply that lock has been established. the nosignal pin can be tied to freerun to create a local loop in which the genlock will not try to lock until a signal is detected at the input. 15 locked indicates when digital pll is locked to incoming video signal. 16 (ml6430) audioclk digital audio clock output. programmable for 32khz, 44.1khz or 48khz output. 16 (ml6431) audioclk/pherrout this is a dual mode pin. pin is selected via serial bus (register 7). audioclk is an audio clock signal (see table 9). pherrout indicates whether incoming hsync is ahead or behind output hsync. 17 field id field flag: odd = 1, even = 0 18 2x clock 2x oversampled pixel clock & output of digital pll. nominal frequency of 27mhz 19 1x clock/4x clock 1x pixel clock. nominal frequency of 13.5mhz or 54mhz 20ppm in freerun with ideal crystal, otherwise locked to video source. pal 4x clock not available (no 4x4.4336mhz clock). 20 gnd b digital ground for output driver buffers. 21 v cc b digital supply for output driver buffers. 22 f reset frame reset; active low for one half line at the high to low transition of field id. in ntsc mode, freset goes low on the high-to-low transition on the field id pin and at the beginning of line 1 (see figure 2). in pal mode, freset goes low on the high-to-low transition on the field id pin and at the end of line 310 (see figure 3). pin description (note: ml6430 and ml6431 pin functions are identical except for pin 16. see below)
ml6430/ml6431 4 pin description (continued) pin name function 23 h reset horizontal reset; active low for one half pixel. 24 v blank vertical blanking, active low 25 h blank horizontal blanking, active low 26 c sync composite sync output. may be either the raw output of sync slicer, or regenerated signal from internal pulse generators. if raw slicer output is selected, then signals disappear when input signal disappears. if regenerated output is selected, then signal is always present regardless of input conditions. preset modes produce regenerated sync. 27 b clamp /burst this is a dual mode pin. user may select either a back porch clamp pulse or a burst gate pulse via the serial control bus. preset is b clamp pulse. pin name function 28 s clamp sync clamp pulse occurs just after leading edge of sync. duration is typically less than 50% of sync pulse to avoid problems with equalizers in the vertical interval, active high. 29 v cc d digital supply pin for digital pll. 30 gnd d digital ground pin for digital pll. 31 p0 this is a three-state pin: low means serial bus is enabled, high or unconnected (high z) means presets are active. refer to table 7. 32 p1 this is a three state pin. refer to table 7. if presets are disabled pin is ignored.
ml6430/ml6431 5 electrical characteristics unless otherwise specified, v cc = 4.5 to 5.5v and t a = 0 to 70c, c in = 0.1f, c ref = 0.1f (note 1). parameter conditions min typ max units supply supply current (analog and digital) 80 120 ma analog supply current v cc a = v cc d = 4.5 35 ma digital supply current max programmed clock rates 45 ma digital inputs low level input voltage 0 0.8 v high level input voltage v cc C 0.8 v cc v low level input current v in = 0v + 0.1v 1.0 a high level input current v in = v cc d C 0.1v 1.0 a input capacitance 2pf ttl inputs (h sync , v sync ) v il input low voltage 0.8 v v ih input high voltage 2.0 v three state digital inputs low level input voltage 0 0.8 v high level input voltage v cc C 0.8 v low level input current v in = 0v 50 150 a high level input current v in = v cc d 50 150 a input capacitance 2pf mid level input voltage with 5v supply 2 3 v digital outputs low level output voltage 0 0.5 v high level output voltage v cc C 0.5 v c load : output capacitance 50 pf output disable leakage 10 a absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. dc supply voltage (v cc a & v cc d) ............. C0.3v to 7v analog & digital inputs/outputs ... C0.3v to v cc a + 0.3v input current per pin ............................................. 25ma storage temperature ............................... C 65c to 150c junction temperature .............................................. 125c operating conditions supply range ............................................... 4.5v to 5.5v temperature range ....................................... 0c to 70c thermal resistance ............................................. 80c/w
ml6430/ml6431 6 genlock performance specifications unless otherwise noted, v in = 1 v pp ntsc test signal for composite inputs, or 100% color bars for component (note 1). see figure 1 for parameter measurement definition parameter conditions min typ max units sync separation min sync amplitude 135 mv max video amplitude 3v clamp timing error ntc7 ac bounce signal (note 2) 10 ns clamp recovery time ntc7 dc bounce signal (note 3) 16 s clock recovery short term output jitter rejection input jitter = 50ns rms C15 db rms residual output clock jitter input jitter <1ns rms 600 ps peak to peak (6 s ), line to line jitter input jitter < 1ns 2.0 2.2 ns head switch recovery time to 1ns error 5s step h change on or before 4 lines line 1 step frequency recovery time to 1ns error 1% step h frequency change on or 12 15 ms before line 1 missing sync sensitivity (note 4) 1.0 ns sync glitch sensitivity (note 5) 1.0 ns 4x clock duty cycle c load = 50pf, f clk4x < 60mhz 40 60 % 2x clock duty cycle c load = 50pf, f clk2x < 30mhz 48 52 % 1x clock duty cycle c load = 50pf, f clk1x < 15mhz 48 52 % clock skew 1x to 2x c load = 50pf, f clk1x < 15mhz 6 ns pulse output rise time c load = 50pf 2 10 ns pulse output fall time c load = 50pf 2 10 ns pulse output setup time c load = 50pf 20 ns pulse output hold time c load = 50pf 20 ns serial bus parameter conditions min typ max units input low level input voltage 0 0.8 v high level input voltage v cc C 0.8 v cc v low level input current v in = 0v 1.0 m a high level input current v in = v cc d 1.0 m a input impedance f clk = 100khz 1 m w input capacitance (c in ) 2pf system timing s clk frequency (f clock ) 100 khz input hysteresis (v hys ) 0.2 v spike suppression (t spike ) max length for zero response 50 ns power setup time to valid data inputs vcc settled to within 1% 10 ms
ml6430/ml6431 7 note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. note 2: parameter is luma dependent. note 3 : reclock time after bounce. note 4 : net phase error for single isolated missing h pulse. note 5 : net phase error for glitch at sync level <50ns. serial bus logic (continued) parameter conditions min typ max units system timing (continued) wait time from stop to start on s data (t wait ) 1.3 s hold time for start on s data (t hd/start ) 0.6 s setup time for start on s data (t su/start ) 0.6 s min low time on s clk (t low ) 1.3 s min high time on s clk (t hi ) 0.6 s hold time on s data (t hd/data ) 5.0 s setup time on (t su/data ) fast mode (note 2) 100 ns slow mode (note 2) 250 ns rise time for s clk & s data (t lh ) 30 300 ns fall time for s clk & s data (t hl ) 30 300 ns setup time for stop on s data (t su/stop ) 0.6 s figure 1. line rate waveforms t heqw composite video in pin 6 regenerated csync pin 26 equalizers serrations h blank pin 25 s clamp pin 28 bgate pin 27 b clamp pin 27 h reset pin 23 t hblk t hblkw t hrw t hsw t hserrw t hstc t hbpcw t hbpgw t hbpc t hstcw note: not to scale
ml6430/ml6431 8 device functional description video formats, timing, clock input free run vga vcr and pulse rates crystal mode clock lock generation ntsc pal ccir601 square 4xfsc 3.58 4.43 pixel mhz mhz ml6430 yes yes yes yes yes yes yes yes. limited yes. limited to yes transition 640x480 between free pixel clock. run modes 1 and 2. (figure 4) ml6431 yes yes* yes yes* yes yes yes yes. faster yes. works yes. transition be- up to 75mhz. tween freerun (table 6) modes 1and 2. (figure 4a) * readjusted the center frequency for pal square pixel with ntsc crystal to achieve greater than +/-5% range. see table 4 table 1. summary of functional differences between the ml6430 and ml6431. device mode register differences pin out differences register 7, register 7, pin 3 pin 16 bit 2 bit 3 ml6430 sleep mode 0 0 sleep audioclk pulse generator mode* 1 0 54mhz** audioclk time base correction mode this function not available in the ml6430 ml6431 sleep mode 0 0 sleep audioclk pulse generator mode* 1 0 54mhz** audioclk pherrout mode* x 1 must be set high pherrout table 2. summary of register differences between the ml6430 and ml6431. *for these modes the sleep mode can only be enable/disabled via serial bus (register 8). **the 54mhz clock input (pin 3) can be any 4 x clock up to 70mhz device differences tables 1 and 2 summarize the differences between the ml6430 and ml6431. the pinouts of the ml6430 and the ml6431 are the same with the exception that the ml6431 has a few enhancements, (center frequency and free run mode, see table 1) and added functionality (see table 2).
ml6430/ml6431 9 functional description dual plls the genlock has the following properties: ? a stable, asynchronous crystal controlled oscillator provides the basic timing signals. ? a precision analog circuit uses the above timing signals to generate an arbitrarily phased output whose phase can be altered at pixel rate. ? a digital pll loop monitors the error signal from a digital phase detector, and generates a pixel by pixel phase adjustment of the output. ? an intelligent state machine further enhances performance by monitoring errors and error history and adjusting the gains of the loop accordingly. ? a circuit automatically detects a vcr signal and increases loop gain for proper tracking and minimum jitter. the digital pll has five operating modes. in normal operation with a stable input the controller will settle to state 1. if errors are large and consistent, controller will move to state 5. if error conditions are corrected, controller will sequentially decrease the state as the errors are reduced toward 0. if small but consistent errors persist while controller is in state 1, then controller may move to states 2 or 3 to help settle out errors more quickly. none of these changes will cause a reset of pixel count, or a discontinuity of output clocks. operating modes are described in greater detail below. 1. normal: gain is low, instantaneous phase gain is 1/32, giving a net short term jitter gain (output/input jitter) of about -30db. full peak to peak jitter (including lower frequency jitter) from a white source is about - 15db. 2. slow: gain is increased by 4x, and settling time reduced by about the same. this mode is used as a transition mode during normal lock sequence, or as a modest speed up mode if errors are high. 3. medium: gain is increased by 8x, and settling time reduced by about the same. this mode is used as a transition mode during normal lock sequence, or as a speed up mode if errors are consistently high. 4. fast: gain is increased by 16x. adds frequency adjustments to mode 5 for fast settling during hot switches or pathological gyro errors in hand held camcorders. 5. phase: only gain is 16x for phase changes, 0 for frequency changes. primarily used to quickly settle head switch phase errors without affecting loop frequency. low power sleep modes sleep mode may be initiated either from the serial control bus, or from an external pin. in both cases the entire chip except the serial bus is shut down. for applications where pherrout is used, the sleep mode can only be enabled/ disabled via serial control. pherrout signal the pherrout pin indicates, on a line by line basis, whether the h sync pulse of the analog input signal is leading or trailing the genlock's output h sync pulse. this information is used by the genlock to decide whether to speed up or slow down the internal clock to achieve locking of the h sync pulses. if pherrout = 0, then the analog sync is ahead; therefore, the internal clock will speed up in an effort to lock the h sync pulses. by contrast, if pherrout = 1, then the analog sync is behind; therefore, the internal clock will slow down in an effort to lock the h sync pulses. ultimately, when the genlock is locked to the incoming analog signal, pherrout will alternate approximately every line between 0 and 1. sync separation sync separation is accomplished using peak tracking analog amplifiers with a precision sync slicer. the closed tracking loop is equipped with timers to discriminate true sync pulses from noise glitches or chroma overshoots. the use of analog sync separation techniques removes a serious source of jitter present in most digital plls. crystal selection the precision crystal source for the ml6430/ml6431 can be supplied in one of four ways. an industry standard 3.58mhz parallel tuned ntsc color subcarrier crystal or a 4.43mhz parallel tuned pal color subcarrier crystal may be used. alternately, a 14.318mhz ntsc or 17.7mhz pal, 4xfs, or a 3.58mhz or 4.43mhz oscillator source may be used. regardless of the crystal used, the ml6430/ ml6431 can lock to pal, ntsc, beta or mii or yuv in either 625 or 525 standards. table 4 provides the clock rate accuracy for both the ntsc and pal clock rates for each crystal selected. note that the range may vary between the ml6430 and the ml6431. table 3. pherrout signal description pherrout (pin 16) description 0 speed up output timing 1 slow down output timing
ml6430/ml6431 10 functional description (continued) table 4. ntsc/ pal clock rate range vs. crystal input disabling automatic vcr signal detection device disable vcr signal detection? ml6430 no. detection function is always on. ml6431 y es. detection function can be disabled or enabled via serial bus only. this feature is enabled by default. table 5. in the ml6430, the vcr detection circuit is always enabled. this circuit detects the presence of a vcr input signal at c vin / h sync (pin 6) and automatically adjusts the gain settings for the digital pll to optimize locking performance. this circuit scans for head switching greater than the thresholds selected by the user threshold bits (via serial bus) and then increases the phase gain of the digital pll to compensate. in the ml6431, the vcr detection circuit operates the same as the ml6430 with the additional ability to disable or enable the vcr detection circuit to optimize for low jitter performance. this feature is enabled by default. this feature can be disabled in the ml6431 only by setting the appropriate values in register 7, bit 0 via the serial bus interface (see table 11). when the vcr detect circuit is disabled, the ml6431 is optimized for low jitter performance. pulse generator mode 54mhz input or any 4x clock the 54mhz pin (pin 3) is an input that clocks the horizontal and vertical counters. in this mode, the ml6430 or ml6431 is used as a pulse generator. the input signal at can be any 4x clock; for example, 54mhz (4 x ccir clock rate of 13.5mhz), 49.09mhz (4 x square pixel clock rate of 12.27mhz), or 57.27 mhz (4 x fsc clock rate of 14.31mhz for ntsc color subcarrier). this input is limited to 70mhz. as a pulse generator, the sync, clamp, blanking, and clock signals are derived from the clock input at the 54mhz pin. this mode is activated by setting the appropriate values in register 7 via the serial bus. see tables 10 or 11. using f reset for ntsc vs. pal modes in ntsc mode, f reset (pin 22) goes low on the high-to- low transition of the field id pin (pin 17) and the beginning of line 1 (see figure 2). in the pal mode, f reset (pin 22)goes low on the low-to- high transition of the field id pin and the end of line 310 (see figure 3). center frequency and range for each frequency standard of the ml6431 video standard clock rate clock rate accuracy 3.58mhz crystal ntsc square pixel 4xclk= 49.09mhz +8.35%/ C5.19% ntsc 601 4xclk= 54.00mhz +6.07%/ C7.18% ntsc 4fsc 4xclk= 57.27mhz +7.15%/ C6.23% pal square pixel 4xclk= 59.00mhz +7.47%/ C5.93% pal 601 4xclk= 54.00mhz +6.07%/C7.18% pal 4fsc 4xclk= 35.47mhz +7.64%/ C5.77% 4.43mhz crystal ntsc square pixel 4xclk= 49.09mhz +8.28%/ C5.23% ntsc 601 4xclk= 54.00mhz +7.81%/ C5.64% ntsc 4fsc 4xclk= 57.27mhz +6.00%/ C7.18% pal square pixel 4xclk= 59.00mhz +7.27%/ C6.13% pal 601 4xclk= 54.00mhz +7.81%/C5.64% pal 4fsc 4xclk= 35.47mhz +7.05%/ C6.31% center frequency and range for each frequency standard of the ml6430 video standard clock rate clock rate accuracy 3.58mhz crystal ntsc square pixel 4xclk= 49.09mhz +8.35%/ C5.19% ntsc 601 4xclk= 54.00mhz +6.07%/ C7.18% ntsc 4fsc 4xclk= 57.27mhz +7.15%/ C6.23% pal square pixel 4xclk= 59.00mhz +4.01%/ C9.10% pal 601 4xclk= 54.00mhz +6.07%/C7.18% pal 4fsc 4xclk= 35.47mhz +9.58%/ C4.14% 4.43mhz crystal ntsc square pixel 4xclk= 49.09mhz +8.28%/ C5.23% ntsc 601 4xclk= 54.00mhz +7.81%/ C5.64% ntsc 4fsc 4xclk= 57.27mhz +6.00%/ C7.18% pal square pixel 4xclk= 59.00mhz +7.27%/ C6.13% pal 601 4xclk= 54.00mhz +7.81%/C5.64% pal 4fsc 4xclk= 35.47mhz +7.05%/ C6.31%
ml6430/ml6431 11 figure 2. ntsc field rate waveforms figure 3. pal 625 field rate waveforms 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 525 263 265 264 266 268 267 269 271 272 274 273 275 277 276 278 280 279 281 283 282 284 262 270 3h 3h 3h vertical blanking interval field 1 h start of field 1 h h h/2 h vertical blanking interval field 2 start of field 2 h/2 vblank pin 24 freset pin 22 fieldid pin 17 9 or 16 lines ? line fieldid pin 17 (odd vertical intervals only) low for odd fields high for even fields ~ ~ ~ 2 4 5 6 7 8 9 10 11 12 13 14 15 16 1 622 625 624 312 311 310 315 314 316 318 319 321 320 322 324 323 325 327 326 328 329 336 317 v blank pin 24 f reset pin 22 oddfld pin 17 7.5 or 16 lines ? line ~ black level blanking level sync level white level end of first field (even) } black level blanking level sync level white level } end of fourth field (odd) broad pulse separation 4.7s 100ns field blanking (25 lines + line blanking) 2.5 lines 5 equalizing pulses 2.5 lines 5 equalizing pulses 2.5 lines field sync 5 broad pulses beginning of first field (even) beginning of second field (odd) 3 623 23 313 high for second field, low for first field (second field vertical interval only)
ml6430/ml6431 12 functional description (continued) freerun mode both the ml6430 and ml6431 can be used in freerun mode. the ml6431 is recommended for applications requiring a more robust freerun mode of operations. figure 4 and figure 4a describe the state diagrams for both the ml6430 and ml6431. note that the ml6431 includes a faster path to go from freerun mode #1 to freerun mode #2. freerun mode: freerun mode #1 is entered when the freerun pin is toggled high while the ml6430/ ml6431 is horizontally locked (i.e. internal horizontal locked signal is present). in this mode, the digital frequency value stored in the line-locked pll is held and the ml6430/ml6431 will freerun at a frequency very close to that of the last locked video source. freerun mode #1 is best used by physically tying the nosignal pin to the freerun pin as shown in figures 9 or 10. freerun mode #2 is entered when the freerun pin is toggled high while the ml6430/ml6431 is not horizontally locked to a video source. in this mode, a rom lookup table is used to set the freerun frequency of the ml6430/ml6431. in this mode the output frequency is as accurate as the crystal plus the accuracy of the look up table. see figures 4 and 4a for the nosignal-locked-freerun state machine diagram. nosignal: nosignal will go low if video is present for one entire field. nosignal will be high if video is not present for one entire field. locked (ml6430): the ml6430 must be line (horizontal) locked to an input video source and also be vertically locked before the locked detect signal goes high. when a video source is removed, the locked signal may be high or low. please note that the locked pin is the logical and of the internal horizontal locked and vertical locked signals. for example, the internal horizontal locked signal may be high even though the locked pin is asserted low. input video within 6% range power up ml6430 w/ freerun pin "low" (typical) power up ml6430 w/ freerun pin "high" (typical) if no video for > 1 frame toggle freerun pin "high" toggle freerun pin "high" toggle freerun pin "high" if input video for > 1 frame freerun pin "low" if no video for > 1 frame freerun pin "low" if input video for > 1 frame toggle freerun pin "high" input video outside 6% range horizontal locked no signal present 3 freerun mode #1 5 horizontal locked signal present 2 horizontal unlocked no signal present 4 freerun mode #2 6 horizontal unlocked signal present 1 figure 4. ml6430 freerun mode state diagram
ml6430/ml6431 13 locked (ml6431): the ml6431 must be line (horizontal) locked to an input video source for at least two fields and also be vertically locked before the locked detect signal goes high. when a video source is removed, the ml6431 will lose horizontal lock after two entire fields with no video present. however, vertical lock may be lost before horizontal lock. because the locked pin is the logical and of the internal horizontal locked and vertical locked signals the locked pin may go low before the internal horizontal locked signal. vga clocks for vga applications the ml6431 is recommended. table 6 provides a list of the vga clocks that can be generated using the ml6431. to use the information in table 6 first find the resolution and refresh rate required. determine which crystal, pal or ntsc is needed. change the crystal to the proper frequency if necessary. over the serial-bus, program the registers as indicated in table 6. supply to pin 6 an horizontal sync signal at ttl or cmos levels and at the specified frequency. trigger an oscilloscope on the falling edge of the horizontal input to view the outputs. the vga pixel clock will be found on pin 18. other useful signals are noted in table 6. external logic may be needed to produce usable vertical sync pulses. audio clocks the audio modes can be activated via serial bus (register 7). when this mode is activated an audio clock frequency can be selected via serial bus (register 8). see table 9. functional description (continued) figure 4a. ml6431 freerun mode state diagram input video within 6% range power up ml6431 w/ freerun pin "low" (typical) power up ml6431 w/ freerun pin "high" (typical) if no video for > 1 frame toggle freerun pin "high" toggle freerun pin "high" toggle freerun pin "high" if input video for > 1 frame freerun pin "low" if no video for > 1 frame freerun pin "low" if input video for > 1 frame toggle freerun pin "high" input video outside 6% range if no video for > 2 frames horizontal locked no signal present 3 freerun mode #1 5 horizontal locked signal present 2 horizontal unlocked no signal present 4 freerun mode #2 6 horizontal unlocked signal present 1
ml6430/ml6431 14 ml6431 data register settings* resolution # pixels refresh horizontal pixel standard original freq. std. palxtal pixel reg pherrout vga external pixel horizontal vertical per line rate frequency frequency type standard # xtal used clk output pulses pulses 640 x 480 800 60 hz 31.5 khz 25.175 mhz industry ntsc sq pix =000 1 572 0 1 4.43 2x hsync,hreset vreset 832 72 hz 37.9 khz 31.500 mhz vesa vs901101 ntsc sq pix =000 0 640 0 1 4.43 2x hsync,hreset vreset 840 75 hz 37.5 khz 31.500 mhz vesa vdmt75hz ntsc sq pix =000 0 656 0 1 4.43 2x hsync,hreset vreset** 800 x 600 1024 56 hz 35.1 khz 36.000 mhz vesa vg900601 pal 4fsc =101 1 512 1 1 4.43 4x hsync,hreset vreset 1056 60 hz 37.9 khz 40.000 mhz vesa vg900602 ntsc sq pix =000 1 544 1 1 3.58 4x hsync,hreset vreset** 1040 72 hz 48.1 khz 50.000 mhz vesa vs900603a ntsc sq pix =000 1 528 1 1 4.43 4x hsync,hreset vreset** 1056 75 hz 46.9 khz 49.500 mhz vesa vdmt75hz ntsc sq pix =000 1 544 1 1 4.43 4x hsync,hreset vreset** 1024 x 768 1264 43 hz/int 35.5 khz 44.900 mhz industry pal 4fsc =101 0 752 1 1 4.43 4x hsync,hreset vreset** 1344 60 hz 48.4 khz 65.000 mhz vesa vg901101a pal 601 = 011 0 832 1 1 4.43 4x hsync,hreset vreset** 1328 70 hz 56.5 khz 75.000 mhz vesa vs910801-2 pal 4fsc =101 0 816 1 1 3.58 4x & clk no no doubler *for data register settings: ttl = high, vga = on, vcr = off, noise gating = on, dis auto ver det = 1 ** w/ external glue logic table 6. vga rates supported
ml6430/ml6431 15 functional description (continued) preset pin control the ml6430/ml6431 may be controlled via a set of four preset mode pins. these pins do not allow access to all the programmable features of the ml6430/ml6431, but are intended to provide a simpler interface for most applications. pulse outputs pulse outputs are defined in table 12. note that the pulse widths and start times are chosen to the nearest clock edge, and indicated errors assume nominal clock operating frequency. p3 p2 p1 p0 std clock rate crystal 0101 ntsc square pixel 3.58mhz 1001 ntsc ccir601 3.58mhz 1101 ntsc 4fsc 3.58mhz 0111pal square pixel 3.58mhz 1 0 1 1 pal ccir601 3.58mhz 1111pal 4fsc 3.58mhz 010z ntsc square pixel 4.43mhz 100z ntsc ccir601 4.43mhz 1 1 0 z ntsc 4fsc 4.43mhz 0 1 1 z pal square pixel 4.43mhz 101zpal ccir601 4.43mhz 1 1 1 z pal 4fsc 4.43mhz 0 z 0 1 ntsc square pixel 14.32mhz z 0 0 1 ntsc ccir601 14.32mhz z z 0 1 ntsc 4fsc 14.32mhz 0 z 1 1 pal square pixel 14.32mhz z 0 1 1 pal ccir601 14.32mhz z z 1 1 pal 4fsc 14.32mhz p3 p2 p1 p0 std clock rate crystal 0 z 0 z ntsc square pixel 17.72mhz z 0 0 z ntsc ccir601 17.72mhz z z 0 z ntsc 4fsc 17.72mhz 0 z 1 z pal square pixel 17.72mhz z 0 1 z pal ccir601 17.72mhz z z 1 z pal 4fsc 17.72mhz z 1 0 1 ntsc square pixel, vga 3.58mhz 1 z 0 1 ntsc ccir601,vga 3.58mhz 0001 ntsc 4fsc, vga 3.58mhz z 1 1 1 pal square pixel, vga 3.58mhz 1 z 1 1 pal ccir601, vga 3.58mhz 0011pal 4fsc, vga 3.58mhz z 1 0 z ntsc square pixel, vga 4.43mhz 1 z 0 z ntsc ccir601, vga 4.43mhz 000z ntsc 4fsc, vga 4.43mhz z 1 1 z pal square pixel, vga 4.43mhz 1 z 1 z pal ccir601, vga 4.43mhz 001zpal 4fsc, vga 4.43mhz xxx0 serial control mode z = floating input, 0 = low input, 1 = high input, x = dont care table 7. preset pin modes
ml6430/ml6431 16 functional description (continued) control register information register setting pulsepol[2:0] 000 clk4x 0 pixel[10:0] determined by preset pin burst 0 csyncraw 0 rawclamp 0 ttl sync 0 wideblank 0 hdelay[6:0] 1000000 noise gating 0 test 3,1,4 0, 0, 0 external 54 clock in 0 faud[1:0] 01 vcr 0 sleep 0 thresh[1:0] 11 vga determined by preset pin div4 determined by preset pin fstd[2:0] d etermined by preset pin palx tal determined by preset pin table 8. default control register settings for preset mode register description sleep : enables or disables sleep mode. when using serial bus control, all registers must be programmed to their intended state after power up to ensure correct operation of the ml6430/ml6431. csr : composite sync register bit controls whether composite sync output is from the sync separator, (raw c sync ) or from the internal pulse generator (regenerated c sync ). pulse polarity control: the active state of output sync pulses, blanking pulses, or clamp pulses may be programmed to either 0 or 1 state by use of these bits. p0 :c sync pulse output is high active when 1, low active when 0. p1 :h blank , and v blank pulse outputs are high active when 1, low active when 0. p2 :s clamp and b clamp pulse outputs are high active when 1, low active when 0. burst : controls the length of burst gate so pulse can be used for either burst gating in encoder applications or back porch clamping. rawclamp : controls the source of the s clamp (sync clamp) pulse. pulse is timed relative to incoming sync edge, or regenerated sync edge. palxtal : controls the expected crystal frequency at the oscillator inputs. 0 = ntsc 3.58mhz, or 1 = pal 4.43mhz. thresh1,thresh0 : selects the pixel error threshold at which relock is initiated. values are: 0,0: 2.5 pixels 0,1: 2.5 pixels 1,0: 1.0 pixels 1,1: 4.0 pixels noise gating : enables a 3/4 line window to lockout any unwanted horizontal sync pulses. vga : produces non-interlaced progressive scan outputs. div4 : controls the prescaler in the m/n loop. high means that 4fs external oscillator signals are expected, low assumes a pal or ntsc fs crystal will be used. vcr : controls the gain range and locking maneuvers of the digital loop. provides better locking to the unpredictability of vcr headswitches and jitter. blanking width control: the number of blanked lines in the vertical interval is programmable to either 9 or 16. xtal : external crystal control: 0=ntsc 3.58mhz, or 1=pal 4.43mhz, for both local crystal and external oscillator mode. external 54mhz clock : this mode permits injecting a 54mhz clock (or other 4x clock) directly into the horizontal pixel counter via the sleep pin. all timing pulses are synchronous to the 54mhz clock (or other 4x clock). serial bus control : to place the ml6430/ml6431 in serial mode, take p0 (preset ) to logical '0' or ground. the serial control system is written to by the external processor in 8- bit bytes. each of these bytes is partitioned into an address (upper 4 bits of serial byte) and a data register (lower 4 bits of serial byte). in table 10, the register heading refers to the 4-bit address, and data bit refers to a particular bit in the 4-bit register (bit0 is lsb). pixel : program all bits to zero to enable default values for each standard. otherwise use the following equation: p[10:0] = 2 (number of pixels per line) C 1024 (1) test : all test bits must be programmed to zero.
ml6430/ml6431 17 functional description (continued) audio clock : the ml6430/ml6431 outputs a clock at 32khz, 44.1khz, or 48khz. this clock is locked in frequency to the basic video clock regardless of the standard being used. with vcr head switches, the phase correction required to track the timing is removed from the audio clock by a patented circuit. this prevents the audio clock from being modulated by step changes in video timing. see the table 9 for the audio clock rates supported and how they are derived internally. additional control registers (ml6431 only) disautovcr : disables the auto vcr detect circuit. register 7, bit 0: disautovcr pherrout: mux phase error signal onto audioclk/pherrout pin. register 7, bit 3: pherrout enable this bit controls the source of audioclk/pherrout. when this bit is low, audioclk/pherrout provides the audio clock output. when this bit is high, audioclk/ pherrout provides the 1-bit digital phase error of each hsync edge. additionally, when both pherrout enable and vga bits are logic high, the reset point of the pixel counter is changed from 512 to 256. this changes the equation for calculating the number of pixels per line verses the pixel counter bits to the following: p[10:0] = 2 (number of pixels per line) C 512 (2) table 9. audio clock generation (ml6430/ml6431) video standard audio rate audio/pixel clock ratio audio/frame rate ratio ccir601 ntsc 48khz (96000 27mhz) 13.5mhz (8008 5) 29.97hz ccir601 ntsc 44.1khz (88200 27mhz) 13.5mhz (147147 100) 29.97hz ccir601 ntsc 32khz (64000 27mhz) 13.5mhz (16016 15) 29.97hz ccir601 pal 48khz (96000 27mhz) 13.5mhz (1920) 25hz ccir601 pal 44.1khz (88200 27mhz) 13.5mhz (1764) 25hz ccir601 pal 32khz (64000 27mhz) 13.5mhz (1280) 25hz ntsc square pixel 48khz (105600 27mhz) 12.27mhz (8008 5) 29.97hz ntsc square pixel 44.1khz (97020 27mhz) 12.27mhz (147147 100) 29.97hz ntsc square pixel 32khz (70400 27mhz) 12.27mhz (16016 15) 29.97hz pal square pixel 48khz (96000 29.5mhz) 14.75mhz (1920) 25hz pal square pixel 44.1khz (88200 29.5mhz) 14.75mhz (1764) 25hz pal square pixel 32khz (64000 29.5mhz) 14.75mhz (1280) 25hz ntsc 4xfsc 48khz (105600 31.5mhz) 14.32mhz (8008 5) 29.97hz ntsc 4xfsc 44.1khz (92400 30mhz) 14.32mhz (147147 100) 29.97hz ntsc 4xfsc 32khz (70400 31.5mhz) 14.32mhz (16016 15) 29.97hz pal 4xfsc 48khz (76800 28.37mhz) 17.72mhz (1920) 25hz pal 4xfsc 44.1khz (70560 28.37mhz) 17.72mhz (1764) 25hz pal 4xfsc 32khz (51200 28.37mhz) 17.72mhz (1280) 25hz
ml6430/ml6431 18 register data description value range bit code bit range 0 0 pulsepol 0 c sync polarity high active-low active 0 or 1 0 1 pulsepol 1 h/v blank polarity high active-low active 0 or 1 0 2 pulsepol 2 s/b clamp polarity high active-low active 0 or 1 0 3 clk 4x select 4x clock low 1x clock = 13.5mhz 0 or 1 high 4x clock = 54mhz 1 0 pixel0 pix counter load bit 0 1 1 pixel1 pix counter load bit 1 1 2 pixel2 pix counter load bit 2 1 3 pixel3 pix counter load bit 3 2 0 pixel4 pix counter load bit 4 2 1 pixel5 pix counter load bit 5 2 2 pixel6 pix counter load bit 6 2 3 pixel7 pix counter load bit 7 3 0 pixel8 pix counter load bit 8 3 1 pixel9 pix counter load bit 9 3 2 pixel10 pix counter load bit 10 3 3 burst burst gate enable low = back porch clamp 0 or 1 high = burst gate 4 0 csyncraw (or c sync regen) low = regenerated c sync 0 or 1 high = raw c sync 4 1 rawclamp (or clamp regen) low = regenerated clamp 0 or 1 high = raw clamp 4 2 ttl sync ttl horizontal + vertical low = sync separator active 0 or 1 sync input high = ttl horiz + vert sync input 4 3 wideblank (or narrow) low = narrow blanking 0 or 1 high = wide blanking 5 0 hdelay0 5 1 hdelay1 5 2 hdelay2 5 3 hdelay3 6 0 hdelay4 6 1 hdelay5 6 2 hdelay6 6 3 noise gating 3/4 line lockout low = noise gating on 0 or 1 high = noise gating off numerical value taken as unsigned binary. actual no. of pixels is: 512 10 0 2 + p: do not vary pixel [10:0] by more than 6% from nominal. 1024 > no. of pixels > 512 and f nom x 1.06 > f new > f nom x 0.94 nom = ~011 0000 0000 max = 011 0011 0000 min = 010 1101 0000 h delay parameter allows moving the entire constellation of output pulses relative to the incoming h sync . exception: sync tip clamp may be selected for delay or triggered from incoming sync depending on application. 7-bit horizontal delay parameter. values: C64p< hdly < 63p, p = 1/f 4xclk 0000000 to 1111111: 0000000 means C64p 1111111 means +63p 1000000 means 0p table 10. ml6430 register map
ml6430/ml6431 19 register data description value range bit code bit range 7 0 test 3 for test mode only: no user programmable features set to 0 0 7 1 test 1 for test mode only: no user programmable features set to 0 0 7 2 ext 54 low = pin 3 is sleep clock in high = pin 3 is 54mhz clock 0 or 1 7 3 test 4 for test mode only: no user programmable features set to 0 0 8 0 faud0 audioclk freq bit 0 00 = 48khz, 01 = 44.1khz, 10 = 32khz 00 to 10 8 1 faud1 audioclk freq bit 1 8 2 vcr enable vcr mode high = enabled, low = disabled 8 3 sleep power down mode high = power down, low = normal 0 or 1 9 0 thresh0 select out of lock threshold 00 = 2.5 pixels 10 = 1.0 pixels 00 to 11 9 1 thresh1 01 = 2.5 pixels 11 = 4.0 pixels 9 2 vga enable vga mode high = enabled, low = disabled 0 or 1 9 3 div4 enable /4 on m/n loop high = enabled, low = disabled 0 or 1 10 0 fstd0 freq std sel bit 0 000 = ntsc sq pix 011 = pal 601 000 to 101 10 1 fstd1 freq std sel bit 1 001 = pal sq pix 100 = ntsc 4fsc 10 2 fstd2 freq std sel bit 2 010 = ntsc 601 101 = pal 4fsc 10 3 palx tal enable pal ref freq high = enabled, low = disabled 0 or 1 table 10. ml6430 register map (continued)
ml6430/ml6431 20 register data description value range bit code bit range 0 0 pulsepol 0 c sync polarity high active-low active 0 or 1 0 1 pulsepol 1 h/v blank polarity high active-low active 0 or 1 0 2 pulsepol 2 s/b clamp polarity high active-low active 0 or 1 0 3 clk 4x select 4x clock low 1x clock = 13.5mhz 0 or 1 high 4x clock = 54mhz 1 0 pixel0 pix counter load bit 0 1 1 pixel1 pix counter load bit 1 1 2 pixel2 pix counter load bit 2 1 3 pixel3 pix counter load bit 3 2 0 pixel4 pix counter load bit 4 2 1 pixel5 pix counter load bit 5 2 2 pixel6 pix counter load bit 6 2 3 pixel7 pix counter load bit 7 3 0 pixel8 pix counter load bit 8 3 1 pixel9 pix counter load bit 9 3 2 pixel10 pix counter load bit 10 3 3 burst burst gate enable low = back porch clamp 0 or 1 high = burst gate 4 0 csyncraw (or c sync regen) low = regenerated c sync 0 or 1 high = raw c sync 4 1 rawclamp (or clamp regen) low = regenerated clamp 0 or 1 high = raw clamp 4 2 ttl sync ttl horizontal + vertical low = sync separator active 0 or 1 sync input high = ttl horiz + vert sync input 4 3 wideblank (or narrow) low = narrow blanking 0 or 1 high = wide blanking 5 0 hdelay0 5 1 hdelay1 5 2 hdelay2 5 3 hdelay3 6 0 hdelay4 6 1 hdelay5 6 2 hdelay6 6 3 noise gating 3/4 line lockout low = noise gating on 0 or 1 high = noise gating off numerical value taken as unsigned binary. actual no. of pixels is: 512 10 0 2 + p: do not vary pixel [10:0] by more than 6% from nominal. 1024 > no. of pixels > 512 and f nom x 1.06 > f new > f nom x 0.94 if pherr enable and vga = 1, the actual no. of pixels is: p[10:0]=2x(no. of pixels per line)C512 nom = ~011 0000 0000 max = 011 0011 0000 min = 010 1101 0000 h delay parameter allows moving the entire constellation of output pulses relative to the incoming h sync . exception: sync tip clamp may be selected for delay or triggered from incoming sync depending on application. 7-bit horizontal delay parameter. values: C64p < hdly < 63p, p = 1/f 4xclk 0000000 to 1111111: 0000000 means C64p 1111111 means +63p 1000000 means 0p table 11. ml6431 register map
ml6430/ml6431 21 register data description value range bit code bit range 7 0 disautovcr 0=auto vcr detect on 0 or 1 1=disable auto vcr detect 7 1 test 1 for test mode only: no user programmable features. set to 0 0 7 2 ext 54 low = pin 3 is sleep clock in high = pin 3 is ext 54mhz clock 0 or 1 7 3 pherrout or audioclk low=pin 16 is audio clk, pin 3 is sleep high=pin 16 is pherrout, pin 3 is reset 0 or 1 8 0 faud0 audioclk freq bit 0 00 = 48khz, 01 = 44.1khz, 10 = 32khz 00 to 10 8 1 faud1 audioclk freq bit 1 8 2 vcr enable vcr mode high = enabled, low = disabled 8 3 sleep power down mode high = power down, low = normal 9 0 thresh0 select out of lock threshold 00 = 2.5 pixels 10 = 1.0 pixels 00 to 11 9 1 thresh1 01 = 2.5 pixels 11 = 4.0 pixels 9 2 vga enable vga mode high = enabled, low = disabled 0 or 1 9 3 div4 enable /4 on m/n loop high = enabled, low = disabled 0 or 1 10 0 fstd0 freq std sel bit 0 000 = ntsc sqpix 011 = pal 601 000 to 100 10 1 fstd1 freq std sel bit 1 001 = pal sq pix 100 = ntsc 4fsc 10 2 fstd2 freq std sel bit 2 010 = ntsc 601 10 3 palx tal enable pal ref freq high = enabled, low = disabled 0 or 1 table 11. ml6431 register map (continued)
ml6430/ml6431 22 functional description (continued) serial bus operation the serial bus control in the ml6430/ml6431 has two levels of addressing: device addressing and register addressing. device addressing : figure 5 shows the physical waveforms generated in order to address the ml6430/ ml6431. there are six basic parts of the waveform: 1. start indication: clock cycle 0 2. device address shifted: clock cycle 1 through 8 3. device address strobed and decoded: clock cycle 9 4. data shifted : clock cycle 10 through 17 5. data strobed into appropriate register: clock cycle 18 6. stop indication: clock cycle 19 register addressing : figure 6 shows the register map of the ml6430/6431. there are two basic parts of each received data byte: address nibble and data nibble 1. address nibble: the upper 4 bits of the data byte gives the register number in which to place the data. 2. data nibble: the lower 4 bits of the data byte is the data to be placed in the currently addressed register nibble. figure 6. definition of data format on serial data bus s data s clk stop msb msb a1 a0 a6 a7 0 1 2 7 8 9 10 11 16 17 18 d7 d6 d1 d0 s clk : s clk : s data : s clk : s clk : s data : s clk : s data ; 9th pulse strobes address decoder rising edge enables data transfer value set to a6, device address (msb-1) falling edge disables data transfer rising edge enables data transfer value set to a7, device address msb falling edge in prep for first address transfer falling edge with s clk hi means start of sequence s data : s data : s clk : s clk : s data : s clk : s clk : s data : rising edge with s clk hi = stop value set low in prep for stop 18th pulse strobes data shift register rising edge enables data transfer value set to d6, data msb-1 falling edge disables data transfer rising edge enables data transfer value set to d7, data msb figure 5. definition of start & stop on serial data bus s data s clk start stop t rise t fall t set/start all other s data transitions must occur while s clk is low start: a falling edge on the s data while s clk is held high stop: a rising edge on the s data while s clk is held high
ml6430/ml6431 23 figure 7. typical serial bus command s data s clk 1 0 0 0 ? ? r3 r2 r1 r0 d3 d2 d1 d0 0 1 1 1 0 1 234 5 9abcd e fgh i s clk : s data : s clk : address decode strobed on 9th clock [data is dont care during strobe] 1011 0010 shifted on next 8 clocks falling edge in prep for device address transfer s data : s data : s data : final clock strobes data into register second 4 bits are register data first 4 bits are register address device addr = b2 data register sub-addr strobe 68 7 figure 8. serial bus command to set bit #2 in register 7 device address register address strobe in address data strobed into appropriate register data 1 1 start s data s clk 23456789abcdef gh istop 0110010 11101 00 0
ml6430/ml6431 24 applications the ml6430 and ml6431 can be used for a variety of applications. the following figures provide a basic setup for the various applications listed below: figure 9: ml6430 or ml6431 in ntsc ccir applications figure 10: ml6430 or ml6431 in pal ccir applications figure 11: ml6431 in vga application figure 12: ml6430 or ml6431 in audio applications figure 13: ml6430 or ml6431 in pulse generator applications
ml6430/ml6431 25 figure 9. ml6430/ml6431 in ntsc ccir applications programmed via preset pins p1 p0 gnd d v cc d s clamp b clamp/burst c sync h blank 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v blank h reset f reset v cc b gnd b 1x clock/4x clock 2x clock field id p2/s data p3/s clk sleep /54mhz v cc s gnd s c vin /h sync cv ref v sync v cc a gnd a xtal in xtal out freerun nosignal locked audioclk/pherrout* 5v for 3.54 mhz xtal or open for 4.43 mhz xtal 5v 5v 5v 5v cv synch out 1.0 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 1.0 m f 0.1 m f 1nf 0.001 m f 1nf 5v led 5v led 3.58mhz or 4.43mhz cv in 75 w ml6430/ml6431 410 400 note 1. for minimum v cc bypassing, connect capacitors v cc a only. (v cc a to gnd a) 5v *pherrout is only available with the ml6431
ml6430/ml6431 26 figure 10. ml6430/ml6431 in pal ccir applications programmed via preset pins p1 p0 gnd d v cc d s clamp b clamp/burst c sync h blank 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v blank h reset f reset v cc b gnd b 1x clock/4x clock 2x clock field id p2/s data p3/s clk sleep /54mhz v cc s gnd s c vin /h sync cv ref v sync v cc a gnd a xtal in xtal out freerun nosignal locked audioclk/pherrout* 5v 5v +5v 5v cv synch out 1.0 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 1.0 m f 0.1 m f 1nf 0.001 m f 1nf 5v led 5v led cv in 75 w ml6431 5v 410 400 note 1. for minimum v cc bypassing, connect capacitors v cc a only. (v cc a to gnd a) 5v *pherrout is only available with the ml6431 3.58mhz or 4.43mhz 5v for 3.54 mhz xtal or open for 4.43 mhz xtal
ml6430/ml6431 27 figure 11. ml6431 in vga applications p1 p0 gnd d v cc d s clamp b clamp/burst c sync h blank 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v blank h reset f reset v cc b gnd b 1x clock/4x clock 2x clock field id p2/s data p3/s clk sleep /54mhz v cc s gnd s c vin /h sync cv ref v sync v cc a gnd a xtal in xtal out freerun nosignal locked audioclk/pherrout* h sync or cv s data s clk 5v 5v 5v 5v cv synch out 1.0 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 0.1 m f 1nf 0.001 m f 1nf 5v led 5v led ml6431 410 400 note 1. for minimum v cc bypassing, connect capacitors v cc a only. (v cc a to gnd a) *pherrout is only available with the ml6431 3.58mhz or 4.43mhz pixel clock output
ml6430/ml6431 28 figure 12. ml6430/ml6431 in audio applications p1 p0 gnd d v cc d s clamp b clamp/burst c sync h blank 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v blank h reset f reset v cc b gnd b 1x clock/4x clock 2x clock field id p2/s data p3/s clk sleep /54mhz v cc s gnd s c vin /h sync cv ref v sync v cc a gnd a xtal in xtal out freerun nosignal locked audioclk/pherrout* s data s clk 5v 5v 5v 5v cv synch out 1.0 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 0.1 m f 1nf 0.001 m f 1nf 5v led 5v led ml6430/ml6431 410 400 note 1. for minimum v cc bypassing, connect capacitors v cc a only. (v cc a to gnd a) note 2. see table 4 for audio clock frequencies and registers *pherrout is only available with the ml6431 1.0 m f cv in 75 w 3.58mhz or 4.43 mhz audio clock out
ml6430/ml6431 29 p1 p0 gnd d v cc d s clamp b clamp/burst c sync h blank 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v blank h reset f reset v cc b gnd b 1x clock/4x clock 2x clock field id p2/s data p3/s clk sleep /54mhz v cc s gnd s c vin /h sync cv ref v sync v cc a gnd a xtal in xtal out freerun nosignal locked audioclk/pherrout* 5v 5v 5v no input needed 5v cv synch out 1.0 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 0.1 m f 1nf 0.001 m f 1nf 5v led 5v led ml6430/ml6431 410 400 note 1. for minimum v cc bypassing, connect capacitors v cc a only. (v cc a to gnd a) note 2. see table 4 for audio clock frequencies and registers *pherrout is only available with the ml6431 1.0 m f cv in 75 w 3.58mhz or 4.43 mhz audio clock out see table 7 for available standards figure 13. ml6430/ml6431 in pulse generator applications
ml6430/ml6431 30 pal at square pixel rate symbol name: ccir 601std typ units description n ha clocks per h: 768 767 cycles active n h clocks per h: 944 944 cycles whole line n va h per frame: 609, 616 lines active n v h per frame: 625 625 lines whole line n vblkw lines of blanking: 15 lines wide n vblkn lines of blanking: 9 lines narrow t h h line time 64.0 64.0 s t hs h sync time 0.0 0.0 s t hsw h sync width 4.7 4.68 s t hrw h reset width 34 s t heqw equalizer sync 2.35 2.31 s width t hserrw serration sync 27.3 27.32 s width t hstc sync tip clamp 300 102 ns pulse t hstcw sync tip clamp 1.5 1.49 s width t hbpc burstpulse 300 339 ns t hbpgw burstwidth 2.43 2.44 s t hbpcw b clamp width 4.0 4.0 s t hblk h blanking pulse C1.5 C1.49 s t hblkw h blanking pulse 12.0 12.0 s width ntsc at square pixel rate symbol name: ccir 601std typ units description n ha clocks per h: 640 648 cycles active n h clocks per h: 780 780 cycles whole line n va h per frame: 486 493,507 lines active n v h per frame: 525 525 lines whole line n vblkw lines of blanking: 16 15 lines wide n vblkn lines of blanking: 9 9 lines narrow t h h line time 63.55 63.55 s t hs h sync time 0.0 0.0 s t hsw h sync width 4.7 4.73 s t hrw h reset width 41 s t heqw equalizer sync 2.35 2.28 s width t hserrw serration sync 27.05 s width t hstc sync tip clamp 300 122 ns pulse t hstcw sync tip clamp 1.5 1.47 s width t hbpc burstpulse 300 326 ns t hbpgw burstwidth 2.51 2.44 s t hbpcw b clamp width 4.0 3.91 s t hblk h blanking pulse C1.5 C1.39 s t hblkw h blanking pulse 10.9 10.76 s width table 12. pulse output timing
ml6430/ml6431 31 pal at 4 x fs rate symbol name: ccir 601std typ units description n ha clocks per h: 922 922 cycles active n h clocks per h: 1135.0064 1135 cycles whole line n va h per frame: 609, 616 lines active n v h per frame: 625 625 lines whole line n vblkw lines of blanking: 15 lines wide n vblkn lines of blanking: 9 lines narrow t h h line time 64.0 64.0 s t hs h sync time 0.0 0.0 s t hsw h sync width 4.7 4.74 s t hrw h reset width 28 s t heqw equalizer sync 2.35 2.25 s width t hserrw serration sync 27.3 27.29 s width t hstc sync tip clamp 300 169 ns pulse t hstcw sync tip clamp 1.5 1.58 s width t hbpc burstpulse 300 225 ns t hbpgw burstwidth 2.43 2.48 s t hbpcw b clamp width 4.0 4.06 s t hblk h blanking pulse C1.5 C1.52 s t hblkw h blanking pulse 12.0 12.12 s width ntsc at 4 x fs rate symbol name: ccir 601std typ units description n ha clocks per h: 768 752 cycles active n h clocks per h: 910 910 cycles whole line n va h per frame: 486 493,507 lines active n v h per frame: 525 525 lines whole line n vblkw lines of blanking: 16 15 lines wide n vblkn lines of blanking: 9 9 lines narrow t h h line time 63.55 63.55 s t hs h sync time 0.0 0.0 s t hsw h sync width 4.7 4.68 s t hrw h reset width 35 s t heqw equalizer sync 2.35 2.30 s width t hserrw serration sync 27.05 27.02 s width t hstc sync tip clamp 300 105 ns pulse t hstcw sync tip clamp 1.5 1.47 s width t hbpc burstpulse 300 349 ns t hbpgw burstwidth 2.51 2.51 s t hbpcw b clamp width 4.0 3.98 s t hblk h blanking pulse C1.5 C1.54 s t hblkw h blanking pulse 10.9 11.03 s width table 12. pulse output timing (continued)
ml6430/ml6431 32 pal at ccir601 rate symbol name: ccir 601std typ units description n ha clocks per h: 720 702 cycles active n h clocks per h: 864 864 cycles whole line n va h per frame: 609, 616 lines active n v h per frame: 625 625 lines whole line n vblkw lines of blanking: 15 lines wide n vblkn lines of blanking: 9 lines narrow t h h line time 64.0 64.0 s t hs h sync time 0.0 0.0 s t hsw h sync width 4.7 4.67 s t hrw h reset width 37 s t heqw equalizer sync 2.35 2.30 s width t hserrw serration sync 27.30 27.33 s width t hstc sync tip clamp 300 111 ns pulse t hstcw sync tip clamp 1.5 1.48 s width t hbpc burstpulse 300 370 ns t hbpgw burstwidth 2.43 2.44 s t hbpcw b clamp width 4.0 4.0 s t hblk h blanking pulse C1.5 C1.48 s t hblkw h blanking pulse 12.0 12.0 s width ntsc at ccir601 rate symbol name: ccir 601std typ units description n ha clocks per h: 720 709 cycles active n h clocks per h: 858 858 cycles whole line n va h per frame: 486 493, 507 lines active n v h per frame: 525 525 lines whole line n vblkw lines of blanking: 16 15 lines wide n vblkn lines of blanking: 9 9 lines narrow t h h line time 63.55 63.55 s t hs h sync time 0.0 0.0 s t hsw h sync width 4.7 4.67 s t hrw h reset width 37 s t heqw equalizer sync 2.35 2.37 s width t hserrw serration sync 27.05 27.04 s width t hstc sync tip clamp 300 111 ns pulse t hstcw sync tip clamp 1.5 1.48 s width t hbpc burstpulse 300 370 ns t hbpgw burstwidth 2.51 2.44 s t hbpcw b clamp width 4.0 4.10 s t hblk h blanking pulse C1.5 C1.55 s t hblkw h blanking pulse 10.9 11.03 s width table 12. pulse output timing (continued)
ml6430/ml6431 33 ds6430_31-01 physical dimensions inches (millimeters) ordering information part number temperature range package ML6430CH 0c to 70c 32-pin tqfp (h32-7) ml6431ch (eol) 0c to 70c 32-pin tqfp (h32-7) 2092 concourse drive san jose, ca 95131 tel: 408/433-5200 fax: 408/432-0295 www.microlinear.com 0.048 max (1.20 max) seating plane 0.354 bsc (9.00 bsc) 0.276 bsc (7.00 bsc) 1 0.276 bsc (7.00 bsc) 0.354 bsc (9.00 bsc) 9 25 17 0.032 bsc (0.8 bsc) pin 1 id 0.012 - 0.018 (0.29 - 0.45) 0.037 - 0.041 ( 0.95 - 1.05 ) 0.018 - 0.030 (0.45 - 0.75) 0.003 - 0.008 (0.09 - 0.20) 0o - 8o package: h32-7 32-pin (7 x 7 x 1mm) tqfp ? micro linear 2000. is a registered trademark of micro linear corporation. all other trademarks are the property of their respective owners. products described herein may be covered by one or more of the following u.s. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. other patents are pending. micro linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is gran ted by this document. the circuits contained in this document are offered as possible applications only. particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. the customer is urged to perform its own engineering review before deciding on a particular application. micro linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of micro linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual prop erty right. micro linear products are not designed for use in medical, life saving, or life sustaining applications.

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