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TC9WMB4FU 2007-10-19 1 toshiba cmos digital integrated circuits silicon monolithic TC9WMB4FU TC9WMB4FU: 4096-bit (512 8-bit) 2-wire serial eeprom the TC9WMB4FU is an electrically erasable/programmable nonvolatile memory (eeprom). features ? 2-wire serial interface (i 2 c bus) ? single power supply read: v cc = 1.8 to 5.5 v write: v cc = 2.3 to 5.5 v ? low power consumption: 5 a (in standby state) 0.5 ma (in read state) ? operating frequency: 400 khz (v cc = 2.3 to 5.5 v) ? byte write and page (16-byte) write ? write protection ? sequential read ? write time: 10 ms (v cc = 3.0 to 5.5 v) 12 ms (v cc = 2.3 to 2.7 v) ? write endurance: 10 5 times ? data retention: 10 years ? wide operating temperature range: ? 40 to 85c ? package: sm8 product marking pin assignment (top view) weight: 0.02 g (typ.) 8 scl sda 76 5 1234 gnd a1 v cc wp nc a2 part number sm8 wmb4 pin 1 index lotno.
TC9WMB4FU 2007-10-19 2 block diagram pin function pin name input/output description scl input serial clock input data is latched on the rising edge of scl and transferred the falling edge of scl. sda input/output serial input/output this pin must be pulled up with a resist or because it is configured as an n-ch open-drain pin for output. wp input write protection input a high on this input disables writing. a low on this input enables writing. a1, a2 input address input this pin is used to c onfigure the slave address. nc ? no connection (not connected internally) v cc 1.8 to 5.5 v (for reading) 2.3 to 5.5 v (for writing) gnd power supply 0 v (gnd) control circuit power supply (booster circuit) memory cell data register timing generator address register address inputs a1 a2 input/output circuit v cc power supply write protection input wp gnd ground command register serial input/output sda serial clock input scl address decoder
TC9WMB4FU 2007-10-19 3 functional description 1. start and stop conditions when scl is high, pulling sda low produces a star t condition and pulling sda high produces a stop condition. every instruction is started when a start co ndition occurs and terminat ed when a stop condition occurs. during a read, a stop condition causes the read to terminate and the device to enter the standby state. during a write, a stop condition causes the fetching of write data to terminate, after which writing starts automatically. upon the completion of writin g, the device enters the standby state. start conditions of five times or more cannot be genera ted from stop condition to the next stop condition. 2. modifying data data on the sda input can be modified while scl is low. when scl is high, modifying the sda input means a start or stop condition. scl t su.dat t hd.dat sda modify data modify data figure 2 figure 1 scl t hd.sta t su.sto sda start condition stop condition t su.sta
TC9WMB4FU 2007-10-19 4 3. acknowledge data is transmitted in 8-bit units. the device se nds ?low? of an acknowle dge signal, by pulling sda during the 9th clock cycle, indicating that it has received data normally. the host releases the bus in the 9th clock cycle to receive an acknowledge signal. during a write operations, the device is always the re ceiver so that an acknowle dge signal is sent each time it has received 8-bit of data. during a read operations, the device sends an acknowledge signal after it receives an address following a start condition. then, a read data is sent and releases the bus to wait for an acknowledge signal from the master. when an acknowledge signal is detected, next address data is sent if a stop condition is not detected. if the device does not detect an acknowledge signal, a read operations is stopped, and enters the standby mode when a stop condition occurs subsequently. if the device does not detect an acknowledge signal nor a stop condition, it keeps the bus released. 4. device addressing after a start condition occurs, 7-bit device address and a 1-bit read/write instruction code are transferred to the device. the first four bits are called device code, which must always be ?1?, ?0?, ?1?,?0?. the next two bits are called slave address and are used to select a device on the bus. the slave address is compared to the value on the address inputs (a1 an d a2). the next bit is called page addr ess (p0). p0 on ?0? selects the memory area of the first 2k-bit (000 to 0ff) and on ?1? select s the memory area of the last 2k-bit (100 to 1ff). the least significant bit ( wr/ : write read/ ) indicates a read instruction when set to ?1? and a write instruction when set to ?0?. an instruction is not executed if the device address does not match the specified value. figure 3 scl t aa sda (input) acknowledge output 1 8 9 sda (output) start condition t dh figure 4 1 0 1 0 a2 a1 p0 w/r msd lsb device code device address read/write instruction code slave address page address
TC9WMB4FU 2007-10-19 5 5. write operation (1) byte write a data is written to the specified address at a byte write operation. after a start condition, a device address, wr/ ( = 0), a word address, and write data are received to the device. when a stop condition is generated subsequently, write operation starts automatically, rewriting the data at the specified address with the input data. a next instruction cannot be received while write operation is in progress. th erefore, no acknowledge signal is returned. after writing the data, the device automatically en ters the standby state. (2) page write a data is written up to16 bytes to the specified page at a page write operation. after a start condition, a device address, wr/ ( = 0), a word address (n), and writ e data (n) are received to the device, in the same way as for a byte write operation. then, write data (n + 1) is immediately received without entering a stop condition, while checking that an acknowledge signal is asserted (0). the first four bits (w4 to w7) of the word addre ss are the same and the lower four bits (w0 to w3) are automatically incremented so that up to 16 bytes of data can be written. when the last address within the page is reached, the lower four bits (w0 to w3) of the word address are rolled over to the first address of th e page. if more than 16 bytes of write data are transferred, the last 16 bytes are valid. when a stop condition is generated subsequently, write operation starts automatically, rewriting the data at the specified addresses with the input data. figure 6 sda line 1 0 1 0 0 w 6 w 4 w 5 w 3 w 1 w 2 w 0 d 7 d 6 d 4 d 5 d 3 d 1 d 2 d 0 d 7 d 6 d 4 d 5 d 3 d 1 d 2 d 0 d 4 d 5 d 3 d 1 d 2 d 0 s t a r t m s b device address w r i t e l s b a c k r / w w 7 word address (n) a c k a c k write data (n) write dat a (n + 1) a c k write data (n + m) s t o p a c k address increment address increment address increment a 2 a 1 p 0 figure 5 sda line 1 0 1 0 0 w 6 w 4 w 5 w 3 w 1 w 2 w 0 d 7 d 6 d 4 d 5 d 3 d 1 d 2 d 0 s t a r t m s b device address w r i t e l s b a c k r / w w 7 word address a c k a c k write data s t o p address increment m s b l s b a 2 a 1 p 0
TC9WMB4FU 2007-10-19 6 (3) acknowledge polling acknowledge polling is a feature for determining wh ether rewrite operation is in progress. during rewrite operation, generate a start condition followed by a device address, and wr/ ( = 0 or 1). the acknowledge feature does not genera te an acknowledge signal while re write operation is in progress. a low acknowledge signal is generated if rewriting has already completed. if the next instruction is a write, supply a word address and write data subsequently. if the next instruction is a read, supply a stop condition and then start read operation. (4) write protection when ?high? is received to the write protection (wp) pin, the device caused to protect the bottom half (100h to 1ffh) of the memory area from being written. rewriting is allowed when ?low? is received to the write protection pi n. while a write is in progress, driving the wp pin high does not stop write operation. reading is always enabled regardless of whether the wp pin is high or low. 6. read operation read operation is performed in one of three modes: current address read, random read, and sequential read. for reading, a device receives a device address and wr/ (= 1) after a start condition. after read data is sent, terminate a read operation by generating a high acknowledge signal (or releasing the bus without supplying an acknowledge signal) and then supplying a stop condition. (1) current address read the internal address counter maintains the addre ss that is next to the last accessed (read or written) word address (n). in current address read mode, data is read from address n + 1, as indicated by the address counter. in current address read mode, supplying a device address and wr/ (= 1) after a start condition, causes the device to generate a low acknowledge si gnal and send a data at the address indicated by the internal address counter. in this case, the page address bit (p0) is ignored and a data is read at the current address indicated by the internal address counter. the address counter is incremented on the falling edge of the scl pu lse where a data at the eighth bit is sent. if the previous operation was reading da ta from the last address, the current address is rolled over to address 0. if the pr evious operation was writing data to the last address of the page, the address is rolled over to the first address of the page. the current address is maintained in an internal regi ster so that it is lost when the power is turned off. for the first read after power-up, specify an address by performing a random read. figure 7 sda line 1 0 1 0 1 d 6 d 4 d 5 d 3 d 1 d 2 d 0 s t a r t m s b device address r e a d l s b a c k r / w d 7 read dat a s t o p n o a c k address increment a 1 a 2
TC9WMB4FU 2007-10-19 7 (2) random read a random read reads data at a specified address. a dummy write is necessary to specify an address. in random read mode, supply a device address, wr/ (= 0), and a word address after a start condition. unlike a byte or page write, where writ e data is supplied immediately, a dummy write only specifies a word address. then, supply a start condition and transfer a device address and wr/ ( = 1) in the same way as for a current address read , to read data from the specified address. (3) sequential read a sequential read reads data sequentially from successive word addresses. for either current address read or random read, up on receiving a start condition, a device address and r/w ( = 1), an acknowledge (low) is placed on the sda line, followed by th e data at the address pointed to by the internal address counter. when an acknowledge (low) is then received, the word address is automatically incremented so that the next data is driven out. after the last address is reached, the wo rd address is rolled over to address 0. figure 9 sda line 1 d 6 d 4 d 5 d 3 d 1 d 2 d 0 d 7 d 6 d 4 d 5 d 3 d 1 d 2 d 0 d 7 d 6 d 4 d 5 d 3 d 1 d 2 d 0 d 4 d 5 d 3 d 1 d 2 d 0 device address r e a d a c k r / w d 7 a c k s t o p data (n) read data (n) data (n + 1) read data (n + 1) a c k data (n + 2) read data (n + 2) a c k d 7 d 6 data (n + m) read data (n + m) n o a c k address increment address increment address increment address increment figure 8 sda line 1 010 0 w 6 w 4 w 5 w 3 w 1 w 2 w 0 s t a r t m s b device address w r i t e l s b a c k r / w w 7 word address (n) a c k a c k d 7 d 6 d 4 d 5 d 3 d 1 d 2 d 0 data (n) s t o p l s b m s b 1010 1 s t a r t m s b device address r e a d l s b read data (n) n o a c k address increment dummy write a 2 a 1 p 0 a 2 p 0 a 1
TC9WMB4FU 2007-10-19 8 7. notes on use (1) powering up the device this device contains a power-on clear circuit, wh ich initializes the internal circuit of the device when the power is turned on. after initialization, the address counter returns to the first address 00h and the sda pin goes to the high-impedance state (sta ndby state). if initialization fails, the device may malfunction. when powering up the device, obse rve the following precauti ons to assure that the clear circuit will operate normally: (a) pull scl and sda high. (b) the power rising time (t r ) must be 10 ms or less. (c) after turning off the power, wait at least 100 ms (t off ) before attempting to power up the device again. (d) the supply voltage must rise from a voltage lower than 0.1 v. (e) after turning on the power, wait at least 10 ms before attempting to send an instruction to the device. (2) pulling up the sda and scl pins the device requires the sda and scl pins to be pulled up with an external resistor. the recommended pull-up resistance range is 1 k to 10 k . (3) noise elimination time for the sda and scl pins the device contains a low-pass filter for eliminat ing noise on the sda and scl pins. its guaranteed value corresponds to the noise suppression time ti, given in the ac characteristics table. (4) write operation (a) the address counter is increm ented when a write instruction is received successfully. it is incremented on the falling edge of the scl puls e where the least significant bit of data is received. increment d1 d0 figure 11 increment timing diagram figure 10 t off t r 0 v 10 ms v cc v cc 0.1 v max
TC9WMB4FU 2007-10-19 9 (b) if a start condition is issued while the device is receiving a write inst ruction (device address, r/w, address, and data), this wr ite instruction is discarded and th e next instruction is accepted. (a byte write is given below as an exampl e. this is the same as a page write.) (c) if a stop condition is issued while the device is receiving a write inst ruction (device address, r/w, address, and data), the device enters the standby state. however, the device ignores the stop condition while sending an acknowledge signal after it receives the d0 bit. (a write operation starts.) (a byte write is given below as an exampl e. this is the same as a page write.) (d) no instruction is accepted while a write operatio n is in progress (after a stop condition for a write instruction is received). ( the device does not receive a start or stop condition during this time. ) (5) read operation (a) the address counter is incremen ted when a read instruction is received successfully. it is incremented on the falling edge of the scl puls e where the least significant bit of data is driven. (b) if a start condition is issued while the device is receiving a read instruction (device address, r/w, address, or data), this read instruction is discarded and the next instruction is accepted. (a start condition is accepted even during data transfer.) ( a current address read is given below as an example. this is the same as the other read modes. ) incremented. start device address r/w ack address ack data ack stop write instruction address counter is not incremented during this period. incremented. start device address r/w ack address ack data ack stop write instruction address counter is not incremented during this period. a write operation starts. increment d1 d0 figure 12 increment timing diagram incremented. start device address r/w ack data nack stop read instruction address counter is not incremented during this period.
TC9WMB4FU 2007-10-19 10 (c) if a stop condition is issued while data is read (device address, r/w, address, and data), the device enters the standby state. ( a stop condition is accepted even during data transfer. ) ( a current address read is given below as an example. this is the same as the other read modes. ) (d) if a start condition is issued while data is read , the sda pin changes from output to input mode and the device is ready to accept the next instruction. (6) software reset the device cannot be reset externally because it does not incorporate a reset pin. instead, the device is reset by software. the software resets th e device to the same state using the power-on clear circuit. the address counter returns to the fi rst address 00h and the sda pin goes to the high-impedance state (standby state). the software reset is invoked when a start conditio n is generated followed by nine scl clock pulses (dummy cycles). while a dummy cycle is inserted , the sda line must be pulled high. this reset operation stops an acknowledge ou tput and data transfer. the reset is completed by generating another start condition. issue a stop co ndition before starting a new transfer. start conditions of five times or more cannot be generated from stop condition to the next stop condition. incremented. start device address r/w ack data nack stop read instruction address counter is not incremented during this period. scl sda 1 2 8 9 stop condition start condition dummy cycles start condition figure 13 software reset
TC9WMB4FU 2007-10-19 11 absolute maximum ratings (note) (gnd = 0 v) characteristics symbol rating unit supply voltage v cc ? 0.3 to 7.0 v input voltage v in ? 0.3 to v cc + 0.3 v output voltage v out ? 0.3 to v cc + 0.3 v power dissipation p d 300 (25c) mw storage temperature t stg ? 55 to 125 c operating temperature t opr ? 40 to 85 c note: exceeding any of the absolute maximum ratings, even br iefly, lead to deterioration in ic performance or even destruction. using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operat ing temperature/current/voltage, etc. ) are within the absolute maximum ratings and the operating ranges. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook (?handling precautions?/?derating concept and methods?) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). operating ranges (note) (gnd = 0 v, t opr = ? 40 to 85c) characteristics symbol test condition min max unit supply voltage (for reading) v cc ? 1.8 5.5 v supply voltage (for writing) v cc ? 2.3 5.5 v 2.3 v v cc 5.5 v 0.7 v cc v cc high-level input voltage v ih 1.8 v v cc < 2.3 v 0.8 v cc v cc v 2.3 v v cc 5.5 v 0 0.3 v cc low-level input voltage v il 1.8 v v cc < 2.3 v 0 0.2 v cc v 2.3 v v cc 5.5 v 0 400 operating frequency f scl 1.8 v v cc < 2.3 v 0 100 khz note: the operating ranges must be maintained to ensure the normal oper ation of the device. unused inputs must be tied to either vcc or gnd.
TC9WMB4FU 2007-10-19 12 electrical characteristics dc characteristics (gnd = 0 v, t opr = ? 40 to 85c) 1.8 v cc < 2.3 v 2.3 v cc 3.6 v 4.5 v cc 5.5 v characteristics symbol test condition min max min max min max unit input current i li ? ? 1 ? 1 ? 1 a output leakage current i lo ? ? 1 ? 1 ? 1 a i ol = 3.2 ma ? ? ? 0.4 ? 0.4 low-level output voltage v ol i ol = 1.5 ma ? 0.5 ? ? ? ? v quiescent supply current i cc1 ? ? 5 ? 5 ? 5 a supply current during read i cc2 f = 400 khz ? 0.2 * ? 0.3 ? 0.5 ma supply current during write i cc3 f = 400 khz ? ? ? 1.5 ? 2.5 ma *: f = 100 khz ac characteristics (gnd = 0 v, t opr = ? 40 to 85c) test conditions input rise/fall time 20 ns input/output testing voltage 0.5 v cc output load 100 pf + 1 k pull-up resistor 1.8 v cc < 2.3 v 2.3 v cc 3.6 v 4.5 v cc 5.5 v characteristics symbol min max min max min max unit scl clock frequency f scl 0 100 0 400 0 400 khz scl clock low time t low 4.7 ? 1.2 ? 1.2 ? s scl clock high time t high 4.0 ? 0.6 ? 0.6 ? s noise suppression time t i ? 100 ? 50 ? 50 ns sda output delay t aa 0.1 4.5 0.1 0.9 0.1 0.9 s bus free time t buf 4.7 ? 1.2 ? 1.2 ? s start condition hold time t hd.sta 4.0 ? 0.6 ? 0.6 ? s start condition setup time t su.sta 4.7 ? 0.6 ? 0.6 ? s data input hold time t hd.dat 0 ? 0 ? 0 ? ns data input setup time t su.dat 250 ? 200 ? 200 ? ns scl, sda input rise time t r ? 1.0 ? 0.3 ? 0.3 s scl, sda input fall time t f ? 0.3 ? 0.3 ? 0.3 s stop condition setup time t su.sto 4.7 ? 0.6 ? 0.6 ? s sda output hold time t dh 100 ? 50 ? 50 ? ns v cc r l = 1 k sda c l = 100 pf
TC9WMB4FU 2007-10-19 13 eeprom characteristics (gnd = 0 v, 2.3 v v cc 2.7 v, t opr = ? 40 to 85c) characteristics symbol test condition min typ. max unit write time t wr ? ? ? 12 ms rewrite endurance n ew ? 1 10 5 ? ? times data retention time t ret ? 10 ? ? years eeprom characteristics (gnd = 0 v, 2.7 v < v cc 5.5 v, t opr = ? 40 to 85c) characteristics symbol test condition min typ. max unit write time t wr ? ? ? 10 ms rewrite endurance n ew ? 1 10 5 ? ? times data retention time t ret ? 10 ? ? years capacitance characteristics (ta = 25c) characteristics symbol test condition v cc (v) typ. unit input capacitance c in ? 5 4 pf output capacitance c o ? 5 3 pf
TC9WMB4FU 2007-10-19 14 ac characteristics timing charts figure 15 write cycle timing scl sda (input) d o write data input acknowledge output t wr stop condition start condition figure 14 bus timing scl t f sda (input) sda (output) t high t low t r t su.sta t hd.sta t hd.dat t su.dat t su.sto t aa t dh t buf
TC9WMB4FU 2007-10-19 15 input/output circuits of pins pin type input/output circuit remarks wp a1/a2 input ? scl input ? sda input/output open-drain output
TC9WMB4FU 2007-10-19 16 package dimensions weight: 0.02 g (typ.)
TC9WMB4FU 2007-10-19 17 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software an d systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product?s quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situat ions in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before creating and producing des igns and using, customers mus t also refer to and comply with (a) the latest versions of all re levant toshiba information, including without limitation, this d ocument, the specifications, the data sheets and applic ation notes for product and the precautions and conditions set forth in the ?tosh iba semiconductor reliability h andbook? and (b) the instructions for the applicati on that product will be used with or for. custome rs are solely responsible for all aspects of t heir own product design or applications, incl uding but not limited to (a) determining th e appropriateness of the use of this product in such design or applications; (b) evaluating and det ermining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers? product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document . product is neither intended nor warranted for use in equipment or sy stems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic s ignaling equipment, equipment used to control combustions or explosions, safety devices, elevat ors and escalators, devices related to el ectric power, and equipment used in finance-related fields. do not use product for unintended use unless specifically permitted in thi s document. ? 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