supertex inc. supertex inc. www.supertex.com doc.# dsfp-hv5622 c072313 hv5622 general descriptionthe hv5622 is a low-voltage serial to high-voltage parallel converter with open drain outputs. this device has been designed for use as a driver for ac-electroluminescent displays. it can also be used in any application requiring multiple output high voltage current sinking capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum luorescent, or large matrix lcd displays. this device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. data is shifted through the shift register on the high to low transition of the clock. the hv5622 shifts in the clockwise direction when viewed from the top of the package. a data output buffer is provided for cascading devices. this output relects the current status of the last bit of the shift register. operation of the shift register is not affected by the le (latch enable), bl (blanking), or the pol (polarity) inputs. transfer of data from the shift register to the latch occurs when the le (latch enable) input is high. the data in the latch is stored when le is low. functional block diagram 32-channel serial to parallel converter with open drain outputs pol bl le data in clk data out hv out 1 (outputs 3 to 30 not shown) latch latch hv out 2 hv out 31 hv out 32 latch latch 32-bit shift register features ? processed with hvcmos ? technology ? sink current minimum 100ma ? shift register speed 8.0mhz ? polarity and blanking inputs ? cmos compatible inputs ? forward and reverse shifting options ? diode to vpp allows eficient power recovery downloaded from: http:///
2 supertex inc. www.supertex.com doc.# dsfp-hv5622 c072313 hv5622 pin conigurations 1 44 1 44 6 40 yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww hv5622pg lllllllll cccccccc aaa yy = year sealed ww = week sealed l = lot number a = assembler id c = country of origin* = ?green? packaging *may be part of top marking top marking bottom marking yyww aaa hv5622pj llllllllll ccccccccccc 44-lead pqfp (top view) 44-lead plcc (top view) product marking 44-lead pqfp 44-lead plcc absolute maximum ratings supply voltage, v dd 1 -0.5v to +15v output voltage, v pp 1 -0.5v to +230v logic input levels 1 -0.5v to v dd +0.5v ground current 2 1.5a continuous total power dissipation 3 1200mw operating temperature range -40 o c to +85 o c storage temperature range -65 o c to +150 o c parameter value sym parameter min max units recommended operating conditions v dd logic voltage supply 10.8 13.2 v hv out high voltage output -0.3 +220 v v ih input high voltage v dd -2.0 v dd v v il input low voltage 0 2.0 v f clk clock frequency - 8.0 mhz t a operating free-air temperature -40 +85 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. notes: 1. all voltages are referenced to v ss 2. duty cycle is limited by the total power dissipated in the package 3. for operation above 25c ambient derate linearly to maximum operating temperature at 20mw/c. power-up sequencepower-up sequence should be the following: 1. connect ground 2. apply v dd 3. set all inputs to a known state power-down sequence should be the reverse of the above. package may or may not include the following marks: si or package may or may not include the following marks: si or ordering information part number package packing HV5622PG-G 44-lead pqfp 96/tray HV5622PG-G m919 44-lead pqfp 500/reel hv5622pj-g 44-lead plcc 27/tube hv5622pj-g m903 44-lead plcc 500/reel typical thermal resistance package ja 44-lead pqfp 51 o c/w 44-lead plcc 37 o c/w -g denotes a lead (pb)-free / rohs compliant package downloaded from: http:///
3 supertex inc. www.supertex.com doc.# dsfp-hv5622 c072313 hv5622 input and output equivalent circuits vdd data in hv out logic inputs dataout logic data output high voltage outputs vdd hv in vss vss vss sym parameter min max units conditions electrical characteristics (over recommended operating conditions unless otherwise noted) dc characteristics ac characteristics (v dd = 12v, t c = 25 o c) sym parameter min max units conditions f clk clock frequency - 8.0 mhz --- t w clock width, high or low 62 - ns --- t su data set-up time before clk falls 25 - ns --- t h data hold time after clk falls 10 - ns --- t on turn-on time, hv out from enable - 500 ns r l = 2.0k to v pp max. t dhl delay time clock to data high to low - 100 ns c l = 15pf t dlh delay time clock to data low to high - 100 ns c l = 15pf t dle delay time clock to le low to high 50 - ns --- t wle width of le pulse 50 - ns --- t sle le setup time before clock falls 50 - ns --- i dd v dd supply current - 15 ma f clk = 8.0mhz, f data = 4.0mhz i ddq v dd supply current (quiescent) - 100 a d in = 0v, all outputs off i o(off) off state output current - 10 a all outputs high, all sws parallel i ih high-level logic input current - 1.0 a v ih = v dd i il low-level logic input current - -1.0 a v il = 0v v oh high-level output data out v dd -1.0v - v i dout = -100a v ol low-level output voltage hv out - 15 v i hvout = +100ma data out - 1.0 v i dout = +100a v oc hv out clamp voltage - -1.5 v i ol = -100ma downloaded from: http:///
4 supertex inc. www.supertex.com doc.# dsfp-hv5622 c072313 hv5622 switching waveforms le hv out w/ s/r high data valid 50% 50% data in cl k data ou t 50% 50% 50% t su t h t wh t wl 50% 50% t dlh t dhl 50% t wle t dle t sle 50% 50% 10% t on v ih v il v ih v il v oh v ol v oh v ol v ih v il v oh v ol functional table function inputs outputs data clk le bl pol shift reg hv outputs data out * 1 2...32 1 2...32 all on x x x l l * *...* on on...on * all off x x x l h * *...* off off...off * invert mode x x l h l * *...* * *...* * load s/r h or l l h h h or l *...* * *...* * load latches x h or l h h * *...* * *...* * x h or l h l * *...* * *...* * transparent latch mode l h h h l *...* off *...* * h h h h h *...* on *...* * notes: h = high level, l = low level, x = irrelevant, = high-to-low transition, = low-to-high transisti on. * dependent on previous stages state before the last clk or last le high. downloaded from: http:///
5 supertex inc. www.supertex.com doc.# dsfp-hv5622 c072313 hv5622 44-lead pqfp pin description pin # function description 1 hv out 22 high voltage outputs. 2 hv out 21 3 hv out 20 4 hv out 19 5 hv out 18 6 hv out 17 7 hv out 16 8 hv out 15 9 hv out 14 10 hv out 13 11 hv out 12 12 hv out 11 13 hv out 10 14 hv out 9 15 hv out 8 16 hv out 7 17 hv out 6 18 hv out 5 19 hv out 4 20 hv out 3 21 hv out 2 22 hv out 1 23 data out data output pin. 24 n/c no internal connection. 25 n/c 26 n/c 27 pol inverts the polarity of the hv out pins 28 clk clock pin, shift registers shifts data on falling edge of input clock. 29 vss reference voltage, usually ground. 30 vdd logic supply voltage. 31 le latch enable pin, data is shifted from shift register to latches on logic input high. 32 data in data input pin. 33 bl blanking pin sets all hv out pins low or high depending upon state of polarity. see function table. 34 n/c no internal connection. 35 hv out 32 high voltage outputs. 36 hv out 31 37 hv out 30 38 hv out 29 39 hv out 28 40 hv out 27 41 hv out 26 42 hv out 25 43 hv out 24 44 hv out 23 downloaded from: http:///
6 supertex inc. www.supertex.com doc.# dsfp-hv5622 c072313 hv5622 44-lead plcc pin description pin # function description 1 hv out 17 high voltage outputs. 2 hv out 16 3 hv out 15 4 hv out 14 5 hv out 13 6 hv out 12 7 hv out 11 8 hv out 10 9 hv out 9 10 hv out 8 11 hv out 7 12 hv out 6 13 hv out 5 14 hv out 4 15 hv out 3 16 hv out 2 17 hv out 1 18 data out data output pin. 19 n/c no internal connection. 20 n/c 21 n/c 22 pol inverts the polarity of the hv out pins 23 clk clock pin, shift registers shifts data on falling edge of input clock. 24 vss reference voltage, usually ground. 25 vdd logic supply voltage. 26 le latch enable pin, data is shifted from shift register to latches on logic input high. 27 data in data input pin. 28 bl blanking pin sets all hv out pins low or high depending upon state of polarity. see function table. 29 n/c no internal connection. 30 hv out 32 high voltage outputs. 31 hv out 31 32 hv out 30 33 hv out 29 34 hv out 28 35 hv out 27 36 hv out 26 37 hv out 25 38 hv out 24 39 hv out 23 40 hv out 22 41 hv out 21 42 hv out 20 43 hv out 19 44 hv out 18 downloaded from: http:///
7 supertex inc. www.supertex.com doc.# dsfp-hv5622 c072313 hv5622 44-lead pqfp package outline (pg) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* 0.80 bsc 0.73 1.95 ref 0.25 bsc 0 o nom - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5 o max 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7 o jedec registration mo-112, variation aa-2, issue b, sep.1995. * this dimension is not speciied in the jedec drawing. drawings not to scale. supertex doc. #: dspd-44pqfppg, version c041309. 1 44 view b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) vi ew b seating plane gauge plane l l1 l2 1 note: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 8 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to: http://www.supertex.com/packaging.html .) doc.# dsfp-hv5622 c072313 hv5622 44-lead plcc package outline (pj) .653x.653in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e r dimension (inches) min .165 .090 .062 .013 .026 .685 .650 .685 .650 .050 bsc .025 nom .172 .105 - - - .690 .653 .690 .653 .035 max .180 .120 .083 .021 .036 ? .695 .656 .695 .656 .045 jedec registration ms-018, variation ac, issue a, june, 1993. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-44plccpj, version f031111. 1 64 0 44 .150max .048/.042 x 45 o d d1 e1 e top vi ew view b a a2 a1 seating plane .056/.042 x 45 o base plane .020min b vi ew b b1 horizontal side view vertical side vi ew .020max(3 places) r e note 1 (index area) note 2 .075max notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. actual shape of this feature may vary. downloaded from: http:///
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