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general description the ds75lv low-voltage (1.7v to 3.7v) digital thermometer and thermostat provides 9, 10, 11, or 12-bit digital temperature readings over a -55c to +125c range with 2c accuracy over a -25c to +100c range. at power-up, the ds75lv defaults to 9-bit resolution for software compatibility with the lm75. communication with the ds75lv is achieved through a simple 2-wire serial interface. the ds75lv thermostat has a dedicated open-drain output (os) and programmable fault tolerance, which allows the user to define the number of consecutive error conditions that must occur before os is activated. there are two thermostatic operating modes that control thermostat operation based on user-defined trip-points (t os and t hyst ). applications personal computers cellular base stations ofice equipment any thermally sensitive system beneits and features extend performance range with low-voltage, 1.7v to 3.7v operating range maximize system accuracy in broad range of thermal management applications ? measures temperature from -55c to +125c (-67f to +257f) ? 2c accuracy over a -25c to 100c range ? user-conigurable resolution from 9 bits (default) to 12 bits (0.5c to 0.0625c) easy upgrade to lm75: pin and software compatible simplify distributed temperature-sensing applications with multidrop capability ? up to eight ds75lvs can operate on 2-wire bus increase reliability and system robustness ? internally filtered data lines for noise immunity (50ns deglitch) ? bus timeout feature prevents lockup on 2-wire interface minimize power consumption with built-in shutdown mode flexible user-defined thermostatic modes with programmable fault tolerance ordering information appears at end of data sheet. 19-7469; rev 4; 3/16 ds75lv digital thermometer and thermostat functional block diagram tos and thyst registers configuration register temperature register oversampling modulator precision reference digital decimator address and i/o control a1a2 a0 scl sda v dd gnd thermostat comparator r p os ds75lv downloaded from: http:///
voltage on v dd , relative to ground .................... -0.3v to +4.0v voltage on any other pin, relative to ground .... -0.3v to +6.0v operating temperature range ......................... -55c to +125c storage temperature range ............................ -55c to +125c lead temperature (soldering, 10s) ................................. +260c (1.7v v dd 3.7v, t a = -55c to +125c, unless otherwise noted.) (1.7v v dd 3.7v, t a = -55c to +125c, unless otherwise noted.) parameter symbol conditions min max units supply voltage v dd 1.7 3.7 v thermometer error (note 1) t err -25 to +100 2.0 c -55 to +125 3.0 input logic-high v ih (note 2) 0.7 x v dd 5.5 v input logic-low v il (note 2) -0.5 0.3 x v dd v sda output logic low voltage (note 2) v ol1 3ma sink current 0 0.4 v v ol2 6ma sink current 0 0.6 os saturation voltage v ol 4ma sink current (notes 1, 2) 0.8 v input current each i/o pin 0.4 < v i/o < 0.9 x v dd -10 +10 a i/o capacitance c i/o 10 pf standby current i dd1 (notes 3, 4) 2 a active current (notes 3, 4) i dd active temp conversions 1000 a communication only 100 parameter symbol conditions min typ max units resolution 9 12 bits temperature conversion time t convt 9-bit conversions 25 ms 10-bit conversions 50 11-bit conversions 100 12-bit conversions 200 scl frequency f scl 400 khz bus free time between a stop and start condition t buf (note 5) 1.3 s start and repeated start hold time from falling scl t hd:sta (notes 5, 6) 600 ns ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristicsac electrical characteristics downloaded from: http:///
(1.7v v dd 3.7v, t a = -55c to +125c, unless otherwise noted.) note 1: internal heating caused by os loading causes the ds75lv to read approximately 0.5c higher if os is sinking the max rated current. note 2: all voltages are referenced to ground. note 3: i dd specified with v dd at 3.0v and sda, scl = 3.0v, 0c to +70c. note 4: i dd specified with os pin open. note 5: see figure 2 for timing diagram. all timing is referenced to 0.9 x v dd and 0.1 x v dd . note 6: after this period, the first clock pulse is generated. note 7: the ds75lv provides an internal hold time of at least 75ns on the sda signal to bridge the undefined region of scls falling edge. note 8: this timeout applies only when the ds75lv is holding sda low. other devices can hold sda low indefinitely and the ds75lv does not reset. parameter symbol conditions min typ max units low period of scl t low (note 5) 1.3 s high period of scl t high (note 5) 0.6 s repeated start condition setup time to rising scl t su:sta (note 5) 600 ns data-out hold time from falling scl t hd:dat (notes 5, 7) 0 0.9 s data-in setup time to rising scl t su:dat (note 5) 100 ns rise time of sda and scl (receive) t r (note 5) 1000 ns fall time of sda and scl (receive) t f (note 5) 300 ns spike suppression filter time (deglitch filter) t ss 0 50 ns stop setup time to rising scl t su:sto (note 5) 600 ns capacitive load for each bus line c b 400 pf input capacitance c i 5 pf serial interface reset time t timeout sda time low (note 8) 75 325 ms ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 3 ac electrical characteristics (continued) downloaded from: http:///
pin description figure 1. block diagram figure 2. timing diagram pin name function 1 sda data input/output. for 2-wire serial communication port. open drain. 2 scl clock input. 2-wire serial communication port. 3 os thermostat output. open drain. 4 gnd ground 5 a2 address input 6 a1 address input 7 a0 address input 8 v dd supply voltage. +1.7v to +3.7v supply pin. tos and thyst registers configuration register temperature register oversampling modulator precision reference digital decimator address and i/o control a1a2 a0 scl sda v dd gnd thermostat comparator r p os ds75lv sda scl t f t r t su;dat t low s t hd;sta t hd;dat t f t su;sta t hd;sta t su;sto t r t buf t sp sr p s ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 4 downloaded from: http:///
detailed description measuring temperature the ds75lv measures temperature using a bandgap temperature sensing architecture. an on-board delta-sigma analog-to-digital converter (adc) converts the measured temperature to a digital value that is calibrated in degrees centigrade; for fahrenheit applications a lookup table or conversion routine must be used. the ds75lv is factory- calibrated and requires no external components to measure temperature. at power-up the ds75lv immediately begins converting temperature to a digital value. the resolution of the digital output data is user-configurable to 9, 10, 11, or 12 bits, corresponding to temperature increments of 0.5c, 0.25c, 0.125c, and 0.0625c, respectively, with 9-bit default resolution at power-up. the resolution is controlled via the r0 and r1 bits in the configuration register as explained in the configuration register section. note that the conversion time doubles for each additional bit of resolution. after each temperature measurement and analog-to-digital conversion, the ds75lv stores the temperature as a 16-bit twos complement number in the 2-byte temperature register (see figure 3 ). the sign bit (s) indicates if the temperature is positive or negative: for positive numbers s = 0 and for negative numbers s = 1. the most recently converted digital measurement can be read from the temperature register at any time. since temperature conversions are performed in the background, reading the temperature register does not affect the operation in progress. bits 3 through 0 of the temperature register are hardwired to 0. when the ds75lv is configured for 12-bit resolution, the 12 msbs (bits 15 through 4) of the temperature register contain temperature data. for 11-bit resolution, the 11 msbs (bits 15 through 5) of the temperature register contain data, and bit 4 reads out as 0. likewise, for 10-bit resolution, the 10 msbs (bits 15 through 6) contain data, and for 9-bit the 9 msbs (bits 15 through 7) contain data, and all unused lsbs contain 0s. table 1 gives examples of 12-bit resolution digital output data and the corresponding temperatures. table 1. 12-bit resolution temperature/ data relationship figure 3. temperature, t os , and t hyst register format temperature (c) digital output (binary) digital output (hex) +125 0111 1101 0000 0000 7d00h +25.0625 0001 1001 0001 0000 1910h +10.125 0000 1010 0010 0000 0a20h +0.5 0000 0000 1000 0000 0080h 0 0000 0000 0000 0000 0000h -0.5 1111 1111 1000 0000 ff80h -10.125 1111 0101 1110 0000 f5e0h -25.0625 1110 0110 1111 0000 e6f0h -55 1100 1001 0000 0000 c900h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ms byte s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ls byte 2 -1 2 -2 2 -3 2 -4 0 0 0 0 ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 5 downloaded from: http:///
shutdown mode for power-sensitive applications, the ds75lv offers a low-power shutdown mode. the sd bit in the configuration register controls shutdown mode. when sd is changed to 1, the conversion in progress is completed and the result stored in the temperature register after which the ds75lv goes into a low-power standby state. the os output is cleared if the thermostat is operating in interrupt mode and os remains unchanged in comparator mode. the 2-wire interface remains operational in shut - down mode, and writing a 0 to the sd bit returns the ds75lv to normal operation. thermostat the ds75lv thermostat has two operating modes, com - parator mode and interrupt mode, which activate and deactivate the open-drain thermostat output (os) based on user-programmable trip-points (t os and t hyst ). the ds75lv powers up with the thermostat in comparator mode, active-low os polarity, over-temperature trip-point (t os ) register set to 80c, and the hysteresis trip-point (t hyst ) register set to 75c. if these power-up settings are compatible with the application, the ds75lv can be used as a standalone thermostat (i.e., no 2Cwire com - munication required). if interrupt mode operation, active- high os polarity or different t os and t hyst values are desired, they must be programmed after power-up, so standalone operation is not possible. in both operating modes, the user can program the ther - mostat fault tolerance, which sets how many consecutive temperature readings (1, 2, 4, or 6) must fall outside of the thermostat limits before the thermostat output is trig - gered. the fault tolerance is set by the f1 and f0 bits in the configuration register. at power-up the fault tolerance is set to 1. the data format of the t os and t hyst registers is identical to that of the temperature register (see figure 3 ), i.e., a 2-byte twos complement representation of the trip-point temperature in degrees centigrade with bits 3 through 0 hardwired to 0. after every temperature conversion, the measurement is compared to the values stored in the t os and t hyst registers. the os output is updated based on the result of the comparison and the operating mode of the ic. the number of t os and t hyst bits used during the thermostat comparison is equal to the conversion resolution set by the r1 and r0 bits in the configuration register. for example, if the resolution is 9 bits, only the 9 msbs of t os and t hyst are used by the thermostat comparator. the active state of the os output can be changed via the pol bit in the configuration register. the power-up default is active low. if the user does not wish to use the thermostat capabilities of the ds75lv, the os output should be left floating. note that if the thermostat is not used, the t os and t hyst registers can be used for general storage of system data. comparator mode: when the thermostat is in compara - tor mode, os can be programmed to operate with any amount of hysteresis. the os output becomes active when the measured temperature exceeds the t os value a consecutive number of times as defined by the f1 and f0 fault tolerance (ft) bits in the configuration register. os then stays active until the first time the temperature falls below the value stored in t hyst . putting the device into shutdown mode does not clear os in comparator mode. thermostat comparator mode operation with ft = 2 is illustrated in figure 4 . interrupt mode: in interrupt mode, the os output first becomes active when the measured temperature exceeds the t os value a consecutive number of times equal to the ft value in the configuration register. once activated, os can only be cleared by either putting the ds75lv into shutdown mode or by reading from any register (temperature, configuration, t os , or t hyst ) on the device. once os has been deactivated, it is only reactivated when the measured temperature falls below the t hyst value a consecutive number of times equal to the ft value. again, os can only be cleared by putting the device into shut - down mode or reading any register. thus, this interrupt/ clear process is cyclical between t os and t hyst events (i.e, t os , clear, t hyst , clear, t os , clear, t hyst , clear, etc.). thermostat interrupt mode operation with ft = 2 is illustrated in figure 4 . ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 6 downloaded from: http:///
coniguration register the configuration register allows the user to program various ds75lv options such as conversion resolution, thermostat fault tolerance, thermostat polarity, thermostat operating mode, and shutdown mode. the configuration register is arranged as shown in figure 5 and detailed descriptions of each bit are provided in table 2 . the user has read/write access to all bits in the configuration register except the msb, which is a reserved read-only bit. the entire register is volatile, and thus powers up in its default state. figure 4. os output operation example figure 5. configuration register in this example the ds75lvis configured to have a fault tolerance of 2. os output - comparator mode conversions inactive active temperature t os t hyst inactive active os output - interrupt mode assumes a read has occurred msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb 0 r1 r0 f1 f0 pol tm sd ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 7 downloaded from: http:///
table 2. configuration register bit descriptions table 3. resolution configuration table 5. register pointer definition table 4. fault tolerance configuration f1 f0 consecutive out-of-limits conversions to trigger os 0 0 1 0 1 2 1 0 4 1 1 6 bit name function 0reserved power-up state = 0the master can write to this bit, but it will always read out as a 0. r1conversion resolution bit 1 power-up state = 0 sets conversion resolution (see table 3) r0conversion resolution bit 0 power-up state = 0 sets conversion resolution (see table 3) f1 thermostat fault tolerance bit 1 power-up state = 0 sets the thermostat fault tolerance (see table 4). f0 thermostat fault tolerance bit 0 power-up state = 0 sets the thermostat fault tolerance (see table 4). polthermostat output (os) polarity power-up state = 0 pol = 0 os is active low. pol = 1 os is active high. tmthermostat operating mode power-up state = 0tm = 0 comparator mode tm = 1 interrupt mode see the thermostat section for a detailed description of these modes. sdshutdown power-up state = 0 sd = 0 active conversion and thermostat operation. sd = 1 shutdown mode. see the shutdown mode section for a detailed description of this mode. r1 r0 thermometer resolution max conversion time ( ms) 0 0 9-bit 25 0 1 10-bit 50 1 0 11-bit 100 1 1 12-bit 200 register p1 p0 temperature 0 0 coniguration 0 1 t hyst 1 0 t os 1 1 ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 8 downloaded from: http:///
register pointer the four ds75lv registers each have a unique 2-bit pointer designation, which is defined in table 5 . when reading from or writing to the ds75lv, the user must point the ds75lv to the register that is to be accessed. when reading from the ds75lv, once the pointer is set, it remains pointed at the same register until it is changed. for example, if the user desires to perform consecutive reads from the temperature register, then the pointer only has to be set to the temperature register one time, after which all reads are automatically from the temperature register until the pointer value is changed. when writing to the ds75lv, the pointer value must be refreshed each time a write is performed, even if the same register is being written to twice in a row. at power-up, the pointer defaults to the temperature register location. the temperature register can be read immediately without resetting the pointer. changes to the pointer setting are accomplished as described in the 2-wire serial data bus section of this data sheet. 2-wire serial data bus the ds75lv communicates over a standard bidirectional 2-wire serial data bus that consists of a serial clock (scl) signal and serial data (sda) signal. the device interfaces to the bus via the scl input pin and open-drain sda i/o pin. all communication is msb first. the following terminology is used to describe 2-wire communication: master device: microprocessor/microcontroller that controls the slave devices on the bus. the master device generates the scl signal and start and stop conditions. slave: all devices on the bus other than the master. the ds75lv always functions as a slave. bus idle or not busy: both sda and scl remain high. sda is held high by a pullup resistor when the bus is idle, and scl must either be forced high by the master (if the scl output is push-pull) or pulled high by a pullup resistor (if the scl output is open-drain). transmitter: a device (master or slave) that is sending data on the bus. receiver: a device (master or slave) that is receiving data from the bus. start condition: signal generated by the master to indicate the beginning of a data transfer on the bus. the master generates a start condition by pulling sda from high to low while scl is high (see figure 6 ). a repeated start is sometimes used at the end of a data transfer (instead of a stop) to indicate that the master will perform another operation. stop condition: signal generated by the master to indicate the end of a data transfer on the bus. the master generates a stop condition by transitioning sda from low to high while scl is high (see figure 6 ). after the stop is issued, the master releases the bus to its idle state. acknowledge (ack): when a device (either master or slave) is acting as a receiver, it must generate an acknowledge (ack) on the sda line after receiving every byte of data. the receiving device performs an ack by pulling the sda line low for an entire scl period (see figure 6 ). during the ack clock cycle, the transmitting device must release sda. a variation on the ack signal is the not acknowledge (nack). when the master device is acting as a receiver, it uses a nack instead of an ack after the last data byte to indicate that it is finished receiv - ing data. the master indicates a nack by leaving the sda line high during the ack clock cycle. slave address: every slave device on the bus has a unique 7-bit address that allows the master to access that device. the ds75lvs 7-bit bus address is 1 0 0 1 a2 a1 a0, where a2, a1, and a0 are user-selectable via the cor - responding input pins. the three address pins allow up to eight ds75lvs to be multi-dropped on the same bus. address byte: the control byte is transmitted by the master and consists of the 7-bit slave address plus a read/write (r/ w ) bit (see figure 7 ). if the master is going to read data from the slave device then r/ w = 1, and if the master is going to write data to the slave device then r/ w = 0. pointer byte: the pointer byte is used by the master to tell the ds75lv which register is going to be accessed during communication. the six msbs of the pointer byte (see figure 8 ) are always 0 and the two lsbs correspond to the desired register as shown in table 5 . ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 9 downloaded from: http:///
general 2-wire information all data is transmitted msb first over the 2-wire bus. one bit of data is transmitted on the 2-wire bus each scl period. a pullup resistor is required on the sda line and, when the bus is idle, both sda and scl must remain in a logic-high state. all bus communication must be initiated with a start condition and terminated with a stop condition. during a start or stop is the only time sda is allowed to change states while scl is high. at all other times, changes on the sda line can only occur when scl is low: sda must remain stable when scl is high. after every 8-bit (1-byte) transfer, the receiving device must answer with an ack (or nack), which takes one scl period. therefore, nine clocks are required for every one-byte data transfer. writing to the ds75lv: to write to the ds75lv, the master must generate a start followed by an address byte containing the ds75lv bus address. the value of the r/w bit must be a 0, which indicates that a write is about to take place. the ds75lv responds with an ack after receiving the address byte. the master then sends a pointer byte which tells the ds75lv which register is being written to. the ds75lv again responds with an ack after receiving the pointer byte. following this ack the master device must immediately begin transmitting data to the ds75lv. when writing to the configuration register, the master must send one byte of data (see figure 9 b ), and when writing to the t os or t hyst registers the master must send two bytes of data (see figure 9 c ). after receiving each data byte, the ds75lv responds with an ack, and the transaction is finished with a stop from the master. figure 6. start, stop, and ack signals figure 7. address byte figure 8. pointer byte scl sda start condition stop condition ack ( or nack ) from receiver bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 0 1 a2 a1 a0 r/ w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 p1 p0 ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 10 downloaded from: http:///
software por: the soft power-on reset (por) com - mand is 54h. the master sends a start followed by an address byte containing the ds75lv bus address. the r/ w bit must be a 0. the ds75lv responds with an ack. if the next byte is a 0x54, the ds75lv resets as if power had been cycled. no ack is sent by the ic after the por command is received. reading from the ds75lv: when reading from the ds75lv, if the pointer was already pointed to the desired register during a previous transaction, the read can be performed immediately without changing the pointer setting. in this case the master sends a start followed by an address byte containing the ds75lv bus address. the r/ w bit must be a 1, which tells the ds75lv that a read is being performed. after the ds75lv sends an ack in response to the address byte, the ds75lv begins trans - mitting the requested data on the next clock cycle. when reading from the configuration register, the ds75lv transmits one byte of data, after which the master must respond with a nack followed by a stop (see figure 9e ). for two-byte reads (i.e., from the temperature, t os or t hyst register), the ds75lv transmits two bytes of data, and the master must respond to the first data byte with an ack and to the second byte with a nack followed by a stop (see figure 9 a ). if only the most significant byte of data is needed, the master can issue a nack followed by a stop after reading the first data byte in which case the transaction is the same as for a read from the configuration register. if the pointer is not already pointing to the desired register, the pointer must first be updated as shown in figure 9 d , which shows a pointer update followed by a single-byte read. the value of the r/ w bit in the initial address byte is a 0 (write) since the master is going to write a pointer byte to the ds75lv. after the ds75lv responds to the address byte with an ack, the master sends a pointer byte that corresponds to the desired register. the master must then perform a repeated start followed by a standard one or two byte read sequence (with r/ w =1) as described in the previous paragraph. bus timeout: the ds75lv has a bus timeout feature that prevents communication errors from leaving the ic in a state where sda is held low disrupting other devices on the bus. if the ds75lv holds the sda line low for a period of t timeout , its bus interface automatically resets and release the sda line. bus communication frequency must be fast enough to prevent a reset during normal operation. the bus timeout feature only applies to when the ds75lv is holding sda low. other devices can hold sda low for an undefined period without causing the interface to reset. ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 11 downloaded from: http:///
figure 9. 2-wire interface timing scl start address byte a) read 2 bytes from the temperature, t os , or t hyst register (current pointer location) sda s 1 0 0 1 a2 a1 a0 r a a n p d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ms data byte (from ds75lv) ls data byte (from ds75lv) ack (ds75lv) ack (master) nack (master) stop scl start address byte e) read from the configuration register (current pointer location) sda s 1 0 0 1 a2 a1 a0 r a n p d7 d6 d5 d4 d3 d2 d1 d0 data byte (from ds75lv) ack (ds75lv) nack (master) stop scl start address byte b) write to the configuration register sda s 1 0 0 1 a2 a1 a0 w a a a p 0 0 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 pointer byte data byte (from master) ack (ds75lv) ack (ds75lv) ack (ds75lv) stop scl start address byte c) write to the t os or t hyst register sda s 1 0 0 1 a2 a1 a0 w a a 0 0 0 0 0 0 p1 p0 d7 d6 d5 d4 d3 d2 d1 d0 pointer byte ms data byte (from master) ack (ds75lv) ack (ds75lv) a a p d7 d6 d5 d4 d3 d2 d1 ls data byte (from master) ack (ds75lv) ack (ds75lv) stop scl start address byte d) read single byte (new pointer location) sda s 1 0 0 1 a2 a1 a0 w a a s 0 0 0 0 0 0 p1 p0 1 0 0 1 a2 a1 a0 pointer byte address byte ack (ds75lv) ack (ds75lv) repeat start r a n p d7 d6 d5 d4 d3 d2 d1 d0 data byte (from ds75lv) ack (ds75lv) nack (master) stop ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 12 downloaded from: http:///
max is a registered trademark of maxim integrated products, inc. +denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. *a + symbol is also marked on the package near the pin 1 indicator. part temp range top mark pin-package ds75lvs+ -55c to +125c ds75l* 8 so ds75lvs+t&r -55c to +125c ds75l* 8 so ds75lvu+ -55c to +125c ds75l 8 sop (max ? ) ds75lvu+t&r -55c to +125c ds75l 8 sop (max) package type package code outline no. land pattern no. 8 so s8+2 21-0141 90-0096 8 max u8+1 21-0036 90-0092 ds75lv digital thermometer and thermostat www.maximintegrated.com maxim integrated 13 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different su ffix character, but the drawing pertains to the package regardless of rohs status. ordering information downloaded from: http:///
revision number revision date description pages changed 0 5/06 initial release 1 11/06 changed the max conversion time for r1 and r0 in table 4 8 2 12/14 updated beneits and features section 1 3 4/15 revised electrical characteristics , table 3, and ordering information 2, 3, 8, 13 4 3/16 updated rise and fall time of scl and sda in electrical characteristics table 3 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ds75lv digital thermometer and thermostat ? 2016 maxim integrated products, inc. 14 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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