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integrated circuit systems, inc. general description features ics9341 block diagram 133mhz clock generator and integrated buffer for powerpc? 9341 rev a 10/12/99 pin configuration 48-pin ssop

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- power groups: 012$012b012$c$c $ b d ..$..b.. *$*b*%&' +0$+0b dd d !/$d !/b !/ d+" $+" b+" pd# cpub_stop# out_sel (0:1) pci_stop# ss_en x1 x2 osc pll spread spectrum ref (0:1) 2 4 4 out out/2 cpuclkb (1:4) cpuclka (1:4) stop c o n t r o l / 2 pll2 8 pciclk (1:8) stop / 8 / 6 / 5 / 4 / 2 / 4 / 5 / 6 / 3 gndref x1 x2 vddpci pciclk1 pciclk2 pciclk3 pciclk4 gndpci gndcpub cpub1 cpub2 cpub3 cpub4 vddcpub vddpci pciclk5 pciclk6 pciclk7 pciclk8 fs0 fs1 *out_sel0 gndpci ref1 ref0 vddref cpua1 cpua2 ss_en gndcpua out_sel1* pd# vddcpua cpua3 cpua4 cpub_stop#** vddd vddout out out/2 gndout gnda gndd n/c n/c *pci_stop# vdda ics9341 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ics9341 pin descriptions pin number pin name type description 1 gndref pwr ground pin for ref clocks. 2 x1 in xtal_in 14.318m hz crystal input. 3 x2 out xtal_out crystal output. 4, 16 vddpci pwr 3.3volts power pin for pciclks. 5, 6, 7, 8, 17, 18, 19, 20 pciclk (1:8) out pci clock output at 3.3v. synchronous to cpu clocks. 9, 24 gndpci pwr ground pin for pci clocks. 10 gndcpub pwr ground pin for cpub clocks. 11, 12, 13, 14 cpub (1:4) out cpuclk outputs up to 133.3mhz. 15 vddcpub pwr power pin for the cpu bank b clks. 3.3v. 21, 22 fs (0:1) in logic - input for frequency selection. 23, 41 *out_sel (0:1) in these control the output functionality of the o ut and o ut/2 pins. refer to table for details. 24 gndpci pwr gnd pin for pciclks. 25 vdda pwr power for analog outputs. 26 *pci_stop# in this active low input stops pci clocks. 27, 28 n/c - not connected 29 gndd pwr digitial ground 30 gnda pwr analog ground 31 gndout pwr ground for output pins. 32 out/2 out h alf the o u t frequency. d ependent on o u t_sel. refer to table for details. 33 out out this output frequency is dependent on ou t_sel. refer to table for details. 34 vddout pwr power for out pins 3.3v. 35 vddd pwr power for digitial outputs. 36 cpub_stop#** in this active low input stops the cpub clocks at a logic "0" level when in p ut low. 45, 44, 38, 37 cpua (1:4) out cpuclk outputs up to 133.3mhz. 39 vddcpua pwr power pin for the cpu bank a clks. 3.3v. 40 pd# in this asynchronous input powers down the chip when drive active(low). the internal plls are disabled and all the output clocks are held at a low state. 42 gndcpua pwr ground pin for cpub clocks. 43 ss_en in spread spectrum is turned on by driving this input high and turned off b y drivin g low. 46 vddref pwr power pin for ref clocks. 47, 48 ref out 14.318mhz reference clock outputs at 3.3v.
ics9341 frequency selection 1 s f0 s f b u p c , a u p c ) z h m ( i c p ) z h m ( f e r ) z h m ( 11 3 . 3 3 13 . 3 38 1 3 . 4 1 10 0 0 13 . 3 38 1 3 . 4 1 01 3 . 3 83 . 3 38 1 3 . 4 1 00 6 . 6 63 . 3 38 1 3 . 4 1 1 l e s _ t u o0 l e s _ t u o t u o ) z h m ( 2 / t u o ) z h m ( 118 44 2 10 0 40 2 014 62 3 00 d e p p o t sd e p p o t s
ics9341 pd# timing diagram ,>

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ics9341 pci_stop# timing diagram a5,+ e
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@ 4 electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2 v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a i dd3.3op66 select @ 66mhz; max discrete cap loads 215 250 ma i dd3.3op83 select @ 83mhz; max discrete cap loads 200 225 ma i dd3.3op100 select @ 100mhz; max discrete cap loads 180 200 ma i dd3.3op133 select @ 133mhz; max discrete cap loads 160 175 ma power down supply curren t i dd3.3pd pd# = 0 160 300 a input frequency f i v dd = 3.3 v 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 13.5 18 22.5 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settlin g time 1 t s from 1st crossing to 1% target freq. 1 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3ms skew 1 t cpua-cpub v t = 1.5 v 100 350 ps skew 1 t cpu-pci v t = 1.5 v 500 800 ps operating supply current input capacitance 1
( ics9341 electrical characteristics - cpua t a = 0 - 70 o c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -8.0 ma 2 2.4 v output low voltage v ol2b i ol = 12 ma 0.32 0.4 v output high current i oh2b v oh =1.7 v -37 -16 ma output low current i ol2b v ol = 0.7 v 19 26 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.4 v 1.5 2.5 ns fall time t f2b 1 v oh = 2.4 v, v ol = 0.4 v 1 2.5 ns duty cycle d t2b 1 vt = 1.5 v 40 50 55 % skew t sk2b 1 vt = 1.5 v 125 175 ps jitter, cycle-to-cycle tj cyc-cyc2b 1 vt = 1.5 v 230 350 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpub t a = 0 - 70 o c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -8.0 ma 2 2.4 v output low voltage v ol2b i ol = 12 ma 0.32 0.4 v output high current i oh2b v oh =1.7 v -37 -16 ma output low current i ol2b v ol = 0.7 v 19 26 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.4 v 1.9 3 ns fall time t f2b 1 v oh = 2.4 v, v ol = 0.4 v 1.6 3 ns duty cycle d t2b 1 vt = 1.5 v 40 49 55 % skew t sk2b 1 vt = 1.5 v 90 175 ps jitter, cycle-to-cycle tj cyc-cyc2b 1 vt = 1.5 v 230 350 ps 1 guaranteed by design, not 100% tested in production.
) ics9341 electrical characteristics - pci t a = 0 - 70 o c; v dd = v ddl = 3.3 v +/-5%; c l =30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.17 0.4 v output high current i oh1 v oh = 2.0 v -60 -22 ma output low current i ol1 v ol = 0.8 v 25 47 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.8 2.5 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.7 2.5 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 150 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 120 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref, out, out/2 t a = 0 - 70 o c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 2.9 v output low voltage v ol5 i ol = 10 ma 0.33 0.4 v output high current i oh5 v oh = 2.0 v -30 -20 ma output low current i ol5 v ol = 0.8 v 16 23 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v; out 1.5 1.8 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v; out 1.5 2 4 ns duty cycle 1 d t5 v t = 1.5 v; out 45 52 55 % rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v; out/2 1.5 2.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v; out/2 1.5 2.1 4 ns duty cycle 1 d t5 v t = 1.5 v; out/2 45 50 55 % rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v; ref 1.5 2.7 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v; ref 1.5 2.8 4 ns duty cycle 1 d t5 v t = 1.5 v; ref 45 50 55 % jitter, cycle-to-cycle1 t j c y c-c y c5 v t = 1.5 v; out, out/2 280 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v; ref 450 1000 ps 1 guaranteed by design, not 100% tested in production.
ics9341 ssop package symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 a2 .088 .090 .092 b .008 .010 .0135 c .005 - .010 d see variations e .292 .296 .299 e 0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9341 y f

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