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| 2 2 - s3 - c72q5/p72q5 - 032002 user's manual s3c72q5/p72q5 4 -bit cmos microcontroller revision 2
s3c72q5/p72q5 4?b it cmos microcontroller user's manual revision 2 important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3c72q5/p72q5 4 -bit cmos microcontroller user's manual, revision 2 publication number: 2 2-s3 - c72q5/p72q5 - 032002 2002 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso-9001 certification (bsi certificate no. fm24653). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, giheung- eup yongin-city, gyeonggi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(031)-209- 1934 fax: (82)-(031)-209-1899 home page: http:// www.samsungsemi.com printed in the republic of korea s3c72q5/p72q5 microcontroller iii preface the s3c72q5/p72q5 microcontroller user's manual is designed for application designers and programmers who are using the s3c72q5/p72q5 microcontroller for application development. it is organized in two parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has five sections: section 1 product overview section 2 address spaces section 3 addressing modes section 4 memory map section 5 sam 48 instruction set section 1, "product overview," is a high-level introduction to the s3c72q5/p72q5, ranging from a general product description to detailed information about pin characteristics and circuit types . section 2, "address spaces," introduces you to the s3c72q5/p72q5 programming model: the program memory (rom) and data memory (ram) structures and how to address them. section 2 also includes information about stack operations, cpu registers, and the bit sequential carrier (bsc) register . section 3, "addressing modes," descriptions types of addressing supported by the sam48 instruction set (direct, indirect, and bit manipulation) and the addressing modes which are supported (1-bit, 4-bit, and 8-bit). numberous programming examples make the information practical and usable. section 4, " memory map ," contains a detailed map of the addressable peripheral hardware registers in the memory-mapped area of the ram (bank 15). section 4 also contains detailed descriptions in standard format of the most commonly used hardware registers. these easy-to-read register descriptions can be used as a quick- reference source when writing programs. section 5, " sam48 instruction set," first introduces the basic features and conventions of the sam48 instruction set. then, two summary tables orient you to the individual instructions: one table is a high-level summary of the most important information about each instruction; the other table is designed to give expert programmers a summary of binary code and instruction notation information. the final part of section 5 contains detailed descriptions of each instruction in a standard format. each instruction description includes one or more practical examples . a basic familiarity with the information in part i will make it easier for you to understand the hardware descriptions in part ii. if you are familiar with the sam48 product family and are reading this user's manual for the first time, we recommend that you read sections 1?3 carefully , and just scan the detailed information in sections 4 and 5 very briefly. later, you can refer back to sections 4 and 5 as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the s3c72q5/p72q5 microcontroller. also included in part ii are electrical, mechanical, otp, and development tools data. part ii has 12 sections : section 6 oscillator circuit section 7 interrupts section 8 power-down section 9 reset section 10 i/o ports section 11 timers and timer/counter 0 section 12 lcd controller/driver section 1 3 external memory interface section 1 4 electrical data section 15 mechanical data section 16 S3P72Q5 otp section 17 development tools two order forms are included at the back of this manual to facilitate customer order for s3c72q5/p72q5 microcontrollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative. s3c72q5/p72q5 microcontroller v table of contents part i ? programming model section 1 product overview overview ................................ ................................ ................................ ................................ ................. 1-1 otp ................................ ................................ ................................ ................................ ......................... 1-1 features summary ................................ ................................ ................................ ................................ .. 1-2 block diagram ................................ ................................ ................................ ................................ ......... 1-3 pin assignments ................................ ................................ ................................ ................................ ...... 1-4 pin descriptions ................................ ................................ ................................ ................................ ....... 1-5 pin circuit diagrams ................................ ................................ ................................ ................................ 1-7 section 2 address spaces program memory (rom) ................................ ................................ ................................ ......................... 2-1 overview ................................ ................................ ................................ ................................ ......... 2-1 general-purpose memory areas ................................ ................................ ................................ ..... 2-2 vector address area ................................ ................................ ................................ ........................ 2-2 instruction reference area ................................ ................................ ................................ .............. 2-4 data memory (ram) ................................ ................................ ................................ ................................ 2-5 overview ................................ ................................ ................................ ................................ ......... 2-5 working registers ................................ ................................ ................................ ........................... 2-9 stack operations ................................ ................................ ................................ ................................ ..... 2-13 stack pointer (sp) ................................ ................................ ................................ ........................... 2-13 push operations ................................ ................................ ................................ .............................. 2-14 pop operations ................................ ................................ ................................ ............................... 2-15 bit sequential carrier (bsc) ................................ ................................ ................................ .................... 2-16 program counter (pc) ................................ ................................ ................................ ............................. 2-17 program status word (psw) ................................ ................................ ................................ ................... 2-17 interrupt status flags (is0, is1) ................................ ................................ ................................ ...... 2-18 emb flag (emb) ................................ ................................ ................................ .............................. 2-19 erb flag (erb) ................................ ................................ ................................ ................................ 2-20 skip condition flags (sc2, sc1, sc0) ................................ ................................ ............................ 2-21 carry flag (c) ................................ ................................ ................................ ................................ . 2-21 vi s3c72q5/p72q5 microcontroller table of contents (continued) section 3 addressing modes overview ................................ ................................ ................................ ................................ ................ 3-1 emb and erb initialization values ................................ ................................ ................................ . 3-3 enable memory bank settings ................................ ................................ ................................ ........ 3-4 select bank register (sb) ................................ ................................ ................................ .............. 3-5 direct and indirect addressing ................................ ................................ ................................ ................ 3-6 1-bit addressing ................................ ................................ ................................ ............................. 3-6 4-bit addressing ................................ ................................ ................................ ............................. 3-8 8-bit addressing ................................ ................................ ................................ ............................. 3-11 section 4 memory map overview ................................ ................................ ................................ ................................ ................ 4-1 i/o map for hardware registers ................................ ................................ ................................ .... 4-1 register descriptions ................................ ................................ ................................ ...................... 4-6 section 5 sam48 instruction set overview ................................ ................................ ................................ ................................ ................ 5-1 instruction set features ................................ ................................ ................................ .......................... 5-1 instruction reference area ................................ ................................ ................................ ............. 5-2 reducing instruction redundancy ................................ ................................ ................................ ... 5-3 flexible bit manipulation ................................ ................................ ................................ ................ 5-4 instructions which have skip conditions ................................ ................................ ........................ 5-4 instructions which affect the carry flag ................................ ................................ ........................ 5-4 adc and sbc instruction skip conditions ................................ ................................ ...................... 5-5 symbols and conventions ................................ ................................ ................................ ...................... 5-6 opcode definitions ................................ ................................ ................................ ................................ . 5-7 high-level summary ................................ ................................ ................................ .............................. 5-8 binary code summary ................................ ................................ ................................ ............................ 5-13 instruction descriptions ................................ ................................ ................................ ........................... 5-23 s3c72q5/p72q5 microcontroller vii table of contents (continued) part ii ? hardware descriptions section 6 oscillator circuits overview ................................ ................................ ................................ ................................ ................. 6-1 main-system oscillator circuits ................................ ................................ ................................ ....... 6-3 sub-system oscillator circuits ................................ ................................ ................................ ........ 6-3 power control register (pcon) ................................ ................................ ................................ ...... 6-4 instruction cycle times ................................ ................................ ................................ ................... 6-5 system clock mode register (scmod) ................................ ................................ .......................... 6-6 switching the cpu clock ................................ ................................ ................................ ................ 6-8 clock output mode register (clmod) ................................ ................................ ............................ 6-10 clock output circuit ................................ ................................ ................................ ........................ 6-11 clock output procedure ................................ ................................ ................................ .................. 6-11 section 7 interrupts overview ................................ ................................ ................................ ................................ ................. 7-1 vectored interrupts ................................ ................................ ................................ .......................... 7-2 multiple interrupts ................................ ................................ ................................ ............................ 7-5 interrupt priority register (ipr) ................................ ................................ ................................ ....... 7-7 external interrupt 0 and 1 mode registers (imod0, imod1) ................................ ........................... 7-8 external interrupt 2 mode register (imod2) ................................ ................................ .................... 7-10 interrupt flags ................................ ................................ ................................ ................................ . 7-12 section 8 power-down overview ................................ ................................ ................................ ................................ ................. 8-1 idle mode timing diagrams ................................ ................................ ................................ ............. 8-4 stop mode timing diagrams ................................ ................................ ................................ ........... 8-5 recommended connections for unused pins ................................ ................................ .................. 8-7 viii s3c72q5/p72q5 microcontroller table of contents (continued) section 9 reset reset overview ................................ ................................ ................................ ................................ ................ 9-1 hardware register values after reset ................................ ................................ ......................... 9-1 section 10 i/o ports overview ................................ ................................ ................................ ................................ ................ 10-1 port mode flags (pm flags) ................................ ................................ ................................ ........ 10-3 pull-up resistor mode register (pumod0) ................................ ................................ .................... 10-4 port 0,1 circuit diagram ................................ ................................ ................................ ................. 10-6 port 4 circuit diagram ................................ ................................ ................................ .................... 10-7 port 5 circuit diagram ................................ ................................ ................................ .................... 10-8 port 6 circuit diagram ................................ ................................ ................................ .................... 10-9 port 7 circuit diagram ................................ ................................ ................................ .................... 10-10 s3c72q5/p72q5 microcontroller ix table of contents (continued) section 11 timers and timer/counter 0 overview ................................ ................................ ................................ ................................ ................. 11-1 basic timer (bt) ................................ ................................ ................................ ................................ ..... 11-2 overview ................................ ................................ ................................ ................................ ......... 11-2 basic timer mode register (bmod) ................................ ................................ ................................ 11-5 basic timer counter (bcnt) ................................ ................................ ................................ ........... 11-6 basic timer operation sequence ................................ ................................ ................................ .... 11-6 watchdog timer mode register (wdmod) ................................ ................................ ..................... 11-8 watchdog timer counter (wdcnt) ................................ ................................ ................................ 11-8 watchdog timer counter clear flag (wdtcf) ................................ ................................ ............... 11-8 8-bit timer/counter 0 (tc0) ................................ ................................ ................................ .................... 11-10 overview ................................ ................................ ................................ ................................ ......... 11-10 tc0 function summary ................................ ................................ ................................ .................. 11-10 tc0 component summary ................................ ................................ ................................ .............. 11-11 tc0 enable/disable procedure ................................ ................................ ................................ ........ 11-12 tc0 programmable timer/counter function ................................ ................................ ................... 11-13 tc0 operation sequence ................................ ................................ ................................ ................ 11-13 tc0 event counter function ................................ ................................ ................................ ........... 11-14 tc0 clock frequency output ................................ ................................ ................................ .......... 11-15 tc0 external input signal divider ................................ ................................ ................................ ... 11-16 tc0 mode register (tmod0) ................................ ................................ ................................ .......... 11-17 tc0 counter register (tcnt0) ................................ ................................ ................................ ....... 11-19 tc0 reference register (tref0) ................................ ................................ ................................ .... 11-20 tc0 output enable flag (toe0) ................................ ................................ ................................ ..... 11-20 tc0 output latch (tol0) ................................ ................................ ................................ ................ 11-20 8-bit timer/counter 1 (tc1) ................................ ................................ ................................ .................... 11-22 overview ................................ ................................ ................................ ................................ ......... 11-22 tc1 function summary ................................ ................................ ................................ .................. 11-22 tc1 component summary ................................ ................................ ................................ .............. 11-23 tc1 enable/disable procedure ................................ ................................ ................................ ........ 11-24 tc1 programmable timer/counter function ................................ ................................ ................... 11-25 tc1 operation sequence ................................ ................................ ................................ ................ 11-25 tc1 mode register (tmod1) ................................ ................................ ................................ .......... 11-26 tc1 counter register (tcnt1) ................................ ................................ ................................ ....... 11-28 tc1 reference register (tref1) ................................ ................................ ................................ .... 11-29 watch timer ................................ ................................ ................................ ................................ ............ 11-30 overview ................................ ................................ ................................ ................................ ......... 11-30 watch timer mode register (wmod) ................................ ................................ ............................. 11-32 x s3c72q5/p72q5 microcontroller table of contents (concluded) section 12 lcd controller/driver overview ................................ ................................ ................................ ................................ ................ 12-1 lcd circuit diagram ................................ ................................ ................................ ....................... 12-2 lcd ram address area ................................ ................................ ................................ ................. 12-3 lcd contrast control register (lcnst) ................................ ................................ ......................... 12-4 lcd output control register 0 (lcon0) ................................ ................................ ........................ 12-5 lcd output control register 1 (lcon1) ................................ ................................ ........................ 12-5 lcd mode register (lmod) ................................ ................................ ................................ ........... 12-6 key scan register (ksr) ................................ ................................ ................................ ............... 12-17 section 13 external memory interface overview ................................ ................................ ................................ ................................ ................ 13-1 external memory control register (emcon) ................................ ................................ .................. 13- 1 how to access the external memory ................................ ................................ ............................. 13-3 external memory write cycle timing diagram ................................ ................................ ............... 13-6 external memory read cycle timing diagram ................................ ................................ ............... 13-6 section 14 electrical data overview ................................ ................................ ................................ ................................ ................ 14-1 timing waveforms ................................ ................................ ................................ ................................ . 14-10 section 15 mechanical data overview ................................ ................................ ................................ ................................ ................ 15-1 section 16 S3P72Q5 otp overview ................................ ................................ ................................ ................................ ................ 16-1 operating mode characteristics ................................ ................................ ................................ ...... 16-3 section 17 development tools overview ................................ ................................ ................................ ................................ ................ 17-1 shine ................................ ................................ ................................ ................................ ............ 17-1 sama assembler ................................ ................................ ................................ ........................... 17-1 sasm57 ................................ ................................ ................................ ................................ ......... 17-1 hex2rom ................................ ................................ ................................ ................................ ...... 17-1 target boards ................................ ................................ ................................ ................................ . 17-1 otps ................................ ................................ ................................ ................................ .............. 17-1 tb72q5 target board ................................ ................................ ................................ .................... 17-3 idle led ................................ ................................ ................................ ................................ ......... 17-5 stop led ................................ ................................ ................................ ................................ ........ 17-5 s3c72q5/p72q5 microcontroller xi list of figures figure title page number number 1-1 s3c72q5/p72q5 specified block diagram ................................ ............................ 1-3 1-2 s3c72q5 pin assignment diagram ................................ ................................ ........ 1-4 1-3 pin circuit type a ................................ ................................ ................................ .. 1-7 1-4 pin circuit type a-3 ................................ ................................ ............................... 1-7 1-5 pin circuit type b ................................ ................................ ................................ .. 1-7 1-6 pin circuit type c ................................ ................................ ................................ .. 1-7 1-7 pin circuit type e-2 ................................ ................................ ............................... 1-8 1-8 pin circuit type e-3 ................................ ................................ ............................... 1-8 1-9 pin circuit type h-4 ................................ ................................ ............................... 1-9 1-10 pin circuit type h-5 ................................ ................................ ............................... 1-9 1-11 pin circuit type h-6 ................................ ................................ ............................... 1-9 1-12 pin circuit type h-7 ................................ ................................ ............................... 1-9 1-13 pin circuit type h-9 ................................ ................................ ............................... 1-10 1-14 pin circuit type h-10 ................................ ................................ ............................. 1-10 1-15 pin circuit type h-11 ................................ ................................ ............................. 1-10 1-16 pin circuit type h-12 ................................ ................................ ............................. 1-10 2-1 rom address structure ................................ ................................ .......................... 2-2 2-2 vector address map ................................ ................................ ............................... 2-2 2-3 s3c72q5 data memory (ram) map ................................ ................................ ...... 2-6 2-4 working register map ................................ ................................ ............................ 2-9 2-5 register pair configuration ................................ ................................ ..................... 2-10 2-6 1-bit, 4-bit, and 8-bit accumulator ................................ ................................ .......... 2-11 2-7 push-type stack operations ................................ ................................ .................. 2-14 2-8 pop-type stack operations ................................ ................................ .................... 2-15 3-1 ram address structure ................................ ................................ .......................... 3-2 3-2 smb and srb values in the sb register ................................ ............................... 3-5 4-1 register description format ................................ ................................ ................... 4-7 6-1 clock circuit diagram ................................ ................................ ............................. 6-2 6-2 crystal/ceramic oscillator ................................ ................................ ...................... 6-3 6-3 external oscillator ................................ ................................ ................................ .. 6-3 6-4 rc oscillator ................................ ................................ ................................ .......... 6-3 6-5 crystal/ceramic oscillator ................................ ................................ ...................... 6-3 6-6 external oscillator ................................ ................................ ................................ .. 6-3 6-7 clo output pin circuit diagram ................................ ................................ ............. 6-11 7-1 interrupt execution flowchart ................................ ................................ ................. 7-3 7-2 interrupt control circuit diagram ................................ ................................ ............ 7-4 7-3 two-level interrupt handling ................................ ................................ .................. 7-5 7-4 multi-level interrupt handling ................................ ................................ ................. 7-6 7-5 circuit diagram for int0 and int1 pins ................................ ................................ . 7-9 7-6 circuit diagram for int2 ................................ ................................ ......................... 7-10 xii s3c72q5/p72q5 microcontroller list of figures (continued) figure title page number number 8-1 timing when idle mode is released by reset ................................ ................... 8-4 8-2 timing when idle mode is released by an interrupt ................................ .............. 8-4 8-3 timing when stop mode is released by reset ................................ ................... 8-5 8-4 timing when stop mode is released by an interrupt ................................ ............ 8-5 9-1 timing for oscillation stabilization a fter reset ................................ .................... 9-1 10-1 port 0,1 circuit diagram ................................ ................................ ........................ 10-6 10-3 port 4 circuit diagram ................................ ................................ ........................... 10-7 10-4 port 5 circuit diagram ................................ ................................ ........................... 10-8 10-5 port 6 circuit diagram ................................ ................................ ........................... 10-9 10-6 port 7 circuit diagram ................................ ................................ ........................... 10-10 11-1 basic timer circuit diagram ................................ ................................ .................. 11-4 11-2 tc0 circuit diagram ................................ ................................ .............................. 11-12 11-3 tc0 timing diagram ................................ ................................ ............................. 11-19 11-4 tc1 circuit diagram ................................ ................................ .............................. 11-24 11-5 tc1 timing diagram ................................ ................................ ............................. 1 1-28 11-6 watch timer circuit diagram ................................ ................................ ................ 11-31 12-1 lcd circuit diagram ................................ ................................ .............................. 12-2 12-2 lcd clock circuit diagram ................................ ................................ .................... 12-2 12-3 display ram organization ................................ ................................ ..................... 12-3 12-4 lcd voltage dividing resistors connection ................................ .......................... 12-8 12-5 re, le and inputs signal waveform (1/9 duty) ................................ ..................... 12-9 12-6 lcd signal waveform for 1/9 duty and 1/4 bias ................................ ................... 12-10 12-7 re, le and inputs signal waveform (1/10 duty) ................................ ................... 12-11 12-8 lcd signal waveform for 1/10 duty and 1/4 bias ................................ ................. 12-12 12-9 re, le and inputs signal waveform (1/11 duty) ................................ ................... 12-13 12-10 lcd signal waveform for 1/11 duty and 1/4 bias ................................ ................. 12-14 12-11 re, le and inputs signal waveform (1/12 duty) ................................ ................... 12-15 12-12 lcd signal waveform for 1/12 duty and 1/4 bias ................................ ................. 12-16 12-13 segment pin output signal when lcon1.3 = 1 ................................ .................... 12-17 13-1 external memory write cycle timing diagram ................................ ...................... 13-6 13-2 external memory read cycle timing diagram ................................ ...................... 13-6 13-3 external interface fuction diagram (s3c72q5, sram, eprom, eeprom) ......... 13-7 s3c72q5/p72q5 microcontroller xiii list of figures (continued) figure title page number number 14-1 standard operating voltage range ................................ ................................ ........ 14-9 14-2 stop mode release timing when initiated by reset ................................ ........... 14-10 14-3 stop mode release timing when initiated by interrupt request ............................ 14-10 14-4 a.c. timing measurement points (except for x in and xt in ) ................................ ... 14-11 14-5 input timing for external interrupts and quasi-interrupts ................................ ........ 14-11 14-6 clock timing measurement at x in ................................ ................................ .......... 14-12 14-7 clock timing measurement at xt in ................................ ................................ ........ 14-12 14-6 tcl0 timing ................................ ................................ ................................ .......... 14-13 14-7 input timing for reset signal ................................ ................................ ............... 14-13 15-1 100-qfp-1420 package dimensions ................................ ................................ ...... 15-1 16-1 S3P72Q5 pin assignments (100-qfp package) ................................ ..................... 16-2 16-2 standard opera ting voltage range ................................ ................................ ........ 16-5 17-1 smds product configuration (smds2+) ................................ ................................ 17-2 17-2 tb72q5 target board configuration ................................ ................................ ...... 17-3 17-3 50-pin connectors for tb72q5 ................................ ................................ ............... 17-6 17-4 tb72q5 adapter cable for 100-qfp package (s3c72q5/p72q5) ......................... 17-6 s3c72q5/p72q5 microcontroller xv list of tables table title page number number 1-1 pin descriptions ................................ ................................ ................................ ..... 1-5 2-1 program memory address ranges ................................ ................................ ......... 2-1 2-2 data memory organization and addressing ................................ ............................ 2-7 2-3 working register organization and addressing ................................ ...................... 2-10 2-4 bsc register organization ................................ ................................ ..................... 2-16 2-5 program status word bit descriptio ns ................................ ................................ .... 2-17 2-6 interrupt status flag bit settings ................................ ................................ ............ 2-18 2-7 valid carry flag manipulation instructions ................................ .............................. 2-21 3-1 ram addressing not affected by the emb value ................................ ................... 3-4 3-2 1-bit direct and indirect ram addressing ................................ ............................... 3-6 3-3 4-bit direct and indirect ram addressing ................................ ............................... 3-8 3-4 8-bit direct and indirect ram addressing ................................ ............................... 3-11 4-1 i/o map for memory bank 15 ................................ ................................ ................. 4-2 4-2 i/o map for memory bank 15 ................................ ................................ ................. 4-3 5-1 valid 1-byte instruction combinations for ref look-ups ................................ ....... 5-2 5-2 bit addressing modes and parameters ................................ ................................ ... 5-4 5-3 skip conditions for adc and sbc instructions ................................ ....................... 5-5 5-4 data type symbols ................................ ................................ ................................ 5-6 5-5 register identifiers ................................ ................................ ................................ . 5-6 5-6 instruction operand notation ................................ ................................ .................. 5-6 5-7 opcode definitions (direct) ................................ ................................ .................... 5-7 5-8 opcode definitions (indirect) ................................ ................................ .................. 5-7 5-9 cpu control instructions ? high-level summary ................................ .................. 5-9 5-10 program control instructions ? high-level summary ................................ ............ 5-9 5-11 data transfer instructions ? high-level summary ................................ ................ 5-10 5-12 logic instructions ? high-level summary ................................ ............................. 5-11 5-13 arithmetic instructions ? high-level summary ................................ ...................... 5-11 5-14 bit manipulation instructions ? high-le vel summary ................................ ............ 5-12 5-15 cpu control instructions ? binary code summary ................................ ............... 5-14 5-16 program control instructions ? binary code summary ................................ ......... 5-15 5-17 data transfer instructions ? binary code summary ................................ .............. 5-16 5-18 logic instructions ? binary code summary ................................ ........................... 5-18 5-19 arithmetic instructions ? binary code summary ................................ ................... 5-19 5-20 bit manipulation instructions ? binary code summary ................................ .......... 5-20 6-1 power control register (pcon) organization ................................ ........................ 6-4 6-2 instruction cycle times for cpu clock rates ................................ ......................... 6-5 6-3 system clock mode register (scmod) organi zation ................................ ............ 6-6 6-4 main oscillation stop mode ................................ ................................ .................... 6-7 6-5 elapsed machine cycles during cpu clock switch ................................ ................ 6-8 6-6 clock output mode register (clmod) organization ................................ .............. 6-10 xvi s3c72q5/p72q5 microcontroller list of tables (continued) table title page number number 7-1 interrupt types and corresponding port pin(s) ................................ ...................... 7-1 7-2 is1 and is0 bit manipulation for multi-level interrupt handling ............................. 7-6 7-3 standard interrupt priorities ................................ ................................ ................... 7-7 7-4 interrupt priority register settings ................................ ................................ ......... 7-7 7-5 imod0 and imod1 register organization ................................ ............................. 7-8 7-6 imod2 register bit settings ................................ ................................ .................. 7-10 7-7 interrupt enable and interrupt request flag addresses ................................ ......... 7-12 7-8 interrupt request flag conditions and priorities ................................ .................... 7-13 8-1 hardware operation during power-down modes ................................ ................... 8-2 8-2 system operating mode comparison ................................ ................................ .... 8-3 8-3 unused pin connections for reducing power consumption ................................ .. 8-7 9-1 hardware register values after reset ................................ ................................ 9-2 10-1 i/o port overview ................................ ................................ ................................ .. 2 10-2 port pin status during instruction execution ................................ .......................... 10-2 10-3 port mode group flags ................................ ................................ ......................... 10-3 10-4 pull-up resistor mode register (pumod0) organization ................................ ...... 10-4 11-1 basic time r register overview ................................ ................................ ............. 11-3 11-2 basic timer mode register (bmod) organization ................................ ................. 11-5 11-3 watchdog timer interval time ................................ ................................ .............. 11-8 11-4 tc0 register overview ................................ ................................ ......................... 11-11 11-5 tmod0 settings for tcl0 edge detection ................................ ............................ 11-14 11-6 tc0 mode register (tmod0) organization ................................ ........................... 11-17 11-7 tmod0.6, tmod0.5, and tmod0.4 bit settings ................................ ................... 11-18 11-8 tc1 register overview ................................ ................................ ......................... 11-23 11-9 tc1 mode register (tmod1) organization ................................ ........................... 11-26 11-10 tmod1.6, tmod1.5, and tmod1.4 bit settings ................................ ................... 11-27 11-11 watch timer mode register (wmod) organization ................................ .............. 11-32 12-1 lcd contrast control register (lcnst) organization ................................ ........... 12-4 12-2 lcd output control register (lcon0) organization ................................ ............. 12-5 12-3 lcd output control register (lcon1) organization ................................ ............. 12-5 12-4 lcd mode control register (lmod) organization ................................ ................. 12-7 12-5 ksr organization ................................ ................................ ................................ .. 12-17 13-1 external memory control register (emcon) organization ................................ .... 13-2 s3c72q5/p72q5 microcontroller xvii list of tables (continued) table title page number number 14-1 absolute maximum ratings ................................ ................................ .................... 14-2 14-2 d.c characteristics ................................ ................................ ................................ . 14-2 14-3 main system clock oscillator characteristics ................................ ......................... 14-5 14-4 rec ommended oscillator constants ................................ ................................ ....... 14-6 14-5 subsystem clock oscillator characteristics ................................ ............................ 14-7 14-6 input/output capacitance ................................ ................................ ....................... 14-7 14-7 a.c. electrical characteristics ................................ ................................ ................ 14-8 14-8 ram data retention supply voltage in stop mode ................................ ................ 14-9 16-1 descriptions of pins used to read/write the eprom ................................ ............ 16-3 16-2 comparison of S3P72Q5 and s3c72q5 features ................................ .................. 16-3 16-3 operating mode selection criteria ................................ ................................ .......... 16-3 16-4 d.c characteristics ................................ ................................ ................................ . 16-4 17-1 power selection settings for tb72q5 ................................ ................................ ..... 17-4 17-2 main-clock selection settings for tb72q5 ................................ .............................. 17-4 17-3 sub-clock selection settings for tb72q5 ................................ ............................... 17-5 s3c72q5/p72q5 microcontroller xix list of programming tips description page number section 2: address spaces defining vectored interrupts ................................ ................................ ................................ .................... 2-3 using the ref look-up table ................................ ................................ ................................ ................. 2-4 clearing data memory bank 0 ,and the page 0 in bank 1 ................................ ................................ ........ 2-8 selecting the working register area ................................ ................................ ................................ ....... 2-12 initializing the stack pointer ................................ ................................ ................................ ..................... 2-13 using the bsc register to output 16-bit data ................................ ................................ ......................... 2-16 setting isx flags for interrupt processing ................................ ................................ ................................ 2-18 using the emb flag to select memory banks ................................ ................................ .......................... 2-19 using the erb flag to select register banks ................................ ................................ .......................... 2-20 using the carry flag as a 1-bit accumulator ................................ ................................ ............................ 2-22 section 3 : addressing modes initializing the emb and erb flags ................................ ................................ ................................ ......... 3-3 1-bit addressing modes ................................ ................................ ................................ ........................... 3-7 4-bit addressing modes ................................ ................................ ................................ ........................... 3-8 8-bit addressing modes ................................ ................................ ................................ ........................... 3-12 section 5 : sam48 instruction set example of the instruction redundancy effect ................................ ................................ ......................... 5-3 section 6 : oscillator circuits setting the cpu clock ................................ ................................ ................................ ............................. 6-4 switching between main-system and sub-system clock ................................ ................................ .......... 6-9 cpu clock output to the clo pin ................................ ................................ ................................ ........... 6-11 section 7 : interrupts setting the int interrupt priority ................................ ................................ ................................ .............. 7-8 using int2 as a key input interrupt ................................ ................................ ................................ ......... 7-11 section 8 : power-down reducing power consumption for key input interrupt processing ................................ ............................ 8-6 xx s3c72q5/p72q5 microcontroller list of programming tips (continued) description page number section 10 : i/o ports configuring i/o ports to input or output ................................ ................................ ................................ .. 10-3 enabling and disabling i/o port pull-up resistors ................................ ................................ .................. 10-4 section 11 : timers and timer/counter 0 using the basic timer ................................ ................................ ................................ ............................. 11-7 using the watchdog timer ................................ ................................ ................................ ..................... 11-9 tc0 signal output to the tclo0 pin ................................ ................................ ................................ ...... 11-15 external tcl0 clock output to the tclo0 pin ................................ ................................ ....................... 11-16 restarting tc0 counting operation ................................ ................................ ................................ ........ 11-18 setting a tc0 timer interval ................................ ................................ ................................ ................... 11-21 restarting tc1 counting operation ................................ ................................ ................................ ........ 11-27 setting a tc1 timer interval ................................ ................................ ................................ ................... 11-29 using the watch timer ................................ ................................ ................................ ........................... 11-33 section 13 : external memory interface external memory interface ................................ ................................ ................................ ...................... 13-4 s3c72q5/p72q5 microcontroller xxi list of register descriptions register full register name page identifier number bmod basic timer mode register ................................ ................................ .......... 4-8 clmod clock output mode register ................................ ................................ ........ 4-9 emcon external memory control register ................................ ............................... 4-10 ie0, 1, irq0, 1 int0, 1 interrupt enable/request flags ................................ ....................... 4-11 ie2, irq2 i nt2 interrupt enable/request flags ................................ ........................... 4-12 ieb, irqb intb interrupt enable/request flags ................................ ........................... 4-13 iep0, irqp0 intp0 interrupt enable/request flags ................................ ......................... 4-14 iet0, irqt0 intt0 interrupt enable/request flags ................................ ......................... 4-15 iet1, irqt1 intt1 interrupt enable/request flags ................................ ......................... 4-16 iew, irqw intw interrupt enable/request flags ................................ .......................... 4-17 imod0 external interrupt 0 (int0) mode register ................................ .................... 4-18 imod1 external interrupt 1 (int1) mode register ................................ .................... 4-19 imod2 external interrupt 2 (int2) mode register ................................ .................... 4-20 ipr interrupt priority register ................................ ................................ ............. 4-21 lcnst lcd co ntrast control register ................................ ................................ ..... 4-22 lcon0 lcd output control register 0 ................................ ................................ ..... 4-23 lcon1 lcd output control register 1 ................................ ................................ ..... 4-24 lmod lcd mode register ................................ ................................ ...................... 4-25 pasr page selection register ................................ ................................ ............... 4-26 pcon power control register ................................ ................................ ................ 4-27 pmg0 port i/o mode register 0 (group 0: port 0, 1) ................................ .............. 4-28 pmg1 port i/o mode register 1 (group 1: port 4, 5) ................................ .............. 4-29 pmg2 port i/o mode register 2 (group 2: port 6, 7) ................................ .............. 4-30 pne0 n-channel open-drain mode register 0 ................................ ....................... 4-31 psw program status word ................................ ................................ .................. 4-32 pumod0 pull-up resistor mode register ................................ ................................ ... 4-33 scmod system clock mode control register ................................ ........................... 4-34 tmod0 timer/counter 0 mode register ................................ ................................ ... 4-35 tmod1 timer/counter 1 mode register ................................ ................................ ... 4-36 toe0 time/output enable flag register ................................ ............................... 4-37 wdflag watch-dog timer?s counter clear flag ................................ ........................ 4-38 wdmod watch-dog timer mode control register ................................ ..................... 4-39 wmod watch timer mode register ................................ ................................ ........ 4-40 s3c72q5/p72q5 microcontroller xxiii list of instruction descriptions instruction full instruction name page mnemonic number adc add with carry ................................ ................................ ........................ 5-24 ads add and skip on overflow ................................ ................................ ....... 5-26 and locical and ................................ ................................ ............................. 5-28 band bit logical and ................................ ................................ ....................... 5-29 bitr bit reset ................................ ................................ ................................ .. 5-31 bits bit se t ................................ ................................ ................................ ...... 5-33 bor bit logical or ................................ ................................ .......................... 5-35 btsf bit test and skip on false ................................ ................................ ....... 5-37 btst bit test and skip on true ................................ ................................ ......... 5-39 btstz bit test and skip on true; clear bit ................................ ......................... 5-41 bxor bit exclusive or ................................ ................................ ...................... 5-43 call call procedure ................................ ................................ ......................... 5-45 calls call procedure (short) ................................ ................................ ............. 5-46 ccf complement carry flahg ................................ ................................ ......... 5-47 com complement accumulator ................................ ................................ ........ 5-48 cpse compare and skip if equal ................................ ................................ ...... 5-49 decs decrement and skip on borrow ................................ ................................ 5-50 di disable interrupts ................................ ................................ ..................... 5-51 ei enable interrupts ................................ ................................ ...................... 5-52 idle idle operation ................................ ................................ .......................... 5-53 incs increment and skip on carry ................................ ................................ .... 5-54 iret return fr om interrupt ................................ ................................ ............... 5-55 jp jump ................................ ................................ ................................ ....... 5-56 jps jump (short) ................................ ................................ ............................ 5-57 jr jump relative (very short) ................................ ................................ ...... 5-58 ld load ................................ ................................ ................................ ........ 5-60 ldb load bit ................................ ................................ ................................ ... 5-64 ldc load code byte ................................ ................................ ....................... 5-66 ldd load data memory and decrement ................................ .......................... 5-68 ldi load data memory and increment ................................ ........................... 5-69 nop no operation ................................ ................................ ........................... 5-70 or logical or ................................ ................................ ............................... 5-71 pop pop from stack ................................ ................................ ........................ 5-72 push push onto stack ................................ ................................ ...................... 5-73 xxiv s3c72q5/p72q5 microcontroller list of instruction descriptions (continued) instruction full instruction name page mnemonic number rcf reset carry flag ................................ ................................ ..................... 5-74 ref reference instruction ................................ ................................ .............. 5-75 ret return from subrouti ne ................................ ................................ ........... 5-78 rrc rotate accumulator right through carry ................................ ................ 5-79 sbc subtract with carry ................................ ................................ ................ 5-80 sbs subtract ................................ ................................ ................................ .. 5-82 scf set carry flag ................................ ................................ ......................... 5-83 smb select memory bank ................................ ................................ ............... 5-84 srb select register bank ................................ ................................ ............... 5-85 sret return from subroutine and skip ................................ ............................ 5-86 stop stop operation ................................ ................................ ........................ 5-87 vent load emb, erb, and vector address ................................ ..................... 5-88 xch exchange a or ea with nibble or byte ................................ ................... 5-90 xchd exchange and decrement ................................ ................................ ....... 5-91 xchi exchange and increment ................................ ................................ ........ 5-92 xor logical exclusive or ................................ ................................ .............. 5-93 s3c72q5/p72q5 product overview 1- 1 1 product overview overview the s3c72q5 is a sam48 core-based 4-bit cmos single-chip microcontroller. it has two timer/counters and lcd drivers. the s3c72q5 is especially suited for use in data bank, telephone and lcd general purpose. it is built around the sam48 core cpu and c ontains rom, ram, 39 i/o lines , programmable timer/counter s , buzzer output, enough lcd dot matrix, external memory interface, and segment drive pins. the s3c72q5 can be used for dedicated control functions in a variety of applications, and is especially designed for multi data bank , telephone and lcd game. otp the s3c72q5 microcontroller is also available in otp (one time programmable) version, S3P72Q5. S3P72Q5 microcontroller has an on-chip 16k-byte one-time-programmable eprom instead of masked rom. the S3P72Q5 is comparable to s3c72q5, both in function and in pin configuration. product overview s3c72q5/p72q5 1- 2 features summary memory 16 k x 8 bit program memory 5 , 120 x 4 bit data memory 1 44 x 5 bit lcd display memory 39 i/o pins i/o: 23 pins output: maximum 16 pins for 1-bit level output (sharing with segment driver outputs) 8-bit basic timer four internal timer functions watch-dog timer 8-bit timer /counter 0 programmable 8-bit timer external event counter arbitrary clock frequency output external clock signal divider 8-bit timer/counter 1 programmable 8-bit timer watch timer time interval generation: 0 . 5ms, 3 . 9 1 ms at 32 , 768hz 4 frequency (2/4/8/16 khz) outputs to buz pin interrupts three external vectored interrupts: int0, int1, intp0 t hree internal vectored interrupts: intb, intt0 , intt1 two quasi-interrupts: intw, int2 memory mapped i/o structure lcd display 60 segments and 12 common termin als 9, 10, 11, and 12 common selectable two internal resistor circuit for lcd bias (selectable) 16 level lcd contrast control (software) external memory interface 512 k x 8 bit external memory access (19 address and 8 data pins-sharing with segment driver outputs) six external memory selection pins ( dm 0- dm 5) 1 data read and 1 data write pins ( dr, dw - sharing with segment driver outputs) power-down modes idle mode (only cpu clock stops) stop mode (main-system clock , sub-system clock and cpu clock stops) oscillation sources crystal, ceramic, or external rc for system clock main - system clock frequency: 0.4 mhz -6 mhz sub - system clock frequency: 32 , 768 khz cpu clock divider circuit (by 4,8 , or 64) instruction execution times 0.67, 1.33, 10.7 m s at 6 mhz 0.95, 1.91, 15.3 m s at 4.19 mhz 122 m s at 32.768 k hz operating temperature -40 c to 85 c operating voltage range 1.8 v to 5.5 v package type 100 - pin qfp package s3c72q5/p72q5 product overview 1- 3 block diagram program status word stack pointer arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block instruction register clock 16 k byte program memory data and display memory p8.0-p8.15/ seg0-seg15 p6.0-p6.3/ks0- ks3 / dm 0- dm 3 p5.0-p5.1 p5.2/buz p5.3/clo p4.0/tcl0 p4.1/tclo0 p4.2/int0 p4.3/int1 i/o port 1 p1.0-p1.2/k4-k6 i/o port 0 p0.0-p0.3/k0-k3 external memory interface 8-bit timer/ counter 0 program counter basic timer xt out x out xt in x in com0-com8 com9-com11/p7.3-p7.1 seg45-seg59 seg44/ dw seg43/ dr seg24-seg42/a0-a18 seg16-seg23/d0-d7 seg0-seg15/p8.0-p8.15 intt0, intt1, intb, intw int0, int1, intp0, int2 8-bit timer/ counter 1 watch timer lcd driver/ controller lcd contrast controller i/o port 5 i/o port 4 i/o port 7 i/o port 6 output port 8 p7.0/ks4/ dm 4 p7.1/ks5/ dm 5 /com11 p7.2-p7.3/ks6-ks7 /com10-9 watch-dog timer figure 1-1. s3c72q5/p72q5 specified block diagram product overview s3c72q 5/p72q5 1- 4 pin assignments seg39/a15 seg40/a16 seg41/a17 seg42/a18 seg43/ dr seg44/ dw seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg38/a14 seg37/a13 seg36/a12 seg35/a11 seg34/a10 seg33/a9 seg32/a8 seg31/a7 seg30/a6 seg29/a5 seg28/a4 seg27/a3 seg26/a2 seg25/a1 seg24/a0 seg23/d7 seg22/d6 seg21/d5 seg20/d4 seg19/d3 seg18/d2 seg17/d1 seg16/d0 seg15/p8.15 seg14/p8.14 seg13/p8.13 seg12/p8.12 seg11/p8.11 seg10/p8.10 seg9/p8.9 seg59 com4 com5 com6 com7 com8 p7.3/ks7/com9 p7.2/ks6/com10 p7.1/ks5/ dm 5/com11 p7.0/ks4/ dm 4 p6.3/ks3/ dm 3 p6.2/ks2/ dm 2 p6.1/ks1/ dm 1 p6.0/ks0/ dm 0 v dd v ss x out x in test xt in xt out reset p5.0 p5.1 p5.2/buz p5.3/clo p4.0/tcl0 p4.1/tclo0 p4.2/int0 p4.3/int1 s3c72q5 (100-qfp-1420c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 seg8/p8.8 seg7/p8.7 seg6/p8.6 seg5/p8.5 seg4/p8.4 seg3/p8.3 seg2/p8.2 seg1/p8.1 seg0/p8.0 com3 com2 com1 com0 p0.0/k0 p0.1/k1 p0.2/k2 p0.3/k3 p1.0/k4 p1.1/k5 p1.2/k6 figure 1-2. s3c72q5 pin assignment diagram s3c72q5/p72q5 product overview 1- 5 pin descriptions table 1- 1 . pin descriptions pin name pin type description circuit type pin number share pin p0.0 - p0.3 p1.0-p1.2 i /o 4-bit i/o port. 1 , 4, and 8-bit read/write, and test are possible. individual pin can be specified as input or output. 7- bit pull - up resistor s are assignable by software. pull- up resistors are automatically disabled for output pins . e-3 37-34 33-31 k0 - k3 k4-k6 p 4 .0 p4.1 p4.2 p4.3 p5.0-p5.1 p5.2 p5.3 4-bit i/o port. 1 , 4, and 8-bit read/write, and test are possible. i ndividual pin can be specified as input or output. 4- bit pull - up resistor s are assignable by software. pull-up resistors are automatically disabled for output pins . individual pins are software configurable as open-drain or push-pull output. e-2 27 28 29 30 23-24 25 26 tcl0 tclo0 int0 int1 ? buz clo p 6 .0 -p6.3 p7.0 p7.1 p7.2-p7.3 4-bit i/o port. 1 , 4, and 8-bit read/write, and test are possible. i ndividual pin can be specified as input or output. 4- bit pull - up resistor s are assignable by software. pull- up resistors are automatically disabled for output pins . e-3 14-11 10 9 8-7 ks0-ks3/ dm 0- dm 3 ks4/ dm 4 ks5/ dm 5/com11 ks6-ks7/com10- com9 p8.0-p8.15 o 4-bit controllable output. (dual function as segment output pins) h-9 42- 5 7 seg0 - seg15 seg0-seg15 lcd segment display signal output. h-9 42-57 p8.0-p8.15 seg16-seg23 i/o lcd segment display signal output. h-10 58-65 d0-d7 seg 24- seg 42 o lcd segment display signal output. h-11 66-84 a0-a18 seg43,seg44 lcd segment display signal output. h-11 85, 86 dr, dw seg45-seg59 lcd segment display signal output. h-5 87-100,1 ? com0 - com8 lcd common signal output. h-4 38-41 2-6 ? com 9- com 10 com11 i/o lcd common signal output. h-12 7-8 9 p7.3-p7.2/ ks7-ks6 p7.1/ks5/ dm 5 int0 - int1 external interrupts. the triggering edge for int0, and int1 is selectable e-2 29-30 p 4.2 - p 4.3 note: p8 can be used to normal output port, when lcd display is off. the value of p8 is determined by ksr0-ksr3 regardless of lmod.0. (refer to p12-17) product overview s3c72q 5/p72q5 1- 6 table 1- 1 . pin descriptions (continued) pin name pin type description circuit type pin num. share pin buz i/o 2,4, 8 k hz or 16 khz frequency output for buzzer signal. e-2 25 p5.2 clo clock output 26 p5.3 tcl0 external clock input for timer/counter0 27 p4.0 tclo0 timer/counter0 clock output 28 p4.1 k0-k6 vector interrupt input. k0-k6: falling edge detection e-3 37-31 p0.0-p1.2 ks0-ks4 ks5 ks6-ks7 quasi-interrupt input for falling edge detection e-3 h-12 14-10 9 8-7 p6.0-p7.0/ dm 0- dm 4 p7.1/ dm 5/com11 p7.2-p7.3/ com10-com9 dm 0- dm 4 dm 5 external data memory select signal e-3 h-12 14-10 p6.0-p7.0/ ks0-ks4 p7.1/ks5/com11 d0-d7 data signal i/o h-10 58-65 seg16-seg23 a0-a18 o address signal out h-11 66-84 seg24-seg42 dr , dw external data memory read/write signal h-11 85, 86 seg43,seg44 x in , x out ? crystal, ceramic or rc oscillator pins for main system clock. ? 18 , 17 ? xt in , xt out ? crystal oscillator pins for sub-system clock. ? 20 , 21 ? reset i reset input (a ctive low). b 22 ? v dd ? power supply. ? 15 ? v ss ? ground. ? 16 ? test i test input: it must be connected to v ss ? 19 ? s3c72q5/p72q5 product overview 1- 7 pin circuit diagrams p-channel n-channel in v dd figure 1-3. pin circuit type a schmitt trigger pull-up resistor v dd pull-up resistor enable in p-channel figure 1-4. pin circuit type a-3 schmitt trigger in v dd pull-up resistor figure 1-5. pin circuit type b p-channel n-channel v dd out output disable data figure 1-6 . pin circuit type c product overview s3c72q 5/p72q5 1- 8 n-ch pull-up resistor enable v dd i/o pne pull-up resistor output disable data schmitt trigger v dd p-ch figure 1-7 . pin circuit type e-2 pull-up resistor enable v dd i/o pull-up resistor output disable data schmitt trigger circuit type c p-ch figure 1-8. pin circuit type e-3 s3c72q5/p72q5 product overview 1- 9 out com v lc1 v lc2 v ss v lc4 n-ch key strobe output disable figure 1- 9. pin circuit type h-4 out seg v lc1 v lc2 v ss v lc3 figure 1-10. pin circuit type h-5 out seg v lc1 v lc2 v ss v lc3 output disable figure 1- 1 1 . pin circuit type h -6 out com v lc1 v lc2 v ss v lc3 output disable figure 1- 1 2. pin circuit type h-7 product overview s3c72q 5/p72q5 1- 10 n-ch out output disable1 data circuit type h-6 n-ch output disable2 seg key strobe figure 1- 1 3. pin circuit type h-9 p-ch n-ch v dd i/o output disable1 data circuit type h-6 output disable2 seg figure 1- 1 4. pin circuit type h-10 p-ch n-ch v dd out output disable1 data circuit type h-6 output disable2 seg figure 1- 1 5. pin circuit type h-11 v dd i/o pull-up resistor output disable2 data p-ch type h-7 resistor enable output disable1 com type c n-ch key strobe figure 1- 1 6. pin circuit type h-12 s3c72q5/p72q5 addre ss space 2 - 1 2 address spaces program memory (rom) overview rom maps for s3c72q5 devices are mask programmable at the factory. in its standard configuration, the device's 16,384 bytes program memory has four areas that are directly addressable by the program counter (pc): ? 1 4 -byte area for vector addresses ? 18 -byte general-purpose area ? 96-byte instruction reference area ? 16,256 -byte general-purpose area general-purpose program memory two program memory areas are allocated for general-purpose use: one area is 18 -byte in size and the other is 16,256 -byte. vector addresses a 1 4 -byte vector address area is used to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to set their initial value for the corresponding service routines. the 1 4 -byte area can be used alternately as general-purpose rom. ref instructions locations 0020h - 007fh are used as a reference area (look-up table) for 1-byte ref instructions. the ref instruction reduces the byte size of instruction operands. ref can reference one 2 -byte instruction, two 1-byte instructions, and one 3 -byte instructions which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom . table 2- 1 . program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h - 000 d h 1 4 general-purpose program memory 000 e h - 001fh 18 ref instruction look-up table area 0020h - 007fh 96 general-purpose program memory 0080h -3 fffh 16,256 address space s3c72 q5/p72q5 2- 2 general-purpose memory areas the 18 -byte area at rom locations 000 e h - 001fh and the 16,256 -byte area at rom locations 0080h -3 fffh are used as general-purpose program memory. unused locations in the vector address area and ref instruction look-up table areas can be used as general-purpose program memory. however, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area the 14 -byte vector address area of the rom is used to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (emb) and enable register bank (erb) flag values that are needed to initialize the service routines. 16-byte vector addresses are organized as follows: emb erb 0 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 to set up the vector address area for specific programs, use the instruction ventn. the programming tips on the next page explain how to do this. vector address area (14 bytes) general purpose area (18 bytes) instruction reference area (96 bytes) general purpose area (16,256 bytes) 0000h 001fh 0020h 007fh 0080h 3fffh 000dh 000eh figure 2- 1 . rom address structure 0000h reset basic timer int0 int1 timer/counter0 timer/counter1 7 0002h 0004h 0006h 0008h 000ah 000ch intp0 6 5 4 3 2 1 0 figure 2- 2 . vector address map s3c72q5/p72q5 addre ss space 2 - 3 + + p rogramming tip ? defining vectored interrupts the following examples show you several ways you can define the vectored interrupt and instruction reference a reas in program memory: 1. when all vector interrupts are used: org 0000h ; vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address by int0 vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address by int1 vent4 0,0,intp0 ; emb ? 0, erb ? 0; jump to intp0 address by intp0 vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address by intt0 vent6 0,0,intt 1 ; emb ? 0, erb ? 0; jump to intt 1 address by intt1 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb org 0006h ; int0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address by int1 vent4 0,0,intp0 ; emb ? 0, erb ? 0; jump to intp0 address by intp0 ; intt0 interrupt not used org 000ch vent6 0,0,intt 1 ; emb ? 0, erb ? 0; jump to intt 1 address by intt1 3. if an int0 and intt1 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a org instruction in example 2, a cpu malfunction will occur: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int 1 address by int1 vent4 0,0,intp0 ; emb ? 0, erb ? 0; jump to int p0 address by intp0 vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address by intt0 in this example, when an intp0 interrupt is generated, the corresponding vector area is not vent4 intp0, but vent5 intt0. this causes an intp0 interrupt to jump incorr ectly to the intt0 address and causes a cpu malfunction to occur. address space s3c72 q5/p72q5 2- 4 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger byte sizes that are stored in ad - dresses 0020h - 007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two 1 -byte instructions, one 2 -byte instruc tion, or one 3 -byte instruction such as a jp (jump) or call. the starting address of the instruction you are referenc ing must always be an even number . to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. in summary, there are three ways to the ref instruction: by using ref instructions , you can execute instructions larger than one byte. in summary, there are three ways you can use the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instruc tions ? br anching to any location by referencing a branch instruct ion stored in the look-up table ? calling subroutines at any location by referencing a call instruct ion stored in the look-up table + + programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h ; jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl abc ld ea,#00h ; 47, ea ? #00h org 0080 ; main nop nop ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a : incs hl ref abc ; ld ea,#00h (1-byte instruction) s3c72q5/p72q5 addre ss space 2 - 5 data memory (ram) overview in its standard configuration, the data memories have four areas: ? 32 x 4-bit working register area ? 224 x 4 -bit general-purpose area in bank 0 which is also used as the stack area ? 20 pages with 256 x 4 - bit in bank1 19 page s for general purpose area (00h- 12h page) 1 page for lcd display data memory (13h page) ? 128 4-bit area in bank 15 for memory-mapped i/o addresses to make it easier to reference, the data memory area has three memory banks ? bank 0, bank 1, and bank 15. the select memory bank instruction (smb) is used to select the bank you want to select as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. one exception is the display data memory area, which is 8-bit addressable only . initialization values for the data memory area are not defined by hardware therefore must be initialized by program software following power reset . however, when reset signal is generated in power-down mode, the most of the data memory contents are held. bank 1 page selection register (pasr) pasr is a 5-bit write -only register for selecting the page of bank1 ,and is mapped to the ram address fa0h. it should be written by a 8-bit ram control instruction only and the msb 3 bits should be "0". pasr retains the previous value as long as change is not required, and the reset value is 0. therefore, when it returns to the b ank 1 from other bank (b ank 0 or b ank 15) without changing the contents of pasr, the previously specified b ank 1 page is selected . the pasr must not be changed in the interrupt service routine because it's value cannot be recovered as the original value when the routine is finished. address space s3c72 q5/p72q5 2- 6 100h page (12h) 1ffh 100h page (11h) 1ffh 100h page (10h) 1ffh 100h page (0fh) 1ffh 100h 1ffh 100h page (07h) 1ffh 100h page (06h) 1ffh 100h page (05h) 1ffh 100h page (04h) 1ffh 100h page (03h) 1ffh 100h page (02h) 1ffh 100h page (01h) 1ffh 000h 1ffh bank 1 (emb=1,smb=1) 0ffh 100h 3 2 1 0 general- purpose registers page (00h) general- purpose and/or stack registers working registers display data registers page (13h) f80h fffh peripheral hardware register bank15 (emb=1 smb=15, or emb=0) bank 0 (emb=1, smb = 0 or emb=0) 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 110h 1abh 1b0h 1b1h 1b2h 1b3h 1b4h 1b5h 1b6h 1b7h 1b8h 1b9h 1bah 1bbh 020h figure 2- 3 . s3c72q5 data memory (ram) map s3c72q5/p72q5 addre ss space 2 - 7 memory banks 0, 1, and 15 bank 0 (000h - 0ffh) the lowest 32 nibbles of bank 0 (000h - 01fh) are used as working registers; the next 224 nibbles (020h - 0ffh) can be used both as stack area and as general- purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (100h - 1ffh) bank 1 has the data memory of 20 pages , the 00h-12h pages for general purpose data memory are compr ised of 256 x 4-bits, and the 13h page for lcd display data memory consists of 1 44 x 5-bits. the s3c72q5 use specially a bank 1 page selection register (pasr) for selecting one of these 20 pages. bank 15 (f80h - fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1, or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access locations 000h - 07fh of bank 0 and bank 15. with indirect addressing, only bank 0 (000h - 0ffh) can be accessed. when the emb flag is set to logic one, all three data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. also, when using 8-bit instructions to address ram locations, remember to use the even-numbered register address as the instruction operand . working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and , 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea as an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and , 3 for interrupt service routines. lcd data register area bit values for lcd segment data are stored in data memory bank 1 (13h page). register locations in this area that are not used to store lcd data can be assigned to general-purpose use. table 2- 2 . data memory organization and addressing addresses register areas bank emb value smb value 000h - 01fh working registers 0 0, 1 0 020h - 0ffh stack and general-purpose registers 100h 1 1ffh general-purpose registers ( 00h-12h pages) lcd display data memory (the 13 th page) 1 1 1 f80h - fffh i/o-mapped hardware registers 15 0, 1 15 note: lcd data register is 13h page in data memory b ank 1 . address space s3c72 q5/p72q5 2- 8 + + programming tip ? clearing data memory bank 0 , and the page 0 in bank 1 clear bank 0 of the data memory area, and the page 0 of the data memory area in bank 1 smb 15 ld ea, #00h ld pasr, ea ramclr smb 1 ; page 0 in bank 1 clear ld hl,#00h ld a,#0h rmcl1 ld @hl,a incs hl jr rmcl1 ; smb 0 ; bank 0 clear ld hl,# 2 0h rmcl0 ld @hl,a incs hl jr rmcl0 s3c72q5/p72q5 addre ss space 2 - 9 working registers working registers, mapped to ram address 000h-01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit unit, 4-bit unit , or using paired registers, as 8-bit unit. a e l h x w z y bank 1 same as bank 0 000h 001h 002h 003h 004h 005h 006h 007h 008h 00fh 010h 017h 018h 01fh register bank 1 (erb = 1, srb = 1) register bank 0 (erb = 0, or erb = 1 and srb = 0) bank 2 same as bank 0 bank 3 same as bank 0 register bank 2 (erb = 1, srb = 2) register bank 3 (erb = 1, srb = 3) figure 2-4. working register map address space s3c72 q5/p72q5 2- 10 working register banks for addressing purposes, the working register area is divided into four register banks - bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srb n) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing. table 2- 3 . working register organization and addressing erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' means don't care. paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers, named y, z, w, x, h, l, e and a, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz and wl. registers a, l, x and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. (msb) (lsb) (msb) (lsb) y w h e z x l a figure 2-5. register pair configuration s3c72q5/p72q5 addre ss space 2 - 11 special-purpose working registers register a is used as a 4-bit accumulator and double register ea as an 8-bit accumulator. the carry flag can also be used as a 1-bit accumulator. 8-bit double registers wx, wl and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working registers as program loop counters by letting you transfer a value to the l register and increment or decrement it using a single instruction. c a ea 1-bit accumulator 4-bit accumulator 8-bit accumulator figure 2-6. 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have been executed successfully, you can restore the register contents from the stack to working memory by using the pop instruction. address space s3c72 q5/p72q5 2- 12 + + programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address ; int0 push sb ; push current smb, srb srb 2 ; instruction does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx register contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register contents from stack pop yz ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address ; int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb , srb iret s3c72q5/p72q5 addre ss space 2 - 13 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp can be read or written by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has been completed, the stack pointer is referenced to restore the pc and psw, and the next in struction is executed. the sp can address stack registers in bank 0 (addresses 000h-0ffh) regardless of the current value of the enable memory bank (emb) flag and the select memory bank (smb) flag. although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. + + p rogramming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of accumulator a is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) ? (sp) - 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h - 7fh, f80h - fffh) address space s3c72 q5/p72q5 2- 14 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push instructions, call instructions, and interrupts. in each case, the sp is decremented by a number determined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has been executed, the sp is decremented by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to six 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc and the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has been executed, the sp is decremented by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. lower register upper register sp - 2 sp - 1 sp push (after push, sp sp - 2) sp - 1 sp pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 0 0 emb erb 0 0 0 0 sp - 2 sp - 3 sp - 4 sp - 5 sp - 6 psw sp - 1 sp interrupt (when int is acknowledged, sp sp - 6) pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb c sp - 2 sp - 3 sp - 4 sp - 5 sp - 6 psw sc2 sc1 sc0 call, lcall (after call or lcall, sp sp - 6) figure 2-7. push-type stack operations s3c72q5/p72q5 addre ss space 2 - 15 pop operations for each push operation, there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. after the pop has been executed, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the six 4-bit stack locations used for the call and to write this data back to the pc, the emb, and the erb. after the ret or sret has been executed, the sp is incremented by six and points to the next free stack location. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4- bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has been executed, the sp is incremented by six and points to the next free stack location. sp pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 0 0 emb erb 0 0 0 0 psw pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb c psw sc2 sc1 sc0 iret (sp sp + 6) ret or sret (sp sp + 6) pop (sp sp + 2) sp + 1 sp + 1 lower register upper register sp + 5 sp + 6 sp + 4 sp + 3 sp + 2 sp + 1 sp sp + 5 sp + 6 sp + 4 sp + 3 sp + 2 sp + 1 sp figure 2-8. pop-type stack operations address space s3c72 q5/p72q5 2- 16 bit sequential carrier (bsc) the bsc can be manipulated using 1-, 4-, and 8-bit ram control instructions. reset clears all bsc bit values to logic zero. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing ( memb.@l). (bit addressing is independent of the current emb value.) in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, the 4-bit register names bsc0 and bsc2 must be specified and the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2- 4 . bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 + + programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p2.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p2.0,c ; p2.0 ? c incs l jr agn ret s3c72q5/p72q5 addre ss space 2 - 17 program counter (pc) a 13 -bit program counter (pc) stores addresses for instruction fetches during program execution. whenever a reset operation or an interrupt occurs, bits pc1 2 through pc0 are set to the vector address. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1- byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an inter rupt request has been serviced. psw values are mapped as follows: fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or hardware interrupt. after the in - terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logic zero. table 2- 5 . program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r address space s3c72 q5/p72q5 2- 18 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. you can manipulate is0 and is1 flags directly using 1-bit ram control instructions. by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next higher priority level. then, when the interrupt service routine ends with an iret instruction, is0 and is1 values are restored to the psw. table 2- 6 shows the effects of is0 and is1 flag settings. since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. before interrupt status flags can be addressed, however, you must first execute a di instruction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei instruction to re -enable interrupt processing. table 2- 6 . interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt(s) as determined in the interrupt priority register (ipr) are serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined + + programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt ? ? ? iret s3c72q5/p72q5 addre ss space 2 - 19 emb flag (emb) the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks. when the emb flag is "0", the data memory address space is restricted to addresses 0f80h - 0fffh of data memory bank 15 and 000h - 07fh of bank 0, regardless of the smb register contents. when the emb flag is set to "1", the addressing area of data memory is expanded and all of data memory space can be accessed by using the appropriate smb value. + + programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 1 ; non-essential instruction since emb = "0" ld a,#9h ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 0 ; non-essential instruction since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential inst ruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h,a ; (f90h) ? a, bank 15 is selected 2. when emb = "1": smb 1 ; select memory bank 1 ld a,#9h ld 90h,a ; (190h) ? a, bank 1 is selected ld 34h,a ; (134h) ? a, bank 1 is selected smb 0 ; select memory bank 0 ld 90h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) ? a, bank 15 is selected address space s3c72 q5/p72q5 2- 20 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (srb). when the erb flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (srb). when an internal reset is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service routine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored interrupt are defined using ventn instructions. + + programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? bank2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea s3c72q5/p72q5 addre ss space 2 - 21 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 indicate the current program skip conditions and are set and reset automatically during program execution. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2- 7, affect the carry flag. table 2- 7 . valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit ldb c,(operand) (1) load contents of the specified bit to carry flag boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes: 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. ' intn' refers to the specific interrupt being executed and is not an instruction. address space s3c72 q5/p72q5 2- 22 + + programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p2.0 and output the result to p5.0: ld h,#3h ; set the upper four bits of the address to the h register ; value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p2.0 ; c ? c and p2.0 ldb p5.0,c ; output result from carry flag to p5.0 s3c72q5/p72q5 addressing modes 3 - 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when the emb flag is set to logic one, you can address the entire ram area; when the emb flag is cleared to logic zero, the addressable area in the ram is restricted to specific locations. the emb flag works in connection with the select memory bank instruction, smbn. you will recall that the smbn instruction is used to select ram bank 0, 1, or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1 ") apply specifically to the m emo ry bank indicated by the smb instruction, and any restrictions to the addressable area within banks 0, 1, or 15. direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. several ram locations are addressable at all times, regardless of the current emb flag setting. here are a few guidelines to keep in mind regarding data memory addressing: ? when you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. ? display ram locations in bank 1 are 8 -bit addressable only. ? always use an even-numbered ram address as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address. addressing modes s3c72q5/p72q5 3 - 2 notes: 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. addressing mode ram areas working registers da da.b @hl @h+da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 emb = 0 emb = 1 x x x bank 0 (general registers and stack) bank 1 000h 01fh 020h 07fh 080h 0ffh 100h 1ffh f80h fffh smb = 0 smb = 0 smb = 1 bank 15 (peripheral hardware registers) smb = 15 smb = 15 ff0h fb0h fbfh fc0h smb = 1 figure 3- 1 . ram address structure s3c72q5/p72q5 addressing modes 3 - 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, initializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has completed. at the beginning of a program, the initial emb and erb flag values for each vectored interrupt must be set by using vent instruction. the emb and erb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0, reset ; emb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 vent4 0,1,intp0 ; emb ? 0, erb ? 1, branch intp0 vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 vent 6 0,1,intt 1 ; emb ? 0, erb ? 1, branch intt 1 reset bitr emb addressing modes s3c72q5/p72q5 3 - 4 enable memory bank settings emb = "1" when the enable memory bank flag emb is set to logic one, you can address the data memory bank specified by the select memory bank (smb) value (0, 1, or 15) using 1-, 4-, or 8-bit instructions. you can use both direct and indirect addressing modes. the addressable ram areas when emb = "1" are as follows: if smb = 0, 000h - 0ffh if smb = 1, 100h - 1ffh if smb = 15, f80h - fffh emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h - 07fh in bank 0 and to locations f80h - fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h - 0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing at any time, several areas of the data memory can be addressed independent of the current status of the emb flag. these exceptions are described in table 3- 1. table 3- 1 . ram addressing not affected by the emb value address addressing method affected hardware program examples 000h - 0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx ld ea,sp fb0h - fbfh ff0h - fffh 1-bit direct addressing psw, scmod, iex, irqx, i/o bits emb bitr ie2 fc0h - fffh 1-bit indirect addressing using the l register i/o btst f3h.@l band c,p3.@l s3c72q5/p72q5 addressing modes 3 - 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3- 2. during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. smb 3 sb register smb srb smb 2 smb 1 smb 0 0 0 srb 1 srb 0 figure 3- 2 . smb and srb values in the sb register select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that is set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero . select memory bank (smb) instruction to select one of the three available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1, or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. (and remember to enable the selected memory bank by making the appropriate emb flag setting). the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero . the push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls. addressing modes s3c72q5/p72q5 3 - 6 direct and indirect addressing 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. indirect addressing specifies a memory location that contains the required direct address. the ks57 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand. 1-bit addressing table 3- 2 . 1-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h - 07fh bank 0 ? da.b direct: bit is indicated by the ram address (da), memory bank selection, and specified bit number (b). 0 f80h - fffh bank 15 all 1-bit ad dressable peripherals (smb = 15) 1 000h - fffh smb = 0, 1, 15 mema.b direct: bit is indicated by ad - dressable area ( mema) and bit number (b). x fb0h - fbfh ff0h - fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.m memb.@l indirect: address is indicated by the up per 6 bits of ram area ( memb) and the upper 2 bits of register l, and bit is indicated by the lower 2 bits or register l. x fc0h - fffh bank 15 pn.m @h + da.b indirect: bit is indicated by the lower four bits of the address (da), memory bank selection, and the h register identifier. 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 15 all 1-bit ad dressable pe ripherals (smb = 15) note : 'x' means don't care. s3c72q5/p72q5 addressing modes 3 - 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 ? 1 btst cflag ; if fbah.0 = 1, skip bits bflag ; else if, fbah.0 = 0, f85h.3 ? 1 bits p2.0 ; ff2h.0 (p2.0) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p2.0 ; ff2h.0 (p2.0) ? 1 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h. 3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fbah.0 ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1 addressing modes s3c72q5/p72q5 3 - 8 4-bit addressing table 3- 3 . 4-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h - 07fh bank 0 ? da direct: 4-bit address indicated by the ram address (da) and the memory bank selection 0 f80h - fffh bank 15 all 4-bit ad dressable pe ripherals 1 000h - fffh smb = 0, 1, 15 (smb = 15) @hl indirect: 4-bit address indi - cated by the memory bank selection and register hl 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 15 all 4-bit ad dressable peripherals (smb = 15) @wx indirect: 4-bit address indi - cated by register wx x 000h - 0ffh bank 0 ? @wl indirect: 4-bit address indi - cated by register wl x 000h - 0ffh bank 0 note : 'x' means don't care. s3c72q5/p72q5 addressing modes 3 - 9 + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 85h smb 15 ; non-essential instruction, since emb = "0" ld a,p4 ; a ? (p4) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f85h (bmod)) ? a 2. if emb = "1": adata equ 46h bdata equ 85h smb 15 ld a,p4 ; a ? (p4) smb 0 ld adata,a ; (046h) ? a ld bdata,a ; (085h) ? a 4-bit indirect addressing (example 1) 1. if emb = "0", compare bank 0 locations 040h - 046h with bank 0 locations 060h - 066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h - 046h) cpse a,@hl ; if bank 0 (060h - 066h) = a, skip sret decs l jr comp ret 2. if emb = "1", co mpare bank 0 locations 040h - 046h to bank 1 locations 160h - 166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h - 046h) cpse a,@hl ; if bank 1 (160h - 166h) = a, skip sret decs l jr comp ret addressing modes s3c72q5/p72q5 3 - 10 + + programming tip ? 4-bit addressing modes (con tinu ed) 4-bit indirect addressing (example 2) 1. if emb = "0", exchange bank 0 locations 040h - 046h with bank 0 locations 060h - 066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h - 046h) xchd a,@hl ; bank 0 (060h - 066h) ? a jr trans 2. if emb = "1", exchange bank 0 locations 040h - 046h to bank 1 locations 160h - 166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h - 046h) xchd a,@hl ; bank 1 (160h - 166h) ? a jr trans s3c72q5/p72q5 addressing modes 3 - 11 8-bit addressing table 3- 4 . 8-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h - 07fh bank 0 ? da direct: 8-bit address indicated by the ram address ( da = even number ) and memory bank selection 0 f80h - fffh bank 15 all 8-bit ad dressable pe ripherals (smb = 15) 1 000h - fffh smb = 0, 1, 15 @hl indirect: the 8-bit address indi - cated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 15 all 8-bit addressable pe ripherals (smb = 15) addressing modes s3c72q5/p72q5 3 - 12 + + programming tip ? 8-bit addressing modes 8-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8ch smb 15 ; non-essential instruction, since emb = "0" ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8ch) ? a, (f8dh) ? e 2. if emb = "1": adata equ 46h bdata equ 8ch smb 15 ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08ch) ? a, (08dh) ? e 8-bit indirect addressing 1. if emb = "0": adata equ 46h smb 1 ; non-essential instruction, since emb = "0" ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) 2. if emb = "1": adata equ 46h smb 1 ld hl,#adata ld ea,@hl ; a ? (146h), e ? (147h) s3c72q5/p72q5 memory map 4 - 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4- 1 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register locations f80h - fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non- manipulable) ? read-only, write-only, or read and write addressability ? 1-bit, 4-bit, or 8-bit data manipulation characteristics memory map s3c72q5/p72q5 4 - 2 table 4- 1 . i/o map for memory bank 15 addressing symbol description affected memory mapped i/o 1 - bit direct addressing da.b the bit indicated by memory bank, da and bit. (emb=0, or emb=1 and smb 15) all peripheral hardware that can be manipulated in 1 bit. 4 - bit direct addressing da the address indicated by memory bank and da. (emb=0, or emb=1 and smb 15) all peripheral hardware that can be manipulated in 4 bits. 8 - bit direct addressing da the address (da specifies an even address) indicated by memory bank and d a. (emb=0, or emb=1 and smb 15) all peripheral hardware that can be manipulated in 8 bits. 4 - bit indirect addressing @hl the address indicated by memory bank and hl register. (emb=1 and smb 15) all peripheral hardware that can be manipulated in 4 bits. 8 - bit indirect addressing @hl the address indicated by memory bank and hl (the contents of the l register are even). (emb=1 and smb 15) all peripheral hardware that can be manipulated in 8 bit. 1 -bit manipulating mema.b the bit indicated by mema and bit. (regardless of the status of emb and smb) is0, is1, emb, erb, iex, irqx, pn.m addressing memb.@l the bit indicated by the lower 2 bits of the l register of the address indicated by the upper 10 bits of memb and the upper 2 bits of the l reigster. (regardless of the status of emb and smb) pn.m @ h+da.b the bit of the address indicated by memory bank, h register and the lower 4 bits of da. (emb=1 and smb=15) all peripheral hardware that can be manipulated in 1 bit. s3c72q5/p72q5 memory map 4 - 3 table 4- 2 . i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 locations f82h-f84h are not mapped. f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h wmod .3 .2 .1 .0 w .3 (1) no yes f89h .7 "0" .5 .4 f8ah lcnst .3 .2 .1 .0 w no no yes f8bh .7 "0" "0" "0" f8ch lmod .3 .2 .1 .0 w no no yes f8dh "0" .6 .5 .4 f8eh lcon0 .3 .2 .1 .0 w no yes no f8fh lcon1 .3 .2 .1 .0 w no yes no f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h "0" toe0 "0" "0" r/w yes yes no location f93h is not mapped. f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h f98h wdmod .3 .2 .1 .0 w no no yes f99h .7 .6 .5 .4 f9ah wdflag (2) wdtcf "0" "0" "0" w .3 yes no locations f9bh-f9fh are not mapped. fa0h pasr .3 .2 .1 .0 w no no yes fa1h "0" "0" "0" .4 fa2h ksr0 .3 .2 .1 .0 w no yes no fa3h ksr1 .3 .2 .1 .0 fa4h ksr2 .3 .2 .1 .0 fa5h ksr3 .3 .2 .1 .0 memory map s3c72q5/p72q5 4 - 4 table 4- 2 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fa6h tmod1 .3 .2 "0" "0" w .3 no yes fa7h "0" .6 .5 .4 fa8h tcnt1 r no no yes fa9h faah tref1 w no no yes fabh locations fach-fafh are not mapped. fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c (3) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 "0" "0" .1 .0 w no yes no fb5h imod1 "0" "0" .1 .0 w no yes no fb6h imod2 "0" .2 .1 .0 w no yes no fb7h scmod .3 .2 "0" .0 w yes no no fb8h "0" "0" ieb irqb r/w yes yes no location fb9h is not mapped. fbah "0" "0" iew irqw r/w yes yes no fbbh "0" "0" iet1 irqt1 r/w yes yes no fbch "0" "0" iet0 irqt0 r/w yes yes no fbdh "0" "0" iep0 irqp0 r/w yes yes no fbeh ie1 irq1 ie0 irq0 r/w yes yes no fbfh "0" "0" ie2 irq2 r/w yes yes no fc0h bsc0 r/w yes yes yes fc1h bsc1 fc2h bsc2 fc3h bsc3 locations fc4h-fc9h are not mapped. fcah emar0 .3 .2 .1 .0 r/w no no yes fcbh .7 .6 .5 .4 fcch emar1 .3/.11 .2/.10 .1/.9 .0/.8 fcdh .7/.15 .6/.14 .5/.13 .4/.12 fceh emar2 "0" .2/.18 .1/.17 .0/.16 r/w no yes no location fcfh is not mapped. s3c72q5/p72q5 memory map 4 - 5 table 4- 2 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fd0h clmod .3 "0" .1 .0 w no yes no location fd1h is not mapped. fd2h emcon .3 .2 .1 .0 w no no yes fd3h .7 .6 .5 .4 fd4h emdr0 .3 .2 .1 .0 r/w no no yes fd5h .7 .6 .5 .4 locations fd6h-fe5h are not mapped. fe6h pne0 (5) .3 .2 .1 .0 w no no yes fe7h .7 .6 .5 .4 fe8h pumod0 (6) "0" "0" "0" pur0 w no no yes fe9h pur7 pur6 pur5 pur4 feah pmg0 pm0.3 pm0.2 pm0.1 pm0.0 w no no yes febh "0" pm1.2 pm1.1 pm1.0 fech pmg1 pm4.3 pm4.2 pm4.1 pm4.0 w no no yes fedh pm5.3 pm5.2 pm5.1 pm5.0 feeh pmg2 pm6.3 pm6.2 pm6.1 pm6.0 w no no yes fefh pm7.3 pm7.2 pm7.1 pm7.0 ff0h port0 (p0) .3 .2 .1 .0 r/w yes yes yes ff1h port1 (p1) "0" .2/.6 .1/.5 .0/.4 locations ff2h-ff3h are not mapped. ff4h port4 (p4) .3 .2 .1 .0 r/w yes yes yes ff5h port5 (p5) .3/.7 .2/.6 .1/.5 .0/.4 ff6h port6 (p6) .3 .2 .1 .0 r/w yes yes yes ff7h port7 (p7) .3/.7 .2/.6 .1/.5 .0/.4 notes: 1. bit 3 in the wmod register is read only. 2. f9ah.0, f9ah.1 and f9ah.2 are fixed to "0". 3. the carry flag can be read or written by specific bit manipulation instructions only. 4. the pne0 register is used to select the output types of ports 4,5 (zero: push-pull output type, one: open-drain output type). the reset value of the pne1 register is "00h". 5. the pumod0 register is used to enable/disable the internal pull-up resistors of port 0, 1, 4, 5, 6 and 7 (zero: disable, one: enable). the reset value of the pumod0 register is "00h". memory map s3c72q5/p72q5 4 - 6 register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4- 1 describes features of the register description format. register descriptions are arranged in alphabetical order. programmers can use this section as a quick-reference source when writing application programs. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. more detailed information about how these registers are used is included in part ii of this manual, "hardware descriptions," in the context of the corresponding peripheral hardware module descriptions. s3c72q5/p72q5 memory map 4 - 7 clmod - clock output mode control register clmod.3 enable/disable clock output control bit clmod.2 bit 2 0 always logic zero clmod.1 - .0 clock source and frequency selection control bits 3 2 1 0 bit identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 r = read-only w = write-only r/w = read/write bit value immediately after a reset bit number in msb to lsb order type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) description of the effect of specific bit settings bit identifier used for bit addressing register and bit ids used for bit addressing cpu fd0h associated hardware module register location in ram bank 15 name of individual bit or related bits register name register id select cpu clock souce fx/4, fx/8, fx/64 (1.05 mhz, 524khz, or 65.5 khz), or fxt/4 select system clock fxx/8 (524 khz at 4.19 mhz) select system clock fxx/16 (262 khz at 4.19 mhz) select system clock fxx/64 (65.5 khz at 4.19 mhz) 0 0 1 1 0 1 0 1 0 disable clock output at the clo pin 0 enable clock output at the clo pin figure 4- 1 . register description format memory map s3c72q5/p72q5 4 - 8 bmod ? basic timer mode register bt f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 bmod.3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero bmod.2 - .0 input clock frequency and interrupt interval time 0 0 0 input clock frequency: interrupt interval time (wait time): fxx/2 12 (1.02 khz) 2 20 / fxx (250 ms) 0 1 1 input clock frequency: interrupt interval time (wait time): fxx/2 9 (8.18 khz) 2 17 / fxx (31.3 ms) 1 0 1 input clock frequency: interrupt interval time (wait time): fxx /2 7 (32.7 khz) 2 15 / fxx (7.82 ms) 1 1 1 input clock frequency: interrupt interval time (wait time): fxx /2 5 (131 khz) 2 13 / fxx (1.95 ms) notes: 1 . when a reset occurs, the oscillator stabilization wait time is 31.3 ms (2 17 / fxx) at 4.19 mhz. 2 . ' fxx' is the system clock frequency (assume that fxx is 4.19 mhz ) . s3c72q5/p72q5 memory map 4 - 9 clmo d ? clock output mode register cpu f d0 h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 clmod .3 enable/disable clock output control bit 0 disable clock output at the clo pin 1 enable clock output at the clo pin clmod .2 bit 2 0 always logic zero clmod .1 - .0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx /8, or fx/ 64 ( 1 m hz, 524 khz, or 65.5 khz) or fxt/4 0 1 select system clock fxx/8 (524 khz) 1 0 select system clock fxx/16 (262 khz) 1 1 select system clock fxx/64 (65.5 khz) note: ' f x x' is the system clock, given a clock frequency of 4.19 mhz. memory map s3c72q5/p72q5 4 - 10 emcon ? external memory control register cpu fd3h, fd2h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w r/w bit addressing 8 8 8 8 8 8 8 8 emcon.7 memory read/write control bit 0 memory read signal output 1 memory write signal output emcon.6-.5 memory access clock selection bits 0 0 fxx/8 0 1 fxx/4 1 0 fxx/2 1 1 fxx/1 emcon.4 address increment control bit 0 the address(a value of emar2 - emar0) is not increased automatically after memory access. 1 the address(a value of emar2 - emar0) is increased automatically after memory access. emcon.3-.1 memory selection bits .3 .2 .1 external data memory selection 0 0 0 data memory 0( dm 0 active) 0 0 1 data memory 1( dm 1 active) 0 1 0 data memory 2( dm 2 active) 0 1 1 data memory 3( dm 3 active) 1 0 0 data memory 4( dm 4 active) 1 0 1 data memory 5( dm 5 active) emcon.0 memory access start bit 0 not busy (read) 1 start a memory access (write), busy (read) notes: 1. when it reads data from a external memory, the data are written to the register emdr0. 2. when it writes data to a external memory, the data to the register emdr0 are written to a external memory. 3. the external memory selection pins of p6.0/dm0 - p7.1/dm5 should be set to push-pull output and the latches should be set to logic "1". 4. p7.1/ dm 5/com11 is not used as dm 5, when it is selected to com. for using dm 5, this pin is set to output high. (in this case, this dm signal is falling to low on access start.) 5. emcon.0 is cleared automatically when memory access is finished. s3c72q5/p72q5 memory map 4 - 11 ie0, irq0 ? int 0 interrupt enable/request flags cpu f be h ie1, irq 1 ? int 1 interrupt enable/request flags cpu f be h bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at int0 pin.) memory map s3c72q5/p72q5 4 - 12 ie2, irq2 ? int 2 interrupt enable/request flags cpu f bf h bit 3 2 1 0 identifier " u " " u " ie2 irq2 reset reset value u u 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 u this bit is undefined. ie2 int2 interrupt enable flag 0 disable int2 interrupt requests at the ks0 - ks7 pins 1 enable int2 interrupt requests at the ks0 - ks7 pins irq2 int2 interrupt request flag ? generate int2 quasi-interrupt (this bit is set and is not cleared automatically by hardware when a falling edge is detected at one of the ks0 - ks7 pins. since int2 is a quasi-interrupt, irq2 flag must be cleared by software.) note: the "u" means a undefined register bit s3c72q5/p72q5 memory map 4 - 13 ieb, irqb ? int b interrupt enable/request flags cpu f b8 h bit 3 2 1 0 identifier " u " " u " ieb irqb reset reset value u u 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 u this bit is undefined. ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (this bit is set and cleared automatically by hardware when reference interval signal received from basic timer.) note: the "u" means a undefined register bit. memory map s3c72q5/p72q5 4 - 14 iep0, irqp0 ? int p0 interrupt enable/request flags cpu f bd h bit 3 2 1 0 identifier " u " " u " ie p 0 irq p 0 reset reset value u u 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 u this bit is undefined. iep0 ints interrupt enable flag 0 disable intp0 interrupt requests 1 enable intp0 interrupt requests irqp0 ints interrupt request flag ? generate intp0 interrupt (this bit is set and cleared automatically by hardware when falling edge is detected at k0-k3 pin.) notes: 1. the "u" means a undefined register bit. 2. to use intp0 interrupt, p0 and p1 must be set to external interrupt pins by lmod.6-lmod.4, input mode by pmg0 and pull-up resistor enable by pumod0. s3c72q5/p72q5 memory map 4 - 15 iet0, irqt0 ? int t0 interrupt enable/request flags cpu f bc h bit 3 2 1 0 identifier " u " " u " ie t0 irqt0 reset reset value u u 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 u this bit is undefined. iet 0 intt 0 interrupt enable flag 0 disable intt 0 interrupt requests 1 enable intt 0 interrupt requests irqt 0 intt 1 interrupt request flag ? generate intt 0 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt 0 and tref 0 registers match.) note: the "u" means a undefined register bit. memory map s3c72q5/p72q5 4 - 16 iet1, irqt1 ? int t1 interrupt enable/request flags cpu f bb h bit 3 2 1 0 identifier " u " " u " ie t1 irqt1 reset reset value u u 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 u this bit is undefined. iet 1 intt 1 interrupt enable flag 0 disable intt 1 interrupt requests 1 enable intt 1 interrupt requests irqt 1 intt 1 interrupt request flag ? generate intt 1 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt 1 and tref 1 registers match.) note: the "u" means a undefined register bit. s3c72q5/p72q5 memory map 4 - 17 iew, irqw ? int w interrupt enable/request flags cpu f ba h bit 3 2 1 0 identifier " u " " u " iew irqw reset reset value u u 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 u this bit is undefined. iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (this bit is set when the timer interval is set to 0.5 seconds or 3. 91 milliseconds.) note s : 1. since intw is a quasi-interrupt, the irqw flag must be cleared by software. 2. the " u " means a undefined register bit. memory map s3c72q5/p72q5 4 - 18 imod0 ? external interrupt 0 (int0) mode register cpu f b4 h bit 3 2 1 0 identifier "0" "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod0 .3 - .2 bit s 3-2 0 always logic zero imod0 .1 - .0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising edge 0 1 interrupt requests are triggered by a falling edge 1 0 interrupt requests are triggered by both rising and falling edges 1 1 interrupt request flag (irq0) cannot be set to logic one s3c72q5/p72q5 memory map 4 - 19 imod1 ? external interrupt 1 (int1) mode register cpu f b5 h bit 3 2 1 0 identifier "0" "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod1 .3 - .2 bit s 3-2 0 always logic zero imod1 .1 - .0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising edge 0 1 interrupt requests are triggered by a falling edge 1 0 interrupt requests are triggered by both rising and falling edges 1 1 interrupt request flag (irq1) cannot be set to logic one memory map s3c72q5/p72q5 4 - 20 imod2 ? external interrupt 2 (int2) mode register cpu f b6 h bit 3 2 1 0 identifier "0" .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod2 .3 bits 3 0 always logic zero imod2 . 2- .0 external interrupt 2 edge detection selection bit 0 0 0 interrupt request at ks 0- ks 3 triggered by falling edge 0 0 1 interrupt request at ks 0- ks 4 triggered by falling edge 0 1 0 interrupt request at ks 0- ks 5 triggered by falling edge 0 1 1 interrupt request at ks0 - ks 6 triggered by falling edge 1 0 0 interrupt request at ks 0- ks7 triggered by falling edge 1 0 1 not available 1 1 0 1 1 1 s3c72q5/p72q5 memory map 4 - 21 ipr ? interrupt priority register cpu f b2 h bit 3 2 1 0 identifier ime .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit 0 disable all interrupt processing 1 enable processing for all interrupt service requests ipr.2-.0 interrupt priority register setting ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb interrupt at highest priority 0 1 0 process int0 interrupt at highest priority 0 1 1 process int1 interrupt at highest priority 1 0 0 process intp0 interrupt at highest priority 1 0 1 process intt0 interrupt at highest priority 1 1 0 process intt 1 interrupt at highest priority 1 1 1 not available memory map s3c72q5/p72q5 4 - 22 lcnst ? lcd contrast control register lcd f8bh, f8ah bit 7 6 5 4 3 2 1 0 identifier .7 "0" "0" "0" .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 lcnst.7 enable/disable lcd contrast control bit 0 disable lcd contrast control 1 enable lcd contrast control lcnst.6-.4 bits 6-4 0 always logic zero lcnst.3-.0 lcd contrast level control bits(16 steps) .3 .2 .1 .0 step 0 0 0 0 1/16 step (the dimmest level) 0 0 0 1 2/16 step 0 0 1 0 3/16 step 1 1 1 1 16/16 step (the brightest level) note: v lcd = v dd x (1-(16-n)/48), where n = 0 - 15(at normal lcd dividing resistors). s3c72q5/p72q5 memory map 4 - 23 lcon0 ? lcd output control register 0 lcd f 8e h bit 3 2 1 0 identifier .3 .2 "0" "0" reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 lcon0.3-.2 bits3-2 0 0 1/9 duty(com0-com8 select) 0 1 1/10 duty(com0-com9 select) 1 0 1/11 duty(com0-com10 select) 1 1 1/12 duty(com0-com11 select) lcon0.1-.0 bit s 1-0 0 always logic zero notes: 1. com has priority over normal port in p7.3/com9-p7.1/com11. this means these port are assigned to co m pins regardless of the value of pmg2, when duty is selected to 1/10, 1/11, or 1/12 at lcon0. 2. the port used com must be set to output to prevent lcd display distortion. memory map s3c72q5/p72q5 4 - 24 lcon1 ? lcd output control register 1 lcd f 8f h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 lcon1.3-.0 bits 3-0 0 1 0 0 lcd display on 0 1 0 1 dimming mode 1 0 0 1 key check signal output with lcd display off notes: 1. to turn off lcd display, you must set lcon1 to 9 not 0. 2. p8 can be used to normal output port, when lcd display is off. the value of p8 is determined by ksr0-ksr3 regardless of lmod.0. (refer to p12-17) s3c72q5/p72q5 memory map 4 - 25 lmod ? lcd mode register lcd f8dh, f 8c h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 lmod.7 bit 7 0 always logic zero lmod.6 - .4 external interrupt (intp0) pins selection bits (1) 0 0 0 interrupt request at k0 triggered by falling edge 0 0 1 interrupt request at k0-k1 triggered by falling edge 0 1 0 interrupt request at k0-k2 triggered by falling edge 0 1 1 interrupt request at k0-k3 triggered by falling edge 1 0 0 interrupt request at k0-k4 triggered by falling edge 1 0 1 interrupt request at k0-k5 triggered by falling edge 1 1 0 interrupt request at k0-k6 triggered by falling edge 1 1 1 interrupt request flag (irqp0) cannot be set to logic one lmod.3 - .2 watch timer clock selection bits (2) .3 .2 when main system clock is selected as watch timer clock by wmod.0 0 0 fx/128 0 1 fx/64 1 0 fx/32 1 1 fx/16 lmod.1 lcd dividing resistor selection bit 0 normal lcd dividing resistors 1 diminish lcd dividing resistors to strengthen lcd drive lmod. 0 key strobe signal output control bit(seg0/p8.0 - seg15/p8.15) 0 enable key strobe signal output 1 disable key strobe signal output (3) notes: 1. the pins which are not selected as external interrupts(k0 - k6) can be used to normal i/o. to use external interrupts, corresponding pins must be set to input and pull-up enable mode. 2. lcd clock can be selected only when main clock( fx) is used as clock source of watch timer. when sub clock( fxt) is used as clock source of watch timer, lcd clock is always fw/48(1/9 duty), fw/44(1/10 duty), fw/40(1/11 duty), or fw/36(1/12 duty). 3. refer to page 12 -7. memory map s3c72q5/p72q5 4 - 26 s3c72q5/p72q5 memory map 4 - 27 pasr ? page selection register memory fa1h, f a0 h bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pasr .7 - .5 bits 7 - 5 0 always logic zero pasr .4-.0 page selection register in the bank1 0 0 0 0 0 00h page in the bank1 0 0 0 0 1 01h page in the bank1 1 0 0 1 1 13h page for lcd display register in the bank1 memory map s3c72q5/p72q5 4 - 28 pcon ? power control register cpu f b3 h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pcon.3 - .2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode pcon.1 - .0 cpu clock frequency selection bits 0 0 if scmod.0 = "0", fx/64; if scmod.0 = "1", fxt/4 1 0 if scmod.0 = "0", fx/8; if scmod.0 = "1", fxt/4 1 1 if scmod.0 = "0", fx/4; if scmod.0 = "1", fxt/4 note: ' fx' is the main system clock; ' fxt' is the subsystem clock. s3c72q5/p72q5 memory map 4 - 29 pmg0 ? port i/o mode register 0 (group 0: port 0,1) i/o febh, feah bit 7 6 5 4 3 2 1 0 identifier "0" pm1.2 pm1.1 pm1.0 pm0.3 pm0.2 pm0.1 pm0.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pmg0.7 bit 7 0 always logic zero pm1.2 p1.2 i/o mode selection flag 0 set p1.2 to input mode 1 set p1.2 to output mode pm1.1 p1.1 i/o mode selection flag 0 set p1.1 to input mode 1 set p1.1 to output mode pm1.0 p1.0 i/o mode selection flag 0 set p1.0 to input mode 1 set p1.0 to output mode pm0.3 p0.3 i/o mode selection flag 0 set p0.3 to input mode 1 set p0.3 to output mode pm0.2 p0.2 i/o mode selection flag 0 set p0.2 to input mode 1 set p0.2 to output mode pm0.1 p0.1 i/o mode selection flag 0 set p0.1 to input mode 1 set p0.1 to output mode pm0.0 p0.0 i/o mode selection flag 0 set p0.0 to input mode 1 set p0.0 to output mode note: to used intp0 interrupt, p0 and p1 must be set to external interrupt pins by lmod.6-lmod.4, input mode by pmg0 and pull-up resistor enable by pumod0. memory map s3c72q5/p72q5 4 - 30 pmg1 ? port i/o mode register 1(group 1: port 4,5) i/o fedh, fech bit 7 6 5 4 3 2 1 0 identifier pm5.3 pm5.2 pm5.1 pm5.0 pm4.3 pm4.2 pm4.1 pm4.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm5.3 p5.3 i/o mode selection flag 0 set p5.3 to input mode 1 set p5.3 to output mode pm5.2 p5.2 i/o mode selection flag 0 set p5.2 to input mode 1 set p5.2 to output mode pm5.1 p5.1 i/o mode selection flag 0 set p5.1 to input mode 1 set p5.1 to output mode pm5.0 p5.0 i/o mode selection flag 0 set p5.0 to input mode 1 set p5.0 to output mode pm4.3 p4.3 i/o mode selection flag 0 set p4.3 to input mode 1 set p4.3 to output mode pm4.2 p4.2 i/o mode selection flag 0 set p4.2 to input mode 1 set p4.2 to output mode pm4.1 p4.1 i/o mode selection flag 0 set p4.1 to input mode 1 set p4.1 to output mode pm4.0 p4.0 i/o mode selection flag 0 set p4.0 to input mode 1 set p4.0 to output mode s3c72q5/p72q5 memory map 4 - 31 pmg2 ? port i/o mode register 2 (group 2: port 6,7) i/o fefh, feeh bit 7 6 5 4 3 2 1 0 identifier pm7.3 pm7.2 pm7.1 pm7.0 pm6.3 pm6.2 pm6.1 pm6.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm7.3 p7.3 i/o mode selection flag 0 set p7.3 to input mode 1 set p7.3 to output mode pm7.2 p7.2 i/o mode selection flag 0 set p7.2 to input mode 1 set p7.2 to output mode pm7.1 p7.1 i/o mode selection flag 0 set p7.1 to input mode 1 set p7.1 to output mode pm7.0 p7.0 i/o mode selection flag 0 set p7.0 to input mode 1 set p7.0 to output mode pm6.3 p6.3 i/o mode selection flag 0 set p6.3 to input mode 1 set p6.3 to output mode pm6.2 p6.2 i/o mode selection flag 0 set p6.2 to input mode 1 set p6.2 to output mode pm6.1 p6.1 i/o mode selection flag 0 set p6.1 to input mode 1 set p6.1 to output mode pm6.0 p6.0 i/o mode selection flag 0 set p6.0 to input mode 1 set p6.0 to output mode note: com has priority over normal port in p7.3/com9-p7.1/com11. this means these port are assigned to com pins regardless of the value of pmg2, when duty is selected to 1/10, 1/11 or 1/12 at lcon0. memory map s3c72q5/p72q5 4 - 32 pne0 ? n-channel open-drain mode register 0 i/o fe7h, fe6h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pne0.7 p5.3 n-channel open-drain configurable bit 0 configure p5.3 as a push-pull 1 configure p5.3 as a n-channel open-drain pne0.6 p5.2 n-channel open-drain configurable bit 0 configure p5.2 as a push-pull 1 configure p5.2 as a n-channel open-drain pne0.5 p5.1 n-channel open-drain configurable bit 0 configure p5.1 as a push-pull 1 configure p5.1 as a n-channel open-drain pne0.4 p5.0 n-channel open-drain configurable bit 0 configure p5.0 as a push-pull 1 configure p5.0 as a n-channel open-drain pne0.3 p4.3 n-channel open-drain configurable bit 0 configure p4.3 as a push-pull 1 configure p4.3 as a n-channel open-drain pne0.2 p4.2 n-channel open-drain configurable bit 0 configure p4.2 as a push-pull 1 configure p4.2 as a n-channel open-drain pne0.1 p4.1 n-channel open-drain configurable bit 0 configure p4.1 as a push-pull 1 configure p4.1 as a n-channel open-drain pne0.0 p4.0 n-channel open-drain configurable bit 0 configure p4.0 as a push-pull 1 configure p4.0 as a n-channel open-drain s3c72q5/p72q5 memory map 4 - 33 psw ? program status word cpu fb1h, f b0 h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset reset value (1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (2) 8 8 8 1/4/8 1/4/8 1/4/8 1/4/8 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2 - sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h - fffh) and to the locations 000h - 07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (srb) instruction operand notes: 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carr y flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information. memory map s3c72q5/p72q5 4 - 34 pumod0 ? pull - up resistor mode register i/o fe9h, fe8h bit 7 6 5 4 3 2 1 0 identifier pur7 pur6 pur5 pur4 "0" "0" "0" pur0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pur7 connect/disconnect port 7 pull-up resistor control bit 0 disconnect port 7 pull-up resistor 1 connect port 7 pull-up resistor pur6 connect/disconnect port 6 pull-up resistor control bit 0 disconnect port 6 pull-up resistor 1 connect port 6 pull-up resistor pur5 connect/disconnect port 5 pull-up resistor control bit 0 disconnect port 5 pull-up resistor 1 connect port 5 pull-up resistor pur4 connect/disconnect port 4 pull-up resistor control bit 0 disconnect port 4 pull-up resistor 1 connect port 4 pull-up resistor pumod0.3-.1 bit 3-1 0 always logic zero pur0 connect/disconnect port 0,1 pull-up resistor control bit 0 disconnect port 0,1 pull-up resistor 1 connect port 0,1 pull-up resistor notes: 1. if port is set to output mode, pull-up resistor is disabled automatically. 2. when p0, p1 are used to external interrupt pins, the pull-up resistors of input mode are determined by key strobe signal (refer to p12-7). s3c72q5/p72q5 memory map 4 - 35 scmod ? system clock mode control register cpu f b7 h bit 3 2 1 0 identifier .3 .2 "0" .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1 1 1 1 scmod.3 bit 3 0 enable main system clock 1 disable main system clock scmod.2 bit 2 0 enable sub system clock 1 disable sub system clock scmod.1 bit 1 0 always logic zero scmod.0 bit 0 0 select main system clock 1 select sub system clock notes: 1. sub-oscillation goes into stop mode only by scmod.2. pcon which r evokes stop mode cannot stop the sub-oscillation. 2. you can use scmod.2 as follows (ex; after data bank was used, a few minutes have passed): main operation ? sub-operation ? sub-idle (lcd on, after a few minutes later without any external input) ? sub operation ? main operation ? scmod.2 = 1 ? main stop mode (lcd off). 3. scmod bit3-0 can not be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions. memory map s3c72q5/p72q5 4 - 36 tmod0 ? timer/counter 0 mode register t/c0 f90h, f 91 h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1 /8 8 8 8 tmod0 .7 bit 7 0 always logic zero tmod0.6-.4 timer/counter0 input clock selection bits (1) (2) 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 0 1 x fxt(subsystem clock: 32.768 khz) 1 0 0 fxx /2 10 ( 4.09 khz) 1 0 1 fxx/2 6 (65.5 khz) 1 1 0 fxx/2 4 (262khz) 1 1 1 fxx (4.19 mhz) tmod0.3 clear counter and resume counting control bit 1 clear tcnt0,irqt0,and tol0 and resume counting immediately.(this bit is cleared automatically when counting starts) tmod0.2 enable/disable timer/counter0 bit 0 disable timer/counter0 ; retain tcnt0 contents 1 enable timer/counter0 tmod0.1 bit 1 0 always logic zero tmod0.0 bit 0 0 always logic zero notes: 1. ' fxx' is the system clock frequency (assume that fxx is 4.19mhz). 2. `x` is don`t care. s3c72q5/p72q5 memory map 4 - 37 tmod1 ? timer/counter 1 mode register t/c1 fa7h, fa6h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 tmod1.7 bit 7 0 always logic zero tmod1.6-.4 timer/counter1 input clock selection bits (1) (2) 0 1 x fxt(subsystem clock: 32.768 khz) 1 0 0 fxx /2 10 ( 4.09 khz) 1 0 1 fxx/2 6 (65.5 khz) 1 1 0 fxx/2 4 (262khz) 1 1 1 fxx (4.19 mhz) tmod1.3 clear counter and resume counting control bit 1 clear tcnt1 and irqt1 and resume counting immediately.(this bit is cleared automatically when counting starts) tmod1.2 enable/disable timer/counter1 bit 0 disable timer/counter1 ; retain tcnt1 contents 1 enable timer/counter1 tmod1.1 bit 1 0 always logic zero tmod1.0 bit 0 0 always logic zero notes: 1. ' fxx' is the system clock frequency (assume that fxx is 4.19mhz). 2. `x` is don`t care. memory map s3c72q5/p72q5 4 - 38 toe0 ? timer/output enable flag register t/c0 f92 h bit 3 2 1 0 identifier "0" toe0 "0" "0" reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1 /4 1 /4 1 /4 1/4 . 3 bit 3 0 always logic zero toe0 clear counter and resume counting control bit 0 disable timer/counter 0 clock output at the tclo0 pin 1 enable timer/counter 0 clock output at the tclo0 pin .1- .0 bit 1-0 0 always logic zero s3c72q5/p72q5 memory map 4 - 39 wdflag ? watch-dog timer?s counter clear flag bt f9ah.3 bit 3 2 1 0 identifier wdtcf "0" "0" "0" reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 1/4 1/4 1/4 wdtcf watch-dog timer's counter clear bit 0 ? 1 clear the wdt's counter to zero and restart the wdt's counter wdflag.2-.0 bit 2-0 0 always logic zero memory map s3c72q5/p72q5 4 - 40 wdmod ? watch-dog timer mode control register bt f 99 h, f 98 h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 wdmod.7-.0 watch-dog timer enable/disable control 0 1 0 1 1 0 1 0 disable watch-dog timer function other values enable watch-dog timer function s3c72q5/p72q5 memory map 4 - 41 wmod ? watch timer mode register wt f89h, f88h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 (note) 0 0 0 read/write w w w w r w w w bit addressing 8 8 8 8 1 8 8 8 wmod.7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output at the buz pin 1 enable buzzer (buz) signal output at the buz pin wmod.6 bit 6 0 always logic zero wmod.5-.4 output buzzer frequency selection bits 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 xt in input level control bit 0 input level to xt in pin is low; 1-bit read-only addressable for tests 1 input level to xt in pin is high; 1-bit read-only addressable for tests wmod.2 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer wmod.1 watch timer speed control bit 0 normal speed: set irqw to 0.5 seconds 1 high-speed operation: set irqw to 3.91 ms wmod.0 watch timer clock selection bit 0 select main system clock( fx)/128 as the watch timer clock select main system clock ( fx) as a lcd clock source. 1 select a subsystem clock as the watch timer clock select a subsystem clock as a lcd clock source. note: reset sets wmod.3 to the current input level of the subsystem clock, xt in . if the input level is high, wmod.3 is set to logic one; if low, wmod.3 is cleared to zero along with all the other bits in the wmod register s3c72q5/p72q5 sam48 instruction set 5- 1 5 sam48 instruction s et overview the sam48 instruction set is specifically designed to support the large register files typically founded in most s3c7-series microcontrollers. the sam48 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and cpu control. i/o instructions for peripheral hardware devices are flexible and easy to use. symbolic hardware names can be substituted as the instruction operand in place of the actual address. other important features of the sam48 instruction set include: ? 1-byte referencing of long instructions (ref instruction) ? redundant instruction reduction (string effect) ? skip feature for adc and sbc instructions instruction operands conform to the operand format defined for each instruction. several instructions have multiple operand formats. predefined values or labels can be used as instruction operands when addressing immediate data. many of the symbols for specific registers and flags may also be substituted as labels for operations such da, mema, memb, b, and so on. using instruction labels can greatly simplify programming and debugging tasks. instruction set features in this section, the following sam48 instruction set features are described in detail: ? instruction reference area ? instruction redundancy reduction ? flexible bit manipulation ? adc and sbc instruction skip condition notes: 1. the rom size accessed by instruction may change for different devices in the sam48 product family (jp, jps, call, and calls). 2. the number of memory bank selected by smb may change for different devices in the sam48 product family. 3. the port names used in the instruction set may change for different devices in the sam48 product family. 4. the interrupt names and the interrupt numbers used in the instruction set may change for different devices in the sam 48 product family. sam48 instruction set s3c72q5/p72q5 5- 2 instruction reference area using the 1-byte ref (reference) instruction, you can reference instructions stored in addresses 0020h-007fh of program memory (the ref instruction look-up table). the location referenced by ref may contain either two 1-byte instructions or a single 2-byte instruction. the starting address of the instruction being referenced must always be an even number. 3-byte instructions such as jp or call may also be referenced using ref. to reference these 3-byte instructions, the 2-byte pseudo commands tjp and tcall must be written in the reference. the pc is not incremented when a ref instruction is executed. after it executes, the program's instruction execution sequence resumes at the address immediately following the ref instruction. by using ref instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the program size. to summarize, the ref instruction can be used in three ways: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions; ? branching to any location by referencing a branch address that is stored in the look-up table; ? calling subroutines at any location by referencing a call address that is stored in the look-up table. if necessary, a ref instruction can be circumvented by means of a skip operation prior to the ref in the execution sequence. in addition, the instruction immediately following a ref can also be skipped by using an appropriate reference instruction or instructions. two-byte instruction can be referenced by using a ref instruction (an exception is xch a, da). if the msb value of the first one-byte instruction in the reference area is ?0?, the instruction cannot be referenced by a ref instruction. therefore, if you use ref to reference two 1-byte instruction stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. these combination examples are described in table 5-1. table 5-1. valid 1-byte instruction combinations for ref look-ups first 1-byte instruction second 1-byte instruction instruction operand instruction operand ld a, #im incs (note) r incs rrb decs (note) r ld a, @rra incs (note) r incs rrb decs (note) r ld @hl, a incs (note) r incs rrb decs (note) r note: the msb value of the instruction is ?0?. s3c72q5/p72q5 sam48 instruction set 5- 3 reducing instruction redundancy when redundant instructions such as ld a,#im and ld ea,#imm are used consecutively in a program sequence, only the first instruction is executed. the redundant instructions which follow are ignored, that is, they are handled like a nop instruction. when ld hl,#imm instructions are used consecutively, redundant instructions are also ignored. in the following example, only the 'ld a, #im' instruction will be executed. the 8-bit load instruction which follows it is interpreted as redundant and is ignored: ld a,#im ; load 4-bit immediate data (#im) to accumulator ld ea,#imm ; load 8-bit immediate data (#imm) to extended accumulator in this example, the statements 'ld a,#2h' and 'ld a,#3h' are ignored: bitr emb ld a,#1h ; execute instruction ld a,#2h ; ignore, redundant instruction ld a,#3h ; ignore, redundant instruction ld 23h,a ; execute instructi on, 023h ? #1h if consecutive ld hl, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, hl) are detected, only the first ld is executed and the lds which immediately follow are ignored. for example, ld hl,#10h ; hl ? 10h ld hl,#20h ; ignore, redundant instruction ld a,#3h ; a ? 3h ld ea,#35h ; ignore, redundant instruction ld @hl,a ; (10h) ? 3h if an instruction reference with a ref instruction has a redundancy effect, the following conditions apply: ? if the instruction preceding the ref has a redundancy effect, this effect is cancelled and the referenced instruction is not skipped. ? if the instruction following the ref has a redundancy effect, the instruction following the ref is skipped. + + p rogramming tip ? example of the instruction redundancy effect org 0020h abc ld ea,#30h ; stored in ref instruction reference area org 0080h ? ? ? ld ea,#40h ; redundancy effe ct is encountered ref abc ; no skip (ea ? #30h) ? ? ? ref abc ; ea ? #30h ld ea,#50h ; skip sam48 instruction set s3c72q5/p72q5 5- 4 flexible bit manipulation in addition to normal bit manipulation instructions like set and clear, the sam48 instruction set can also perform bit tests, bit transfers, and bit boolean operations. bits can also be addressed and manipulated by special bit addressing modes. three types of bit addressing are supported: ? mema.b ? memb.@l ? @h+da.b the parameters of these bit addressing modes are described in more detail in table 5-2. table 5-2. bit addressing modes and parameters addressing mode addressable peripherals address range mema.b erb, emb, is1, is0, iex, irqx fb0h-fbfh ports ff0h-fffh memb.@l ports, and bsc fc0h-fffh @h+da.b all bit-manipulatable peripheral hardware all bits of the memory bank specified by emb and smb that are bit-manipulatable note : some device in the sam48 product family don?t have bsc. instructions which have skip conditions the following instructions have a skip function when an overflow or borrow occurs: xchi incs xchd decs ldi ads ldd sbs if there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. however, the carry flag value is unaffected. the instructions btst, btsf, and cpse also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. instructions which affect the carry flag the only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: adc ldb c,(operand) sbc band c,(operand) scf bor c,(operand) rcf bxor c,(operand) ccf iret rrc s3c72q5/p72q5 sam48 instruction set 5- 5 adc and sbc instruction skip conditions the instructions 'adc a,@hl' and 'sbc a,@hl' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ads a,#im'. if an 'ads a,#im' instruction immediately follows an 'adc a,@hl' or 'sbc a,@hl' instruction in a program sequence, the ads instruction does not skip the instruction following it, even if it has a skip function. if, however, an 'adc a,@hl' or 'sbc a,@hl' instruction is immediately followed by an 'ads a,#im' instruction, the adc (or sbc) skips on overflow (or if there is no borrow) to the instruction immediately following the ads, and program execution continues. table 5-3 contains additional information and examples of the 'adc a,@hl' and 'sbc a,@hl' skip feature. table 5-3. skip conditions for adc and sbc instructions sample instruction sequences if the result of instruction 1 is: then, the execution sequence is: reason adc a,@hl ads a,#im xxx xxx 1 2 3 4 overflow no overflow 1, 3, 4 1, 2, 3, 4 ads cannot skip instruc- tion 3, even if it has a skip function. sbc a,@hl ads a,#im xxx xxx 1 2 3 4 borrow no borrow 1, 2, 3, 4 1, 3, 4 ads cannot skip instruc- tion 3, even if it has a skip function. sam48 instruction set s3c72q5/p72q5 5- 6 symbols a nd conventions table 5-4. data type symbols symbol data type d immediate data a address data b bit data r register data f flag data i indirect addressing data t memc 0.5 immediate data table 5-5. register identifiers full register name id 4-bit accumulator a 4-bit working registers e, l, h, x, w, z, y 8-bit extended accumulator ea 8-bit memory pointer hl 8-bit working registers wx, yz, wl select register bank 'n' srb n select memory bank 'n' smb n carry flag c program status word psw port 'n' pn 'm'-th bit of port 'n' pn.m interrupt priority register ipr enable memory bank flag emb enable register bank flag erb table 5-6. instruction operand notation symbol definition da direct address @ indirect address prefix src source operand dst destination operand (r) contents of register r .b bit location im 4-bit immediate data (number) imm 8-bit immediate data (number) # immediate data prefix adr 000h-3fffh immediate address adrn 'n' bit address r a, e, l, h, x, w, z, y ra e, l, h, x, w, z, y rr ea, hl, wx, yz rra hl, wx, wl rrb hl, wx, yz rrc wx, wl mema fb0h-fbfh, ff0h-fffh memb fc0h-fffh memc code direct addressing: 0020h-007fh sb select bank register (8 bits) xor logical exclusive-or or logical or and logical and [(rr)] contents addressed by rr s3c72q5/p72q5 sam48 instruction set 5- 7 opcode definitions table 5-7. opcode definitions (direct) register r2 r1 r0 a 0 0 0 e 0 0 1 l 0 1 0 h 0 1 1 x 1 0 0 w 1 0 1 z 1 1 0 y 1 1 1 ea 0 0 0 hl 0 1 0 wx 1 0 0 yz 1 1 0 r = immediate data for register table 5-8. opcode definitions (indirect) register i2 i1 i0 @hl 1 0 1 @wx 1 1 0 @wl 1 1 1 i = immediate data for indirect addressing calculating additional machine cycles for skips a machine cycle is defined as one cycle of the selected cpu clock. three different clock rates can be selected using the pcon register. in this document, the letter 's' is used in tables when describing the number of additional machine cycles re quired for an instruction to execute, given that the instruction has a skip function ('s' = skip). the addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped ? whether it is a 1-byte, 2-byte, or 3-byte instruction. a skip is also executed for smb and srb instructions. the values in additional machine cycles for 's' for the three cases in which skip conditions occur are as follows: case 1: no skip s = 0 cycles case 2: skip is 1-byte or 2-byte instruction s = 1 cycle case 3: skip is 3-byte instruction s = 2 cycles note : ref instructions are skipped in one machine cycle. sam48 instruction set s3c72q5/p72q5 5- 8 high-level summary this section contains a high-level summary of the sam48 instruction set in table format. the tables are designed to familiarize you with the range of instructions that are available in each instruction category. these tables are a useful quick-reference resource when writing application programs. if you are reading this user's manual for the first time, however, you may want to scan this detailed information briefly, and then return to it later on. the following information is provided for each instruction: ? instruction name ? operand(s) ? brief operation description ? number of bytes of the instruction and operand(s) ? number of machine cycles required to execute the instruction the tables in this section are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions s3c72q5/p72q5 sam48 instruction set 5- 9 table 5-9. cpu control instructions ? high-level summary name operand operation description bytes cycles scf ? set carry flag to logic one 1 1 rcf reset carry flag to logic zero 1 1 ccf complement carry flag 1 1 ei enable all interrupts 2 2 di disable all interrupts 2 2 idle engage cpu idle mode 2 2 stop engage cpu stop mode 2 2 nop no operation 1 1 smb n select memory bank 2 2 srb n select register bank 2 2 ref memc reference code 1 1 ventn emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location 2 2 table 5-10. program control instructions ? high-level summary name operand operation description bytes cycles cpse r,#im compare and skip if register equals #im 2 2 + s @hl,#im compare and skip if indirect data memory equals #im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s jp adr jump to direct address (14 bits) 3 3 jps adr jump direct in page (12 bits) 2 2 jr #im jump to immediate address 1 2 @wx branch relative to wx register 2 3 @ea branch relative to ea 2 3 call adr call direct in page (14 bits) 3 4 calls adr call direct in page (11 bits) 2 3 ret ? return from subroutine 1 3 iret ? return from interrupt 1 3 sret ? return from subroutine and skip 1 3 + s sam48 instruction set s3c72q5/p72q5 5- 10 table 5-11. data transfer instructions ? high-level summary name operand operation description bytes cycles xch a,da exchange a and direct data memory contents 2 2 a,ra exchange a and register (ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory con tents 2 2 ea,rrb exchange ea and register pair (rrb) contents 2 2 ea,@hl exchange ea and indirect data memory con tent s 2 2 xchi a,@hl exchange a and indirect data memory contents; increment contents of register l and skip on carry 1 2 + s xchd a,@hl exchange a and indirect data memory contents; decrement contents of register l and skip on carry 1 2 + s ld a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 ldi a,@hl load indirect data memory to a; increment register l contents and skip on carry 1 2 + s ldd a,@hl load indirect data memory contents to a; decrement register l contents and skip on carry 1 2 + s ldc ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 rrc a rotate right through carry bit 1 1 push rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 pop rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2 s3c72q5/p72q5 sam48 instruction set 5- 11 table 5-12. logic instructions ? high-level summary name operand operation description bytes cycles and a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair (rrb) 2 2 or a, #im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 xor a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair (rrb) to ea 2 2 com a complement accumulator (a) 2 2 table 5-13. arithmetic instructions ? high-level summary name operand operation description bytes cycles adc a,@hl add indirect data memory to a with carry 1 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair (rrb) with carry 2 2 ads a, #im add 4-bit immediate data to a and skip on carry 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on carry 2 2 + s a,@hl add indirect data memory to a and skip on carry 1 1 + s ea,rr add register pair (rr) contents to ea and skip on carry 2 2 + s rrb,ea add ea to register pair (rrb) and skip on carry 2 2 + s sbc a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair (rrb) with carry 2 2 sbs a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair (rrb); skip on borrow 2 2 + s decs r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s incs r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s rrb increment register pair (rrb); skip on carry 1 1 + s sam48 instruction set s3c72q5/p72q5 5- 12 table 5-14. bit manipulation instructions ? high-level summary name operand operation description bytes cycles btst c test specified bit and skip if carry flag is set 1 1 + s da.b test specified bit and skip if memory bit is set 2 2 + s mema.b memb.@l @h+da.b btsf da.b test specified memory bit and skip if bit equals "0" mema.b memb.@l @h+da.b btstz mema.b test specified bit; skip and clear if memory bit is set memb.@l @h+da.b bits da.b set specified memory bit 2 2 mema.b memb.@l @h+da.b bitr da.b clear specified memory bit to logic zero mema.b memb.@l @h+da.b band c,mema.b logical-and carry flag with specified memory bit c,memb.@l c,@h+da.b bor c,mema.b logical-or carry with specified memory bit c,memb.@l c,@h+da.b bxor c,mema.b exclusive-or carry with specified memory bit c,memb.@l c,@h+da.b ldb mema.b,c load carry bit to a specified memory bit memb.@l,c load carry bit to a specified indirect memory bit @h+da.b,c c,mema.b load specified memory bit to carry bit c,memb.@l load specified indirect memory bit to carry bit c,@h+da.b s3c72q5/p72q5 sam48 instruction set 5- 13 binary code summary this section contains binary code values and operation notation for each instruction in the sam48 instruction set in an easy-to-read, tabular format. it is intended to be used as a quick-reference source for programmers who are experienced with the sam48 instruction set. the same binary values and notation are also included in the detailed descriptions of individual instructions later in section 5. if you are reading this user's manual for the first time, please just scan this very detailed information briefly. most of the general information you will need to write application programs can be found in the high-level sum mary tables in the previous section. the following information is provided for each instruction: ? instruction name ? operand(s) ? binary values ? operation notation the tables in this section are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions sam48 instruction set s3c72q5/p72q5 5- 14 table 5-15. cpu control instructions ? binary code summary name operand binary code operation notation scf ? 1 1 1 0 0 1 1 1 c ? 1 rcf 1 1 1 0 0 1 1 0 c ? 0 ccf 1 1 0 1 0 1 1 0 c ? c ei 1 1 1 1 1 1 1 1 ime ? 1 1 0 1 1 0 0 1 0 di 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 idle 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 stop 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 nop 1 0 1 0 0 0 0 0 no operation smb n 1 1 0 1 1 1 0 1 smb ? n 0 1 0 0 d3 d2 d1 d0 srb n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 ref memc t7 t6 t5 t4 t3 t2 t1 t0 pc13-0 ? memc.5-0+ (memc+1).7-0 ventn emb (0,1) erb (0,1) adr e m b e r b a13 a12 a11 a10 a9 a8 rom (2 x n) 7-6 ? emb, erb rom (2 x n) 5-4 ? pc12,pc13 rom (2 x n) 3-0 ? pc11-8 rom (2 x n + 1) 7-0 ? pc7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0 s3c72q5/p72q5 sam48 instruction set 5- 15 table 5-16. program control instructions ? binary code summary name operand binary code operation notation cpse r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 jp adr 1 1 0 1 1 0 1 1 pc13-0 ? adr13-0 0 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 jps adr 1 0 0 1 a11 a10 a9 a8 pc13-0 ? pc13-12 + adr11-0 a7 a6 a5 a4 a3 a2 a1 a0 jr #im * pc13-0 ? adr (pc-15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc13-0 ? pc13-8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc13-0 ? pc13-8 + (ea) 0 1 1 0 0 0 0 0 call adr 1 1 0 1 1 0 1 1 [(sp-1) (sp-2)] ? emb, erb 0 1 a13 a12 a11 a10 a9 a8 [(sp-3) (sp-4)] ? pc7-0 a7 a6 a5 a4 a3 a2 a1 a0 [(sp-5) (sp-6)] ? pc13-8 calls adr 1 1 1 0 1 a10 a9 a8 [(sp-1) (sp-2)] ? emb, erb a7 a6 a5 a4 a3 a2 a1 a0 [(sp-3) (sp-4)] ? pc7-0 [(sp-5) (sp-6)] ? pc14-8 first byte condition * jr #im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc-1 to pc-15 sam48 instruction set s3c72q5/p72q5 5- 16 table 5-16. program control instructions ? binary code summary (continued) name operand binary code operation notation ret ? 1 1 0 0 0 1 0 1 pc13-8 ? (sp + 1) (sp) pc7-0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 4) sp ? sp + 6 iret ? 1 1 0 1 0 1 0 1 pc13-8 ? (sp + 1) (sp) pc7-0 ? (sp + 3) (sp + 2) psw ? (sp + 5) (sp + 4) sp ? sp + 6 sret ? 1 1 1 0 0 1 0 1 pc13-8 ? (sp + 1) (sp) pc7-0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 4) sp ? sp + 6 table 5-17. data transfer instructions ? binary code summary name operand binary code operation notation xch a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? (rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 xchi a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h xchd a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l-1; skip if l = 0fh ld a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? (rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0 s3c72q5/p72q5 sam48 instruction set 5- 17 table 5-17. data transfer instructions ? binary code summary (continued) name operand binary code operation notation ld ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0 rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 ldi a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h ldd a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l-1; skip if l = 0fh ldc ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc13-8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc13-8 + (ea)] rrc a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n-1 ? a.n (n = 1, 2, 3) push rr 0 0 1 0 1 r2 r1 1 ((sp-1)) ((sp-2)) ? (rr), (sp) ? (sp)-2 sb 1 1 0 1 1 1 0 1 ((sp-1)) ? (smb), ((sp-2)) ? (srb), (sp) ? (sp)-2 0 1 1 0 0 1 1 1 sam48 instruction set s3c72q5/p72q5 5- 18 table 5-17. data transfer instructions ? binary code summary (concluded) name operand binary code operation notation pop rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp + 1) sp ? sp + 2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp + 1), sp ? sp + 2 0 1 1 0 0 1 1 0 table 5-18. logic instructions ? binary code summary name operand binary code operation notation and a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 or a, #im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 xor a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 0 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 com a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1 s3c72q5/p72q5 sam48 instruction set 5- 19 table 5-19. arithmetic instructions ? binary code summary name operand binary code operation notation adc a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 ads a, #im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on carry ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on carry d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a+ (hl); skip on carry ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on carry 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on carry 1 0 0 1 0 r2 r1 0 sbc a,@hl 0 0 1 1 1 1 0 0 c,a ? a - (hl) - c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea -rr - c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb - ea - c 1 1 0 0 0 r2 r1 0 sbs a,@hl 0 0 1 1 1 1 0 1 a ? a - (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea - rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb - ea; skip on borrow 1 0 1 1 0 r2 r1 0 decs r 0 1 0 0 1 r2 r1 r0 r ? r-1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr-1; skip on borrow 1 1 0 1 1 r2 r1 0 incs r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry sam48 instruction set s3c72q5/p72q5 5- 20 table 5-20. bit manipulation instructions ? binary code summary name operand binary code operation notation btst c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7-2 + l.3-2]. [l.1-0] = 1 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3-0].b = 1 0 0 b1 b0 a3 a2 a1 a0 btsf da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7-2 + l.3-2]. [l.1-0] = 0 0 1 0 0 a5 a4 a3 a2 @h da.b 1 1 1 1 1 0 0 0 skip if [h + da.3-0].b = 0 0 0 b1 b0 a3 a2 a1 a0 btstz mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7-2 + l.3-2]. [l.1-0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3-0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 bits da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7-2 + l.3-2].[l.1-0] ? 1 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 1 1 1 [h + da.3-0].b ? 1 0 0 b1 b0 a3 a2 a1 a0 s3c72q5/p72q5 sam48 instruction set 5- 21 table 5-20. bit manipulation instructions ? binary code summary (continued) name operand binary code operation notation bitr da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7-2 + l3-2].[l.1-0] ? 0 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 1 1 0 [h + da.3-0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 band c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7-2 + l.3-2]. [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 bor c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7-2 + l.3-2]. [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 bxor c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7-2 + l.3-2]. [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh sam48 instruction set s3c72q5/p72q5 5- 22 table 5-20. bit manipulation instructions ? binary code summary (concluded) name operand binary code operation notation ldb mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7-2 + [l.3-2]. [l.1-0] ? c 0 1 0 0 a5 a4 a3 a2 @h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3-0].b ? (c) 0 0 b1 b0 a3 a2 a1 a0 c,mema.b * 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7-2 + [l.3-2] . [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 fff0h-fffh s3c72q5/p72q5 sam48 instruction set 5- 23 instruction descriptions this section contains detailed information and programming examples for each instruction of the sam48 instruction set. information is arranged in a consistent format to improve readability and for use as a quick- reference re source for application programmers. if you are reading this user's manual for the first time, please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set. the information elements of the instruction description format are as follows: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruc tion operand ? operation overview (from the "high-level summary" table) ? textual description of the instruction's effect ? binary code overview (from the "binary code summary" table) ? programming example(s) to show how the instruction is used sam48 instruction set s3c72q5/p72q5 5- 24 adc ? add with carry adc dst,src operation: operand operation summary bytes cycles a,@hl add indirect data memory to a with carry 1 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair (rrb) with carry 2 2 description: the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. if there is an overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is cleared. if 'adc a,@hl' is followed by an 'ads a,#im' instruction in a program, adc skips the ads instruction if an overflow occurs. if there is no overflow, the ads instruction is executed normally. (this condition is valid only for 'adc a,@hl' instructions. if an overflow occurs following an 'ads a,#im' instruction, the next instruction will not be skipped.) operand binary code operation notation a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" adc ea,hl ; ea ? 0c3h + 0aah + 1h = 6eh, c ? "1" jps xxx ; jump to xxx; no skip after adc 2. if the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" adc ea,hl ; ea ? 0c3h + 0aah + 0h = 6dh, c ? "1" jps xxx ; jump to xxx; no skip after adc s3c72q5/p72q5 sam48 instruction set 5- 25 adc ? add with carry adc (continued) examples: 3. if adc a,@hl is followed by an ads a,#im, the adc skips on carry to the instruction immediately after the ads. an ads instruction immediately after the adc does not skip even if an overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? oeh + 9h + c(0) = 7h, c ? "1" ads a,#0ah ; skip this instruction because c = "1" after adc result jps xxx b. 3 + 4 decimal a ddition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx sam48 instruction set s3c72q5/p72q5 5- 26 ads ? add and skip on overflow ads dst,src operation: operand operation summary bytes cycles a, #im add 4-bit immediate data to a and skip on overflow 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on overflow 2 2 + s a,@hl add indirect data memory to a and skip on overflow 1 1 + s ea,rr add register pair (rr) contents to ea and skip on overflow 2 2 + s rrb,ea add ea to register pair (rrb) and skip on overflow 2 2 + s description: the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. if there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. if 'ads a,#im' follows an 'adc a,@hl' instruction in a program, adc skips the ads instruction if an overflow occurs. if there is no overflow, the ads instruction is executed normally. this skip condition is valid only for 'adc a,@hl' instructions, however. if an overflow occurs following an ads instruction, the next instruction is not skipped. operand binary code operation notation a, #im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on overflow ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on overflow d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a + (hl); skip on overflow ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on overflow 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on overflow 1 0 0 1 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 0aah = 6dh ; ads skips on overflow, but carry flag value is not affected. jps xxx ; this instruction is skipped since ads had an overflow. jps yyy ; jump to yyy. s3c72q5/p72q5 sam48 instruction set 5- 27 ads ? add and skip on overflow ads (continued) examples: 2. if the extended accumulator contains the value 0c3h, register pair hl the value 12h, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 12h = 0d5h jps xxx ; jump to xxx; no skip after ads. 3. if 'adc a,@hl' is followed by an 'ads a,# im', the adc skips on overflow to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'adc a,@hl' does not skip even if overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? oeh + 9h + c(0) = 7h, c ? "1" ads a,#0ah ; skip this instruction beca use c = "1" after adc result. jps xxx b. 3 + 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh, c ? "0" ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx sam48 instruction set s3c72q5/p72q5 5- 28 and ? logical and and dst,src operation: operand operation summary bytes cycles a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair (rrb) 2 2 description: the source operand is logically anded with the destination operand. the result is stored in the destination. the logical and operation results in a "1" whenever the corresponding bits in the two operands are both "1"; otherwise a "0" is stored in the corresponding destination bit. the contents of the source are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 example: if the extended accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction and ea,hl leaves the value 41h (01000001b) in the extended accumulator ea . s3c72q5/p72q5 sam48 instruction set 5- 29 band ? bit logical and band c,src.b operation: operand operation summary bytes cycles c,mema.b logical-and carry flag with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically anded with the carry flag bit value. if the boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. the bit value of the source operand is not affected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7-2 + l.3-2]. [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. the following instructions set the carry flag if p1.0 (port 1.0) is equal to " 1" (and assuming the carry flag is already set to "1"): smb 15 ; c ? "1" band c,p1.0 ; if p1.0 = "1", c ? "1" ; if p1.0 = "0", c ? "0" 2. assume the p1 address is ff1h and the value for register l is 5h (0101b). the address (memb.7-2) is 111100b; (l.3-2) is 01b. the resulting address is 11110001b or ff1h, specifying p1. the bit value for the band instruction, (l.1-0) is 01b which specifies bit 1. therefore, p1.@l = p1.1: ld l,#5h band c,p1.@l ; p1.@l is specified as p1.1 ; c and p1.1 sam48 instruction set s3c72q5/p72q5 5- 30 band ? bit logical and band (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3-0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the band instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h band c,@h+flag ; c and flag (20h.3) s3c72q5/p72q5 sam48 instruction set 5- 31 bitr ? bit reset bitr dst.b operation: operand operation summary bytes cycles da.b clear specified memory bit to logic zero 2 2 mema.b 2 2 memb.@l 2 2 @h+da.b 2 2 description: a bitr instruction clears to logic zero (resets) the specified bit within the destination operand. no other bits in the destination are affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7-2 + l3-2].[l.1-0] ? 0 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 1 1 0 [h + da.3-0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. if the bit location 30h.2 in the ram has a current value of "1". the following instruction clears the third bit of location 30h to"0": bitr 30h.2 ; 30h.2 ? "0" 2. you can use bitr in the same way to manipulate a port address bit: bitr p0.0 ; p0.0 ? "0" sam48 instruction set s3c72q5/p72q5 5- 32 bitr ? bit reset bitr (continued) examples: 3. for clearing p0.2, p0.3, and p1.0-p1.3 to "0": ld l,#2h bp2 bitr p0. @l ; first, p0.@2h = p0.2 ; (111100b) + 00b.10b = 0f0h.2 incs l cpse l,#8h jr bp2 4. if bank 0, location 0a0h.0 is cleared (and regardless of whether the emb value is logic zero), bitr has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bitr @h+flag; bank 0 (ah + 0h).0 = 0a0h.0 ? "0? note: since the bitr instruction is used for output functions, the pin names used in the examples above may change for different devices i n the sam48 product family. s3c72q5/p72q5 sam48 instruction set 5- 33 bits ? bit set bits dst.b operation: operand operation summary bytes cycles da.b set specified memory bit 2 2 mema.b 2 2 memb.@l 2 2 @h+da.b 2 2 description: this instruction sets the specified bit within the destination without affecting any other bits in the destination. bits can manipulate any bit that is addressable using direct or indirect addressing modes. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7-2 + l.3-2].[l.1-0] ? 1 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 1 1 1 [h + da.3-0] ? 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. if the bit location 30h.2 in the ram has a current value of "0", the following instruction sets the second bit of location 30h to "1". bits 30h.2 ; 30h.2 ? "1" 2. yo u can use bits in the same way to manipulate a port address bit: bits p0.0 ; p0.0 ? "1" sam48 instruction set s3c72q5/p72q5 5- 34 bits ? bit set bits (continued) examples: 3. for setting p0.2, p0.3, and p1.0-p1.3 to "1": ld l,#2h bp2 bits p0.@l ; first, p0.@2h = p0.2 ; (111100b) + 00b.10b = 0f0h.2 incs l cpse l,#8h jr bp2 4. if bank 0, location 0a0h.0, is set to "1" and the emb = "0", bits has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bits @h+flag; bank 0 (ah + 0h).0 = 0a0h.0 ? "1" note: since the bits instruction is used for output functions, pin names used in the examples above may change for different devices in the sam48 product family. s3c72q5/p72q5 sam48 instruction set 5- 35 bor ? bit logical or bor c,src.b operation: operand operation summary bytes cycles c,mema.b logical-or carry with specified memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically ored with the carry flag bit value. the value of the source is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7-2 + l.3-2]. [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. the carry flag is logically ored with the p1.0 value: rcf ; c ? "0" bor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 1h (0001b). the address (memb.7-2) is 111100b and (l.3-2) = 00b. the resulting address is 11110000b or ff0h, specifying p0. the bit value for the bor instruction, (l.1-0) is 01b which specifies bit 1. therefore, p1.@l = p0.1: ld l,#1h bor c,p1.@l ; p1.@l is specified as p0.1; c or p0.1 sam48 instruction set s3c72q5/p72q5 5- 36 bor ? bit logical or bor (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address o f h is 0010b and flag(3-0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bor c,@h+flag ; c or flag (20h.3) s3c72q5/p72q5 sam48 instruction set 5- 37 btsf ? bit test and skip on false btsf dst.b operation: operand operation summary bytes cycles da.b test specified memory bit and skip if bit equals "0" 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "0", the btsf instruction skips the instruction which immediately follows it; otherwise the instruction following the btsf is executed. the destination bit value is not affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7-2 + l.3-2]. [l.1-0] = 0 0 1 0 0 a5 a4 a3 a2 @h + da.b 1 1 1 1 1 0 0 0 skip if [h + da.3-0].b = 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. if ram bit location 30h.2 is set to "0", the following instruction sequence will cause the program to continue execution from the instruction identifed as label2: btsf 30h.2 ; if 30h.2 = "0", then skip ret ; if 30h.2 = "1", return jp label2 2. you can use btsf in the same way to test a port pin address bit: btsf p1.0 ; if p1.0 = "0", then skip ret ; if p1.0 = "1", then return jp label3 sam48 instruction set s3c72q5/p72q5 5- 38 btsf ? bit test and skip on false btsf (continued) examples: 3. p0.2, p0.3 and p1.0-p1.3 are tested: ld l,#2h bp2 btsf p0.@l ; first, p1.@2h = p0.2 ; (111100b) + 00b.10b = 0f0h.2 ret incs l cpse l,#8h jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btsf has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btsf @h+flag; if bank 0 (a h + 0h).0 = 0a0h.0 = "0", then skip ret ? ? ? s3c72q5/p72q5 sam48 instruction set 5- 39 btst ? bit test and skip on true btst dst.b operation: operand operation summary bytes cycles c test carry bit and skip if set (= "1") 1 1 + s da.b test specified bit and skip if memory bit is set 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is "1", the instruction that immediately follows the btst instruction is skipped; otherwise the instruction following the btst instruction is executed. the destination bit value is not affected. operand binary code operation notation c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7-2 + l.3-2]. [l.1-0] = 1 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3-0].b = 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. if ram bit location 30h.2 is set to "0", the following instruction sequence will execute the ret instruction: btst 30h.2 ; if 30h.2 = "1", then skip ret ; if 30h.2 = "0", return jp label2 sam48 instruction set s3c72q5/p72q5 5- 40 btst ? bit test and skip on true btst (continued) examples: 2. you can use btst in the same way to test a port pin address bit: btst p1.0 ; if p1.0 = "1", then skip ret ; if p1.0 = "0", then return jp label3 3. p0.2, p0.3 and p1.0-p1.3 are tested : ld l,#2h bp2 btst p0.@l ; first, p0.@2h = p0.2 ; (111100b) + 00b.10b = 0f0h.2 ret incs l cpse l,#8h jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btst has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btst @h+flag; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", then skip ret ? ? ? s3c72q5/p72q5 sam48 instruction set 5- 41 btstz ? bit test and skip on true; clear bit btstz dst.b operation: operand operation summary bytes cycles mema.b test specified bit; skip and clear if memory bit is set 2 2 + s memb.@l 2 2 + s @h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "1", the instruction immediately following the btstz instruction is skipped; otherwise the instruction following the btstz is executed. the destination bit value is cleared. operand binary code operation notation mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7-2 + l.3-2]. [l.1-0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3-0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. port pin p0.0 is toggled by checking the p0.0 value (level): btstz p0.0 ; if p0.0 = "1", then p0.0 ? "0" and skip bits p0.0 ; if p0.0 = "0", then p0.0 ? "1" jp label3 2. for toggling p2.2, p2.3 and p3.0-p3.3: ld l,#0ah bp2 btstz p2.@l ; first, p2.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 bits p2.@l incs l jr bp2 sam48 instruction set s3c72q5/p72q5 5- 42 btstz ? bit test and skip on true; clear bit btstz (continued) examples: 3. bank 0, location 0a0h.0, is tested and emb = "0": flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btstz @h+flag; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", clear and skip bits @h+flag; if 0a0h.0 = "0", then 0a0h.0 ? "1" s3c72q5/p72q5 sam48 instruction set 5- 43 bxor ? bit exclusive or bxor c,src.b operation: operand operation summary bytes cycles c,mema.b exclusive-or carry with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically xored with the carry bit value. the resultant bit is written to the carry flag. the source value is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7-2 + l.3-2]. [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh examples: 1. the carry flag is logically xored with the p1.0 value: rcf ; c ? "0" bxor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 1h (0001b). the a ddress (memb.7-2) is 111100b and (l.3-2) = 00b. the resulting address is 11110000b or ff0h, specifying p0. the bit value for the bxor instruction, (l.1-0) is 01b which specifies bit 1. therefore, p1.@l = p0.1: ld l,#1h bxor c,p0.@l ; p1.@l is specified as p0.1; c xor p0.1 sam48 instruction set s3c72q5/p72q5 5- 44 bxor ? bit exclusive or bxor (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3-0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor in struction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bxor c,@h+flag ; c xor flag (20h.3) s3c72q5/p72q5 sam48 instruction set 5- 45 call ? call procedure call dst operation: operand operation summary bytes cycles adr call direct in page (14 bits) 3 4 description: call calls a subroutine located at the destination address. the instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decreasing the stack pointer by six. the emb and erb are also pushed to the stack. program execution continues with the instruction at this address. the subroutine may therefore begin anywhere in the full 16 k byte program memory address space. operand binary code operation notation adr 1 1 0 1 1 0 1 1 [(sp-1) (sp-2)] ? emb, erb 0 1 a13 a12 a11 a10 a9 a8 [(sp-3) (sp-4)] ? pc7-0 a7 a6 a5 a4 a3 a2 a1 a0 [(sp-5) (sp-6)] ? pc13-8 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0e3fh. executing the instruction call play at location 0123h will generate the following values: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 3h 0fbh = 0h 0fah = 1h pc = 0e3fh data is written to stack locations 0ffh - 0fah as follows: sp - 6 (0fah) pc11 ? pc8 sp - 5 (0fbh) 0 0 pc13 pc12 sp - 4 (0fch) pc3 ? pc0 sp - 3 (0fdh) pc7 ? pc4 sp - 2 (0feh) 0 0 emb erb sp - 1 (0ffh) 0 0 0 0 sp ? (00h) sam48 instruction set s3c72q5/p72q5 5- 46 calls ? call procedure ( short ) calls dst operation: operand operation summary bytes cycles adr call direct in page (11 bits) 2 3 description: the calls instruction unconditionally calls a subroutine located at the indicated address. the instruction increments the pc twice to obtain the address of the following instruction. then, it pushes the result onto the stack, decreasing the stack pointer six times. the higher bits of the pc, with the exception of the lower 11 bits, are cleared. the calls instruction can be used in the all range (0000h-3fffh), but the subroutine must therefore be located within the 2 k byte block (0000h-07ffh) of program memory. operand binary code operation notation adr 1 1 1 0 1 a10 a9 a8 [(sp-1) (sp-2)] ? emb, erb a7 a6 a5 a4 a3 a2 a1 a0 [(sp-3) (sp-4)] ? pc7-0 [(sp-5) (sp-6)] ? pc14-8 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0345h. executing the instruction calls play at location 0123h will generate the following values: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 3h 0fbh = 0h 0fah = 1h pc = 0345h data is written to stack locations 0ffh - 0fah as follows: sp - 6 (0fah) pc11 ? pc8 sp - 5 (0fbh) 0 pc14 pc13 pc12 sp - 4 (0fch) pc3 ? pc0 sp - 3 (0fdh) pc7 ? pc4 sp - 2 (0feh) 0 0 emb erb sp - 1 (0ffh) 0 0 0 0 sp ? (00h) s3c72q5/p72q5 sam48 instruction set 5- 47 ccf ? complement carry flag ccf operation: operand operation summary bytes cycles ? complement carry flag 1 1 description: the carry flag is complemented; if c = "1" it is changed to c = "0" and vice-versa. operand binary code operation notation ? 1 1 0 1 0 1 1 0 c ? c example: if the carry flag is logic zero, the instruction ccf changes the value to logic one. sam48 instruction set s3c72q5/p72q5 5- 48 com ? complement accumulator com a operation: operand operation summary bytes cycles a complement accumulator (a) 2 2 description: the accumulator value is complemented; if the bit value of a is "1", it is changed to "0" and vice versa. operand binary code operation notation a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1 example: if the accumulator contains the value 4h (0100b), the instruction com a leaves the value 0bh (1011b) in the accumulator. s3c72q5/p72q5 sam48 instruction set 5- 49 cpse ? compare and skip if equal cpse dst,src operation: operand operation summary bytes cycles r,#im compare and skip if register equals #im 2 2 + s @hl,#im compare and skip if indirect data memory equals #im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s description: cpse compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. neither operand is affected by the comparison. operand binary code operation notation r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 example: the extended accumulator contains the value 34h and register pair hl contains 56h. the second instruction (ret) in the instruction sequence cpse ea,hl ret is not skipped. that is, the subroutine returns since the result of the comparison is 'not equal.' sam48 instruction set s3c72q5/p72q5 5- 50 decs ? decrement and skip on borrow decs dst operation: operand operation summary bytes cycles r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s description: the destination is decremented by one. an original value of 00h will underflow to 0ffh. if a borrow occurs, a skip is executed. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 0 1 r2 r1 r0 r ? r-1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr-1; skip on borrow 1 1 0 1 1 r2 r1 0 examples: 1. register pair hl contains the value 7fh (01111111b). the following instruction leaves the value 7eh in register pair hl: decs hl 2. register a contains the value 0h. the following instruction sequence leaves the value 0ffh in register a. since a "borrow" occurs, the 'call play1' instruction is skipped and the 'call play2' instruction is executed: decs a ; "borrow" occurs call play1 ; skipped call play2 ; executed s3c72q5/p72q5 sam48 instruction set 5- 51 di ? disable interrupts di operation: operand operation summary bytes cycles ? disable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr, ime, is cleared to logic zero, disabling all interrupts. interrupts can still set their respective interrupt status latches, but the cpu will not directly service them. operand binary code operation notation ? 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic one (e.g., all instructions are enabled), the instruction di sets the ime bit to logic zero, disabling all interrupts. sam48 instruction set s3c72q5/p72q5 5- 52 ei ? enable interrupts ei operation: operand operation summary bytes cycles ? enable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr (ime) is set to logic one. this allows all interrupts to be serviced when they occur, assuming they are enabled. if an interrupt's status latch was previously enabled by an interrupt, this interrupt can also be serviced. operand binary code operation notation ? 1 1 1 1 1 1 1 1 ime ? 1 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic zero (e.g., all instructions are disabled), the instruction ei sets the ime bit to logic one, enabling all interrupts. s3c72q5/p72q5 sam48 instruction set 5- 53 idle ? idle operation idle operation: operand operation summary bytes cycles ? engage cpu idle mode 2 2 description: idle causes the cpu clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (pcon). after an idle instruction has been executed, peripheral hard - ware remains operative. in application programs, an idle instruction mus t be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. if three or more nop instructions are not used after idle instruction, leakage current could be flown because of the floating state in the internal bus. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 example: the instruction sequence idle nop nop nop sets bit 2 of the pcon register to logic one, stopping the cpu clock. the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed. sam48 instruction set s3c72q5/p72q5 5- 54 incs ? increment and skip on carry incs dst operation: operand operation summary bytes cycles r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s rrb increment register pair (rrb); skip on carry 1 1 + s description: the instruction incs increments the value of the destination operand by one. an original value of 0fh will, for example, overflow to 00h. if a carry occurs, the next instruction is skipped. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry example: register pair hl contains the value 7eh (01111110b). ram location 7eh contains 0fh. the instruction sequence incs @hl ; 7eh ? "0" incs hl ; skip incs @hl ; 7eh ? "1" leaves the register pair hl with the value 7eh and ram location 7eh with the value 1h. since a carry occurred, the second instruction is skipped. the carry flag value remains unchanged. s3c72q5/p72q5 sam48 instruction set 5- 55 iret ? return from interrupt iret operation: operand operation summary bytes cycles ? return from interrupt 1 3 description: iret is used at the end of an interrupt service routine. it pops the pc values successively from the stack and restores them to the program counter. the stack pointer is incremented by six and the psw, enable memory bank (emb) bit, and enable register bank (erb) bit are also automatically restored to their pre-interrupt values. program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. if a lower-level or same-level interrupt was pending when the iret was executed, iret will be executed before the pending interrupt is processed. since the 'a14' bit of an interrupt return address is not stored in the stack, this bit location is always interpreted as a logic zero. the starting address in the rom must for this reason be located in 0000h-3fffh. operand binary code operation notation ? 1 1 0 1 0 1 0 1 pc13-8 ? (sp + 1) (sp) pc7-0 ? sp + 3) (sp + 2) psw ? (sp + 5) (sp + 4) sp ? sp + 6 example: the stack pointer contains the value 0fah. an interrupt is detected in the instruction at location 0123h. ram locations 0fdh, 0fch, and 0fah contain the values 2h, 3h, and 1h, respectively. the instruction iret leaves the stack pointer with the value 00h and the program returns to continue execution at location 0123h. during a return from interrupt, data is popped from the stack to the program counter. the data in stack locations 0ffh-0fah is organized as follows: sp ? (0fah) pc11 ? pc8 sp + 1 (0fbh) 0 0 pc13 pc12 sp + 2 (0fch) pc3 ? pc0 sp + 3 (0fdh) pc7 ? pc4 sp + 4 (0feh) is1 is0 emb erb sp + 5 (0ffh) c sc2 sc1 sc0 sp + 6 (00h) sam48 instruction set s3c72q5/p72q5 5- 56 jp ? jump jp dst operation: operand operation summary bytes cycles adr jump to direct address (14 bits) 3 3 description: jp causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. the destination can be anywhere in the 16 k byte program memory address space. operand binary code operation notation adr 1 1 0 1 1 0 1 1 pc13-0 ? adr13-0 0 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'syscon' is assigned to the instruction at program location 07ffh. the instruction jp syscon at location 0123h will load the program counter with the value 07ffh. s3c72q5/p72q5 sam48 instruction set 5- 57 jps ? jump (short) jps dst operation: operand operation summary bytes cycles adr jump direct in page (12 bits) 2 2 description: jps causes an unconditional branch to the indicated address with the 4 k byte program memory address space. bits 0-11 of the program counter are replaced with the directly specified address. the destination address for this jump is specified to the assembler by a label or by an actual address in program memory. operand binary code operation notation adr 1 0 0 1 a11 a10 a9 a8 pc13-0 ? pc13-12 + adr11-0 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'sub' is assigned to the instruction at program memory location 00ffh. the instruction jps sub at location 0eabh will load the program counter with the value 00ffh. normally, the jps instruction jumps to the address in the block in which the instruction is located. if the first byte of the instruction code is located at address xffeh or xfffh, the instruction will jump to the next block. if the instruction 'jps sub' were located instead at program memory address 0ffeh or 0fffh, the instruction 'jps sub' would load the pc with the value 10ffh, causing a program malfunction. sam48 instruction set s3c72q5/p72q5 5- 58 jr ? jump relative (very short) jr dst operation: operand operation summary bytes cycles #im branch to relative immediate address 1 2 @wx branch relative to contents of wx register 2 3 @ea branch relative to contents of ea 2 3 description: jr causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the pc. the range of the relative address is current pc - 15 to current pc + 16. the destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (-). for immediate addressing, the (+) range is from 2 to 16 and the (-) range is from -1 to -15. if a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. for jr @wx and jr @ea branch relative instructions, the valid range for the relative address is 0h-0ffh. the destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. normally, the 'jr @wx' and 'jr @ea' instructions jump to the address in the page in which the instruction is located. however, if the first byte of the instruction code is located at address xxfeh or xxffh, the instruction will jump to the next page. operand binary code operation notation #im * pc13-0 ? adr (pc-15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc13-0 ? pc13-8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc13-0 ? pc13-8 + (ea) 0 1 1 0 0 0 0 0 first byte condition * jr #im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc-1 to pc-15 s3c72q5/p72q5 sam48 instruction set 5- 59 jr ? jump relative (very short) jr (continued) examples: 1. a short form for a relative jump to label 'kk' is the instruction jr kk where 'kk' must be within the allowed range of current pc-15 to current pc+16. the jr instruction has in this case the effect of an unconditional jp instruction. 2. in the following instruction sequence, if the instruction 'ld wx, #02h' were to be executed in place of 'ld wx,#00h', the program would jump to 1004h and 'jps ccc' would be executed. if 'ld wx,#03h' were to be executed, the jump would be to1006h and 'jps ddd' would be executed. org 1000h jps aaa jps bbb jps ccc jps ddd xxx ld wx,#00h ; wx ? 00h ld ea,wx ads wx,ea ; wx ? (wx) + (ea) jr @wx ; current pc12-8 (10h) + wx (00h) = 1000h ; jump to address 1000h and execute jps aaa 3. here is another example: org 1100h ld a,#0h ld a,# 1h ld a,#2h ld a,#3h ld 30h,a ; address 30h ? a jps yyy xxx ld ea,#00h ; ea ? 00h jr @ea ; jump to address 1100h ; address 30h ? 00h if 'ld ea,#01h' were to be executed in place of 'ld ea,#00h', the program would jump to 1101h and address 30h would contain the value 1h. if 'ld ea,#02h' were to be executed, the jump would be to 1102h and address 30h would contain the value 2h. sam48 instruction set s3c72q5/p72q5 5- 60 ld ? load ld dst,src operation: operand operation summary bytes cycles a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 description: the contents of the source are loaded into the destination. the source's contents are unaffected. if an instruction such as 'ld a,#im' (ld ea,#imm) or 'ld hl,#imm' is written more than two times in succession, only the first ld will be executed; the other similar instructions that immediately follow the first ld will be treated like a nop. this is called the 'redundancy effect' (see examples below). operand binary code operation notation a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? (rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0 ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0 s3c72q5/p72q5 sam48 instruction set 5- 61 ld ? load ld (continued) description: operand binary code operation notation rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 examples: 1. ram location 30h contains the value 4h. the ram location values are 40h, 41h and 0ah, 3h respectively. the following instruction sequence leaves the value 40h in point pair hl, 0ah in the accumulator and in ram location 40h, and 3h in register e. ld hl,#30h ; hl ? 30h ld a,@hl ; a ? 4h ld hl,#40h ; hl ? 40h ld ea,@hl ; a ? 0ah, e ? 3h ld @hl,a ; ram (40h) ? 0ah sam48 instruction set s3c72q5/p72q5 5- 62 ld ? load ld (continued) examples: 2. if an i nstruction such as ld a,#im (ld ea,#imm) or ld hl,#imm is written more than two times in succession, only the first ld is executed; the next instructions are treated as nops. here are two examples of this 'redundancy effect': ld a,#1h ; a ? 1h ld ea,#2h ; nop ld a,#3h ; nop ld 23h,a ; (23h) ? 1h ld hl,#10h ; hl ? 10h ld hl,#20h ; nop ld a,#3h ; a ? 3h ld ea,#35 ; nop ld @hl,a ; (10h) ? 3h the following table contains descriptions of special characteristics of the ld instruction when used in different addressing modes: instruction operation description and guidelines ld a,#im since the 'redundancy effect' occurs with instructions like ld ea,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like nops. ld a,@rra load the data memory contents pointed to by 8-bit rra register pairs (hl, wx, wl) to the a register. ld a,da load direct data memory contents to the a register. ld a,ra load 4-bit register ra (e, l, h, x, w, z, y) to the a register. ld ra,#im load 4-bit immediate data into the ra register (e, l, h, x, w, y, z). ld rr,#imm load 8-bit immediate data into the ra register (ea, hl, wx, yz). there is a redundancy effect if the operation addresses the hl or ea registers. ld da,a load contents of register a to direct data memory address. ld ra,a load contents of register a to 4-bit ra register (e, l, h, x, w, z, y). s3c72q5/p72q5 sam48 instruction set 5- 63 ld ? load ld (concluded) examples: instruction operation description and guidelines ld ea,@hl load data memory contents pointed to by 8-bit register hl to the a register, and the contents of hl+1 to the e register. the contents of register l must be an even number. if the number is odd, the lsb of register l is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to hl and the next instruction 'ld ea,@hl' loads the contents of 36h to register a and the contents of 37h to register e. ld ea,da load direct data memory contents of da to the a register, and the next direct data memory contents of da + 1 to the e register. the da value must be an even number. if it is an odd number, the lsb of da is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld ea,37h' loads the contents of 36h to the a register and the contents of 37h to the e register. ld ea,rrb load 8-bit rrb register (hl, wx, yz) to the ea register. h, w, and y register values are loaded into the e register, and the l, x, and z values into the a register. ld @hl,a load a register contents to data memory location pointed to by the 8-bit hl register value. ld da,ea load the a register contents to direct data memory and the e register contents to the next direct data memory location. the da value must be an even number. if it is an odd number, the lsb of the da value is recognized as logic zero (an even number), and is not replaced with the true value. ld rrb,ea load contents of ea to the 8-bit rrb register (hl, wx, yz). the e register is loaded into the h, w, and y register and the a register into the l, x, and z register. ld @hl,ea load the a register to data memory location pointed to by the 8-bit hl register, and the e register contents to the next location, hl + 1. the contents of the l register must be an even number. if the number is odd, the lsb of the l register is recognized as logic zero (an even number), and is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to register hl; the instruction 'ld @hl,ea' loads the contents of a into address 36h and the contents of e into address 37h. sam48 instruction set s3c72q5/p72q5 5- 64 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: operand operation summary bytes cycles mema.b,c load carry bit to a specified memory bit 2 2 memb.@l,c load carry bit to a specified indirect memory bit 2 2 @h+da.b,c 2 2 c,mema.b load memory bit to a specified carry bit 2 2 c,memb.@l load indirect memory bit to a specified carry bit 2 2 c,@h+da.b 2 2 description: the boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. one of the operands must be the carry flag; the other may be any directly or indirectly addressable bit. the source is unaffected. operand binary code operation notation mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7-2 + [l.3-2]. [l.1-0] ? c 0 1 0 0 a5 a4 a3 a2 @h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3-0].b ? (c) 0 0 b1 b0 a3 a2 a1 a0 c,mema.b* 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7-2 + [l.3-2] . [l.1-0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3-0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h-fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h-fffh s3c72q5/p72q5 sam48 instruction set 5- 65 ldb ? load bit ldb (continued) examples: 1. the carry flag is set and the data value at input pin p1.0 is logi c zero. the following instruction clears the carry flag to logic zero. ldb c,p1.0 2. the p1 address is ff1h and the l register contains the value 9h (1001b). the address (memb.7-2) is 111100b and (l.3-2) is 10b. the resulting address is 11110010b or ff2h and p2 is addressed. the bit value (l.1-0) is specified as 01b (bit 1). ld l,#9h ldb co,p1.@l ; p1.@l specifies p2.1 and c ? p2.1 3. the h register contains the value 2h and flag = 20h.3. the address for h is 0010b and for flag(3-0) the address is 0000b. the resulting address is 00100000b or 20h. the bit value is 3. therefore, @h+flag = 20h.3. flag equ 20h.3 ld h,#2h ldb c,@h+flag ; c ? flag (20h.3) 4. the following instruction sequence sets the carry flag and the loads the "1" data value to the output pin p2.0, setting it to output mode: scf ; c ? "1" ldb p2.0,c ; p2.0 ? "1" 5. the p1 address is ff1h and l = 9h (1001b). the address (memb.7-2) is 111100b and (l.3- 2) is 10b. the resulting address, 11110010b specifies p2. the bit value (l.1-0) is specified as 01b (bit 1). therefore, p1.@l = p2.1. scf ; c ? "1" ld l,#9h ldb p1.@l,c ; p1.@l specifies p2.1 ; p2.1 ? "1" 6. in this example, h = 2h and flag = 20h.3 and the address 20h is specified. since the bit value is 3, @h+flag = 20h.3: flag equ 20h.3 rcf ; c ? "0" ld h,#2h ldb @h+flag,c ; flag(20h.3) ? "0" note : port pin names used in examples 4 and 5 may vary with different sam48 devices. sam48 instruction set s3c72q5/p72q5 5- 66 ldc ? load code byte ldc dst,src operation: operand operation summary bytes cycles ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 description: this instruction is used to load a byte from program memory into an extended accumulator. the address of the byte fetched is the six highest bit values in the program counter and the contents of an 8-bit working register (either wx or ea). the contents of the source are unaffected. operand binary code operation notation ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc13-8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc13-8 + (ea)] examples: 1. the following instructions will load one of four values defined by the define byte (db) directive to the extended accumulator: ld ea,#00h call display jps main org 0500h db 66h db 77h db 88h db 99h display ldc ea,@ea ; ea ? address 0500h = 66h ret if the instruction 'ld ea,#01h' is executed in place of 'ld ea,#00h', the content of 0501h (77h) is loaded to the ea register. if 'ld ea,#02h' is executed, the content of address 0502h (88h) is loaded to ea. s3c72q5/p72q5 sam48 instruction set 5- 67 ldc ? load code byte ldc (continued) examples: 2. the following instructions will load one of four values defined by the define byte (db) directive to the extended accumulator: org 0500h db 66h db 77h db 88h db 99h display ld wx,#00h ldc ea,@wx ; ea ? address 0500h = 66h ret if the instruction 'ld wx,#01h' is executed in place of 'ld wx,#00h', then ea ? address 0501h = 77h. if the instruction 'ld wx,#02h' is executed in place of 'ld wx,#00h', then ea ? address 0502h = 88h. 3. normally, the ldc ea, @ea and the ldc ea, @wx instructions reference the table data on the page on which the instruction is located. if, however, the instruction is located at address xxffh, it will reference table data on the next page. in this example, the upper 4 bits of the address at location 0200h is loaded into register e and the lower 4 bits into register a: org 01fdh 01fdh ld wx,#00h 01ffh ldc ea,@wx ; e ? upper 4 bits of 0200h address ; a ? lower 4 bits of 0200h address 4. here is another example of page referencing with the ldc instruction: org 0100h db 67h smb 0 ld hl,#30h ; even number ld wx,#00h ldc ea,@wx ; e ? upper 4 bits of 0100h address ; a ? lower 4 bits of 0100h address ld @hl,ea ; ram (30h) ? 7, ram (31h) ? 6 sam48 instruction set s3c72q5/p72q5 5- 68 ldd ? load data memory and decrement ldd dst operation: operand operation summary bytes cycles a,@hl load indirect data memory contents to a; decrement register l contents and skip on borrow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are decreased by one. if a "borrow" occurs (e.g., if the resulting value in register l is 0fh), the next instruction is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l-1; skip if l = 0fh example: in this example, assume that register pair hl contains 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ldd a,@hl ; a ? (hl) and l ? l-1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0fh the instruction 'jps xxx' is skipped since a "borrow" occurred after the 'ldd a,@hl' and instruction 'jps yyy' is executed. s3c72q5/p72q5 sam48 instruction set 5- 69 ldi ? load data memory and increment ldi dst,src operation: operand operation summary bytes cycles a,@hl load indirect data memory to a; increment register l contents and skip on overflow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are incremented by one. if an overflow occurs (e.g., if the resulting value in register l is 0h), the next instruction is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: assume that register pair hl contains the address 2fh and internal ram location 2fh con tains the value 0fh: ld hl,#2fh ldi a,@hl ; a ? (hl) and l ? l+1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0h the instruction 'jps xxx' is skipped since an overflow occurred after the 'ldi a,@hl' and the instruction 'jps yyy' is executed. sam48 instruction set s3c72q5/p72q5 5- 70 nop ? no operation nop operation: operand operation summary bytes cycles ? no operation 1 1 description: no operation is performed by a nop instruction. it is typically used for timing delays. one nop causes a 1-cycle delay: with a 1 s cycle time, five nops would therefore cause a 5 s delay. program execution continues with the instruction immediately following the nop. only the pc is affected. at least three nop instructions should follow a stop or idle instruction. operand binary code operation notation ? 1 0 1 0 0 0 0 0 no operation example: three nop instructions follow the stop instruction to provide a short interval for clock stabilization before power-down mode is initiated: stop nop nop nop s3c72q5/p72q5 sam48 instruction set 5- 71 or ? logical or or dst,src operation: operand operation summary bytes cycles a, #im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 description: the source operand is logically ored with the destination operand. the result is stored in the destination. the contents of the source are unaffected. operand binary code operation notation a, #im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 example: if the accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction or ea,@hl leaves the value 0d7h (11010111b) in the accumulator . sam48 instruction set s3c72q5/p72q5 5- 72 pop ? pop from stack pop dst operation: operand operation summary bytes cycles rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2 description: the contents of the ram location addressed by the stack pointer is read, and the sp is incremented by two. the value read is then transferred to the variable indicated by the destination operand. operand binary code operation notation rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp+1) sp ? sp+2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp+1), sp ? sp+2 0 1 1 0 0 1 1 0 example: the sp value is equal to 0edh, and ram locations 0efh through 0edh contain the values 2h, 3h, and 4h, respectively. the instruction pop hl leaves the stack pointer set to 0efh and the data pointer pair hl set to 34h. s3c72q5/p72q5 sam48 instruction set 5- 73 push ? push onto stack push src operation: operand operation summary bytes cycles rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 description: the sp is then decreased by two and the contents of the source operand are copied into the ram location addressed by the stack pointer, thereby adding a new element to the top of the stack. operand binary code operation notation rr 0 0 1 0 1 r2 r1 1 (sp-1) ? rr h , (sp-2) ? rr l sp ? sp-2 sb 1 1 0 1 1 1 0 1 (sp-1) ? smb, (sp-2) ? srb; (sp) ? sp-2 0 1 1 0 0 1 1 1 example: as an interrupt service routine begins, the stack pointer contains the value 0fah and the data pointer register pair hl contains the value 20h. the instruction push hl leaves the stack pointer set to 0f8h and stores the values 2h and 0h in ram locations 0f9h and 0f8h, respectively. sam48 instruction set s3c72q5/p72q5 5- 74 rcf ? reset carry flag rcf operation: operand operation summary bytes cycles ? reset carry flag to logic zero 1 1 description: the carry flag is cleared to logic zero, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 0 c ? 0 example: assuming the carry flag is set to logic one, the instruction rcf resets (clears) the carry flag to logic zero. s3c72q5/p72q5 sam48 instruction set 5- 75 ref ? reference instruction ref dst operation: operand operation summary bytes cycles memc reference code 1 1 (note) note : the instruction referenced by ref determines instruction cycles. description: the ref instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the ref instruction reference area in program memory. ref reduces the number of program memory accesses for a program. operand binary code operation notation memc t7 t6 t5 t4 t3 t2 t1 t0 pc13-0 ? memc5-0 + (memc+1).7-0 tjp and tcall are 2-byte pseudo-instructions that are used only to specify the reference area: 1. when the reference area is specified by the tjp instruction, memc.7-6 = 00 pc13-0 ? memc.5-0 + (memc+1).7-0 2. when the reference area is specified by the tcall instruction, memc.7-6 = 01 [(sp-1) (sp-2)] ? emb, erb [(sp-3) (sp-4)] ? pc7-0 [(sp-5) (sp-6)] ? pc13-8 sp ? sp-6 pc-0 ? memc.5-0 + (memc+1).7-0 when the reference area is specified by any other instruction, the 'memc' and 'memc + 1' instructions are executed. instructions referenced by ref occupy 2 bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020h to 007fh in rom. in addition, the destination address of the tjp and tcall instructions must be located with the 3fffh address. tjp and tcall are reference instructions for jp/jps and call/calls. if the instruction following a ref is subject to the 'redundancy effect', the redundant instruction is skipped. if, however, the ref follows a redundant instruction, it is executed. on the other hand, the binary code of a ref instruction is 1 byte. the upper 4 bits become the higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction becomes the lower address, producing a total of 8 bits or 1 byte (see example 3 below). note : if the msb value of the first one-byte binary code in instruction is ?0?, the instruction cannot be referenced by a ref instruction. sam48 instruction set s3c72q5/p72q5 5- 76 ref ? reference instruction ref (continued) examples: 1. instructions can be executed efficiently using ref, as shown in the following example: org 0020h aaa ld hl,#00h bbb ld ea,#ffh ccc tcall sub1 ddd tjp sub2 ? ? ? org 0080h ref aaa ; ld hl,#00h ref bbb ; ld ea,#ffh ref ccc ; call sub1 ref ddd ; jp sub2 2. the following example shows how the ref instruction is executed in relation to ld instructions that have a 'redundancy effect': org 0020h aaa ld ea,#40h ? ? ? org 0100h ld ea,#30h ref aaa ; not skipped ? ? ? ref aaa ld ea,#50h ; skipped srb 2 s3c72q5/p72q5 sam48 instruction set 5- 77 ref ? reference instruction ref (concluded) examples: 3. in this example the binary code of 'ref a1' at locations 20h-21h is 20h, for 'ref a2' at locations 22h-23h, it is 21h, and for 'ref a3' at 24h-25h, the binary code is 22h : opcode symbol instruction org 0020h 83 00 a1 ld hl,#00h 83 03 a2 ld hl,#03h 83 05 a3 ld hl,#05h 83 10 a4 ld hl,#10h 83 26 a5 ld hl,#26h 83 08 a6 ld hl,#08h 83 0f a7 ld hl,#0fh 83 f0 a8 ld hl,#0f0h 83 67 a9 ld hl,#067h 41 0b a10 tcall sub1 01 0d a11 tjp sub2 ? ? ? org 0100h 20 ref a1 ; ld hl,#00h 21 ref a2 ; ld hl,#03h 22 ref a3 ; ld hl,#05h 23 ref a4 ; ld hl,#10h 24 ref a5 ; ld hl,#26h 25 ref a6 ; ld hl,#08h 26 ref a7 ; ld hl,#0fh 27 ref a8 ; ld hl,#0f0h 30 ref a9 ; ld hl,#067h 31 ref a10 ; call sub1 32 ref a11 ; jp sub2 sam48 instruction set s3c72q5/p72q5 5- 78 ret ? return from subroutine ret operation: operand operation summary bytes cycles ? return from subroutine 1 3 description: ret pops the pc values successively from the stack, incrementing the stack pointer by six. program execution continues from the resulting address, generally the instruction immediately following a call or calls. operand binary code operation notation ? 1 1 0 0 0 1 0 1 pc13-8 ? (sp + 1) (sp) pc7-0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 4) sp ? sp + 6 example: the stack pointer contains the value 0fah. ram locations 0fah, 0fbh, 0fch, and 0fdh contain 1h, 0h, 5h, and 2h, respectively. the instruction ret leaves the stack pointer with the new value of 00h and program execution continues from location 0125h. during a return from subroutine, pc values are popped from stack locations as follows: sp ? (0fah) pc11 ? pc8 sp + 1 (0fbh) 0 0 pc13 pc12 sp + 2 (0fch) pc3 ? pc0 sp + 3 (0fdh) pc7 ? pc4 sp + 4 (0feh) 0 0 emb erb sp + 5 (0ffh) 0 0 0 0 sp + 6 (000h) s3c72q5/p72q5 sam48 instruction set 5- 79 rrc ? rotate accumulator right through carry rrc a operation: operand operation summary bytes cycles a rotate right through carry bit 1 1 description: the four bits in the accumulator and the carry flag are together rotated one bit to the right. bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position. c 3 0 operand binary code operation notation a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n-1 ? a.n (n = 1, 2, 3) example: the accumulator contains the value 5h (0101b) and the carry flag is cleared to logic zero. the instruction rrc a leaves the accumulator with the value 2h (0010b) and the carry flag set to logic one. note the number of memory bank selected by smb may change for different devices in the sam48 product family. sam48 instruction set s3c72q5/p72q5 5- 80 sbc ? subtract with carry sbc dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair (rrb) with carry 2 2 description: sbc subtracts the source and carry flag value from the destination operand, leaving the result in the destination. sbc sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. the contents of the source are unaffected. if the carry flag was set before the sbc instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. in this case, the carry bit is subtracted from the destination along with the source operand. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 0 c,a ? a - (hl) - c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea -rr - c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb - ea - c 1 1 0 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" sbc ea,hl ; ea ? 0c3h - 0aah - 1h, c ? "0" jps xxx ; jump to xxx; no skip after sbc 2. if the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" sbc ea,hl ; ea ? 0c3h - 0aah - 0h = 19h, c ? "0" jps xxx ; jump to xxx; no skip after sbc s3c72q5/p72q5 sam48 instruction set 5- 81 sbc ? subtract with carry sbc (continued) examples: 3. if sbc a,@hl is followed by an ads a,#im, the sbc skips on 'no borrow' to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'sbc a,@hl' instruction does not skip even if an overflow occurs. this function is useful for decimal adjustment operations. a. 8 - 6 decimal addition (the contents of the address specified by the hl register is 6h): rcf ; c ? "0" ld a,#8h ; a ? 8h sbc a,@hl ; a ? 8h - 6h - c(0) = 2h, c ? "0" ads a,#0ah ; skip this instruction because no borrow after sbc result jps xxx b. 3 - 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h sbc a,@hl ; a ? 3h - 4h - c(0) = 0fh, c ? "1" ads a, #0ah ; no skip. a ? 0fh + 0ah = 9h ; (the skip function of 'ads a,#im' is inhibited after a ; 'sbc a,@hl' instruction even if an overflow occurs.) jps xxx sam48 instruction set s3c72q5/p72q5 5- 82 sbs ? subtract sbs dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair (rrb); skip on borrow 2 2 + s description: the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. a skip is executed if a borrow occurs. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 1 a ? a - (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea - rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb - ea; skip on borrow 1 0 1 1 0 r2 r1 0 examples: 1. the accumulator contains the valu e 0c3h, register pair hl contains the value 0c7h, and the carry flag is cleared to logic zero: rcf ; c ? "0" sbs ea,hl ; ea ? 0c3h - 0c7h ; sbs instruction skips on borrow, ; but carry flag value is not affected jps xxx ; skip because a borrow occurred jps yyy ; jump to yyy is executed 2. the accumulator contains the value 0afh, register pair hl contains the value 0aah, and the carry flag is set to logic one: scf ; c ? "1" sbs ea,hl ; ea ? 0afh - 0aah jps xxx ; jump to xxx ; jps was not skipped since no "borrow" occurred after sbs s3c72q5/p72q5 sam48 instruction set 5- 83 scf ? set carry flag scf operation: operand operation summary bytes cycles ? set carry flag to logic one 1 1 description: the scf instruction sets the carry flag to logic one, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 1 c ? 1 example: if the carry flag is cleared to logic zero, the instruction scf sets the carry flag to logic one. sam48 instruction set s3c72q5/p72q5 5- 84 smb ? select memory bank smb n operation: operand operation summary bytes cycles n select memory bank 2 2 description: the smb instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. the constants 0, 1, and 15 are usually used as the smb operand to select the corresponding memory bank. all references to data memory addresses fall within the following address ranges: please note that since data memory spaces differ for various devices in the sam4 product family, the 'n' value of the smb instruction will also vary. addresses register areas bank smb 000h-01fh working registers 0 0 020h-0ffh stack and general-purpose registers n00h-nffh general-purpose registers n n display registers (n = 1-14) (n = 1-14) f80h-fffh i/o-mapped hardware registers 15 15 the enable memory bank (emb) flag must always be set to "1" in order for the smb instruction to execute successfully for memory bank 0 - 15. format binary code operation notation n 1 1 0 1 1 1 0 1 smb ? n 0 1 0 0 d3 d2 d1 d0 example: if the emb flag is set, the instruction smb 0 selects the data memory address range for bank 0 (000h-0ffh) as the working memory bank. notes: 1. number of memory bank selected by smb may change for different device in the sam48 product family. 2. after reset , the smb value is zero. s3c72q5/p72q5 sam48 instruction set 5- 85 srb ? select register bank srb n operation: operand operation summary bytes cycles n select register bank 2 2 description: the srb instruction selects one of four register banks in the working register memory area. the constant value used with srb is 0, 1, 2, or 3. the following table shows the effect of srb settings: erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' = not applicable. the enable register bank flag (erb) must always be set for the srb instruction to execute successfully for register banks 0, 1, 2, and 3. in addition, if the erb value is logic zero, register bank 0 is always selected, regardless of the srb value. operand binary code operation notation n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 example: if the erb flag is set, the instruction srb 3 selects register bank 3 (018h-01fh) as the working memory register bank. sam48 instruction set s3c72q5/p72q5 5- 86 sret ? return from subroutine and skip sret operation: operand operation summary bytes cycles ? return from subroutine and skip 1 3 + s description: sret is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a call or calls instruction. sret skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. operand binary code operation notation ? 1 1 1 0 0 1 0 1 pc13-8 ? (sp + 1) (sp) pc7-0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 4) sp ? sp + 6 example: if the stack pointer contains the value 0fah and ram locations 0fah, 0fbh, 0fch, and 0fdh contain the values 1h, 0h, 5h, and 2h, respectively, the instruction sret leaves the stack pointer with the value 00h and the program returns to continue execution at location 0125h, then skips unconditionally. during a return from subroutine, data is popped from the stack to the pc as follows: sp ? (0fah) pc11 ? pc8 sp + 1 (0fbh) 0 0 pc13 pc12 sp + 2 (0fch) pc3 ? pc0 sp + 3 (0fdh) pc7 ? pc4 sp + 4 (0feh) 0 0 emb erb sp + 5 (0ffh) 0 0 0 0 sp + 6 (000h) s3c72q5/p72q5 sam48 instruction set 5- 87 stop ? stop operation stop operation: operand operation summary bytes cycles - engage cpu stop mode 2 2 description: the stop instruction stops the system clock by setting bit 3 of the power control register (pcon) to logic one. when stop executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. in application programs, a stop instruction must be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. if three or more nop instructions are not used after stop instruction, leakage current could be flown because of the floating state in the internal bus. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 example: given that bit 3 of the pcon register is cleared to logic zero, and all systems are operational, the instruction sequence stop nop nop nop sets bit 3 of the pcon register to logic one, stopping all controller operations (with the exception of some peripheral hardware). the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed. sam48 instruction set s3c72q5/p72q5 5- 88 vent ? load emb, erb, and vector address ventn dst operation: operand operation summary bytes cycles emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location. 2 2 description: the vent instruction loads the contents of the enable memory bank flag (emb) and enable register bank flag (erb) into the respective vector addresses. it then points the interrupt service routine to the corresponding branching locations. the program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. the emb and erb flags should be modified using vent before the vector interrupts are acknowledged. then, when an interrupt is generated, the emb and erb values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. after the return from interrupt (iret) you do not need to set the emb and erb values again. instead, use bitr and bits to clear these values in your program routine. the starting addresses for vector interrupts and reset operations are pointed to by the ventn instruction. these starting addresses must be located in rom ranges 0000h-3fffh. generally, the ventn instructions are coded starting at location 0000h. the format for vent instructions is as follows: ventn d1,d2,addr emb ? d1 ("0" or "1") erb ? d2 ("0" or "1") pc ? addr (address to branch n = device-specific module address code (n = 0-n) operand binary code operation notation emb (0,1) erb (0,1) adr e m b e r b a13 a12 a11 a10 a9 a8 rom (2 x n) 7-6 ? emb, erb rom (2 x n) 5-4 ? pc13, pc12 rom (2 x n) 3-0 ? pc12-8 rom (2 x n + 1) 7-0 ? pc7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0 s3c72q5/p72q5 sam48 instruction set 5- 89 vent ? load emb, erb, and vector address ventn (continued) example: the instruction sequence org 0000h vent0 1,0,reset vent1 0,1,inta vent2 0,1,intb vent3 0,1,intc vent4 0,1,intd vent5 0,1,inte vent6 0,1,intf vent7 0,1,intg causes the program sequence to branch to the reset routine labeled reset , setting emb to "1" and erb to "0" when reset is activated. when a basic timer interrupt is generated, vent1 causes the program to branch to the basic timer's interrupt service routine, inta, and to set the emb value to "0" and the erb value to "1". vent2 then branches to intb, vent3 to intc, and so on, setting the appropriate emb and erb values. note: the number of ventn interrupt names used in the examples above may change for different devices in the sam48 product family . sam48 instruction set s3c72q5/p72q5 5- 90 xch ? exchange a or ea with nibble or byte xch dst,src operation: operand operation summary bytes cycles a,da exchange a and data memory contents 2 2 a,ra exchange a and register (ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory con tents 2 2 ea,rrb exchange ea and register pair (rrb) contents 2 2 ea,@hl exchange ea and indirect data memory contents 2 2 description: the instruction xch loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. operand binary code operation notation a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? (rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 example: double register hl contains the address 20h. the accumulator contains the value 3fh (00111111b) and internal ram location 20h the value 75h (01110101b). the instruction xch ea,@hl leaves ram location 20h with the value 3fh (00111111b) and the extended accumulator with the value 75h (01110101b). s3c72q5/p72q5 sam48 instruction set 5- 91 xchd ? exchange and decrement xchd dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; decrement contents of register l and skip on borrow 1 2 + s description: the instruction xchd exchanges the contents of the accumulator with the ram location addressed by register pair hl and then decrements the contents of register l. if the content of register l is 0fh, the next instruction is skipped. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l-1; skip if l = 0fh example: register pair hl contains the address 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ld a,#0h xch d a,@hl ; a ? 0fh and l ? l - 1, (hl) ? "0" jps xxx ; skipped since a borrow occurred jps yyy ; h ? 2h, l ? 0fh yyy xchd a,@hl ; (2fh) ? 0fh, a ? (2fh), l ? l - 1 = 0eh ? ? ? the 'jps yyy' instruction is executed since a skip occurs after the xchd instruction. sam48 instruction set s3c72q5/p72q5 5- 92 xchi ? exchange and increment xchi dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; increment contents of register l and skip on overflow 1 2 + s description: the instruction xchi exchanges the contents of the accumulator with the ram location addressed by register pair hl and then increments the contents of register l. if the content of register l is 0h, a skip is executed. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: register pair hl contains the address 2fh and internal ram location 2fh contains 0fh: ld hl,#2fh ld a,#0h xchi a,@hl ; a ? 0fh and l ? l + 1 = 0, (hl) ? "0" jps xxx ; skipped since an overflow occurred jps yyy ; h ? 2h, l ? 0h yyy xchi a,@hl ; (20h) ? 0fh, a ? (20h), l ? l + 1 = 1h ? ? ? the 'jps yyy' instruction is executed since a skip occurs after the xchi instruction. s3c72q5/p72q5 sam48 instruction set 5- 93 xor ? logical exclusive or xor dst,src operation: operand operation summary bytes cycles a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair (rrb) to ea 2 2 description: xor performs a bitwise logical xor operation between the source and destination variables and stores the result in the destination. the source contents are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 0 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 example: if the extended accumulator contains 0c3h (11000011b) and register pair hl contains 55h (01010101b), the instruction xor ea,hl leaves the value 96h (10010110b) in the extended accumulator. sam48 instruction set s3c72q5/p72q5 5- 94 notes s3c72q5/p72q5 oscillator circuits 6- 1 6 oscillator circuits overview the s3c72q5 microcontroller has two oscillator circuits: a main-system clock circuit, and a sub-system clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. specifically, a clock pulse is required by the following peripheral modules: ? lcd controller ? basic timer ? timer/counter 0 ? timer/counter 1 ? watch timer ? clock output circuit cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main-system clock fxt sub-system clock fxx selected system clock clock control registers when the system clock mode control register scmod and the power control register pcon registers are both cleared to zero after reset , the normal cpu operating mode is enabled, a main-system clock of fx/64 is selected, and main-system clock oscillation is initiated. the power control register, pcon, is used to select normal cpu operating mode or one of two power-down modes ? stop or idle. bits 3 and 2 of the pcon register can be manipulated by a stop or idle instruction to engage stop or idle power-down mode. the system clock mode control register, scmod, lets you select the main-system clock (fx) or a sub-system clock (fxt) as the cpu clock and to start (or stop) main-system clock oscillation. the resulting clock source, either main-system clock or sub-system clock, is referred to as the selected system clock (fxx) . the main-system clock is selected and oscillation started when all scmod bits are cleared to logic zero. by setting scmod.3 and scmod.0 to different values, you can select a sub-system clock source and start or stop main-system clock oscillation. to stop main-system clock oscillation, you must use the stop instruction (assuming the main-system clock is selected) or manipulat e scmod.3 to ?1? (assuming the sub- system clock is selected). the main-system clock frequencies can be divided by 4, 8, or 64 and a sub-system clock frequencies can only be divided by 4. by manipulating pcon bits 1 and 0, you select one of the following frequencies as the cpu clock, fx/4, fxt/4, fx/8, fx/64 . oscillator circuits s3c72q5/p72q5 6- 2 using a sub-system clock if a sub-system clock is being used as the selected system clock , the idle power-down mode can be initiated by executing an idle instruction. since the sub-system clock source cannot be stopped internally, you cannot, however, use a stop instruction to enable the stop power-down mode. the watch timer, buzzer and lcd display operate normally with a sub-system clock source, since they operate at very low speed (as low as 122 s at 32.768 khz) and with very low power consumption. x in x out xt in xt out oscillator stop selector fxx selector oscillator stop sub-system oscillator circuit watch timer lcd controller selector fx/1, 2, 16 fxt 1/1-1/4096 frequency dividing circuit 1/2 1/16 basic timer watch timer lcd controller clock output circuit timer/counter 0/1 wait release signal internal reset signal power down release signal oscillator control circuit pcon.3, .2 clear 1/4 cpu clock fx: main-system clock fxt: sub-system clock fxx: selected system clock cpu stop signal (idle mode) idle stop fx fxt main-system oscillator circuit scmod.3 scmod.0 scmod.2 pcon.0 pcon.1 pcon.2 pcon.3 figure 6- 1. clock circuit diagram s3c72q5/p72q5 oscillator circuits 6- 3 main-system oscillator circuits x in x out figure 6- 2. crystal/ceramic oscillator x in x out figure 6- 3 . external oscillator x in x out r figure 6- 4 . rc oscillator sub-system oscillator circuits xt in xt out 32.768 khz figure 6- 5 . crystal/ceramic oscillator xt in xt out external clock figure 6- 6 . external oscillator oscillator circuits s3c72q5/p72q5 6- 4 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. pcon can be addressed di rectly by 4-bit write instructions or indirectly by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon bits 3 and 2 are addressed by the stop and idle instructions, respectively, to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 are used to select a specific system clock frequency. there are two basic choices: ? main-system clock (fx) or sub-system clock (fxt); ? divided fx /4, 8, 64 or fxt /4 clock frequency. pcon.1 and pcon.0 settings are also connected with the system clock mode control register, scmod. if scmod.0 = "0" the main-system clock is always selected by the pcon.1 and pcon.0 setting; if scmod.0 = "1" the sub-system clock is selected. reset sets pcon register values (and scmod) to logic zero: scmod.3 and scmod.0 select the main-system clock (fx) and start clock oscillation; pcon.1 and pcon.0 divide the selected fx frequency by 64, and pcon.3 and pcon.2 enable normal cpu operating mode. table 6 - 1. power control register (pcon) organization pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 if scmod.0 = "0" if scmod.0 = "1" 0 0 fx/64 fxt/4 1 0 fx/8 1 1 fx/4 + + programming tip ? setting the cpu clock to set the cpu clock to 0.95 s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a s3c72q5/p72q5 oscillator circuits 6- 5 instruction cycle times the unit of time that equals one machine cycle varies depending on whether the main-system clock (fx) or a sub- system clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). table 6 - 2 shows corresponding cycle times in microseconds. table 6 - 2. instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time (sec) fx/64 65.5 khz 15.3 fx/8 524.0 khz fx = 4.19 mhz 1.91 fx/4 1.05 mhz 0.95 fxt/4 8.19 khz fxt = 32.768 khz 122.0 oscillator circuits s3c72q5/p72q5 6- 6 system clock mode register (scmod) the system clock mode register, scmod, is a 4-bit register that is used to select the cpu clock and to control main and sub- system clock oscillation. the scmod is mapped to the ram address fb7h. the main clock oscillation is stopped by setting scmod.3 when the clock source is subsystem clock and subsystem clock can be stopped by setting scmod.2 when the clock source is main system clock. scmod.0, scmod.3 cannot be simultaneously modified. the subsystem clock is stopped only by setting scmod.2, and pcon which revokes stop mode cannot stop the subsystem clock. the stop of subsystem clock is released by reset when the selected system clock is main system clock or subsystem clock and is released by setting scmod.2 when the selected system clock is main system clock. reset clears all scmod values to logic zero, selecting the main system clock (fx) as the cpu clock and starting clock oscillation. the reset value of the scmod is ?0? scmod.0, scmod.2, and scmod.3 bits can be manipulated by 1-bit write instructions (in other words, scmod.0, scmod.2, and scmod.3 cannot be modified simultaneously by a 4-bit write). bit 1 is always logic zero. fb7h scmod.3 scmod. 2 "0" scmod.0 a subsystem clock (fxt) can be selected as the system clock by manipulating the scmod.3 and scmod.0 bit settings. if scmod.3 = "0" and scmod.0 = "1", the subsystem clock is selected and main system clock oscillation continues. if scmod.3 = "1" and scmod.0 = " 1 ", fxt is selected, but main system clock oscillation stops. even i f you have selected fx as the cpu clock, setting scmod.3 to "1" will stop main system clock oscillation , and malfunction may be occured. to operate safely, main system clock should be stopped by a stop instruction is main system clock mode. table 6-3. system clock mode register (scmod) organization scmod register bit settings resulting clock selection scmod.3 scmod.0 cpu clock source fx oscillation 0 0 fx on 0 1 fxt on 1 1 fxt off scmod.2 sub-oscillation on/off 0 enable sub system clock 1 disable sub system clock note: you can use scmod.2 as follows (ex; after data bank was used, a few minutes have passed): main operation ? sub-operation ? sub-idle (lcd on, after a few minutes later without any external input) ? sub- operation ? main operation ? scmod.2 = 1 ? main stop mode (lcd off). s3c72q5/p72q5 oscillator circuits 6- 7 table 6-4 . main oscillation stop mode mode condition method to issue osc stop osc stop release source (2) main oscillation stop mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. stop instruction: main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). interrupt and reset : after releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. and then the cpu operates. oscillation stabilization time is 1/ {256 x bt clock (fx)}. when scmod.3 is set to ?1? (1), main oscillator stops, halting the cpu operation. sub oscillator still runs (stops). reset : interrupt can?t start the main oscillation. therefore, the cpu operation can never be restarted. main oscillator runs. sub oscillator runs. system clock is the sub oscillation clock. stop instruction (1) : main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). sub oscillator still runs. bt overflow, interrupt, and reset : after the overflow of basic timer [1/ {256 x bt clock (fxt)}], cpu operation and main oscillation automatically start. when scmod.3 is set to ?1?, main oscillator stops. the cpu, however, would still operate. sub oscillator still runs. set scmod.3 to ?0? or reset sub oscillation stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. when scmod.2 to ?1?, sub oscillator stops, while main oscillator and the cpu would still operate. set scmod.2 to ?0? or reset main oscillator runs (stops). sub oscillator runs. system clock is the sub oscillation clock. when scmod.2 to ?1?, sub oscillator stops, halting the cpu operation. main oscillator still runs (stops). reset notes: 1. this mode must not be use d. 2. oscillation stabilization time by interrupt is 1/(256 x bt clocks). oscillation stabilization time by a reset is 31.3ms at 4.19mhz, main oscillation clock. oscillator circuits s3c72q5/p72q5 6- 8 switching the cpu clock together, bit settings in the power control register, pcon, and the system clock mode register, scmod, determine whether a main system or a subsystem clock is selected as the cpu clock, and also how this frequency is to be divided. this makes it possible to switch dynamically between main and subsystem clocks and to modify op erating frequencies. scmod.3 , scmod.2, and scmod.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main system and sub system clock oscillation. pcon.1 and pcon.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, or 64, or fxt clock by 4. note a clock switch operation does not go into effect immediately when you make the scmod and pcon register modifications ? the previously selected clock continues to run for a certain number of machine cycles. for example, you are using the default cpu clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. to do this, you first need to set scmod.0 to "1". this switches the clock from fx to fxt but allows main system clock oscillation to continue. before the switch actually goes into effect, a certain number of machine cycles must elapse. after this time interval, you can then disable main system clock oscillation by setting scmod.3 to "1". this same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear scmod.3 to "0" to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all scmod values to logic zero. following a reset , cpu operation starts with the lowest main system clock frequency of 15.3 s at 4.19 mhz after the standard oscillation stabilization interval of 31.3 ms has elapsed. table 6 -5 details the number of machine cycles that must elapse before a cpu clock switch modification goes into effect. table 6-5 . elapsed machine cycles during cpu clock switch after scmod.0 = 0 scmod.0 = 1 before pcon.1 = 0 pcon.0 = 0 pcon.1 = 1 pcon.0 = 0 pcon.1 = 1 pcon.0 = 1 pcon.1 = 0 n/a 1 machine cycle 1 machine cycle n/a pcon.0 = 0 scmod.0 = 0 pcon.1 = 1 8 machine cycles n/a 1 machine cycles n/a pcon.0 = 0 pcon.1 = 1 16 machine cycles 1 machine cycles n/a fx / 4fxt pcon.0 = 1 scmod.0 = 1 n/a n/a 1machine cycles n/a notes: 1. even if oscillation is stopped by setting scmod.3 during main system clock operation, the stop mode is not entered. 2. since the x in input is connected internally to v ss to avoid current leakage due to the crystal oscillator in stop mode, do not set scmod.3 to "1" or do not use stop instruction when an external clock is used as the main system clock. 3. when the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in table 6 -5 . 4. 'n/a' means 'not available'. 5. fx: main-system clock, fxt: sub-system clock. when fx is 4.19 mhz, and fxt is 32.768 khz. s3c72q5/p72q5 oscillator circuits 6- 9 + + programming tip ? switching between main-system and sub-system clock 1. switch from the main-system clock to the sub-system clock: ma2sub bits scmod.0 ; switches to sub-system clock call dly80 ; delay 80 machine cycles bits scmod.3 ; stop the main-system clock ret dly80 ld a,#0fh del1 nop nop decs a jr del1 ret 2. switch from the sub-system clock to the main-system clock: sub2ma bitr scmod.3 ; start main-system clock oscillation call dly80 ; delay 80 machine cycles call dly80 bitr scmod.0 ; switch to main-system clock ret oscillator circuits s3c72q5/p72q5 6- 10 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is ad dressable by 4-bit write instructions only. fd0h clmod.3 "0" clmod.1 clmod.0 reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fxx/8, fxx/16, or fxx/64. table 6-6. clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64, fxt/4) 1.05mhz,524khz,65.5khz or 8.19khz 0 1 fxx/8 523.8 khz 1 0 fxx/16 261.9 khz 1 1 fxx/64 65.5 khz clmod.3 result of clmod.3 setting 0 disable c lock output at the clo pin. 1 e nable c lock output at the clo pin. note s : 1. fx : main-system clock 2. fxt: sub-system clock 3. frequencies assume that fxx, fx = 4,19mhz, and fxt = 32.768khz s3c72q5/p72q5 oscillator circuits 6- 11 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? port mode flag ? clo output pin 4 clock selector clo clocks (cpu clock, fxx/8, fxx/16, fxx/64) clmod.3 clmod.2 clmod.1 clmod.0 p5.3 latch pm5.3 figure 6- 7 . clo output pin circuit diagram clock output procedure the procedure for outputting clock pulses to the clo pin may be summarized as follows: 1. disable clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load a "0" to the output latch of the clo pin. 4. set the port mode flag to output mode. 5. enable clock output by setting clmod.3 to logi c one. + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb smb 15 ld ea,# 8 0h ld pmg1,ea ; p 5.3 ? output mode bitr p5.3 ; clear the clo pin output latch ld a,#8 h ld clmod,a oscillator circuits s3c72q5/p72q5 6- 12 notes s3c72q5/p72q5 interrupts 7- 1 7 interrupts overview the s3c72q5? s interrupt control circuit has five functional components: ? interrupt enable flags ( iex) ? interrupt request flags ( irqx) ? interrupt master enable register (ime) ? interru pt priority register (ipr) ? power-down release signal circuit three kinds of interrupts are supported: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and as clock sources table 7- 1 . interrupt types and corresponding port pin(s) interrupt type interrupt name corresponding port pins external interrupts int0, int1, intp0 p 4.2 , p 4.3 , p0(k0-k3) internal interrupts intb, intt0 , intt1 not applicable quasi-interrupts int2 p6,p7(ks0?ks7) intw not applicable interrupts s3c72q5/p72q5 7- 2 vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt ( intn) are set to logic one: ? interrupt enable flag ( iex) ? interrupt master enable flag (ime) ? interr upt request flag ( irqx) ? interrupt status flags (is0, is1) ? interrupt priority register (ipr) if all condition s are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. emb and erb flags for ram memory banks and registers are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. the initial flag values determine the vectors for resets and interrupts. enable flag values are saved during the main routine, as well as during service routines. any changes that are made to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the emb and erb values before the interrupt is initiated are saved along with the pro - gram status word (psw), and the emb and the erb flag for the interrupt are fetched from the respective vector address. then, if necessary, you can modify the enable flags during the interrupt service routine. when the interrupt service routine is returned to the main routine by the iret instruction, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. multiple interrupt s by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe cuted in the same register bank. when the routines have executed successfully, you can restore the register con tents from the stack to working memory by using the pop instruction. power-down mode release an interrupt can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0". s3c72q5/p72q5 interrupts 7- 3 no no retain value until ime = 1 retain value until iex = 1 no interrupt is generated (int xx) is1, 0 = 0, 0? is1, 0 = 0, 1? request flag (irqx) 1 generate corresponding vector interrupt and release power-down mode store contents of pc and psw in the stack area and the contents of pc are set by the contents to corresponding vector address high-priority interrupt ? is1, 0 = 1, 0 retain value until interrupt service routine is completed no the corresponding irqx is automatically reset jump to interrupt start address yes no yes yes yes ime = 1? iex = 1? is1, 0 = 1, 0 figure 7- 1 . interrupt execution flowchart interrupts s3c72q5/p72q5 7- 4 intb vector interrupt generator @ = edge detection circuit power-down mode release signal ks0-ks7 int0 int1 intw k0-k6 intt0 ie2 iew iep0 iet1 ie1 ie0 ieb imod0 imod1 irqb irq0 irq1 irqp0 irqt0 irqw irq2 @ @ intt1 irqt1 imod2 selector iet0 interrupt control unit ipr ime is1 is0 figure 7- 2 . interrupt control circuit diagram s3c72q5/p72q5 interrupts 7- 5 multiple interrupts the interrupt controller can serv e multiple interrupts in two ways: as two-level interrupts, where either all inter rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see figure 7- 3). whenever an interrupt request is accepted, is1 and is0 are incremented by one, and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt service flag, however, you must first disable interrupt processing with a di instruction. when is1 = "0" and is0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (ipr). high level interrupt generated normal program processing (status 0) set ipr int enable int disable high or low level interrupt processing (status 1) high level interrupt processing (status 2) low or high level interrupt generated figure 7- 3 . two-level interrupt handling interrupts s3c72q5/p72q5 7- 6 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter - rupt is being serviced. this is done by manipulating the interrupt status flags, is0 and is1 (see table 7- 2). when an interrupt is requested during normal program execution, interrupt status flags is0 and is1 are set to "1" and "0", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high- and low -priority requests can be serviced in parallel (see figure 7- 4). table 7- 2 . is1 and is0 bit manipulation for multi-level interrupt handling process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? normal program processing (status 0) low or high level interrupt generated int enable low or high level interrupt generated set ipr int disable int disable modify status int enable high level interrupt generated single interrupt status 0 status 0 3-level interrupt status 2 2-level interrupt status 1 status 1 figure 7- 4 . multi-level interrupt handling s3c72q5/p72q5 interrupts 7- 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling and its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 7- 3 . standard interrupt priorities interrupt default priority intb 1 int0 2 int1 3 intp0 4 intt0 5 intt1 6 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 7- 4 . interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 normal interrupt handling according to default priority settings. 0 0 1 process intb interrupt at highest priority 0 1 0 process int0 interrupt at highest priority 0 1 1 process int1 interrupt at highest priority 1 0 0 process intp0 interrupt at highest priority 1 0 1 process intt0 interrupt at highest priority 1 1 0 process intt 1 interrupt at highest priority 1 1 1 n/a note: during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in table 7- 3 (the default priority assigned by hardware when the lower three ipr bits = "0"). in this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. then, when the high-priority interrupt is returned from its service routine by an iret instruction, the inhibited service routine is started. interrupts s3c72q5/p72q5 7- 8 + + programming tip ? setting the int interrupt priority the following instruction sequence sets the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt 0 and 1 mode registers (imod0, imod1) the following components are used to process external interrupts at the int0 and int1 pin: ? edge detection circuit ? two mode registers, imod0 and imod1 the mode registers are used to control the triggering edge of the input signal. imod0 and imod1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. fb4h "0" "0" imod0.1 imod0.0 fb5h "0" "0" imod1.1 imod1.0 imod0 and imod1 are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7- 5 . imod0 and imod1 register organization imod x "0" "0" imod x .1 imod x .0 effect of imod settings 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" note: "x" means "0" or "1" s3c72q5/p72q5 interrupts 7- 9 external interrupt 0 and 1 mode registers ( continued) ? you can use int0/int1 to release power-down mode edge detection imodx irqx note: "x" is "0" or "1" intx figure 7- 5 . circuit diagram for int0 and int1 pins when modifying the imod0 and imod1 registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod0 or imod1 register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropriate iex flag. 5. enable all interrup ts with an ei instruction. note: int0 and int1 are same in the function. interrupts s3c72q5/p72q5 7- 10 external interrupt 2 mode register (imod2) to generate a key interrupt on a falling edge at ks0 - ks7, all ks0 - ks7 pins must be configured to input mode . imod2 is write - only register that can be written by 4-bit ram control instruction only. it is mapped to the ram address fb6h and the reset value of imod2 is 0. fb6h "0" imod2. 2 imod2.1 imod2.0 when a falling edge in any one of ks0 - ks7 pins is detected, irq2 is set and the release signal of power down mode is generated . int2, however, does not generate a vector interrupt. among the pins which were selected as key interrupt, one or more pins which are in input low or output low don't execute a key interrupt function. table 7-6. imod2 register bit settings imod2 0 imod2. 2 imod2.1 imod2.0 effect of imod2 settings 0 0 0 select falling edge of ks 0- ks 3 0 0 1 select falling edge of ks 0- ks 4 0 1 0 select falling edge of ks 0- ks 5 0 1 1 select falling edge of ks0 - ks 6 1 0 0 select falling edge of ks0 - ks 7 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 p6.5/ks5 p6.6/ks6 p6.7/ks7 falling edge detection circuit irq2 mux a b c d s0 s1 p6.4/ks4 mux a b s imod2.1 imod2.0 imod2.2 figure 7- 6 . circuit diagram for int2 s3c72q5/p72q5 interrupts 7- 11 + + programming tip ? using int2 as a key input interrupt when the int2 interrupt is used as a key entry interrupt, the selected key interrupt source pin must be set to input: 1. when ks0 ?ks3 are selected (four pins): bits emb smb 15 ld a,# 0 h ld imod2,a ; (imod2) ? # 0 h, ks0 - ks3 falling edge select ld ea,#00h ld pmg 2 ,ea ; p6 ? input mode ld a,#4 0 h ld pumod0,a ; enable p6 pull-up resistors interrupts s3c72q5/p72q5 7- 12 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in - terrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3). it can be directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts interrupt enable flags ( iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags can be read, written, or tested directly by 1-bit instructions. iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. table 7- 7 . interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h " u " " u " ieb irqb fbah " u " " u " iew irqw fbbh " u " " u " iet1 irqt1 fbch " u " " u " iet0 irqt0 fbdh " u " " u " iep0 irqp0 fbeh ie1 irq1 ie0 irq0 fbfh " u " " u " ie2 irq2 notes: 1. iex refers to all interrupt enable flags. 2. irqx refers to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode. s3c72q5/p72q5 interrupts 7- 13 interrupt request flags ( irqx) interrupt request flags are read/write addressable by 1-bit or 4-bit in structions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx flag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero when the interrupt has been serviced. exceptions are the watch timer interrupt request flags, irqw, and the external interrupt 2 flag irq2, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. when irqx is set to "1" by software, an interrupt is generated. table 7- 8 . interrupt request flag conditions and priorities interrupt source internal/ external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 intp0 e falling edge detected at k0?k 6 (p0.0 - p 1.2 ) 4 irqp0 intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 intt1 i signals for tcnt1 and tref1 registers match 6 irqt1 int2 ( note ) e falling edge is detected at any of the ks0 - ks7 pins ? irq2 intw i time interval of 0.5 s or 3.19 ms ? irqw note: refer to page 7- 10 , 7- 11 . interrupts s3c72q5/p72q5 7- 14 notes s3c72q5/p72q5 power-down 8- 1 8 power-down overview the s3c72q5 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mode, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. in stop mode, main-system clock oscillation is halted (assuming it is currently operating), and peripheral hard ware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, serial i/o, timer/ counters 0 and 1, watch timer, and lcd controller ? and on external interrupt requests, is detailed in table 8?1. idle or stop modes are terminated either by a reset , or by an interrupt which is enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset , a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = ?0?; if the power down mode release signal is generated, after releasing the power-down mode, program execution starts immediately under the instruction to enter power down mode without execution of interrupt service routine. the interrupt request flag remains set to logic one. ? if the ime flag = ? 1 ?; if the power down mode release signal is generated, after releasing the power down mode, two instructions following the instruction to enter power down mode are executed first and the interrupt service routine is executed, finally program is resumed. however, when the release signal is caused by int2 or intw, the operation is identical to the ime = ?0? condition because int2 and intw are a quasi-interrupt. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. power-down s3c72q5/p72q5 8- 2 table 8- 1 . hardware operation during power-down modes operation stop mode idle mode instruction stop idle system clock status stop mode c an be us ed only i f the main- system clock is selected as system clock (cpu clock) idle mode c an be used if the main- system clock or sub-system clock is selected as system clock (cpu clock) clock oscillator main-system clock oscillation stops only cpu clock oscillation stops (main and sub-system clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates timer/counter1 timer/counter1 stops timer/counter 1 operates watch timer operates only if sub-system clock ( fxt) is selected as the counter clock watch timer operates lcd controller operates only if a sub-system clock is se lected as lcdck lcd controller operates external interrupts int0,int1,int2 and intp0 are acknowledged . int0,int1,int2 and intp0 are acknowledged . cpu all cpu operations are disabled all cpu operations are disabled mode release signal interrupt request signals are enable by an interrupt enable flag or by reset input . interrupt request signals are enable by an interrupt enable flag or by reset input . s3c72q5/p72q5 power-down 8- 3 table 8-2 . system operating mode comparison mode condition stop/idle mode start method current consumption main operating mode main oscillator runs. sub oscillator runs system clock is the main oscillation clock. ? a main idle mode main oscillator runs. sub oscillator runs system clock is the main oscillation clock. idle instruction b main stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. stop instruction d sub operating mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. ? c sub ldle mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. idle instruction d note: the current consumption is: a > b > c > d power-down s3c72q5/p72q5 8- 4 idle mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset idle istruction normal mode normal mode normal mode clock signal normal oscillation figure 8- 1 . timing when idle mode is released by reset reset clock signal normal oscillation mode release signal idle istruction interrupt acknowledge (ime = 1) normal mode idle mode normal mode figure 8- 2 . timing when idle mode is released by an interrupt s3c72q5/p72q5 power-down 8- 5 stop mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset stop istruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes figure 8- 3 . timing when stop mode is released by reset reset oscillator stabilization wait time (bmod setting) stop istruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes mode release signal int ack(ime=1) figure 8- 4 . timing when stop mode is released by an interrupt power-down s3c72q5/p72q5 8- 6 + + programming tip ? reducing power consumption for key input interrupt processing the following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. in this example, the system clock source is switched from the main-system clock to a sub-system clock and the lcd display is turned on: keyclk di call ma2sub ; main-system clock ? sub-system clock switch subroutine smb 15 ld ea,#00h ld p4,ea ; all key strobe outputs to low level ld a,# 4 h ld imod2,a ; select ks0 - ks7 enable smb 0 bitr irqw bitr irq2 bits iew bits ie2 clks1 call watdis ; execute clock and display changing subroutine btstz irq2 jr cidle call sub2ma ; sub-system clock ? main-system clock switch subroutine ei ret cidle idle ; engage idle mode nop nop nop jps clks1 s3c72q5/p72q5 power-down 8- 7 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8-3 . table 8-3. unused pin connections for reduc ing power consumption pin/share pin names recommended connection p0.0-p0.3/k0-k3 p 1.0-p1.2/k4-k6 p4.0/tcl0 p4.1/tclo0 p5.0-p5.1 p5.2/buz p6.0-p6.3/ks0-ks3/ dm 0- dm 3 p7.0/ks4/ dm 4 p7.1/ks5/ dm 5/com11 p7.2-p7.3/ks6-ks7/com10-com11 input mode: connect to v dd output mode: no connect ion p 4.2 / int0 - p 4.3 /int1 connect to v dd seg0 - seg 15/p8.0-p8.15 seg16-seg23/d0-d7 seg24-seg42/a0-a18 seg43-seg44/ dr , dw seg45-seg59 com0 - com 11 no connect ion test connect to v ss power-down s3c72q5/p72q5 8- 8 note s s3c72q5/p72q5 reset reset 9- 1 9 reset reset overview when a reset signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during a power-down mode ? most hardware register values are set to the reset values described in table 9?1. the current status of several register values is, however, always retained when a reset occurs during idle or stop mode; if a reset occurs during normal operating mode, their values are undefined. current values that are retained in this case are as follows: ? carry flag ? data memory values ? general-purpose registers e, a, l, h, x, w, z, and y oscillator stabilization wait time (31.3 ms/4.19 mhz) normal mode normal mode idle mode reset operation normal mode or power-down mode reset input figure 9 - 1 . timing for oscillation stabilization a fter reset reset hardware register values after reset reset table 9?1 gives you detailed information about hardware register values after a reset occurs during power- down mode or during normal operation. reset reset s3c72q5/p72q5 9- 2 table 9- 1 . hardware register values after reset reset hardware component or subcomponent if reset reset occurs during power down mode if reset reset occurs during normal operating program counter (pc) lower six bits of address 0000h are transferred to pc13?8, and the contents of 0001h to pc7?0. lower six bits of address 0000h are transferred to pc13?8, and the contents of 0001h to pc7?0. program status word (psw): carry flag (c) retained undefined skip flag (sc0 - sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained (note) undefined bank selection registers (smb, srb) 15 , 0 15 , 0 bsc register (bsc0 - bsc3) 0 0 bank1 page select register (pasr) 0 0 key scan register (ksr0 - ksr3) 0 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 system clock mode register (scmod) 0 0 interrupts: interrupt request flags ( irqx) 0 0 interrupt enable flags ( iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0 note: the values of the 0f8h?0fdh are not retained when a reset signal is input. s3c72q5/p72q5 reset reset 9- 3 table 9- 1 . hardware register values after reset reset (continued) hardware component or subcomponent if reset reset occurs during power down mode if reset reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod0) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 watch -dog timer: watch-dog timer mode selection (wdmod) a5 a5 watch-dog timer counter clear flag(wdflag) 0 0 timer/counter 0: count register (tcnt0) 0 0 reference register (tref0) ffh ffh mode register (tmod0) 0 0 output enable flag (toe0) 0 0 timer/counter 1 : count register (tcnt 1 ) 0 0 reference register (tref 1 ) ffh ffh mode register (tmod 1 ) 0 0 watch timer: watch timer mode register (wmod) 0 0 lcd driver/controller: lcd mode register (lmod0/1) 0 0 display data memory values retained undefined output buffers off off reset reset s3c72q5/p72q5 9- 4 note s s3c72q5/p72q5 i/o ports 10- 1 10 i/o ports overview the s3c72q5 has 39 i/o lines. there are total of 16 output pins, 23 configurable i/o pins, for a total number of 39 pins. port mode flags port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in one 8-bit, 4-bit register and are addressable by 8-b it, 4-bit write instructions resp ectively. output ports 8 output ports 8 consists of 16 pins that can be used either for lcd segment data output or for normal 1-bit out put. when lcd display is off, p8 can be used to normal output. the value of p8 is determined by ksr0-ksr3 regardless of lmod.0. (refer to p12-17) pull- u p resistor mode register (pumod0) the pull-up resistor mode register (pumod0) is 8 -bit register used to assign internal pull-up resistors by software to specific i/o ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod0 bit setting. pumod0 is addressable by 8 -bit write instructions only. reset clears pumod0 register values to logic zero, automatically disconnecting all software- assignable port pull-up resis tors. n-channel open-drain mode register (pne0) the n-channel open-drain mode register (pne0) is used to configure outputs as n-channel open-drain outputs or as push-pull outputs. i/o ports s3c72q5/p72q5 10- 2 table 10- 1 . i/o port overview port i/o pins pin names address function description 0 i /o 4 p0.0 - p0.3 (k0 - k3) ff0h 4-bit i/o port. 1,4, and 8-bit read/write, and test are possible. 1 3 p1.0 - p1. 2 (k4 - k6) ff1h individual pins can be specified as input or output. 7-bit pull-up resistors are assignable by software. pull-up resistors are automatically disabled for output pins. 4 5 4 4 p4.0 - p4. 3 p5.0 - p5.3 ff4h ff5h 4-bit i/o port. 1, 4, and 8-bit read/write, and test are possible. 4-bit unit pins are software configurable as input or output. individual pins are software configurable as open-drain or push-pull output. 4-bit pull-up resistors are assignable by software and pull-up resistors are automatically disabled for output pins. 6 7 4 4 p6.0 - p6.3 p7.0 - p7.3 ff6h ff7h 4-bit i/o port. 1,4, and 8-bit read/write, and test are possible. individual pins can be specified as input or output. 4-bit pull-up resistors are assignable by software. pull-up resistors are automatically disabled for output pins. 8 o 16 p 8 .0 - p 8.15 fa2 h - fa5h 4-bit contollable output table 10- 2 . port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p0.1 c,p1.3 a,p6 ea,p4 input or test data at each pin input or test data at output latch 1-bit output bitr p 4 .0 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p5,a p6,ea transfer accumulator data to the output latch transfer accumulator data to the output pin s3c72q5/p72q5 i/o ports 10- 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in one 8-bit registers and are ad dressable by 8-bit write instructions refectively. for convenient program reference, pm flags are organized into three groups ? pmg0, pmg1 , and pmg2 as shown in table 10-3. when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logical zero, automatically configuring the corresponding i/o ports to input mode. table 10- 3 . port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg 0 feah pm 0.3 pm 0.2 pm 0.1 pm 0.0 febh ?0? pm 1.2 pm 1.1 pm 1.0 pmg 1 fech pm 4.3 pm 4.2 pm 4.1 pm 4.0 fedh pm 5.3 pm 5.2 pm 5.1 pm 5.0 pmg2 feeh pm 6.3 pm 6.2 pm 6.1 pm 6.0 feeh pm 7.3 pm 7.2 pm 7.1 pm 7.0 note: if bit = "0", the corresponding i/o pin is set to input mode. if bit = "1", the pin is set to output mode. all flags are cleared to "0" following reset . to use intp0 interrupt, p0 and p1 must be set to external interrupt pins by lmod.6-lmod.4, input mode by pmg0 and pull-up resistor enable by pumod0. + + programming tip ? configuring i/o ports to input or output configure p 4 as an output port: bits e mb smb 15 ld ea,#0fh ld pmg1,ea ; p 4 ? output i/o ports s3c72q5/p72q5 10- 4 pull-up resistor mode register (pumod0) the pull-up resistor mode register (pumod0) is an 8 -bit register used to assign internal pull-up resistors by soft - ware to specific i/o ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled even though the pin's pull-up is enabled by a corresponding pumod0 bit setting . reset clears pumod0 register values to logic zero, automatically disconnecting all software- assignable port pull-up resis tors. table 10- 4 . pull-up resistor mode register (pumod0) organization bit name pumod0 function pumod0. 7 0 disconnect port 7 pull - up resistor 1 connect port 7 pull - up resistor pumod0. 6 0 disconnect port 6 pull - up resistor 1 connect port 6 pull - up resistor pumod0. 5 0 disconnect port 5 pull - up resistor 1 connect port 5 pull - up resistor pumod0. 4 0 disconnect port 4 pull - up resistor 1 connect port 4 pull - up resistor pumod0.3 0 always logic zero pumod0.2 0 always logic zero pumod0.1 0 always logic zero pumod0.0 0 disconnect port 0,1 pull - up resistor 1 connect port 0,1 pull - up resistor note: when p0, p1 are used to external interrupt pins, the pull-up resistors of input mode are determined by key strobe signal (refer to p12-7). + + programming tip ? enabling and disabling i/o port pull-up resistors p6 enable pull-up resistors. bits emb smb 15 ld e a,#4 0 h ld pumod0, e a ; p6 pull-up resist o r enable s3c72q5/p72q5 i/o ports 10- 5 n-channel open-drain mode register (pne0) pne0 address bit3 bit2 bit1 bit0 fe6h pne4.3 pne4.2 pne4.1 pne4.0 fe7h pne5.3 pne5.2 pne5.1 pne5.0 the n-channel open-drain mode register, pne0, is used to configure port4 and 5 to n-channel open-drain outputs or as push-pull outputs. when a bit in the pne0 register is set to one, the corresponding output pin is configured to n-channel open-drain; when set to ?0", the output pin is configured to push-pull. the pne0 register consists of an 8-bit, as shown above. pne0 can be addressed by 8-bit write instructions only. i/o ports s3c72q5/p72q5 10- 6 port 0 ,1 circuit diagram m u x notes: 1. the pull-up resistor enable(re) signal is automatically generated and synchronized to lcd segment signals. 2. when a port pin serves as an output, its pull-up resistor is automatically disabled regradless of pumod0. v dd irqp0 re: resistor enable le: latch enable re v dd re p0.0/ k0 output latch 1, 4, 8 pm0.0 pm0.1 pm1.2 pm1.1 pm1.0 pm0.3 pm0.2 pm0.0 re le p0.1/ k1 p0.2/ k2 p0.3/ k3 p1.0/ k4 p1.1/ k5 p1.2/ k6 internal latch pm0.1 pm0.2 pm0.3 pm0.0 pm0.1 pm0.2 re a a b c d s0 s1 m u x a b c d s0 s1 y y mux a b s y falling edge detection circuit lmod.4 lmod.6 lmod.5 figure 10- 1 . port 0 ,1 circuit diagram s3c72q5/p72q5 i/o ports 10- 7 port 4 circuit diagram cmos push-pull or n-channel open-drain when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (pumod0). note: p4.0/tclo p4.1/tclo0 p4.2/int0 output data input data pm4.x x=0-3 type a v dd p-ch n-ch v dd pur4 type a pm4.3 output latch 1, 4, 8 1, 4, 8 m u x pne4.x tcl0 tclo0 type a type a p4.3/int1 type a pm4.2 pm4.1 pm4.0 pm4.0 pm4.1 pm4.2 pm4.3 pne4.3 pne4.2 pne4.1 pne4.0 int0 int1 figure 10- 2 . port 4 cir c uit diagram i/o ports s3c72q5/p72q5 10- 8 port 5 circuit diagram cmos push-pull or n-channel open-drain notes: 1. when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (pumod0). 2. if this port is set to output ports, the input signal is not transmitted to the mux. p5.0 p5.1 p5.2/buz output data input data pm5.x x=0-3 type b v dd p-ch n-ch v dd pur5 type b pm5.3 output latch 1, 4, 8 1, 4, 8 m u x pne5.x type b type b p5.3/clo type b pm5.2 pm5.1 pm5.0 pm5.0 pm5.1 pm5.2 pne5.3 pne5.2 pne5.1 pne5.0 buz clo pm5.3 figure 10-3. port 5 circuit diagram s3c72q5/p72q5 i/o ports 10- 9 port 6 circuit diagram when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (pumod0). note: p6.0/ks0 p6.1/ks1 p6.2/ks2 v dd pumod0.6 pm6.3 output latch 1, 4, 8 1, 4, 8 m u x p6.3/ks3 pm6.2 pm6.1 pm6.0 ks0 ks1 ks2 ks3 pm6.3 pm6.2 pm6.1 pm6.0 figure 10 -4. port 6 circuit diagram i/o ports s3c72q5/p72q5 10- 10 port 7 circuit diagram when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (pumod0). note: p7.0/ks4 p7.1/ks5 p7.2/ks6 v dd pumod0.7 pm7.3 output latch 1, 4, 8 1, 4, 8 m u x p7.3/ks7 ks4 ks5 ks6 ks7 pm7.0 pm7.1 pm7.2 pm7.3 pm7.2 pm7.1 pm7.0 figure 10 -5. port 7 circuit diagram s3c72q5/p72q5 timers and timer/counter s 11- 1 11 timers and timer/counter s overview the s3c72q5 microcontroller has two timer s, and two timer/counter s modules: ? 8-bit basic timer (bt) ? 8-bit timer/counter 0 (tc0) ? 8-bit timer/counter 1 (tc 1 ) ? watch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer and watch-dog timer . it generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. the basic timer also is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset . the 8-bit timer/counter 0 (tc0) is a programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. the 8-bit timer/counter 1 (tc1) is a programmable timer/counter that is used primarily for event counting and for clock frequency modification. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. it also generates a clock signal for the lcd controller. timers and timer/counter s s3c72q5/p72q5 11- 2 basic timer (bt) overview the 8-bit basic timer (bt) has six functional components: ? clock selector logic ? 4-bit mode register (bmod) ? 8-bit counter register (bcnt) ? 8-bit watchdog timer mode register (wdmod) ? watchdog timer counter clear flag (wdtcf) ? 3-bit watchdog timer counter register(wdcnt) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . bit settings in the basic timer mode register bmod turns the bt module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. interval timer function the basic timer's primary function is to measure elapsed time intervals. the standard time interval is equal to 256 basic timer clock pulses. to restart the basic timer, one bit setting is required: bit 3 of the mode register bmod should be set to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2-bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs ( 3 255). an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is than generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation error. for this purpose, instruction that clear the watchdog timer (bits wdtcf) should be executed at proper points in a program within given period. if an instruction that clears the watchdog timer is not executed within the given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset status. an operation of watchdog timer is as follows: ? write some values (except #5ah) to watchdog timer mode register, wdmod. ? if wdcnt overflows, system reset is generated. s3c72q5/p72q5 timers and timer/counter s 11- 3 oscillation stabilization interval control bits 2-0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as ?wait time?) required to stabilize clock signal oscillation when stop mode is released by an interrupt. when a reset signal is inputted, the standard stabilization interval for system clock oscillation following the reset is 31.3 ms at 4.19 mhz. table 11- 1 . basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after stop mode release or reset 4-bit f85h 4-bit write-only; bmod.3: 1-bit writeable ?0? bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h-f87h 8-bit read-only u (note) wdmod control controls watchdog timer operation. 8-bit f98h-f99h 8-bit write-only a5h wdtcf control clears the watchdog timer?s counter. 1-bit f9ah.3 1-, 4-bit write ?0? note: 'u' means the value is undetermined after a reset . timers and timer/counter s s3c72q5/p72q5 11- 4 notes: 1. wait means stabilization time after reset or stabilization time after stop mode release. 2. the reset signal can be generated if the wdmod is toggled for 8 times where "toggle" means change from 5ah to other value and vice versa. 3. when the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to "0", the bcnt value is not clearedbut increased continuously. as a result, the 3-bit counter of the watchdog timer (wdcnt) cna be increased by 1. for example, when the bmod value is x000b and the watchdog timer is enabled, the watchdog timer interval time is from 2 3 x 2 12 x 2 8 /fxx to (2 3 - 1) x 2 12 x 2 8 /fxx. bmod.3 bmod.2 bmod.1 bmod.0 bits instruction overflow clear bcnt "clear" signal 1 pulse period = bt input clock 2 8 (1/2 duty) interrupt request clear irqb cpu clock start signal (power-down release) wait (note) 3-bit counter clear overflow reset bits instruction reset wdtfc clock selector wdcnt wdmod reset signal generation delay clear stop 8 8 bcnt irqb 1-bit r/w clock input 4 figure 11- 1 . basic timer circuit diagram s3c72q5/p72q5 timers and timer/counter s 11- 5 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic tim er; ? control the frequency of clock signal input to the basic timer; ? determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fxx/2 12 to fxx/2 5 , are se lectable. since bmod's reset value is logic zero, the default clock frequency setting is fxx/2 12 . the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation is restarted. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determine the clock input frequency and oscillation stabilization interval. table 11- 2 . basic timer mode register (bmod) organization bmod.3 basic timer enable/disable control bit 1 restart basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock interrupt interval time (wait time) 0 0 0 fxx/2 12 (1.02 khz) 2 20 /fxx (250 ms) 0 1 1 fxx/2 9 (8.18 khz) 2 17 /fxx (31.3 ms) 1 0 1 fxx/2 7 (32 .7 khz) 2 15 /fxx (7.82 ms) 1 1 1 fxx/2 5 (131 khz) 2 13 /fxx (1.95 ms) notes: 1. clock frequencies and interrupt interval time assume a system oscillator clock frequency (fxx) of 4.19 mhz. 2. fxx = selected system clock frequency. 3. wait time is the time required to stabilize clock signal oscillation after stop mode is released. the data in the table column 'interrupt interval time ' can also be interpreted as " oscillation stabilization ." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz. timers and timer/counter s s3c72q5/p72q5 11- 6 basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it can be addressed by 8-bit read instructions. reset leaves the bcnt counter value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incremented to hexadecimal 'ffh' ( 3 255 clock pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set bmod.3 to logic one to restart the basic timer 2. bcnt is then incremented by one after each clock pulse corresponding to bmod selection 3. bcnt overflows if bcnt 3 255 (bcnt = ffh) 4. when an overflow occurs, the irqb flag is set by hardware to logic one 5. the i nterrupt request is generated 6. bcnt is then cleared by hardware to logic zero 7. basic timer resumes counting clock pulses s3c72q5/p72q5 timers and timer/counter s 11- 7 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt , set the oscillation stabilization interval to 31.3ms (at 4.19mhz): bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3ms nop stop ; se t stop power-down mode nop nop nop cpu operation stop instruction stop mode is released by interrupt normal operating mode stop mode idle mode normal operating mode (31.3 ms) 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3 timers and timer/counter s s3c72q5/p72q5 11- 8 watchdog timer mode register (wdmod) the watchdog timer mode register, wdmod, is a 8-bit write-only register. wdmod register controls to enable or disable the watchdog function. wdmod values are set to logic ?a5h? following reset and this value enables the watchdog timer. watchdog timer is set to the longest interval because bt overflow signal is generated with the longest interval. wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function watchdog timer counter (wdcnt) the watchdog timer counter, wdcnt, is a 3-bit counter. wdcnt is automatically cleared to logic zero, and restarts whenever the wdtcf register control bit is set to ?1?. reset, stop, and wait signal clears the wdcnt to logic zero also. wdcnt increments each time a clock pulse of the overflow frequency determined by the current bmod bit setting is generated. when wdcnt has incremented to hexadecimal ?07h?, it is cleared to ?00h? and an overflow is generated. the overflow causes the system reset . when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. watchdog timer counter clear flag (wdtcf) the watchdog timer counter clear flag, wdtcf, is a 1-bit write instruction. when wdtcf is set to one, it clears the wdcnt to zero and restarts the wdcnt. wdtcf register bits 2?0 are always logic zero. table 11 - 3. watchdog timer interval time bmod bt input clock wdcnt input clock wdt interval time x000b fxx/2 12 fxx/(2 12 2 8 ) (7 or 8) 3 (2 12 2 8 )/fxx = 1.75?2 sec x011b fxx/2 9 fxx/(2 9 2 8 ) (7 or 8) 3 (2 9 2 8 )/fxx = 218.7?250 ms x101b fxx/2 7 fxx/(2 7 2 8 ) (7 or 8) 3 (2 7 2 8 )/fxx = 54.6?62.5 ms x111b fxx/2 5 fxx/(2 5 2 8 ) (7 or 8) 3 (2 5 2 8 )/fxx = 13.6?15.6 ms notes: 1. clock frequencies assume a system oscillator clock frequency (fxx) of 4.19 mhz. 2. fxx = system clock frequency. s3c72q5/p72q5 timers and timer/counter s 11- 9 + + programming tip ? using the watchdog timer reset di ld ea,#00h ld sp,ea ld a,#0dh ; wdcnt input clock is 7.82 ms ld bmod,a main bits wdtcf ; main routine operation period must be shorter than ; watchdog-timer?s period jp main timers and timer/counter s s3c72q5/p72q5 11- 10 8-bit timer/counter 0 (tc0) overview timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmod0 register during program execution. tc0 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre - quency. external event counter counts various system "events" based on edge detection of external clock sig - nals at the tc0 input pin, tcl0. to start the event counting operation, tmod0.2 is set to "1" and tmod0.6 is cleared to "0". arbitrary frequency output outputs selectable clock frequencies to the tc0 output pin, tclo0. external signal divider divides the frequency of an incoming external clock signal according to a modi fiable reference value (tref0), and outputs the modified frequency to the tclo0 pin. s3c72q5/p72q5 timers and timer/counter s 11- 11 tc0 component summary mode register (tmod0) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl0 pin. reference register (tref0) stores the reference value for the desired number of clock pulses between in - terrupt requests. counter register (tcnt0) counts internal or external clock pulses based on the bit settings in tmod0 and tref0. clock selector circuit together with the mode register (tmod0), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt0) with the reference value previously programmed into the reference register (tref0). output enable flag (toe0) must be set to logic one before the contents of the tol0 latch can be output to tclo0. interrupt request flag (irqt0) cleared when tc0 operation starts and the tc0 interrupt service routine is executed and enabled whenever the counter value and reference value coincide. interrupt enable flag (iet0) must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed. table 11-4. tc0 register overview register name type description size ram address addressing mode reset value tmod0 control controls tc0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6 - 4) 8-bit f90h - f91h 8-bit write- only; (tmod0.3 is also 1 -bit writeable) "0" tcnt0 counter counts clock pulses matching the tmod0 frequency setting 8-bit f94h - f95h 8-bit read-only "0" tref0 reference stores reference value for the timer/counter 0 interval setting 8-bit f96h - f97h 8-bit write-only ffh toe0 flag controls timer/counter 0 output to the tclo0 pin 1-bit f92h.2 1-bit and 4-bit read/write "0" timers and timer/counter s s3c72q5/p72q5 11- 12 clear set clear inverted clocks (fxx/2 10 , fxx/2 6 , fxx/2 4 , fxx) tcl0 clear clock selector tcnt0 tref0 8 8 8-bit comparator irqt0 tol0 p4.1 toe0 pm4 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.3 tmod0.2 tmod0.1 tmod0.0 8 tclo0 fxt figure 11- 2 . tc0 circuit diagram tc0 enable/disable procedure enable timer/counter 0 ? set tmod0.2 to logic one ? set the tc0 interrupt enable flag iet0 to logic one ? set tmod0.3 to logic one tcnt0, irqt0, and tol0 are cleared to logic zero, and timer/counter operation starts. disable timer/counter 0 ? set tmod0.2 to logic zero clock signal input to the counter register tcnt0 is halted. the current tcnt0 value is retained and can be read if necessary. s3c72q5/p72q5 timers and timer/counter s 11- 13 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc0 mode register tmod0 is used to activate the timer/counter and to select the clock frequency. the reference register tref0 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to program timer/counter 0 to generate interrupt requests at specific intervals, choose one of five internal clock frequencies (divisions of the system clock, fxx ,fxt ) and load a counter reference value into the tref0 register. tcnt0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod0.4 - tmod0.6 settings. to generate an interrupt request, the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h and tc0 continues counting. the interrupt request mechanism for tc0 includes an interrupt enable flag (iet0) and an interrupt request flag (irqt0). tc0 operation sequence the general sequence of operations for using tc0 can be summarized as follows: 1. set tmod0.2 to "1" to enable tc0 2. set tmod0.6 to "1" to enable the system clock (fxx) input 3. set tmod0.5 and tmod0.4 bits to desired internal frequency (fxx/2 n ) 4. load a value to tref0 to specify the interval between interrupt requests 5. set the tc0 interrupt enable flag (iet0) to "1" 6. set tmod0.3 bit to "1" to clear tcnt0, irqt0, and tol0 and start counting 7. tcnt0 increments with each internal clock pulse 8. when the comparat or shows tcnt0 = tref0, the irqt0 flag is set to "1" , and an interrupt request is generated. 9. output latch (tol0) logic toggles high or low 1 0 . tcnt0 is cleared to 00h and counting resumes 11. programmable timer/counter operation continues until tmod0.2 is cleared to "0". timers and timer/counter s s3c72q5/p72q5 11- 14 tc0 event counter function timer/counter 0 can monitor or detect system 'events' by using the external clock input at the tcl0 pin (i/o port 4.0) as the counter source. the tc0 mode register selects rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmod0.4 - tmod0.6 settings, the operation sequence for tc0's event counter function is identical to its programmable timer/counter function. to activate the tc0 event counter function, ? set tmod0.2 to "1" to enable tc0; ? clear tmod0.6 to "0" to select the external clock source at the tcl 0 pin; ? select tcl0 edge detection for rising or falling signal edges by loading the appropriate values to tmod0.5 and tmod0.4. ? p4.0 must be set to input mode. table 11-5. tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges note: if you set p4.0 to a open-drain, you can use p4.0 as tclo pin for external tco clock, even if p4.0 is set to output mode. s3c72q5/p72q5 timers and timer/counter s 11- 15 tc 0 clock frequency output using timer/counter 0, a modifiable clock frequency can be output to the tc0 clock output pin, tclo0. to select the clock frequency, load the appropriate values to the tc0 mode register, tmod0. the clock interval is selected by loading the desired reference value into the reference register tref0. to enable the output to the tclo0 pin at i/o port 4.1, the following conditions must be met: ? tc0 output enable flag toe0 must be set to "1" ? i/o mode flag for p4.1 (pm4) must be set to output m ode ("1") ? output latch value for p4.1 must be set to "0" in summary, the operational sequence required to output a tc0-generated clock signal to the tclo0 pin is as follows: 1. load a reference value to tref0. 2. set the internal clock frequency in tmod0. 3. initiate tc0 clock output to tclo0 (tmod0.2 = "1"). 4. set port 4 mode flag (pm4) to "1". 5. set p4. 1 output latch to "0". 6. set toe0 flag to "1". each time tcnt0 overflows and an interrupt request is generated, the state of the output latch tol0 is in verted and the tc0-generated clock signal is output to the tclo0 pin. + + programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin (at 4.19 mhz): bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld a,#1h ld pmg2,a ; p4.1 ? output mode bitr p4.1 ; p4.1clear bits toe0 timers and timer/counter s s3c72q5/p72q5 11- 16 tc0 external input signal divider by selecting an external clock source and loading a reference value into the tc0 reference register, tref0, you can divide the incoming clock signal by the tref0 value and then output this modified clock frequency to the tclo0 pin. the sequence of operations used to divide external clock input can be summarized as follows: 1. load a signal divider value to the tref0 register 2. clear tmod0.6 to "0" to enable external clock input at the tcl0 pin 3. set tmod0.5 and tmod0.4 to desired tcl0 signal edge detection 4. set port 4 mode flag (pm4) to output ("1") 5. set p4.1 output latch to "0" 6. set toe0 flag to "1" to enable output of the divided frequency to the tclo0 pin + + programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divided by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld a,#1h ld pmg2,a ; p4.1 ? output mode bitr p4.1 ; p4.1 clear bits toe0 note : the port 4.0 must be a open-drain pin for external tc0 clock input to the tcl0 pin , when the port 4 is set to output mode. s3c72q5/p72q5 timers and timer/counter s 11- 17 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter 0. it is addressable by 8-bit write instructions. one bit, tmod0.3, is also 1-bit writeable. reset clears all tmod0 bits to logic zero and disables tc0 operations. f90h tmod0.3 tmod0.2 "0" "0" f91h "0" tmod0.6 tmod0.5 tmod0.4 tmod0.2 is the enable/disable bit for timer/counter 0. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register tcnt0 are retained until tc0 is re-enabled. the tmod0.6, tmod0.5, and tmod0.4 bit settings are used together to select the tc0 clock source. this selection involves two variables: ? syn chronization of timer/counter operations with either the rising edge or the falling edge of the clock sig nal input at the tcl0 pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc0 operation. table 11-6. tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 always logic zero f91h tmod0.6 0,1 specify input clock edge and internal frequency tmod0.5 tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) f90h tmod0.2 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 tmod0.1 0 always logic zero tmod0.0 0 always logic zero timers and timer/counter s s3c72q5/p72q5 11- 18 table 11-7. tmod0.6, tmod0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 0 1 x fxt (subsytem clock: 32.768 khz) 1 0 0 fxx/2 10 (4.09 khz) 1 0 1 fxx /2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx ( 4.19 mhz ) note : 'fxx' = selected system clock of 4.19 mhz. + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb sm b 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3 s3c72q5/p72q5 timers and timer/counter s 11- 19 tc0 counter register (tcnt0) the 8-bit counter register for timer/counter 0, tcnt0, is read-only and can be addressed by 8-bit ram control instructions. reset sets all tcnt0 register values to logic zero (00h). whenever tmod0.3 is enabled, tcnt0 is cleared to logic zero and counting resumes. the tcnt0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmod0 register (specifically, tmod0.6, tmod0.5, and tmod0.4). each time tcnt0 is incremented, the new value is compared to the reference value stored in the tc0 reference buffer, tref0. when tcnt0 = tref0, an overflow occurs in the tcnt0 register, the interrupt request flag, irqt0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. reference value = n 0 n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ n count clock tref0 tcnt0 ~ ~ interval time tol0 timer start instruction (tmod0.3 is set) irqt0 set irqt0 set 1 2 n-1 0 1 2 n-1 0 1 2 3 match match ~ ~ figure 11- 3 . tc0 timing diagram timers and timer/counter s s3c72q5/p72q5 11- 20 tc0 reference register (tref0) the tc0 reference register tref0 is an 8-bit write-only register. it is addressable by 8-bit ram control instructions. reset initializes the tref0 value to 'ffh'. tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc0 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the tcnt0 value. when tcnt0 = tref0, the tc0 output latch (tol0) is inverted and an interrupt request is generated to signal the interval or event. the tref0 value, together with the tmod0 clock frequency selection, determines the specific tc0 timer interval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting (tref0 value 1 0) tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. toe0 is addressable by 1-bit and 4-bit read / write instruction. (msb) (lsb) f92h "0" toe0 " u " "0" note: the "u" means a undefined register bit. when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. whenever a reset occurs, toe0 is automatically set to logic zero, disabling all tc0 output. even when the toe0 flag is disabled, timer/counter 0 can continue to output an internally generated clock frequency, via tol0. tc0 output latch (tol0) tol0 is the output latch for timer/counter 0. when the 8-bit comparator detects a correspondence between the value of the counter register tcnt0 and the reference value stored in the tref0 register, the tol0 value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of tol0 is switched, the tc0 signal is output. tc0 output may be directed to the tclo0 pin. assuming tc0 is enabled, when bit 3 of the tmod0 register is set to "1", the tol0 latch is cleared to logic zero, along with the counter register tcnt0 and the interrupt request flag, irqt0, and counting resumes immedi ately. when tc0 is disabled (tmod0.2 = "0"), the contents of the tol0 latch are retained and can be read, if necessary. s3c72q5/p72q5 timers and timer/counter s 11- 21 + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 62.5ms (assume the tc0 counter clock = fxx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 val ue: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea timers and timer/counter s s3c72q5/p72q5 11- 22 8-bit timer/counter 1 (tc 1 ) overview timer/counter 1 (tc 1 ) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc 1 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc 1 can be used to measure specific time intervals. tc 1 has a reloadable counter that consists of two parts: an 8-bit reference register (tref 1 ) into which you write the counter reference value, and an 8-bit counter register (tcnt 1 ) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod 1 , is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmod 1 register during program execution. tc 1 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre - quency. s3c72q5/p72q5 timers and timer/counter s 11- 23 tc 1 component summary mode register (tmod 1 ) activates the timer/counter and selects the internal clock frequency. reference register (tref 1 ) stores the reference value for the desired number of clock pulses between in - terrupt requests. counter register (tcnt 1 ) counts internal or external clock pulses based on the bit settings in tmod 1 and tref 1 . clock selector circuit together with the mode register (tmod 1 ), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt 1 ) with the reference value previously programmed into the reference register (tref 1 ). interrupt request flag (irqt 1 ) cleared when tc 1 operation starts and the tc 1 interrupt service routine is executed and enabled whenever the counter value and reference value coincide. interrupt enable flag (iet 1 ) must be set to logic one before the interrupt requests generated by timer/counter 1 can be processed. table 11-8. tc 1 register overview register name type description size ram address addressing mode reset value tmod 1 control controls tc 1 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6 - 4) 8-bit f a6 h - f a7 h 8-bit write- only; (tmod 1 .3 is also 1 -bit writeable) "0" tcnt 1 counter counts clock pulses matching the tmod 1 frequency setting 8-bit f a8 h - f a9 h 8-bit read-only "0" tref 1 reference stores reference value for the timer/counter 1 interval setting 8-bit f aa h - f ab h 8-bit write-only ffh timers and timer/counter s s3c72q5/p72q5 11- 24 clear set clocks (fxx/2 10 , fxx/2 8 , fxx/2 6 , fxx 4 ) fxt clear clock selector tcnt1 tref1 8 8 8-bit comparator irqt1 tmod1.7 tmod1.6 tmod1.5 tmod1.4 tmod1.3 tmod1.2 tmod1.1 tmod1.0 8 figure 11-4. tc 1 circuit diagram tc 1 enable/disable procedure enable timer/counter 1 ? set tmod 1 .2 to logic one ? set the tc 1 interrupt enable flag iet 1 to logic one ? set tmod 1 .3 to logic one tcnt 1 , irqt 1 , and tol 1 are cleared to logic zero, and timer/counter operation starts. disable timer/counter 1 ? set tmo d 1 .2 to logic zero clock signal input to the counter register tcnt 1 is halted. the current tcnt 1 value is retained and can be read if necessary. s3c72q5/p72q5 timers and timer/counter s 11- 25 tc 1 programmable timer/counter function timer/counter 1 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc 1 mode register tmod 1 is used to activate the timer/counter and to select the clock frequency. the reference register tref 1 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt 1 , counts the incoming clock pulses, which are compared to the tref 1 value as tcnt 1 is incremented. when there is a match (tref 1 = tcnt 1 ), an interrupt request is generated. to program timer/counter 1 to generate interrupt requests at specific intervals, choose one of five internal clock frequencies (divisions of the system clock, fxx ,fxt ) and load a counter reference value into the tref 1 register. tcnt 1 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod 1 .4 - tmod 1 .6 settings. to generate an interrupt request, the tc 1 interrupt request flag (irqt 1 ) is set to logic one, and the interrupt is generated. the content of tcnt 1 is then cleared to 00h and tc 1 continues counting. the interrupt request mechanism for tc 1 includes an interrupt enable flag (iet 1 ) and an interrupt request flag (irqt 1 ). tc 1 operation sequence the general sequence of operations for using tc 1 can be summarized as follows: 1. set tmod 1 .2 to "1" to enable tc 1 2. set tmod 1 .6 to "1" to enable the system clock (fxx) input . 3. s et tmod 1 .5 and tmod 1 .4 bits to desired internal frequency (fxx/2 n ) or tmod1.6 and tmod1.5 to ?1? to enable the system clock fxt input. 4 . load a value to tref 1 to specify the interval between interrupt requests 5 . set the tc 1 interrupt enable flag (iet 1 ) to "1" 6 . set tmod 1 .3 bit to "1" to clear tcnt 1 , irqt 1 , and tol 1 and start counting 7 . tcnt 1 increments with each internal clock pulse 8 . when the comparator shows tcnt 1 = tref 1 , the irqt 1 flag is set to "1" , and an interrupt request is generated. 9 . tcnt 1 is cleared to 00h and counting resumes 10. programmable timer/counter operation continues until tmod 1 .2 is cleared to "0". timers and timer/counter s s3c72q5/p72q5 11- 26 tc 1 mode register (tmod 1 ) tmod 1 is the 8-bit mode control register for timer/counter 1 . it is addressable by 8-bit write instructions. one bit, tmod 1 .3, is also 1-bit writeable. reset clears all tmod 1 bits to logic zero and disables tc 1 operations. f a6 h tmod 1 .3 tmod 1 .2 "0" "0" f a7 h "0" tmod 1 .6 tmod 1 .5 tmod 1 .4 tmod 1 .2 is the enable/disable bit for timer/counter 1 . when tmod 1 .3 is set to "1", the contents of tcnt 1 , and irqt 1 , are cleared, counting starts from 00h, and tmod 1 .3 is automatically reset to "0" for normal tc 1 operation. when tc 1 operation stops (tmod 1 .2 = "0"), the contents of the tc 1 counter register tcnt 1 are retained until tc 1 is re-enabled. the tmod 1 .6, tmod 1 .5, and tmod 1 .4 bit settings are used together to select the tc 1 clock source. this selection involves: ? selection of one of f ive frequencies, based on division of the incoming system clock frequency, or subsytem clock frequency, for use in internal tc 1 operation. table 11-9. tc 1 mode register (tmod 1 ) organization bit name setting resulting tc 1 function address tmod 1 .7 0 always logic zero fa7h tmod 1 .6 0,1 specify input clock edge and internal frequency tmod 1 .5 tmod 1 .4 tmod 1 .3 1 clear tcnt 1 , and irqt 1 , and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) fa6h tmod 1 .2 0 disable timer/counter 1 ; retain tcnt 1 contents 1 enable timer/counter 1 tmod 1 .1 0 always logic zero tmod 1 . 1 0 always logic zero s3c72q5/p72q5 timers and timer/counter s 11- 27 table 11-10. tmod 1 .6, tmod 1 .5, and tmod 1 .4 bit settings tmod 1 .6 tmod 1 .5 tmod 1 .4 resulting counter source and clock frequency 0 1 x fxt (subsytem clock: 32.768 khz) 1 0 0 fxx/2 10 (4.09 khz) 1 0 1 fxx /2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx ( 4.19 mhz ) note : 'fxx' = selected system clock of 4.19 mhz. + + programming tip ? restarting tc 1 counting operation 1. set tc 1 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod 1 ,ea ei bits iet 1 2. clear tcnt 1 , and irqt 1 , and restart tc 1 counting operation: bits emb smb 15 bits tmod 1 .3 timers and timer/counter s s3c72q5/p72q5 11- 28 tc 1 counter register (tcnt 1 ) the 8-bit counter register for timer/counter 1 , tcnt 1 , is read-only and can be addressed by 8-bit ram control instructions. reset sets all tcnt 1 register values to logic zero (00h). whenever tmod 1 .3 is enabled, tcnt 1 is cleared to logic zero and counting resumes. the tcnt 1 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmod 1 register (specifically, tmod 1 .6, tmod 1 .5, and tmod 1 .4). each time tcnt 1 is incremented, the new value is compared to the reference value stored in the tc 1 reference buffer, tref 1 . when tcnt 1 = tref 1 , an overflow occurs in the tcnt 1 register, the interrupt request flag, irqt 1 , is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. reference value = n 0 n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ n count clock tref1 tcnt1 timer start instruction (tmod1.3 is set) irqt1 set irqt1 set 1 2 n-1 0 1 2 n-1 0 1 2 3 figure 11-5. tc 1 timing diagram s3c72q5/p72q5 timers and timer/counter s 11- 29 tc 1 reference register (tref 1 ) the tc 1 reference register tref 1 is an 8-bit write-only register. it is addressable by 8-bit ram control instructions. reset initializes the tref 1 value to 'ffh'. tref 1 is used to store a reference value to be compared to the incrementing tcnt 1 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc 1 is being used to perform ? as a programmable timer/counter . during timer/counter operation, the value loaded into the reference register is compared to the tcnt 1 value. when tcnt 1 = tref 1 an interrupt request is generated to signal the interval. the tref 1 value, together with the tmod 1 clock frequency selection, determines the specific tc 1 timer interval. use the following formula to calculate the correct value to load to the tref 1 reference register: tc 1 timer interval = (tref 1 value + 1) 1 tmod 1 frequency settin g (tref 1 value 1 1 ) + + programming tip ? setting a tc 1 timer interval to set a 30 ms timer interval for tc 1 , given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 1 mode register with a maximum setup time of 62.5ms (assume the tc 1 counter clock = fxx/2 10 , and tref 1 is set to ffh): 2. calculate the tref0 value: 30 ms = tref 1 value + 1 4.09 khz tref 1 + 1 = 30 ms 244 s = 122.9 = 7ah tref 1 value = 7ah ? 1 = 79h 3. load the value 79h to the tref 1 register: bits emb smb 15 ld ea,#79h ld tref 1 ,ea ld ea,#4ch ld tmod 1 ,ea timers and timer/counter s s3c72q5/p72q5 11- 30 watch timer overview the watch timer is a multi-purpose timer which consists of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and interval timing for the main and sub - system clock. it is also used as a clock source for the lcd controller and for generating buzzer (buz) output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register (wmod.2) to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5- second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a main system or subsystem clock source the watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. when the zero bit of the wmod register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if wmod.0 = "0", the main system clock (fx) is used as the signal source, according to the following for - mula: watch timer clock (fw) = main system clock (fx) 128 = 32.768 khz (fx = 4.19 mhz) this feature is useful for controlling timer-related operations during stop mode. when stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. by using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag irqw to "1", thereby releasing stop mode. buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin at selected clock for watch timer . to select the desired buz frequency , load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit is set to "1" ? the output latch for i/o port 5.2 is cleared to "0" ? the port 5.2 output mode flag (pm 5.2 ) set to 'output' mode s3c72q5/p72q5 timers and timer/counter s 11- 31 timing tests in high-speed mode by setting wmod.1 to "1", the watch timer will operate in high-speed mode, generating an interrupt every 3.91 ms at oscillation clock of 4.19 mhz. at its normal speed (wmod.1 = '0'), the watch timer generates an interrupt request every 0.5 sec onds. high-speed mode is useful for timing events for program debugging sequences. check subsystem clock level feature the watch timer can also check the input level of the subsystem clock by testing wmod.3. if wmod.3 is "1", the input level at the xt in pin is high; if wmod.3 is "0", the input level at the xt in pin is low. fw/16 fw/8 fw/4 fw/2 enable/ disable irqw fw/2 14 fw/2 7 fw (32.768 khz) (note) fx = main-system clock fxt = sub-system clock fw = watch timer frequency mux clock selector fxt fx/16 frequency dividing circuit wmod.7 wmod.6 wmod.5 wmod.4 wmod.3 wmod.2 wmod.1 wmod.0 8 buz p5.2 latch pm5.2 selector circuit m u x fx/32 fx/64 fx/128 lmod.3-.2 note: fw = 32.768 khz, when fx is 4.19 mhz and fx/128 is selected. to lcd controller figure 11-6. watch timer circuit diagram timers and timer/counter s s3c72q5/p72q5 11- 32 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is 8-bit write-only addressable. an exception is wmod bit 3 (the xt in input level control bit) which is 1-bit read-only addressable. a reset automatically sets wmod.3 to the current input level of the subsystem clock, xt in (high, if logic one; low, if logic zero), and all other wmod bits to logic zero. f88h wmod.3 wmod.2 wmod.1 wmod.0 f89h wmod.7 "0" wmod.5 wmod.4 in summary, wmod settings control the following watch timer functions: ? watch timer clock and lcd clock selection (wmod.0) ? watch timer speed control (wmod.1) ? enable/disable watch timer (wmod.2) ? xt in input level control (wmod.3) ? buzzer frequency selection (wmod.4 and wmod.5) ? enable/disable buzzer output (wmod.7) table 11-11. watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output at the buz pin f89h 1 enable buzzer (buz) signal output at the buz pin wmod.6 0 always logic zero wmod.5 ? .4 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 0 input level to xt in pin is low f88h 1 input level to xt in pin is high wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer wmod.1 0 normal mode; sets irqw to 0.5 second 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 select (fx/128) as the watch timer clock (fw) select a lcd clock source as main system clock 1 select subsystem clock as watch timer clock (fw) select a lcd clock source as sub system clock note: main system clock frequency (fx) is assumed to be 4.19 mhz; subsystem clock (fxx) is assumed to be 32.768 khz. s3c72q5/p72q5 timers and timer/counter s 11- 33 + + programming tip ? using the watch timer 1. select a subsystem clock as the lcd display clock, a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#40 h ld pmg1,ea ; p 5.2 ? output mode bitr p 5.2 ld ea,#85h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt g eneration ? ? ; increment hour, minute, second timers and timer/counter s s3c72q5/p72q5 11- 34 notes s3c72q5/p72q5 lcd controller/driver 12 - 1 12 lcd controller/driver overview the s3c72q5 microcontroller can directly drive an up-to-12- characters (5 x 12 dots) lcd panel. its lcd block has the following components: ? lcd controller/driver ? display ram (100h - 1b b h) for storing display data (13h page) ? 60 segment output pins (seg0 - seg59) ? 12 common output pins (com0 - com 11 ) ? lcd contrast control circuit by software (16 steps) the frame frequency, lcd divide resistors, key strobe signal output key, and check signal output are determined by bit settings in the lcd mode register, lmod. the lcd duty and normal lcd display are determined by bit settings in the lcd control registers, lcon0 and lcon1. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during main stop and idle modes. lcd controller/driver s3c72q5/p72q5 12 - 2 lcd circuit diagram memory bank1 (page 13h) display ram 8 4 segment driver m u x seg59 seg58 seg44/ dw seg16/ d 0 seg15/p8.15 seg14/p8.14 seg0/p8.0 ksr0-3 lmod lcon0 lcon1 lcnst 4 lcd controller voltage divider com control v lc1 v lc2 v lc3 v lc4 com11 com10 com0 4 fxt or divided main-system clock(fx) 4 8 figure 12- 1 . lcd circuit diagram m u x fx/16 fx/32 fx/64 fx/128 lmod clock selector fxt wmod.0 to lcd controller figure 12- 2 . lcd clock circuit diagram s3c72q5/p72q5 lcd controller/driver 12 - 3 lcd ram address area ram addresses 100h - 1b b h of bank1 page 13h are used as lcd data memory. these locations can be addressed by 8-bit instructions only. however, the upper 3 bits of each address must be written to zero. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0 - seg59 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. s e g 0 lsb msb lsb msb lsb msb lsb msb 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh a0h a1h a2h a3h a4h a5h a6h a7h a8h a9h aah abh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh b0h b1h b2h b3h b4h b5h b6h b7h b8h b9h bah bbh s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 5 0 s e g 5 1 s e g 5 2 s e g 5 3 s e g 5 4 s e g 5 5 s e g 5 6 s e g 5 7 s e g 5 8 s e g 5 9 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 figure 12- 3 . display ram organization lcd controller/driver s3c72q5/p72q5 12 - 4 lcd contrast control register (lcnst) the lcd contrast control register (lcnst) is used to control the lcd contrast up to 16 step contrast level. following a reset , all lcnst values are cleared to "0". this disable the lcd contrast control. f8ah lcnst.3 lcnst.2 lcnst.1 lcnst.0 f8bh lcnst.7 0 0 0 table 12-1. lcd contrast control register (lcnst) organization lcd contrast control enable/disable bit lcnst .7 enable/disable lcd contrast control 0 disable lcd contrast control 1 enable lcd contrast control bits 6-4 bits 6-4 always logic zero segment/port output selection bits lcnst.3 lcnst.2 lcnst.1 lcnst.0 16 step contrast level 0 0 0 0 1/16 step (the dimmest level) 0 0 0 1 2/16 step 0 0 1 0 3/16 step 0 0 1 1 4/16 step 0 1 0 0 4/16 step 1 1 1 1 16/16 step (the brightest level) note: v lcd = v dd (1-(16-n)/48), when n = 0-15 (at normal lcd dividing resistors) s3c72q5/p72q5 lcd controller/driver 12 - 5 lcd output control register 0 (lcon0) the lcd output control register 0, lcon0 can be manipulated using 4-bit write instructions. f8eh lcon0.3 lcon0.2 "0" "0" lcon0 can select lcd duty. table 12-2. lcd output control register (lcon0) organization lcon0.3 lcon0.2 duty 0 0 1/9 duty (com0-com8 select) 0 1 1/10 duty (com0-com9 select) 1 0 1/11 duty (com0-com10 select) 1 1 1/12 duty (com0-com11 select) notes: 1. com has priority over normal port in p7.3/com9-p7.1/com11. this means these port are assigned to com pins regardless of the value of pmg2, when duty is selected to 1/10, 1/11, or 1/12 at lcon0 register. 2. the port used com must be set to output to prevent lcd display distortion. lcd output control register 1 (lcon1) the lcd output control register 1, lcon1 can be manipulated using 4-bit write instructions. f8fh lcon1.3 lcon1.2 lcon1.1 lcon1.0 lcon1 control the following lcd functions. ? lcd display on/off lcon1.2 ? key check signal output with lcd display off (lcon1.3) ? diming mode (lcon1.0) table 12-3. lcd output control register (lcon1) organization lcon1.3 lcon1.2 lcon1.1 lcon1.0 bias selection for lcd display 0 1 0 0 lcd display on 0 1 0 1 dimming mode 1 0 0 1 key check signal output with lcd display off notes: 1. to turn off lcd display, you must set lcon1 to 9 not 0. 2. p8 can be used to normal output port, when lcd display off. the value of p8 is determined by ksr0-ksr3 regardless of lmod.0. (refer to p12-17) lcd controller/driver s3c72q5/p72q5 12 - 6 lcd mode register (lmod) the lcd mode register lmod can be manipulated using 8 -bit write instructions. f8 d h ?0? lmod .6 lmod .5 lmod .4 f8 c h lmod .3 lmod.2 lmod.1 lmod.0 lmod controls the following lcd functions: ? external interrupt intp0 enable/disable selection bits (lmod.6, lmod.5, and lmod.4) ? external interrupt intp0 detection pins can be select (lmod.6, lmod.5, and lmod.4) ? when main system clock is selected as watch timer clock by wmod.0, watch timer clock selection bits (lmod.3 and lmod.2) ? lcd dividing resistors sel ection (lmod.1) ? key strobe signal disable /enable selection (lmod.0) s3c72q5/p72q5 lcd controller/driver 12 - 7 table 12 -4. lcd mode control register (lmod) organization external interrupt (intp0) pins selection bits (1) lmod .6 lmod .5 lmod .4 external interrupt (intp0) pins selection bits (1) 0 0 0 interrupt request at k0 triggered by falling edge 0 0 1 interrupt request at k0-k1 triggered by falling edge 0 1 0 interrupt request at k0-k2 triggered by falling edge 0 1 1 interrupt request at k0-k3 triggered by falling edge 1 0 0 interrupt request at k0-k4 triggered by falling edge 1 0 1 interrupt request at k0-k5 triggered by falling edge 1 1 0 interrupt request at k0-k6 triggered by falling edge 1 1 1 interrupt request flag (irqp0) cannot be set to logic one watch timer clock selection bits (2) lmod.3 lmod.2 when main system clock is selected as watch timer clock by wmod.o 0 0 fx/128 0 1 fx/64 1 0 fx/32 1 1 fx/16 lcd dividing resistor selection bits lmod.1 lcd dividing resistor 0 normal lcd dividing resistors 1 diminish lcd dividing resistors to strength lcd drive key strobe signal output control bits (seg0/p8.0-seg15/p8.15) lmod.0 key strobe signal output control (seg0/p8.0-seg15/p8.15) 0 enable key strobe signal output (3) 1 disable key strobe signal output (4) note s : 1. the pins which are not selected as external interrupt (k0-k6) can be used to normal i/o. to use external interrupts, corresponding pins must be set to input mode. 2. lcd clock can be se lected only when main clock(fx) is used as clock source of watch timer. when sub clock(fxt) is used as clock source of watch timer, lcd clock is always fw/48 (1/9 duty), fw/44 (1/10 duty), fw/40 (1/11duty), or fw/36 (1/12 duty). 3. in this case, pull-up resistors of port0,1 are disabled if the value of pur0 is "0", when the value of pur0 is "1", the pull- up resistors of selected pins as interrupt input are enabled or disabled by key strobe signal, and that of non-selected pins are disabled. 4. in th is case, pull-up resistors of port 0,1 are disabled or enabled by the value of pur0 flag. lcd controller/driver s3c72q5/p72q5 12 - 8 notes: 1. when the lcd module is turned off, load lcon1 to "9" to reduce power consumption. 2. when lcnst.7 is logic one, lcd contrast can be controlled by writing data to lcnst.3-.0. 3. where r cn is lcd contrast controller's resistor. application with internal contrast control fixed v ss application without internal contrast control v dd "0" lcon1 (on) v lc1 v lc2 v lc3 v lc4 v lc5 "1" lcd controller contrast r1 r2 r3 r4 s3c72q5 v lcd v lcd = v dd lcnst.7 = 0 fixed v ss v dd "0" lcon1 (on) v lc1 v lc2 v lc3 v lc4 v lc5 "1" lcd controller contrast r1 r2 r3 r4 s3c72q5 v lcd lcnst.7 = 1 v lcd = r lcd + r cn x v dd r lcd figure 12-4. lcd voltage dividing resistors connection s3c72q5/p72q5 lcd controller/driver 12 - 9 when lcon1 is 4 or 5, lmod.0 are set to "0" and pull-up enable by pumod0, re and le signal are generated as below: 0 8 7 6 5 4 3 2 1 com0 com t com = 1.46 ms (t xt = 32.768 khz) t f = 13.18 ms t s max = 2.93 ms t s min = 1.46 ms ~ ~ ~ ~ t e t d t r e = 1.5 t xt = 45.8 m s t l e = t xt/2 = t e = t d = 15.3 m s resistor enable : re input latch enable : le > t s max ~ ~ valid input signals: p0.0-p1.2 latch data ~ ~ figure 12-5. re, le and inputs signal waveform (1/9 duty) lcd controller/driver s3c72q5/p72q5 12 - 10 com0 com1 v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lcd 3/4v lcd 2/4v lcd 1/4v lcd v ss -1/4v lcd -2/4v lcd -v lcd -3/4v lcd f f = 75.85 hz t ast = 45.8 m s com8 seg0 com0 -seg0 note: the upper figure is com and seg signal waveform when lmod.0 is set to logic "0" and fw is 32.768 khz. on off on off off off off off on on figure 12-6. lcd signal waveform for 1/9 duty and 1/4 bias s3c72q5/p72q5 lcd controller/driver 12 - 11 when lcon1 is 4 or 5, lmod.0 are set to "0" and pull-up enable by pumod0, re and le signal are generated as below: 9 8 7 6 5 4 3 2 1 com0 com t com = 1.46 ms (t xt = 32.768 khz) t f = 14.64 ms t s = 2.93 ms ~ ~ ~ ~ t e t d t r e = 1.5 t xt = 45.8 m s t l e = t xt/2 = t e = t d = 15.3 m s resistor enable : re input latch enable : le > t s max ~ ~ valid input signals: p0.0-p1.2 latch data ~ ~ 0 figure 12-7. re, le and inputs signal waveform (1/10 duty) lcd controller/driver s3c72q5/p72q5 12 - 12 com0 com1 v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lcd 3/4v lcd 2/4v lcd 1/4v lcd v ss -1/4v lcd -2/4v lcd -v lcd -3/4v lcd f f = 68.3hz t ast = 45.8 m s com9 seg0 com0 -seg0 note: the upper figure is com and seg signal waveform when lmod.0 is set to logic "0" and fw is 32.768 khz. on off on off off on off figure 12-8. lcd signal waveform for 1/10 duty and 1/4 bias s3c72q5/p72q5 lcd controller/driver 12 - 13 when lcon1 is 4 or 5, lmod.0 are set to "0" and pull-up enable by pumod0, re and le signal are generated as below: 9 8 7 6 5 4 3 2 1 com0 com t com = 1.46 ms (t xt = 32.768 khz) t smax = 2.93 ms ~ ~ ~ ~ t e t d t r e = 1.5 t xt = 45.8 m s t l e = t xt/2 = t e = t d = 15.3 m s resistor enable : re input latch enable : le > t s max ~ ~ valid input signals: p0.0-p1.2 latch data ~ ~ 10 0 t f = 16.1 ms t smin = 1.46 ms figure 12-9. re, le and inputs signal waveform (1/11 duty) lcd controller/driver s3c72q5/p72q5 12 - 14 com0 com1 v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lcd 3/4v lcd 2/4v lcd 1/4v lcd v ss -1/4v lcd -2/4v lcd -v lcd -3/4v lcd f f = 62.11 hz t ast = 45.8 m s com10 seg0 com0 -seg0 note: the upper figure is com and seg signal waveform when lmod.0 is set to logic "0" and fw is 32.768 khz. on off off off on off on off on off off figure 12-10. lcd signal waveform for 1/11 duty and 1/4 bias s3c72q5/p72q5 lcd controller/driver 12 - 15 when lcon1 is 4 or 5, lmod.0 are set to "0" and pull-up enable by pumod0, re and le signal are generated as below: 9 8 7 6 5 4 3 2 1 com0 com t com = 1.46 ms (t xt = 32.768 khz) t s = 2.93 ms ~ ~ ~ ~ t e t d t r e = 1.5 t xt = 45.8 m s t l e = t xt/2 = t e = t d = 15.3 m s resistor enable : re input latch enable : le > t s max ~ ~ valid input signals: p0.0-p1.2 latch data ~ ~ 10 0 t f = 17.56 ms 11 figure 12-11. re, le and inputs signal waveform (1/12 duty) lcd controller/driver s3c72q5/p72q5 12 - 16 com0 com1 v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lc1 v lc2 v lc3 v lc4 v ss v lcd 3/4v lcd 2/4v lcd 1/4v lcd v ss -1/4v lcd -2/4v lcd -v lcd -3/4v lcd f f = 56.95 hz t ast = 45.8 m s com11 seg0 com0 -seg0 note: the upper figure is com and seg signal waveform when lmod.0 is set to logic "0" and fw is 32.768 khz. on off off off on off on off on off off figure 12-12. lcd signal waveform for 1/12 duty and 1/4 bias s3c72q5/p72q5 lcd controller/driver 12 - 17 key scan register (ksr) the 16 output pins (p8.0 - p8.15) of 60 segments can be used for key check signal output. ksr0? ksr3 are mapped to the ram addr ess fa2h - fa5h, and the reset value is "0". ksr is the write-only register that can be manipulated by 4-bits ram write instruction only. table 12 -5. ksr organization ksr0 ksr0.3 ksr0.2 ksr0.1 ksr0.0 fa2h ksr1 ksr1.3 ksr1.2 ksr1.1 ksr1.0 fa3h ksr2 ksr2.3 ksr2.2 ksr2.1 ksr2.0 fa4h ksr3 ksr3.3 ksr3.2 ksr3.1 ksr3.0 fa5h when lcon1 is 9, the values of ksr0 -ksr3 are output to segment pins for key check regardless of lmod.0. at this time, only one of 16 bits (ksr0.0 - ksr3.3) must be set to logic "1" , and the contents of ksr must be changed 16 times one by one for 16 key check by software . when a bit value of ksr is "1", the corresponding segment pin becomes the low level . f igure 12 -14 shows its segment pin output. ksrx.0 = 1 seg i seg i + 1 seg i + 2 ksrx.0 = 0 ksrx.1 = 0 ksrx.2 = 0 ksrx.2 = 1 ksrx.1 = 1 non-overlap note: "x" means 0, 1, 2 and 3. figure 12-13. segment pin output signal when lcon1.3 = 1 lcd controller/driver s3c72q5/p72q5 12 - 18 notes s3c72q5/p72q5 external memory interface 13- 1 13 external memory interface overview the s3c72q5 microcontroller can directly interface the external memory up to 6 x 4 m-bit. it external memory interface block has the following components. ? 8-bit external memory control r egister (emcon) ? external memory address register 0, 1, 2 (emar0-emar2) ? 8-bit external memory data register 0 (emdr0) ? external memory interface clock selector ? six external memory selection pins ( dm 0- dm 5) ? eight data and nineteen address pins (d0-d7, a0-a18) it should be taken care to the lcd contrast due to an external memory interface, since all external memory interface lines except dm0-dm5 are shared with segment driver pins of lcd driver/controller. external memory control register (emcon) the external memory control register (emcon) is used to read data from or write data in a external memory, to select external memory interface clock frequency, to increase automatically the address (a value of emar2- emar0) or not, and to select data memory pin (one of dm 0- dm 5). the emcon can be manipulated using 8-bit write. fd2h emcon.3 emcon.2 emcon.1 emcon.0 fd3h emcon.7 emcon.6 emcon.5 emcon.4 the memory access clock frequency, f m , determines the read and write time for external memory. the f m should be selected appropriately because a memory has read and write time specified and the external memory interface lines except dm0-dm5 are shared with segment driver pins of lcd driver/controller. external memory interface s3c72q5/p72q5 13- 2 table 13-1. external memory control register (emcon) organization memory read/write control bit emcon.7 0 memory read signal output 1 memory write signal output memory access clock selection bits emcon.6 emcon.5 memory access clock frequency (f m ) 0 0 fxx/8 0 1 fxx/4 1 0 fxx/2 1 1 fxx/1 address increment control bit emcon.4 0 the address(a value of emar2 - emar0) is not increased automatically after memory access. 1 the address(a value of emar2 - emar0) is increased automatically after memory access. memory selection bits emcon.3 emcon.2 emcon.1 external data memory selection 0 0 0 data memory 0( dm 0 active) 0 0 1 data memory 1( dm 1 active) 0 1 0 data memory 2( dm 2 active) 0 1 1 data memory 3( dm 3 active) 1 0 0 data memory 4( dm 4 active) 1 0 1 data memory 5( dm 5 active) memory access start bit (this bit is cleared automatically when memory access is finished) emcon.0 0 not busy (read) 1 start a memory access (write) busy (read) notes: 1. when it reads data from a external memory, the data are written to the register emdr0. 2. when it writes data to a external memory, the data to the register emdr0 are written to a external memory. 3. the external memory selection pins of p6.0/ dm 0 - p7.1/ dm 5 should be set to push-pull output and the latches should be set to logic "1". s3c72q5/p72q5 external memory interface 13- 3 how to access the external memory the pin which are selected for external memory interface of dm 0- dm 5 should be set to push-pull output and the latches should be set to logic ?1?. the procedure for external memory interface may be summarized as follows. 1. to read data form external memory ? load the address of external memory to emar2-emar0 in bank 15. ? clear emcon.7 to logic 0, load appropriate values to emcon.6-.1 ? wait for memory access set-up time ? set emcon.0 to logic 1. ? check emcon.0 until for not busy ("0") ? read a v alue of emdr0 in bank 15 if emcon.0 is "0". 2. to write data to external memory ? load the address of external memory to emar2-emar0 in bank 15. ? load data to emdr0 in bank 15 ? set emcon.7 to logic 1, load appropriate values to emcon.6-.1 ? wait for memory access set-up time ? set emcon.0 to logic 1. ? check emcon.0 until not busy (0) before writing other data to external memory. external memory interface s3c72q5/p72q5 13- 4 + + programming tip ? external memory interface the external memory selection pins of p6.0/ dm 0-p7.1/ dm 5 should be set to push-pull output and the latches should be set to logic ?1?. 1. to read data form external memory when dm 0 and dm 1 are used to control cs pins external memories respectively. bits emb ; initial part smb 15 ld ea, #03h ld pmg2,ea ; dm 0 and dm 1 ? output ld ea, #03h ld p6,ea ; dm 0(p6.0) and dm 1 (p6.1) latches ? "1" ld ea,#00010000b ; read mode, increase address automatically, ; select dm0 , f m = fxx/8 ld emcon,ea : ; need set-up time : : bits emb smb 15 ld ea,#00h ld emar0,ea ld emar1,ea ld a,#4h ld emar2,a ; external memory address ? 40000h ld ea,#00010001b ld emcon,ea ; start a memory reading ; delay ld ea,emcon and a,#0001b decs a jps delay next ld ea,emdr0 ; data smb 0 ld adatr_b,ea [s3c72q5] sram (1) a0-a18 d0-d7 dw dr dm0 ( a ctive) dm1 (2) s3c72q5/p72q5 external memory interface 13- 5 + + programming tip ? external memory interface (continued) 2. to write data to external memory when dm 0 and dm 1 are used to control cs pins of external memory, respectively. bits emb ; initial part smb 15 ld ea, #03h ld pmg2,ea ; dm 0 and dm 1 ? output ld ea, #03h ld p6,ea ; dm 0(p6.0) and dm 1 (p6.1) latches ? ?1? ld ea,#10010010b ; write mode, increase address automatically, ; select dm1 , fm = fxx/8 ld emcon,ea : ; need set-up time : : bits emb smb 15 ld ea,#00h ld emar0,ea ld emar1,ea ld a,#4h ld emar2,a ; external memory address 40000h ld ea,#38h ld emdr0,ea ; data ld ea,#10010011b ld emcon,ea ; write mode, increase address automatically, ; select dm1 , f m = fxx/8 ; delay ld ea,emcon and a,#0001b decs a jps delay next smb 0 ld ea,adatr_b smb 15 ld emdr0,e a ; data [s3c72q5] sram (0) a0-a18 d0-d7 dw dr dm0 dm1 ( a ctive) (1) external memory interface s3c72q5/p72q5 13- 6 external memory write cycle timing diagram seg16/d0-seg23/d7 seg24/a0-seg42/a18 memory access clock: f m seg43/ dr d0-d7, a0-a18 seg signal seg signal seg signal seg signal seg signal seg signal emcon.0 "1" seg44/ dw dm 2/f m figure 13-1. external memory write cycle timing diagram external memory read cycle timing diagram seg16/d0-seg23/d7 seg24/a0-seg42/a18 memory access clock: f m seg43/ dr d0-d7, a0-a18 seg signal seg signal seg signal seg signal seg44/ dw dm 2/f m seg signal seg signal figure 13-2. external memory read cycle timing diagram s3c72q5/p72q5 external memory interface 13- 7 s3c72q5x sram0 (4 m bit) a0-a18 d0-d7 dw dr dm0 dm1 1 dm2 dm3 dm4 dm5 a0-a18 d0-d7 de we cs cs 2 cs 3 cs 4 cs 5 cs lcd pannel figure 13-3. external interface fuction diagram (s3c72q5, sram, eprom, eeprom) external memory interface s3c72q5/p72q5 13- 8 notes s3c72q5/p72q5 electrical data 14- 1 1 4 electrical data overview in this section, information on s3c72q5 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abso lute maximum ratings ? d.c electrical characteristics ? main-system clock oscillator characteristics ? sub-system clock oscillator characteristics ? i/o capacitance ? a.c electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl0 timing ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data retention supply volt age in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request electrical data s3c72q5/p72q5 14- 2 table 14- 1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? - 0.3 to + 6.5 v input voltage v i ports 0, 1, 4 - 7 - 0.3 to v dd + 0.3 v output voltage v o ? - 0.3 to v dd + 0.3 v output current high i oh one i/o pin active - 15 ma all i/o pins active - 30 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) total for ports 0, 1, 4 - 7, 8 + 100 (peak value) + 60 (note) operating temperature t a ? - 40 to + 85 c storage temperature t stg ? - 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 14 -2. d.c characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v ih1 ports 0, 1, 4 - 7 and d0 - d7 0.8v dd ? v dd v voltage v ih2 reset 0.7v dd v dd v ih3 x in , x out , and xt in v dd - 0.1 v dd input low v il1 ports 0, 1, 4 - 7 and d0 - d7 ? 0.2v dd voltage v il2 reset 0.3v dd v il3 x in , x out , and xt in 0.1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = - 1 ma ports 0,1,4-7,memory access pins v dd - 1.0 ? output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 0,1,4-7,memory access pins ? 2.0 v dd = 1.8 v to 5.5 v i ol = 1.6 ma 0.4 s3c72q5/p72q5 electrical data 14- 3 table 14 -2. d.c characteristics (continued) (t a = - 40 c to + 85c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih 2 ? ? 3 m a i lih2 v i = v dd x in , x out , xt in 20 input low leakage current i lil1 v i = 0 v all input pins except reset , x in , x out , and xt in - 3 i lil2 v i = 0 v x in , x out , xt in - 20 output high leakage current i loh v o = v dd all output pins 3 output low leakage current i lol v o = 0 v all output pins - 3 pull-up resistor r l1 v i = 0 v; v dd = 5v ports 0, 1, 4 - 7 25 50 75 k w v dd = 3v 50 100 150 r l2 v i = 0 v; v dd = 5v; reset 100 200 300 v dd = 3v 250 500 750 lcd voltage dividing resistor r lcd1 t a = + 25 c when lmod.1 = "0" 46 66 86 r lcd2 t a = + 25 c when lmod.1 = "1" 23 33 43 ? v lc1 - com i ? voltage drop ( i = 0-11) v dc - 15 m a per common pin ? ? 120 mv ? v lc1 - segx ? voltage drop (x = 0-59) v ds - 15 m a per common pin ? ? 120 middle output v lc2 v dd = 2.4v to 5.5v, 1/4 bias 0.75v dd - 0.2 0.75v dd 0.75v dd + 0.2 v voltage (1) v lc3 lcd clock = 0hz 0.5v dd - 0.2 0.5v dd 0.5v dd + 0.2 v lc4 0.25v dd - 0.2 0.25v dd 0.25v dd + 0.2 notes: 1. it is middle output voltage when lcd controller/driver is 1/12 duty and 1/4 bias. 2. low leakage current is absolute value. electrical data s3c72q5/p72q5 14 ? 4 table 14 -2. d.c characteristics (continued) (t a = ? 40 c to + 85c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) v dd = 5 v 10% crystal oscillator c1 = c2 = 22pf 6 mhz 4.19 mhz ? 4.5 3.2 8.0 5.5 ma v dd = 3 v 10% 6 mhz 4.19 mhz 2.0 1.5 4.0 3.0 i dd2 (2) idle mode v dd = 5 v 10% crystal oscillator c1 = c2 = 22pf 6 mhz 4.19 mhz 1.3 1.0 2.5 1.8 v dd = 3 v 10% 6 mhz 4.19 mhz 0.5 0.4 1.5 1.0 i dd3 (3) v dd = 3 v 10% 32 khz crystal oscillator 20 35 m a i dd4 (3) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 5.0 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents. 2. data includes power consumption for subsystem clock oscillation. 3. when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b". s3c72q5/p72q5 electrical data 14- 5 table 14- 3 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillation frequency( fx) (1) ? 0.4 ? 6 mhz oscillator x in c1 c2 x out stabilization time (2) after v dd reaches the minimum level of its variable range; v dd = 2.0 v to 5.5 v ? ? 4 ms crystal oscillation frequency( fx) (1) ? 0.4 ? 6 mhz oscillator x in c1 c2 x out stabilization time (2) v dd = 4.5 v to 5.5 v ? ? 10 ms v dd = 2.0 v to 5.5 v ? ? 30 external x in input frequency( fx) (1) ? 0.4 ? 6 mhz clock x in x out x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency v dd = 5 v 0.4 ? 2 mhz v dd = 3 v 0.4 ? 1 notes: 1. oscillation frequency and input frequency data are for oscill ator characteristics only. 2. stabilization time is the interval required for oscillator stabilization after a power-on or release of stop mode. electrical data s3c72q5/p72q5 14 ? 6 table 14-4 . recommended oscillator constants (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) manufacturer series number (1) frequency range load cap ( pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz-6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz-6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz-6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. s3c72q5/p72q5 electrical data 14- 7 table 14-5 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillation frequency (1) ? 32 32.768 35 khz oscillator xt in c1 c2 xt out stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 2.0 v to 5.5 v ? ? 10 external xt in input frequency (1) ? 32 ? 100 khz clock xt in xt out xt in input high and low level width (t xtl , t xth ) 5 ? 15 us notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs or release of sub c lock stop table 14-6. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out i/o capacitance c io electrical data s3c72q5/p72q5 14 ? 8 table 14-7 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 us v dd = 1.8 v to 5.5 v 1.33 64 with subsystem clock ( fxt) 114 122 125 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 khz tcl0 input high, t tih v dd = 2.7 v to 5.5 v 0.48 ? ? us low width t til v dd = 1.8 v to 5.5 v 1.8 interrupt input high, low width f inth , f intl int0, int1, ks0 - ks7 10 k0 - k6 reset input low width t rsl input 10 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source. s3c72q5/p72q5 electrical data 14- 9 1.5 mhz cpu clock 0.75 mhz 15.625 khz main oscillator frequency 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v figure 14- 1. standard operating voltage range table 14-8 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 ua release signal set time t srel ? 0 ? ? us oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes: 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time. electrical data s3c72q5/p72q5 14 ? 10 timing waveforms execution of stop instruction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 14- 2. stop mode release timing when initiated by reset reset execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 14- 3. stop mode release timing when initiated by interrupt request s3c72q5/p72q5 electrical data 14- 11 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14- 4. a.c. timing measurement points (except for x in and xt in ) int0, 1 intp0 (k0-k6) ks0 to ks2 t inth t intl 0.8 v dd 0.2 v dd figure 14-5 . input timing for external interrupts and quasi-interrupts electrical data s3c72q5/p72q5 14 ? 12 x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14-6 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 14-7. clock timing measurement at x t in s3c72q5/p72q5 electrical data 14- 13 tcl0 t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 14-6 . tcl0 timing reset t rsl 0.3 v dd figure 14-7 . input timing for reset reset signal electrical data s3c72q5/p72q5 14 ? 14 notes s3c72q5/p72q5 mechanical data 1 5- 1 15 mechanical data overview the s3c72q5 microcontroller is currently available in a 100-pin qfp package. note : dimensions are in millimeters. 100-qfp-1420c #100 #1 20.00 0.2 14.00 0.2 17.90 0.3 23.90 0.3 0.10 max 0.65 (0.83) 0.10 max (0.58) 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.15 +0.10 -0.05 0-8 0.3 0.1 0.80 0.20 figure 15-1. 100-qfp -1420 package dimensions mechanical data s3c72q5/p72q5 1 5- 2 notes s3c72q5/p72q5 S3P72Q5 otp 16- 1 16 S3P72Q5 otp overview the S3P72Q5 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c72q5 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P72Q5 is fully compatible with the s3c72q5, both in function and in pin configuration. because of its simple programming requirements, the S3P72Q5 is ideal for use as an evaluation chip for the s3c72q5. S3P72Q5 otp s3c72q5/p72q5 16- 2 seg39/a15 seg40/a16 seg41/a17 seg42/a18 seg43/ dr seg44/ dw seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg38/a14 seg37/a13 seg36/a12 seg35/a11 seg34/a10 seg33/a9 seg32/a8 seg31/a7 seg30/a6 seg29/a5 seg28/a4 seg27/a3 seg26/a2 seg25/a1 seg24/a0 seg23/d7 seg22/d6 seg21/d5 seg20/d4 seg19/d3 seg18/d2 seg17/d1 seg16/d0 seg15/p8.15 seg14/p8.14 seg13/p8.13 seg12/p8.12 seg11/p8.11 seg10/p8.10 seg9/p8.9 seg59 com4 com5 com6 com7 com8 p7.3/ks7/com9 p7.2/ks6/com10 p7.1/ks5/ dm 5/com11 p7.0/ks4/ dm 4 p6.3/ks3/ dm 3 p6.2/ks2/ dm 2 sdat /p6.1/ks1/ dm 1 sclk /p6.0/ks0/ dm 0 v dd v ss x out x in v pp /test xt in xt out reset p5.0 p5.1 p5.2/buz p5.3/clo p4.0/tcl0 p4.1/tclo0 p4.2/int0 p4.3/int1 S3P72Q5 (100-qfp-1420c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 seg8/p8.8 seg7/p8.7 seg6/p8.6 seg5/p8.5 seg4/p8.4 seg3/p8.3 seg2/p8.2 seg1/p8.1 seg0/p8.0 com3 com2 com1 com0 p0.0/k0 p0.1/k1 p0.2/k2 p0.3/k3 p1.0/k4 p1.1/k5 p1.2/k6 figure 16-1. S3P72Q5 pin assignments (100-qfp package) s3c72q5/p72q5 S3P72Q5 otp 16- 3 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.1 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p3.0 sclk 14 i/o serial clock pin. input only pin. test v pp (test) 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 22 i chip initialization v dd / v ss v dd / v ss 15/16 i logic power supply pin. v dd should be tied to +5 v during programming. table 16-2. comparison of S3P72Q5 and s3c72q5 features characteristic S3P72Q5 s3c72q5 program memory 16 kbyte eprom 16 kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P72Q5, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level. S3P72Q5 otp s3c72q5/p72q5 16- 4 table 16 - 4. d.c characteristics (t a = ? 40 c to + 85c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (2) v dd = 5 v 10% crystal oscillator c1 = c2 = 22pf 6 mhz 4.19 mhz ? 4.5 3.2 8.0 5.5 ma v dd = 3 v 10% 6 mhz 4.19 mhz 2.0 1.5 4.0 3.0 i dd2 (2) idle mode v dd = 5 v 10% crystal oscillator c1 = c2 = 22pf 6 mhz 4.19 mhz 1.3 1.0 2.5 1.8 v dd = 3 v 10% 6 mhz 4.19 mhz 0.5 0.4 1.5 1.0 i dd3 (3) v dd = 3 v 10% 32 khz crystal oscillator 20 35 m a i dd4 (3) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 5.0 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents. 2. data includes power consumption for subsystem clock oscillation. 3. when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this tabl e is measured when the power control register (pcon) is set to "0011b". s3c72q5/p72q5 S3P72Q5 otp 16- 5 1.5 mhz cpu clock 0.75 mhz 15.625 khz main oscillator frequency 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v 400 khz figure 16-2. standard operating voltage range S3P72Q5 otp s3c72q5/p72q5 16- 6 notes s3c72q5/p72q5 development tools 17- 1 17 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c9, s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is an relocatable assembler for samsung's s3c7 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area upto the maximum rom size of the target device automatically. target boards target boards are available for all s3c7 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the s3c72q5 microcontroller and otp programmer (gang) are now available. development tools s3c72q5/p72q5 17- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam4 base unit power supply unit ibm-pc at or compatible tb72q5 target board eva chip target application system figure 17-1. smds product configuration (smds2+) s3c72q5/p72q5 development tools 17- 3 tb72q5 target board the tb72q5 target board is used for the s3c72q5 microcontroller. it is supported by the smds2+ development system. tb72q5 sm1271a + idle 100-pin connector 25 1 reset to user_v cc off on j102 52 51 99 100 160 qfp s3e7200 eva chip mds xti xtal external triggers ch1 ch2 74hc11 u2 + stop 50-pin connector 50-pin connector 2 1 mds xi xtal 49 50 j101 figure 17-2. tb72q5 target board configuration development tools s3c72q5/p72q5 17- 4 table 17-1. power selection settings for tb72q5 'to user_vcc' settings operating mode comments to user_v cc off on target system smds2/smds2+ tb72q5 v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2+ tb72q5 external v cc v ss v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. table 17-2. main-clock selection settings for tb72q5 sub clock setting operating mode comments xi mds xtal no connection smds2/smds2+ 100 pin connector eva chip s3e72q0 x in x out set the xi switch to ?mds? when the target board is connected to the smds2/smds2+. xi mds xtal target board eva chip s3e72q0 x in x out xtal set the xi switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+. s3c72q5/p72q5 development tools 17- 5 table 17-3. sub-clock selection settings for tb72q5 sub clock setting operating mode comments xtal mds xti no connection smds2/smds2+ 100 pin connector eva chip s3e72q0 xt in xt out set the xti switch to ?mds? when the target board is connected to the smds2/smds2+. xti mds xtal target board eva chip s3e72q0 xt in xt out xtal set the xti switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+. idle led this led is on when the evaluation chip (s3e72q0) is in idle mode. stop led this led is on when the evaluation chip (s3e72q0) is in stop mode. development tools s3c72q5/p72q5 17- 6 j102 seg9/p8.9 seg11/p8.11 seg13/p8.13 seg15/p8.15 seg17/d1 seg19/d3 seg21/d5 seg23/d7 seg25/a1 seg27/a3 seg29/a5 seg31/a7 seg33/a9 seg35/a11 seg37/a13 seg39/a15 seg41/a17 seg43/ dr seg45 seg47 seg49 seg51 seg53 seg55 seg57 seg10/p8.10 seg12/p8.12 seg14/p8.14 seg16/d0 seg18/d2 seg20/d4 seg22/d6 seg24/a0 seg26/a2 seg28/a4 seg30/a6 seg32/a8 seg34/a10 seg36/a12 seg38/a14 seg40/a16 seg42/a18 seg44/ dw seg46 seg48 seg50 seg52 seg54 seg56 seg58 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 50-pin dip connector j101 seg59 com5 com7 p7.3/ks7/com9 p7.1/ks5/ dm 5/com11 p6.3/ks3/ dm3 p6.1/ks1/ dm1 v dd x out test xt out p5.0 p5.2/buz p4.0/tcl0 p4.2/int0 p1.2/k6 p1.0/k4 p0.2/k2 p0.0/k0 com1 com3 seg1/p8.1 seg3/p8.3 seg5/p8.5 seg7/p8.7 com4 com6 com8 p7.2/ks6/com10 p7.0/ks4/ dm 4 p6.2/ks2/ dm2 p6.0/ks0/ dm0 v ss x in xt in reset p5.1 p5.3/clo p4.1/tclo0 p4.3/int1 p1.1/k5 p0.3/k3 p0.1/k1 com0 com2 seg0/p8.0 seg2/p8.2 seg4/p8.4 seg6/p8.5 seg8/p8.8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 50-pin dip connector figure 17-3. 5 0-pin connector s for tb72q5 target board 50-pin dip connector target system 50-pin dip connector j102 51 52 99 100 j101 1 2 49 50 target cable for 50-pin connector part name: (as50d-a) order cods: sm6305 j102 51 52 99 100 j101 1 2 49 50 figure 17-4. tb72q5 adapter cable for 100-qfp package ( s3c72q5/p72q5 ) (for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3c7 series mask rom order form product description: device number: s3c7__________- ___________(write down the rom code number) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: + + for what kind of product will you be using this order? new product upgrade of an existing product replacement of an existing product other if you are replacing an existing product, please indicate the former product name ( ) + + what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager) (for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3c7 series request for production at customer risk customer information: company name: __________________________ ______________________________________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: s3c7________- ________ (write down the rom code number) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: __ ______________________________________________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: _______________________________ _________________________________ _____ _ (person placing the risk order) (sec sales representative) s3c72q5 mask option selection form device number: s3c72q5-_________ (write down the rom code number) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: ______________________________________ __________________________ signature (engineer): ________________________________________________________________ please answer the following questions: + + application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office a utomation remocon other please describe in detail its application ___________________________________________________________________________ s3c7 series otp factory writing order form (1/2) product d escription: device number: s3p ________-________(write down the rom code number) product order form: package pellet w afer if the product order form is package: package type: _____________________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantity: rom code release date required delivery date of device quantity please answer the following questions: + + what is the purpose of this order ? new product development upgrade of an existing product replacement of an existing microcontroller other if you are replacing an existing microcontroller , please indicate the former microcontroller name ( ) + + what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager) (for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) S3P72Q5 otp factory writing order form (2/2) device number: s3p ___-__________ (write down the rom code number) customer checksums: _________ ____________________________ _________________________ _ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ read protection (1) : yes no please answer the following questions: + + are you going to continue ordering this device? yes no if so, how much will you be ordering? _________________pcs + + application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office a utomation remocon other please describe in detail its application ___________________________________________________________________________ notes 1. once you choose a read protection, you cannot read again the programming code from the eprom. 2. flash mcu writing will be executed in our manufacturing site. 3. the writing program is completely verified by a customer. samsung does not take on any responsibility for errors occurred from the writing program. |
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