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is25lp 256 2 56 mbit 3v serial flash memory with 1 66 mhz multi i/o spi & dtr interface advanced data sheet advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 2 rev.00a 1/ 16 /2014 features ? industry standard serial interface - is25lp 25 6: 256mbit/32mbyte - 3 or 4 byte addressing m ode - supports standard spi, fast, dual, dual i/o, quad, quad i/o, spi dtr, dual i/o dtr, quad i/o dtr, and qpi - software & hardware reset - supports serial flash discoverable parameters (sfdp) ? high performance serial flash (spi) - 80mhz normal read - up to166mhz fast read - up to 80mhz dtr (dual transfer rate) - equivalent throughput of 664 mb /s - selectable dummy cycles - configurable drive strength - supports spi modes 0 and 3 - more than 100,000 erase/program cycles - more than 20-year data retention ? flexible & efficient memory architecture - chip erase with uniform: sector/bloc k erase (4/32/64 kbyte) - program 1 to 256 byte per page - program/erase sus pend & resume ? efficient read and program modes - low instruction overhead operations - continuous read 8/16/32/64 byte burst - selectable burst length - qpi for reduc ed instruction overhead - autoboot operation ? low power with wide temp. ranges - single 2.30v to 3.60v voltage supply - 10 ma active read current - 8 a standby current - 1 a deep power down - temp grades: extended: -40c to +105c extended+ : -40c to +125c auto grade: up to +125c note: extended+ should not be used for automotive ? advanced security protection - software and hardware write protection - advanced sector protection - top/bottom block protection and complement - individual block/sector unlock - power supply lock protection - 4x256 byte dedicated security area with user-lockable bits, (otp) one time programmable memory - 128 bit unique id for each device (call factory) ? industry standard pin-out & packages - m = 16 -pin soic 300mil - l = 8-contact wson 8x6 mm - g = 24-ball tfbga 6x8mm (4x6 ball array) - kgd (call factory) 2 56 mbit 3v s erial flash memory w ith 166 mhz multi i/o spi & dtr interface advanced information advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 3 rev.00a 1/ 16 /2014 general description the IS25LP256 serial flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. issis indus try stan dard serial interface f lash is for systems that require limited space, a low pin count, and low power consumption. the device is accessed through a 4-wire spi interface consisting of a serial data input ( si ), serial data output (so), serial clock (sck), and chip enable (ce#) pins, which can also be configured to serve as multi-i/o (see pin descriptions). the device supports dual and quad i/o as well as standard , dual output, and quad output spi. clock frequencies of up to 1 66 mhz allow for equivalent clock rates of up to 664mhz (1 66 mhz x 4) which equates to over 80mbytes/data th roughput. the is25xp series of flash adds support for dtr (double transfer rate) commands that transfer address es and read data on both edges of the clock. these transfer rates can out perform 16-bit parallel flash memories allowing for efficient memory access to support xip (execute in place) operation. the memory array is organized into programmable pages of 256 bytes. this family supports page program mode where 1 to 256 bytes of data are programmed in a single command. qpi (quad peripheral interface) supports 2-cycle instruction further reducing instruction times. pages can be erased in groups of 4kbyte sectors, 32kbyte blocks, 64kbyte blocks, and/ or the entire chip. the uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention. glossary standard spi in this operation, a 4-wire spi interface is utilized, consisting of serial data input ( si ), serial data output (so), serial clock (sck), and chip enable (ce#) pins. instructions are sent via the si pin to encode instructions, addresses, or input data to the device. the so pin is used to read data or to check the status of the device. this device supports spi bus operation modes (0,0) and (1,1). mutil i/o spi multi-i/o operation utilizes an enhanced spi protocol to allow the device to function with dual output, dual in put and output, quad output, and quad input and output capability. executing these instructions through spi mode will achieve double or quadruple the transfer bandwidth for read and program operations. quad i/o q pi the device enables qpi protocol by is suing an enter qpi mode (35h) command. the qpi mode uses four io pins for input and output to decrease spi instruction overhead and increase output bandwidth. si and so pins become bidirectional io0 and io1, and wp# and hold# pins become io2 and io3 respectively during qpi mode. issuing an exit qpi (f5h) command will cause the device to exit qpi mode. power reset or hardware/software reset can also return the device into the standard spi mode. dtr in addition to spi and qpi features, the device also supports spi dtr read. spi dtr allows high data throughput while running at lower clock frequencies. spi dtr read mode uses both rising and falling edges of the clock to drive output , resulting in reducing the input and output cycles by half. programmable drive strength and selectable burst setting. the IS25LP256 offers programmable output drive strength and selectable burst (wrap) length features to increase the efficiency and performance of read operation. the driver strength and burst setting features are controlled by setting the read registers. a total of six different drive strengths and four different burst sizes (8/16/32/64 byte) are available for selection. advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 4 rev.00a 1/ 16 /2014 pin configuration notes: 1. according to the p7 bit setting in read register, either hold# (p7=0) or reset# (p7=1) pin can be selected. 2. for the dedicated parts that dont have the additional reset# pin on pin3, either hold# or reset# pin can be selected on pin1 by the p7 bit setting in read register when qe=0. for the dedicated parts with additional reset# pin on pin3, onl y hold# pin is selected for pin1 regardless of the p7 bit of read register when qe=0. 3. the dedicated parts have additional reset# pin (pin3) on 16-pin soic 300mil package. for the parts, function register bit0 (reset# enable/disable) will be set to 0. the reset# pin is independent of the p7 bit of read register and qe bit of status register. the reset# pin has an internal pull-up resistor and may be left floating if not used. call factory for the reset# pin option. 12 10 11 9 13 15 14 5 7 6 8 4 2 3 1 6 1 vcc hold# (io3) hold# or reset# (io3) sck ce# wp# (io2) gnd nc nc nc nc nc si (io0) s o (io 1 ) nc nc reset#/nc 16 - pin soic 300mil (1) (1) ( 3 ) (2 ) advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 5 rev.00a 1/ 16 /2014 notes: 1. for the dedicated parts that dont have the additional reset# pin on ball a3, either hold# (p7=0) or reset# (p7=1) pin can be selected on ball d4 by the p7 bit setting in read register when qe=0. for the dedicated parts with additional reset# pin on ball a3 , only hold# pin is selected for ball d4 regardless of the p7 bit of read register when qe=0. 2. the dedicated parts have additional reset# pin (ball a3) on 24 -ball tfbga 6x8mm package. for the parts, function regist er bit0 (reset# enable/disable) will be set to 0. the reset# pin is independent of the p7 bit of read register and qe bit of status register. the reset# pin has an internal pull-up resistor and may be left floating if not used. call factory for the reset# pin option. 24 - ball tfbga 6x8mm ( 2 ) ( 1 ) ( 1 ) ( 2 ) top view , balls facing down 4x 6 ball array nc nc nc nc f1 f2 f3 f4 nc reset# nc nc sck gnd vcc nc ce # nc wp #( io 2) nc so ( io 1) si ( io 0) hold # or reset # ( io 3 ) nc nc nc nc nc a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 e1 e2 e3 e4 a1 nc nc reset# nc sck gnd vcc nc ce # nc wp #( io 2) nc so ( io 1) si ( io 0) hold # or reset # ( io 3 ) nc nc nc nc nc nc nc nc top view , balls facing down nc 5x 5 ball array a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 e1 e2 e3 e4 a5 b5 c5 d5 e5 advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 6 rev.00a 1/ 16 /2014 pin descriptions for all other packages except 16-pin soic 300mil with additional reset# pin option symbol type description ce# input chip enable: the chip enable (ce#) pin enables and disables the devices operation. when ce# is high the d evice is deselected and output pins are in a high impedance state. when deselected the devices non - critical internal circuitry power down to allow minimal levels of power consumption while in a standby state. when ce# is pulled low the device will be selec ted and brought out of standby mode. the device is considered active and instructions can be written to, data read, and written to the device. after power - up, ce# must transition from high to low before a new instruction will be accepted. keeping ce# in a high state deselects the device and switches it into its low power state. data will not be accepted when ce# is high. si (io0), so (io1) input/output serial data input, serial output, and ios (si, so, io0, and io1): this device supports standard spi, dual spi, and quad spi operation. standard spi instructions use the unidirectional si (serial input) pin to write instructions, addresses, or data to the device on the rising edge of the serial clock (sck). standard spi also uses the unidirectional so (serial output) to read data or status from the device on the falling edge of the serial clock (sck). in dual and quad spi mode, si and so become bidirectional io pins to write instructions, addresses or data to the device on the rising edge of the serial clock (s ck) and read data or status from the device on the falling edge of sck. quad spi instructions use the wp# and hold# pins as io2 and io3 respectively. wp# (io 2 ) input/output write protect/serial data io (io2): the wp# pin protects the status register from being written in conjunction with the srwd bit . when the srwd is set to 1 and the wp# is pulled low , the s tatus r egister bit s (srwd, qe, bp3, bp2, bp1, bp0) are write - protected and vice - versa for wp# high. when the srwd is set to 0, the status register is not w rite - protected regardless of wp # state. when the qe bit is set to 1, the wp# pin (write protect) function is not available since this pin is used for io2. hold# or reset# (io 3 ) input/output hold# or reset#/serial data io (io3): when the qe bit of status register is set to 1, hold# pin or reset# is not available since it becomes io3. when qe=0, the pin acts as hold# or reset# and either one can be selected by the p7 bit setting in read register. hold# will be selected if p7=0 (default) and rese t# will be selected if p7=1 . the hold# pin allows the device to be paused while it is selected. it p auses serial communication by the master device without resetting the serial sequence. the hold# pin is active low. when hold# is in a low state and ce# is low, the so pin will be at high impedance. device operation can resume when hold# pin is brought to a high state. reset# pin is a hardware reset signal. when reset# is driven high, the memory is in the normal operating mode. when reset# is driven low, the memory enters reset mode and output is high - z. if reset# is driven low while an internal write, program, or erase operation is in progress, data may be lost. sck input serial data clock: synchronized clock for input and output timing operations. vcc powe r power: device core power supply gnd ground ground: connect to ground when referenced to vcc nc unused nc: pins labeled nc stand for no connect and should be left unconnected. advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 7 rev.00a 1/ 16 /2014 for 16-pin soic 300mil package with additional reset# pin option - reset# pin will be added to another pin without sharing with hold# pin (call factory for the parts) symbol type description ce# input same as the description in previous page si (io0), so (io1) input/output same as the description in previous page wp# (io 2 ) input/output same as the description in previous page hold# (io 3 ) input/output hold#/serial data io (io3): when the qe bit of status register is set to 1, hold# pin is not available since it becomes io3. when qe=0 the pin acts as hold# regardless of th e p7 bit of r ead register. the hold# pin allows the device to be paused while it is selected. it p auses serial communication by the master device without resetting the serial sequence. the hold# pin is active low. when hold# is in a low state and ce# is lo w, the so pin will be at high impedance. device operation can resume when hold# pin is brought to a high state. reset# input/output reset: this pin is available only for d edicated parts (call factory). the reset# pin is a hardware reset signal. when reset # is driven high, the memory is in the normal operating mode. when reset# is driven low, the memory enters reset mode and output is high - z. if reset# is driven low while an internal write, program, or erase operation is in progress, data may be lost. sck input same as the description in previous page vcc power same as the description in previous page gnd ground same as the description in previous page nc unused same as the description in previous page advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 8 rev.00a 1/ 16 /2014 block diagram note1: in case of 16-pin soic package, reset# pin will be added to another pin without sharing with hold# pin for the dedicated parts. call factory for the additional reset# pin option. wp# (io 2 ) (1) control logic high voltage generator i/o buffers and data latches 256 bytes page buffer y-decoder x-decoder serial peripheral interface status register address latch & counter memory array ce # sck wp # ( io 2) si ( io 0) so (io 1) hold# or reset# ( io 3) advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 9 rev.00a 1/ 16 /2014 spi modes description multiple IS25LP256 devices can be connected on the spi serial bus and controlled by a spi master, i.e. microcontroller, as shown in figure 4.1 . the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity. when the spi master is in stand-by mode, the serial clock remains at 0 (sck = 0) for mode 0 and the clock remains at 1 (sck = 1) for mode 3. please refer to figure 4 .2 and figure 4 .3 for spi and qpi mode. in both modes, the input data is latched on the rising edge of serial clock (sck), and the output data is available from the falling edge of sck. figure 4.1 connection diagram among spi master and spi slaves (memory devices) note s: 1. in case of 16-pin soic package, reset# pin will be added to another pin without sharing with hold# pin for th e dedicated parts. call factory for the additional reset# pin option. 2. si and so pins become bidirectional io0 and io1, and wp# and hold# pins become io2 and io3 respectively during qpi mode. ( 1) (1) (1) spi interface with (0,0 ) or (1,1) spi master (i.e . microcontroller) spi memory device spi memory device spi memory device sck so si sck sdi sdo ce # wp # hold# or reset sck so si ce # wp # hold# or reset# sck so si ce # wp # cs 3 cs 2 cs 1 hold# or reset# advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 10 rev.00a 1/ 16 /2014 block/sector address es table block/sector addresses of IS25LP256 memory density block no. (64kb yte) block no. (32kb yte) sector no. sector size (kb yte) address range 256 mbit block 0 block 0 sector 0 4 000000h - 000fffh : : : block 1 : : : sector 15 4 00f000h - 00ffffh block 1 block 2 sector 16 4 010000h - 010fffh : : : block 3 : : : sector 31 4 01f000h - 01ff ffh block 2 block 4 sector 32 4 020000h - 020fffh : : : block 5 : : : sector 47 4 02f000h - 02ffffh : : : : : block 254 block 508 sector 4064 4 fe 0000h C fe 0fffh : : : block 509 : : : sector 4079 4 fe f000h C fe ffffh block 255 block 510 sector 4080 4 f f 0 000h C ff0 fffh : : : block 511 : : : sector 4095 4 f ff 000h C ff ffffh : : : : : block 510 block 1 0 2 0 sector 8160 4 1 fe 0000h C 1 fe 0fffh : : : block 1021 : : : sector 8175 4 1 fe f000h C 1 fe ffffh block 511 block 1022 sector 8176 4 1 f f 0 000h C 1 ff0 fffh : : : block 1023 : : : sector 8191 4 1 f ff 000h C 1 ff ffffh advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 11 rev.00a 1/ 16 /2014 package type information 8-contact ultra-thin small outline no-lead (wson) package 8x6mm (jl) . note: all dimensions are in millimeters. s y m b o l d i m e n s io n in m m m i n. n o m m a x a 0 . 70 0 . 7 5 0 .80 a 1 0.00 0. 0 2 0.05 a 2 - - - 0 . 2 0 - - - d 7 . 90 8 . 0 0 8 . 10 e 5 . 90 6 . 0 0 6 . 10 d1 4.65 4. 7 0 4.75 e1 4.55 4. 6 0 4.65 e - - - 1 . 2 7 - - - b 0 . 35 0 . 4 0 0 . 48 l 0.4 0. 5 0 0.60 advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 12 rev.00a 1/ 16 /2014 16 -lead plastic small outline package (300 mils body width) (jm) note: all dimensions are in millimeters. 1.27 0.51 0.33 2.4 2.25 2.35 2.65 0.1 8 0 0 0 1.27 0.4 detail a detail a 0.23 millimeters 1 8 9 16 10.5 10.1 7.4 7.6 10.0 10.65 0.32 0.1 0.3 advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 13 rev.00a 1/ 16 /2014 24 -ball thin profile fine pitch bga 6x8mm 4x6 ball array (jg) symbol dimensions (mm) min nom max a - - 1.20 a1 0 .27 - 0.37 a2 0.21 ref a3 0.54 ref d 6 bsc e 8 bsc d1 - 3.00 - e1 - 5.00 - e - 1.00 - b - 0.40 - note: all dimensions are in millimeters. (top view) ( bottom view) a1 corner index area a1 corner index area d e 4 3 2 1 a b c d e f e1 e d1 a a3 a2 a1 e nx ?b advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 14 rev.00a 1/ 16 /2014 ordering information- valid part numbers IS25LP256 - j m l e temperature range e = extended (- 40 c to +105 c) e1 = extended+ (- 40 c to +125 c) a1 = automotive grade (- 40 c to +85 c) a2 = automotive grade (- 40 c to +105 c) a3 = automotive grade (- 40 c to +125 c) packaging content l = rohs compliant package type (1) l = 8-contact wson (8x6mm) m = 16-pin soic 300mil g = 24 -ball tfbga (6x8mm) 4x6 ball array w = kgd (call factory) options j = standard r = additional reset# pin option for 16-pin soic 300mil die revision blank = first revision density 256 = 256 megabit base part number ic = integrated silicon solution inc. 25lp = flash, 2.30 v ~ 3.60v , qpi note: 1. for the additional reset# pin option, call factory advanced information
IS25LP256 integrated silicon solution, inc.- www.issi.com 15 rev.00a 1/ 16 /2014 notes: 1. a*= a1, a2, a3: meets aec-q100 requirements with ppap, e1= extended+ non-auto qualified temp grades: e= -40 to 105 c, e1 = -40 to 125 c, a1= -40 to 85 c, a2= -40 to 105 c, a3= -40 to 125 c 2. the dedicated parts have additional reset# pin on pin3. density frequency (mhz) order part number (1) package 256mb 166 IS25LP256 - j l le IS25LP256 - j l l e1 8 - contact wson ( 8 x 6 mm) IS25LP256 - jmle IS25LP256 - jml e1 16 - pin soic 300mil IS25LP256 - j g le IS25LP256 - j g l e1 24 - ball tfbga (6x8mm) 4x6 ball array is25l p 256 - rmle is25l p 256 - rml e1 16 - pin soic 300mil (2) IS25LP256 - j l la* 8 - contact wson ( 8 x 6 mm) (call factory) is25lp2 56 - jmla* 16 - pin soic 300mil (call factory) IS25LP256 - jgla* 24 - ball tfbga (6x8mm) 4x6 ball array (call factory) is25l p 256 - rmla* 16 - pin soic 300mil (2) (call factory) IS25LP256 - jw le kgd (call factory) advanced information

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