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A48P4616B 16m x 16 bit ddr dram (january, 2014, version 1.0) amic technology, corp. document title 16m x 16 bit ddr dram revision history rev. no. history issue date remark 1.0 initial issue january 9, 2014 final
A48P4616B 16m x 16 bit ddr dram (january, 2014, version 1.0) 1 amic technology, corp. features cas latency and frequency maximum operating frequency (mhz) cas latency ddr400 (5) 2 133 2.5 166 3 200 ? double data rate architecture: two data transfers per clock cycle. ? bidirectional data strobe (dq s ) is transmitted and received with data, to be us ed in capturing data at the receiver. ? dq s is edge-aligned with data for reads and is center- aligned with data for writes. ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation. ? data mask (dm) for write data. ? dll aligns dq and dq s transitions with ck transitions. ? commands entered on each pos itive ck edge; data and data mask referenced to both edges of dq s . ? burst lengths: 2, 4, or 8 ? cas latency: 2/2.5/3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? 8192 refresh cycles / 64ms (4 banks concurrent refresh) ? 2.5v (sstl_2 compatible) i/o ? v dd = v ddq = 2.5v 0.2v ? industrial operating tem perature range: -40oc to +85oc for -u series. ? available lead free packaging ? all pb-free (lead-free) products are rohs compliant general description the 256mb ddr sdram uses a double-data-rate architecture to achieve high- speed operation. the double data rate architecture is essent ially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr sdram effectivel y consists of a single 2n- bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dq s ) is transmitted externally, along with data, for use in data capture at the receiver. dq s is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dq s is edge- aligned with data for reads and center-aligned with data for writes. the 256mb ddr sdram operates from a differential clock (ck and ck; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) ar e registered at every positive edge of ck. input data is regi stered on both edges of dqs, and output data is referenced to both edges of dq s , as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, thereby providing hi gh effective bandwidth by hiding row pre-charge and activation time. an auto refresh mode is provided along with a power-saving power down mode. all inputs are compatible with the jedec standard for sstl_2. a ll outputs are sstl_2, class ii compatible. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation.
A48P4616B (january, 2014, version 1.0) 2 amic technology, corp. pin configuration ? tsop (ii) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq dq 7 nc v ddq ldqs nc v dd nc ldm* we 66 65 64 63 62 64 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ck udm* v ss v ref nc udqs v ssq nc dq 8 v ddq dq 9 dq 10 v ssq dq 11 dq 12 v ddq dq 13 dq 14 v ssq dq 15 A48P4616Bv cas v ss v dd ck 23 24 25 26 27 28 29 30 31 32 33 ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss 44 43 42 41 40 39 38 37 36 35 34 column address table organization row address column address 16mb x16 a0-a12 a0-a8 * dm is internally loaded to match dq and dqs identically
A48P4616B (january, 2014, version 1.0) 3 amic technology, corp. block diagram (16mb x 16) sense amplifiers bank0 memory array (8192 x 256 x 32) bank1 bank2 bank3 column decoder i/o gating dm mask logic 256 (x32) 8192 bank0 row-address latch & decoder 8192 bank control logic column-address counter/latch 8 1 col0 row-address mux refresh counter 13 2 13 command decode mode registers control logic address register 9 15 a0-a12, ba0, ba1 15 2 cke ck ck cs we cas ras read latch write fifo & drivers clk out clk in 32 32 32 mux 16 16 col0 drivers 16 data dll ck, ck dqs generator 1 dqs receivers input register 1 1 16 16 2 32 mask data 1 1 16 16 1 16 ck, ck col0 1 dq0-dq15, ldm, udm ldqs, udqs 13 note: 1. this functional block diagram is intended to facilitat e user understanding of the oper ation of the device; it does not represent an actual circuit implementation. 2. dm is a unidirectional signal (input only), but is inte rnally loaded to match the load of the bidirectional dq and dq s signals.
A48P4616B (january, 2014, version 1.0) 4 amic technology, corp. pin descriptions symbol type description ck, ck input clock: ck and ck are differential clock inputs. a ll address and control input signals are sampled on the crossi ng of the positive edge of ck and negative edge of ck. output (read) data is referenc ed to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and outpu t drivers. taking cke low provides precharge power down and self refresh oper ation (all banks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and writ e accesses. input buffers, excluding ck, ck and cke are disabled during power down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas , we (along with cs ) define the command being entered. udm, ldm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dq s . although dm pins are input only, the dm loading matches the dq and dq s loading. during a read, dm can be driven high, low, or floated. ldm corresponds to the data on dq 0 -dq 7 ; udm corresponds to the data on dq 8 -dq 15 . ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0-a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. dq input / output data input/output: data bus. ldqs, udqs input / output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data. ldqs corresponds to the data on dq 0 -dq 7 ; udqs corresponds to the data on dq 8 -dq 15 nc no connect: no internal electrical connection is present. v ddq supply dq power supply: 2.5v 0.2v. v ssq supply dq ground v dd supply power supply: 2.5v 0.2v. v ss supply ground v ref supply sstl_2 reference voltage: (v ddq / 2) 1%.
A48P4616B (january, 2014, version 1.0) 5 amic technology, corp. functional description the 256mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 268, 435, 456 bits. the 256mb ddr sdram is internally configured as a quad-bank dram. the 256mb ddr sdram uses a double-data-rate architecture to achieve high-speed operation. the double- data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr sdram consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the ba nk; a0-a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. initialization the following relationships must be followed: v ddq is driven after or with v dd such that v ddq < v dd + 0.3v v tt is driven after or with v ddq such that v tt < v ddq + 0.3v v ref is driven after or with v ddq such that v ref < v ddq + 0.3v the dq and dq s outputs are in the high-z state, where they remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke must be brought high. following the nop command, a precharge all command must be applied. next a mode register set command must be issued for the extended mode register, to enable the dll, then a mode register set command must be issued for the mode register, to reset the dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any read command. a precharge all command should be applied, placing the device in the ?all banks idle? state once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i.e. to program operating parameters without resetting the dll) must be performed. following these cycles, the ddr sdram is ready for normal operation. ddr sdram?s may be reinitialized at any time during normal operation by asserting a valid mrs command to either the base or extended mode registers without affecting the contents of the memory array. the contents of either the mode register or extended mode register can be modified at any valid time during device operation without affecting the state of the internal address refresh counters used for device refresh.
A48P4616B (january, 2014, version 1.0) 6 amic technology, corp. register definition mode register the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (sequential or interleaved), a4-a6 specify the cas latency, and a7-a12 specify the operating mode. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements results in unspecified operation. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. mode register operation ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 0* 0* operating mode cas latency bt burst length mode register operating mode cas latency a3 burst type burst length a12-a9 a8 a7 a6-a0 type a6 a5 a4 type 0 sequential a2 a1 a0 type 0 0 0 valid normal operation do not reset dll 0 0 0 reserved 1 interleave 0 0 0 reserved 0 1 0 valid normal operation in dll reset 0 0 1 reserved 0 0 1 2 0 1 0 2 0 1 0 4 0 1 1 3 0 1 1 8 1 0 0 reserved 1 0 0 reserved 1 0 1 reserved 1 0 1 reserved 1 1 0 2.5 1 1 0 reserved 1 1 1 reserved 1 1 1 reserved note: * ba0 and ba1 must be 0, 0 to select the mode register (vs. the extended mode register).
A48P4616B (january, 2014, version 1.0) 7 amic technology, corp. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definition on page 7. read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2, 2.5 or 3 clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. burst definition starting column address order of accesses within a burst burst length a2 a1 a0 type = sequential type = interleaved 0 0-1 0-1 2 1 1-0 1-0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 4 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6- 7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7- 0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0- 1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1- 2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2- 3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3- 4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4- 5 6-7-4-5-2-3-0-1 8 1 1 1 7-0-1-2-3-4-5- 6 7-6-5-4-3-2-1-0 note: 1. for a burst length of two, a1-ai selects the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
A48P4616B (january, 2014, version 1.0) 8 amic technology, corp. operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 to zero, and bits a0- a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9- a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode. all other combinations of values for a7-a12 are reserved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. cas latencies read nop nop nop nop cl=2 ck ck command dqs dq cas latency = 2, bl = 4 shown with nominal t ac , t dqsck and t dqsq : don't care nop read nop nop nop nop cl=3 ck ck command dqs dq cas latency = 3, bl = 4 nop read nop nop nop nop nop cl=2.5 ck ck command dqs dq cas latency = 2.5, bl = 4
A48P4616B (january, 2014, version 1.0) 9 amic technology, corp. extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions include dll enable/disable, bit a0; output drive strength selection, bit a1. these functions are controlled via the bit settings shown in the extended mode register definition. the extended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements result in unspecified operation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a read command can be issued. this is the reason for introducing timing parameter t xsrd for ddr sdram?s (exit self refresh to read command). non- read commands can be issued 2 clocks after the dll is enabled via the emrs command (t mrd ) or 10 clocks after the dll is enabled via self refresh exit command (t xsnr , exit self refresh to non-read command). output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. extended mode register definition ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 0* 1* 0 0 0 0 0 0 0 0 0 0 0 ds dll extended mode register drive strength a0 dll a1 type 0 enable 0 normal 1 disable 1 week note: * ba0 and ba1 must be 1, 0 to select the extended mode register (vs. the base mode register)
A48P4616B (january, 2014, version 1.0) 10 amic technology, corp. commands truth tables 1a and 1b provide a reference of the commands supported by ddr sdram device. a verbal description of each command follows. name (function) cs ras cas we address mne note deselect (nop) h x x x x nop 1, 9 no operation (nop) l h h h x nop 1, 9 active (select bank and activate row) l l h h bank/row act 1, 3 read (select bank and activate column, and start read burst) l h l h bank/col read 1, 4 write (select bank and activate column, and start write burst) l h l l bank/col write 1, 4 burst terminate l h h l x bst 1, 8 precharge (deactivate row in bank or banks) l l h l code pre 1, 5 auto refresh or self refresh (enter self refresh mode) l l l h x ar/sr 1, 6, 7 mode register set l l l l op-code mrs 1, 2 note: 1. cke is high for all commands shown except self refresh. 2. ba0, ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a12 provide the op-code to be written to the selected mode register.) 3. ba0-ba1 provide bank address and a0-a12 provide row address. 4. ba0, ba1 provide bank address; a0-a8 provide column address; a10 high enables the auto precharge feature (non- persistent), a10 low disables the auto precharge feature. 5. a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row and bank addressing; all inputs and i/os are ?don?t care? except for cke. 8. applies only to read bursts with auto precharge disabled; th is command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts 9. deselect and nop are functionally interchangeable. truth table 1b: dm operation name (function) dm dqs note write enable l valid 1 write inhibit h x 1 note: used to mask write data; provided coincident with the corresponding data.
A48P4616B (january, 2014, version 1.0) 11 amic technology, corp. deselect the deselect function prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a ddr sdram. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a12, ba0 and ba1 while issuing the mode register set command. see mode register descriptions in the register definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge (or read or write with auto precharge) is issued to that bank. a precharge (or read or write with auto precharge) command must be issued and completed before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. write the write command is used to initiate a burst write access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a write is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is non-persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensur es that the precharge is initiated at the earliest valid stage within a burst. this is determined as if an explicit precharge command was issued at the earliest possible time without violating t ras(min) . the user must not issue another command to the same bank until the precharge (t rp ) is completed.
A48P4616B (january, 2014, version 1.0) 12 amic technology, corp. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command is truncated, as shown in the operation section of this data sheet. write burst cycles are not to be terminated with the burst terminate command. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 256mb ddr sdram requires auto refresh cycles at an average periodic interval of 7.8 s (maximum). self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated as an auto refresh command coincident with cke transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke (low) are ?don?t care? during self refresh operation. the procedure for exiting self refresh requires a sequence of commands. ck (and ck) must be stable prior to cke returning high. once cke is high, the sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command.
A48P4616B (january, 2014, version 1.0) 13 amic technology, corp. operations bank/row activation before any read or write commands can be issued to a bank within the ddr sdram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0-a12, ba0 and ba1 (see activating a specific row in a specific bank), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd . reads subsequent to programming the mode register with cas latency, burst type, and burst length, read bursts are initiated with a read command. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of ck and ck). the following timing figure entitled ?read burst: cas latencies (burst length=4)? illustrates the general timing for each supported cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dq s and dq s goes high-z. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown in timing figure entitled ?consecutive read bursts: cas latencies (burst length =4 or 8)?. a read command can be initiated on any positive clock cycle following a previous read command. nonconsecutive read data is shown in timing figure entitled ?non-consecutive read bursts: cas latencies (burst length = 4)?. full-speed random read accesses: cas latencies (burst length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 18. activating a specific row in a specific bank ck ra ba high ck cke cs ras cas we a0-a12 ba0, ba1 ra = row address ba = bank address : don't care
A48P4616B (january, 2014, version 1.0) 14 amic technology, corp. t rcd and t rrd definition act nop act nop nop rd/wr nop nop row row col ba x ba y ba y t rrd t rcd : don't care ck ck command a0-a12 ba0, ba1 read command ck ca high ck cke cs ras cas we a0-a8 a10 ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge : don't care ba0, ba1 ba en ap dis ap
A48P4616B (january, 2014, version 1.0) 15 amic technology, corp. read burst: cas latencies (burst length = 4) read nop nop nop nop nop ba a, col n cl=2 doa-n ck ck command address dqs dq cas latency = 2 : don't care read nop nop nop nop nop ba a, col n cl=2.5 doa-n ck ck command address dqs dq cas latency = 2.5 doa-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following doa-n. shown with nominal t ac , t dqsck , and t dqsq . read nop nop nop nop nop ba a, col n ck ck command address cas latency = 3 cl=3 dqs dq doa-n
A48P4616B (january, 2014, version 1.0) 16 amic technology, corp. consecutive read bursts: cas latencies (burst length = 4 or 8) read nop nop nop read nop ba a, col n cl=2 doa-n ck ck command address dqs dq cas latency = 2 : don't care doa-n (or a-b) = data out from bank a, column n (or bank a, column b). when burst length = 4, the bursts are concatenated. when burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following doa-n. 3 (or 7) subsequent elements of data out appear in the programmed order following doa-b. shown with nominal t ac , t dqsck , and t dqsq . ba a, col b doa-b read nop nop nop read nop ba a, col n cl=3 doa-n ck ck command address dqs dq cas latency = 3 ba a, col b doa-b read nop nop nop read nop ba a, col n cl=2.5 doa-n ck ck command address dqs dq cas latency = 2.5 ba a, col b doa-b
A48P4616B (january, 2014, version 1.0) 17 amic technology, corp. non-consecutive read bursts: cas latencies (burst length = 4) : don't care doa-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following doa-n (and following doa-b). shown with nominal t ac , t dqsck , and t dqsq . read nop nop nop nop read ba a, col n cl=2 doa-n ck ck command address dqs dq cas latency = 2 ba a, col b doa-b read nop nop nop nop read ba a, col n cl=2.5 doa-n ck ck command address dqs dq cas latency = 2.5 ba a, col b doa-b nop read nop nop nop nop read ba a, col n cl= 3 doa-n ck ck command address dqs dq cas latency = 3 ba a, col b doa-b nop
A48P4616B (january, 2014, version 1.0) 18 amic technology, corp. random read accesses: cas latencies (burst length = 2, 4 or 8) read read nop nop read read ba a, col n cl=2 doa-n ck ck command address dqs dq cas latency = 2 ba a, col b doa-b ba a, col x ba a, col g doa-n , doa-x doa-x , doa-b , doa-g read read nop nop read read ba a, col n doa-n ck ck command address dqs dq cas latency = 2.5 ba a, col b doa-b ba a, col x ba a, col g doa-n , doa-x doa-x , doa-b , cl=2.5 : don't care doa-n, etc. = data out from bank a, column n etc. n , etc. = odd or even complement of n, etc. (i.e., column address lsb inverted). reads are to active rows in any banks. shown with nominal t ac , t dqsck , and t dqsq . read read nop nop read read ba a, col n doa-n ck ck command address dqs dq cas latency = 3 ba a, col b doa-b ba a, col x ba a, col g doa-n , doa-x doa-x , cl=3
A48P4616B (january, 2014, version 1.0) 19 amic technology, corp. data from any read burst may be truncated with a burst terminate command, as shown in timing figure entitled terminating a read burst: cas latencies (burst length = 8) on page 20. the burst terminate latency is equal to the read (cas) latency, i.e. the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs. data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in timing figure entitled read to write: cas latencies (burst length = 4 or 8) on page 21. the example is shown for t dqss(min) . the t dqss(max) case, not shown here, has a longer bus idle time. t dqss(min) and t dqss(max) are defined in the section on writes. a read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated). the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown in timing figure read to precharge: cas latencies (b urst length = 4 or 8) on page 22 for read latencies of 2, 2.5 and 3. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
A48P4616B (january, 2014, version 1.0) 20 amic technology, corp. terminating a read burst: cas latencies (burst length = 8) read nop nop nop bst nop ba a, col n cl=2 doa-n ck ck command address dqs dq cas latency = 2 : don't care doa-n = data out from bank a, column n. cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following doa-n. shown with nominal t ac , t dqsck , and t dqsq . read nop nop nop bst nop ba a, col n cl=2.5 doa-n ck ck command address dqs dq cas latency = 2.5 no further output data after this point. dqs tristated. no further output data after this point. dqs tristated. read nop nop nop bst nop ba a, col n cl=3 doa-n ck ck command address dqs dq cas latency = 3 no further output data after this point. dqs tristated.
A48P4616B (january, 2014, version 1.0) 21 amic technology, corp. read to write: cas latencies (burst length = 4 or 8) read bst nop nop nop write ba a, col n cl=2 doa-n ck ck command address dqs dq cas latency = 2 : don't care doa-n = data out from bank a, column n. dia-b = data in to bank a, column b. 1 subsequent elements of data out appear in the programmed order following doa-n. data in elements are applied following dia-b in the programmed order, according to burst length. shown with nominal t ac , t dqsck , and t dqsq . ba a, col b dia-b dm t dqss (min) read bst write nop nop nop ba a, col n cl=2.5 doa-n ck ck command address dqs dq cas latency = 2.5 ba a, col b dia-b dm t dqss (min) read bst write nop nop nop ba a, col n cl= 3 doa-n ck ck command address dqs dq cas latency = 3 ba a, col b dm t dqss (min) dia-b
A48P4616B (january, 2014, version 1.0) 22 amic technology, corp. read to precharge: cas latencies (burst length = 4 or 8) read nop nop act pre nop ba a, col n cl=2 doa-n ck ck command address dqs dq cas latency = 2 : don't care doa-n = data out from bank a, column n. cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following doa-n. shown with nominal t ac , t dqsck , and t dqsq . read nop nop act pre nop ba a, col n cl=2.5 doa-n ck ck command address dqs dq cas latency = 2.5 ba a or all ba a, row t rp t rp ba a or all ba a, row read nop nop act pre nop ba a, col n cl= 3 doa-n ck ck command address dqs dq cas latency = 3 t rp ba a or all ba a, row
A48P4616B (january, 2014, version 1.0) 23 amic technology, corp. read with auto precharge: cas latencies (burst length = 4) nop nop nop read with auto precharge nop cl=2 doa-n ck ck command address dqs dq cas latency = 2 : don't care doa-n = data out from bank a, column n. cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following doa-n. shown with nominal t ac , t dqsck , and t dqsq . t rp nop nop nop act nop ba a, col n cl=3 doa-n ck ck command address dqs dq cas latency = 3 t rp ba a or all ba a, row read with auto precharge nop nop nop act nop ba a, col n cl=2.5 doa-n ck ck command address dqs dq cas latency = 2.5 t rp ba a or all ba a, row read with auto precharge nop
A48P4616B (january, 2014, version 1.0) 24 amic technology, corp. writes write bursts are initiated with a write command, as shown in timing figure write command on page 25. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element is registered on the first rising edge of dq s following the write command, and subsequent data elements are registered on successive edges of dq s . the low state on dq s between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data- in element is known as the write postamble. the time between the write command and the first corresponding rising edge of dqs (t dqss ) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the write diagrams that follow are drawn for the two extreme cases (i.e. t dqss(min) and t dqss(max) ). timing figure write burst (burst length = 4) on page 26 shows the two extremes of t dqss for a burst of four. upon completion of a burst, assuming no other commands have been initiated, the dq s and dq s enters high-z and any additional input data is ignored. data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). timing figure write to write (burst length = 4) on page 27 shows concatenated bursts of 4. an example of nonconsecutive writes is shown in timing figure write to write: max dqss, non-consecutive (burst length = 4) on page 28. full speed random write accesses within a page or pages can be performed as shown in timing figure random write cycles (burst length = 2, 4 or 8) on page 29. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr (write to read) should be met as shown in timing figure write to read: non-interrupting (cas latency = 2; burst length = 4) on page 30. data for any write burst may be truncated by a subsequent (interrupting) read command. this is illustrated in timing figures ?write to read: interrupting (cas latency =2; burst length = 8)?, ?write to read: minimum dqss, odd number of data (3 bit write), interrupting (cas latency = 2; burst length = 8)?, and ?write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8)?. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm, as shown in the diagrams noted previously. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met as shown in timing figure write to precharge: non-interrupting (burst length = 4) on page 34. data for any write burst may be truncated by a subsequent precharge command, as shown in timing figures write to precharge: interrupting (burst length = 4 or 8) on page 35 to write to precharge: nominal dqss (2 bit write), interrupting (burst length = 4 or 8) on page 37. note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data in should be masked with dm. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a write burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
A48P4616B (january, 2014, version 1.0) 25 amic technology, corp. write command ck ca high ck cke cs ras cas we a0-a8 a10 ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge : don't care ba0, ba1 ba en ap dis ap
A48P4616B (january, 2014, version 1.0) 26 amic technology, corp. write burst (burst length = 4) write nop nop nop ba a, col b t dqss (max) dia-b ck ck command address dqs dq dm t1 t2 t3 t4 maximum d qss write nop nop nop ba a, col b t dqss (min) dia-b ck ck command address dqs dq dm t1 t2 t3 t4 minimum d qss : don't care dia-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following dia-b. a non-interrupted burst is shown. a10 is low with the write command (auto precharge is disabled).
A48P4616B (january, 2014, version 1.0) 27 amic technology, corp. write to write (burst length = 4) write nop nop nop write nop ba a, col b t dqss (max) ck ck command address dqs dq maximum d qss : don't care dia-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following dia-b. 3 subsequent elements of data in are applied in the programmed order following dia-n. a non-interrupted burst is shown. each write command may be to any bank. ba a, col n dm dia-n dia-b t1 t2 t3 t4 t5 t6 write nop nop nop write nop ba a, col b t dqss (min) ck ck command address dqs dq minimum d qss ba a, col n dm dia-n dia-b t1 t2 t3 t4 t5 t6
A48P4616B (january, 2014, version 1.0) 28 amic technology, corp. write to write: max dqss, non-consecutive (burst length = 4) write nop nop nop write ba a, col b t dqss (max) ck ck command address dqs dq ba a, col n dm t1 t2 t3 t4 t5 dia-b dia-n : don't care dia-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following dia-b. 3 subsequent elements of data in are applied in the programmed order following dia-n. a non-interrupted burst is shown. each write command may be to any bank.
A48P4616B (january, 2014, version 1.0) 29 amic technology, corp. random write cycles (burst length = 2, 4 or 8) . write write write write write ba a, col b t dqss (max) ck ck command address dqs dq ba a, col a dm t1 t2 t3 t4 t5 dia-b dia-b , dia-x dia-x , dia-n dia-n , dia-a dia-a , ba a, col x ba a, col n ba a, col g maximum d qss write write write write write ba a, col b t dqss (min) ck ck command address dqs dq ba a, col a dm t1 t2 t3 t4 t5 dia-b : don't care dia-b , dia-x dia-x , dia-n dia-n , dia-a dia-a , ba a, col x ba a, col n ba a, col g minimum d qss dia-g dia-b, etc. = data in for bank a, column b, etc. b , , etc. = odd or even complement of b, etc (i.e., column address lsb inverted). each write command may be to any bank.
A48P4616B (january, 2014, version 1.0) 30 amic technology, corp. write to read: non-interrupting (cas latency = 2; burst length = 4) write nop read nop nop nop ba a, col b t dqss (max) ck ck command address dqs dq maximum d qss dm t1 t2 t3 t4 t5 t6 ba a, col n t wtr dia-b cl=2 write nop read nop nop nop ba a, col b t dqss (min) ck ck command address dqs dq minimum d qss dm t1 t2 t3 t4 t5 t6 ba a, col n t wtr cl=2 dia-b = data in for bank a, column b. 3 subsequent elements of data in are applie d in the programmed order following dia-b. a non-interrupted burst is shown. t wtr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write command (auto precharge is disabled). the road and write commands may be to any bank. : don't care dia-b t7 nop t7 nop
A48P4616B (january, 2014, version 1.0) 31 amic technology, corp. write to read: interrupting (cas latency = 2; burst length = 8) write nop read nop nop nop ba a, col b t dqss (max) ck ck command address dqs dq maximum d qss dm t1 t2 t3 t4 t5 t6 ba a, col n t wtr dia-b cl=2 write nop read nop nop nop ba a, col b t dqss (min) ck ck command address dqs dq minimum d qss dm t1 t2 t3 t4 t5 t6 ba a, col n t wtr cl=2 dia-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following dia-b. t wtr is referenced from the first positive ck edge after the last data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. 1 = these bits are incorrectly written into the memory array if dm is low. : don't care dia-b 11 11 t7 nop t7 nop 1 1 1 1
A48P4616B (january, 2014, version 1.0) 32 amic technology, corp. write to read: minimum dqss, odd number of data (3 bit write), interrupting (cas latency = 2; burst length = 8) write nop read nop nop nop ba a, col b t dqss (min) ck ck command address dqs dq dm t1 t2 t3 t4 t5 t6 ba a, col n t wtr dia-b cl=2 12 2 dia-b = data in for bank a, column b. an interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are app lied in the programmed order following dia-b. t wtr is referenced from the first positive ck edge after the la st desired data in pair (not the last desired data in element). the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. 1 = this bit is correctly written into the memory array if dm is low. 2 = these bits are incorrectly written into the memory array if dm is low. : don't care t7 nop 2 2
A48P4616B (january, 2014, version 1.0) 33 amic technology, corp. write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8) write nop read nop nop nop ba a, col b t dqss ck ck command address dqs dq dm t1 t2 t3 t4 t5 t6 ba a, col n t wtr cl=2 dia-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are app lied in the programmed order following dia-b. t wtr is referenced from the first positive ck edge after the last desired data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. 1 = these bits are incorrectly written into the memory array if dm is low. : don't care dia-b 11 t7 nop 1 1
A48P4616B (january, 2014, version 1.0) 34 amic technology, corp. write to precharge: non-interrupting (burst length = 4) write nop nop pre nop nop ba a, col b t dqss (max) ck ck command address dqs dq maximum d qss dm t1 t2 t3 t4 t5 t6 ba(a or all) t wr dia-b t rp write nop nop pre nop nop ba a, col b t dqss (min) ck ck command address dqs dq minimum d qss dm t1 t2 t3 t4 t5 t6 t wr dia-b dia-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following dia-b. a non-interrupted burst is shown. t wr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write command (auto precharge is disabled). : don't care ba(a or all) t rp
A48P4616B (january, 2014, version 1.0) 35 amic technology, corp. write to precharge: interrupting (burst length = 4 or 8) write nop pre nop nop nop ba a, col b t dqss (max) ck ck command address dqs dq maximum d qss dm t1 t2 t3 t4 t5 t6 t wr dia-b t rp write nop pre nop nop nop ba a, col b t dqss (min) ck ck command address dqs dq minimum d qss dm t1 t2 t3 t4 t5 t6 t wr dia-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following dia-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst, for burst length = 8. a10 is low with the write command (auto precharge is disabled). 1 = can be do not care for programmed bust length of 4. 2 = for programmed bust length of 4, dq s becomes do not care at this point. 3 = these bits are incorrectly written into the memory array if dm is low. : don't care ba(a or all) t rp ba(a or all) 2 33 1 1 2 dia-b 33 1 1
A48P4616B (january, 2014, version 1.0) 36 amic technology, corp. write to precharge: minimum dqss, odd number of data (1 bit write), interrupting (burst length = 4 or 8) write nop pre nop nop nop ba a, col b t dqss (min) ck ck command address dqs dq dm t1 t2 t3 t4 t5 t6 t wr dia-b t rp ba(a or all) 2 44 1 1 3 dia-b = data in for bank a, column b. an interrupted burst is shown, 1 data elements are written. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be do not care for programmed bust length of 4. 2 = for programmed bust length of 4, dqs becomes do not care at this point. 3 = this bit is correctly written into the memory array if dm is low. 4 = these bits are incorrectly written into the memory array if dm is low. : don't care
A48P4616B (january, 2014, version 1.0) 37 amic technology, corp. write to precharge: nominal dq ss (2 bit write), interrupting (burst length = 4 or 8) write nop pre nop nop nop ba a, col b t dqss ck ck command address dqs dq dm t1 t2 t3 t4 t5 t6 t wr dia-b t rp ba(a or all) 2 dia-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following dia-b t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be do not care for programmed bust length of 4. 2 = for programmed bust length of 4, dqs becomes do not care at this point. 3 = these bits are incorrectly written into the memory array if dm is low. : don't care 3 1 1 3
A48P4616B (january, 2014, version 1.0) 38 amic technology, corp. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) is available for a subsequent row access some specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. precharge command ck high ck cke cs ras cas we a0-a9, a11, a12 a10 ba = bank address (if a10 is low, otherwise don't care) : don't care ba0, ba1 ba all banks one bank
A48P4616B (january, 2014, version 1.0) 39 amic technology, corp. power down power down is entered when cke is registered low (no accesses can be in progress). if power down occurs when all banks are idle, this mode is referred to as precharge power down; if power down occurs when there is a row active in any bank, this mode is referred to as active power down. entering power down deactivates the input and output buffers, excluding ck, ck and cke. the dll is still running in power down mode, so for maximum power savings, the user has the option of disabling the dll prior to entering power down. in that case, the dll must be enabled after exiting power down, and 200 clock cycles must occur before a read command can be issued. in power down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, and all other input signals are ?don?t care?. however, power down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power down mode. the power down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command may be applied one clock cycle later. power down ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ valid nop nop valid no column access in progress enter power down mode (burst read or write operation must not be in progress) exit power down mode t xpnr / t xprd : don't care ck ck cke command t is t is
A48P4616B (january, 2014, version 1.0) 40 amic technology, corp. truth table 2: clock enable (cke) cke n-1 cke n current previous cycle previous cycle command n action n note self refresh l l x maintain self-refresh self refresh l h deselect or nop exit self-refresh 1 power down l l x maintain power down power down l h deselect or nop exit power down all banks idle h l deselect or nop precharge power down entry all banks idle h l auto refresh self refresh entry bank(s) active h l deselect or nop active power down entry h h see ?truth table 3: current state bank n - command to bank n (same bank)? on page 41 note: 1. cke n is the logic state of cke at clock edge n: cke n-1 was the state of cke at the previous clock edge. 2. current state is the st ate of the ddr sdram immediat ely prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the self refresh exit (t xsnr ) period. a minimum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock.
A48P4616B (january, 2014, version 1.0) 41 amic technology, corp. truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action note h x x x deselect nop. continue previous operation 1-6 any l h h h no operation nop. continue previous operation 1-6 l l h h active select and activate row 1-6 l l l h auto refresh 1-7 idle l l l l mode register set 1-7 l h l h read select column and start read burst 1-6, 10 l h l l write select column and start write burst 1-6, 10 row active l l h l precharge deactivate row in bank(s) 1-6, 8 l h l h read select column and start new read burst 1-6, 10 l l h l precharge 1-6, 8 read (auto precharge disabled) l h h l burst terminate burst terminate 1-6, 9 l h l h read select column and start read burst 1-6, 10, 11 l h l l write select column and start write burst 1-6, 10 write (auto precharge disabled) l l h l precharge truncate write burst, start precharge 1-6, 8, 11 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to truth table 4. 5. the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking.
A48P4616B (january, 2014, version 1.0) 42 amic technology, corp. truth table 4: current state bank n - command to bank m (different bank) current state cs ras cas we command action note h x x x deselect nop/continue previous operation 1-6 any l h h h no operation nop/continue previous operation 1-6 idle x x x x any command otherwise allowed to bank m 1-6 l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7 l h l l write select column and start write burst 1-7 row activating, active, or precharging l l h l precharge 1-6 l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7 read (auto precharge disabled) l l h l precharge 1-6 l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-8 l h l l write select column and start new write burst 1-7 write (auto precharge disabled) l l h l precharge 1-6 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except wher e noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see note 10. write with auto precharge enabled: see note 10. 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column inclu de reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. 10. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then fo llowed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access perio d starts with registration of the command and ends where the precharge period (or t rp ) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other bank may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided).
A48P4616B (january, 2014, version 1.0) 43 amic technology, corp. truth table 5: current state bank n - comma nd to bank m (different bank) (continued) current state cs ras cas we command action note l l h h active select and activate row 1-6 l h l h read select column and start new read burst 1-7, 10 l h l l write select column and start write burst 1-7, 9, 10 read (with auto precharge) l l h l precharge 1-6 l l h h active select and activate row 1-6 l h l h read select column and start read burst 1-7, 10 l h l l write select column and start new write burst 1-7, 10 write (with auto precharge) l l h l precharge 1-6 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2: clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except wher e noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see note 10. write with auto precharge enabled: see note 10. 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column inclu de reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output. 10. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access per iod starts with registration of the command and ends where the precharge period (or t rp ) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other bank may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided).
A48P4616B (january, 2014, version 1.0) 44 amic technology, corp. simplified state diagram power on precharge preall mrs emrs power applied idle self refresh mrs refs refsx auto refresh refa precharge power down burst stop read read a row active precharge preall active power down white read a white a write a act pre ckel ckeh ckeh ckel write write a read a read read a pre pre pre read preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge automatic sequence command sequence preall mrs
A48P4616B (january, 2014, version 1.0) 45 amic technology, corp. absolute maximum ratings* symbol parameter rating unit v out voltage on i/o pins relative to v ss q -0.5 to v ddq + 0.5 v v in voltage on inputs relative to v ss -1.0 to 3.6 v v dd voltage on v dd supply relative to v ss -1.0 to 3.6 v v ddq voltage on v ddq supply relative to v ss q -1.0 to 3.6 v t a operating temperature (ambient) 0 to +70 c t atg storage temperature (plastic) -55 to +150 c p d power dissipation at t a = 25 c 1.0 w i out output current 50 ma notes: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance parameter symbol min max unit note input capacitance: ck, ck ci1 2.5 3.5 pf 1 delta input capacitance: ck, ck delta ci1 0.3 pf 1 input capacitance: all other input-only pins (except dm) ci2 2.5 3.5 pf 1 delta input capacitance: all other input-only pins (except dm) delta ci2 1.0 pf 1 input/output capacitance: dq, dqs, dm ci/o 4.0 5.0 pf 1.2 delta input/output capacitance: dq, dqs, dm delta ci/o 1.0 pf 1 notes: 1. v ddq = v dd = 2.5v 0.2v (minimum range to maximum range), f = 100mhz, t a = 25 c, vo dc = v ddq/2 , vo peak -peak = 0.2v. 2. although dm is an input-only pin, the input capacitance of th is pin must model the input capacitance of the dq and dqs pins. this is required to match input propagation times of dq, dqs and dm in the system.
A48P4616B (january, 2014, version 1.0) 46 amic technology, corp. dc electrical characteristics and operating conditions (t a = 0oc to +70oc for commercial or t a =-40oc to +85oc for industrial; v ddq = 2.5v 0.2v, v dd = + 2.5v 0.2v) symbol parameter min max unit note v dd supply voltage 2.3 2.7 v 1 v ddq i/o supply voltage 2.3 2.7 v 1 v ss , v ssq supply voltage i/o supply voltage 0 0 v v ref i/o reference voltage 0.49 x v ddq 0.51 x v ddq v 1.2 v tt i/o termination voltage (system) v ref - 0.04 v ref + 0.04 v 1.3 v ih (dc) input high voltage v ref + 0.15 v ddq + 0.3 v 1 v il (dc) input low voltage -0.3 v ref - 0.15 v 1 v in (dc) input voltage level, ck and ck inputs -0.3 v ddq + 0.3 v 1 v id (dc) input differential voltage, ck and ck inputs 0.36 v ddq + 0.6 v 1.4 i i input leakage current any input 0v v in v dd ; (all other pins not under test = 0v) -2 2 a 1 i oz output leakage current (dqs are disabled; 0v v out v ddq -5 5 a 1 i oh high current (v out = 1.95v) -16.2 i ol low current (v out = 0.35v) 16.2 ma 1 notes: 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak- to-peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck .
A48P4616B (january, 2014, version 1.0) 47 amic technology, corp. ac characteristics (notes 1-5 apply to the following tables; electrical characte ristics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. refer to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environm ent, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guaran teed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il (ac) and v ih (ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. ac output load circuit diagrams z 0 = v tt = v ref 30pf 50 ? v ref 50 ? v out dqs v ref v ref dq output timing measurement reference point ac input operating conditions (t a = 0oc to +70oc for commercial or t a =-40oc to +85oc for industrial; v dd = v ddq = 2.5v 0.2v) symbol parameter/condition min max unit note v ih (ac) input high voltage, dq, dqs, and dm signals v ref + 0.31 v 1, 2 v il (ac) input low voltage, dq, dqs, and dm signals v ref ? 0.31 v 1, 2 v id (ac) input differential voltage, ck and ck inputs 0.7 v ddq + 0.6 v 1, 2, 3 v ix (ac) input crossing point voltage, ck and ck inputs 0.5*v ddq ? 0.2 0.5* v ddq + 0.2 v 1, 2, 4 notes: 1. input slew rate = 1v/ns. 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same.
A48P4616B (january, 2014, version 1.0) 48 amic technology, corp. i dd specifications and conditions (t a = 0oc to +70oc for commercial or t a =-40oc to +85oc for industrial; v dd = v ddq = 2.5v 0.2v, output open, unless otherwise noted) limits (max.) symbol parameter / test condition -5 unit note i dd0 operating current for one bank active-precharge: one bank active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dqs and dm inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; cs = high between valid commands 85 ma i dd1 operating current for one ban k operation: one bank active-read-precharge; burst length = 4; t rc = t rc (min); t ck =t ck (min); i out = 0ma; address and control inputs changing once per clock cycle; cs = high between valid commands; 50% of data changing on every transfer 110 ma i dd2p precharge power down standby current: all banks idle; power down mode; cke v il (max); t ck = t ck (min); v in = v ref for dq, dqs, and dm 20 ma i dd2f precharge floating standby current: cs v ih (min); all banks idle; cke v ih (min); t ck = t ck (min); address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm 40 ma i dd2q precharge quiet standby current: cs v ih (min); all banks idle; cke v ih (min); t ck = t ck (min); address and other control inputs stable at v ih (min) or v il (max); v in = v ref for dq, dqs, and dm 35 ma i dd3p active power down standby curr ent: one bank active; power down mode; cke v il (max); t ck = t ck (min); v in = v ref for dq,dqs, and dm 45 ma i dd3n active standby current: cs v ih (min); cke v ih (min); one bank active; t rc = t ras (max); t ck = t ck (min); dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 80 ma i dd4r operating current for burst read: burst length = 2; read; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); 50% of data changing on every transfer; i out = 0ma 160 ma i dd4w operating currentfor burst write: burst length = 2; write; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dqs, and dm inputs changing twice per clock cycle; 50% of input data changing at every transfer 130 ma i dd5 auto refresh current: t rc = t rfc (min) 90 ma i dd6 self refresh current: cke 0.2v, t ck = t ck (min) 5 ma i dd7 operating current for four ba nk operation: four bank interleaving with burst length = 4, refer to note.22 for detailed test condition 210 ma 22
A48P4616B (january, 2014, version 1.0) 49 amic technology, corp. electrical characteristics & ac ti ming - absolute specifications (t a = 0oc to +70oc for commercial or t a =-40oc to +85oc for industrial; v dd = v ddq = 2.5v 0.2v) -5 symbol ac characteristics parameter min max unit note t ac dq output access time from ck / ck -0.70 +0.70 ns t dqsck dqs output access time from ck / ck -0.6 +0.6 ns t ch ck high level width 0.45 0.55 t ck t cl ck low level width 0.45 0.55 t ck cl=3.0 5 12 cl=2.5 6 12 t ck clock cycle time cl=2.0 7.5 12 ns t ds input setup time (dq,dm) 0.4 ns t dh input hold time (dq,dm) 0.4 ns t ipw control & address input pulse width (for each input) 2.2 ns t dipw dq and dm input pulse width (for each input) 1.75 ns t hz data-out high impedance time from ck / ck +0.70 ns 14 t lz data-out low impedance time from ck / ck -0.70 +0.70 ns 14 t dqsq dq valid data delay time from dqs 0.40 ns t hp clock half period t cl min or t ch min ns 20 t qh dq output hold time from dqs (per access) t hp -t qhs ns t qhs data hold skew factor (for dqs & associated dq signals) 0.50 ns t dqss write command to first dqs latching transition 0.72 1.25 t ck t dqsh dqs input high level width 0.35 t ck t dqsl dqs input low level width 0.35 t ck t dss dqs falling edge to ck setup time 0.2 t ck t dsh dqs falling edge hold time from ck 0.2 t ck t mrd mode register set command cycle time 2 t ck t wpres write preamble setup time 0 ns 16 t wpst write postamble 0.4 0.6 t ck 15 t wpre write preamble max(0.25* t ck , 1.5ns) ns t is input setup time (address and control) 0.6 ns 19 t ih input hold time (address and control) 0.6 ns 19 t rpst read postamble 0.4 0.6 t ck t rpre read preamble 0.9 1.1 t ck
A48P4616B (january, 2014, version 1.0) 50 amic technology, corp. electrical characteristics & ac timing - absolute specifications (continued) (t a = 0oc to +70oc for commercial or t a =-40oc to +85oc for industrial; v dd = v ddq = 2.5v 0.2v) -5 symbol ac characteristics parameter min max unit note t ras row active time 40 70k ns t rc row cycle time(operation) 55 ns t rfc auto refresh to active/auto refresh command period 70 ns t rcd row to column delay 15 ns t rp row precharge time 15 ns t rrd act to act delay time 10 ns t wr write recovery time 15 ns t dal auto precharge write recovery + precharge time t ck 21 t wtr internal write to read command delay 2 t ck t xsnr exit self refresh to non-read command 75 ns t xsrd exit self refresh to read command 200 t ck t xpnr exit power down to command 1 t ck t xprd exit power down to read command 1 t ck 18 t refi average periodic refresh interval 7.8 s 17 notes: 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck / ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il (ac) and v ih (ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. v ref is expected to be equal to 0.5* v ddq of the transmitting device, and to track variations in the dc level of the same. peak- to-peak noise on v ref may not exceed +2% of the dc value. 6. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 7. v id is the magnitude of the difference between the input level on ck and the input level on ck . 8. the value of v ix is expected to equal 0.5* v ddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. i dd specifications are tested after the device is properly initialized. 11. the ci1, ci2, ci/o are sampled. v ddq = 2.5v+0.2v, v dd = 2.5v+0.2v, f =100mhz, t a = 25 c, v out (dc) = v ddq /2, v out (peak to peak) = 0.2v. dm inputs are grouped with i/o pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the ck / ck input reference level (for timing referenced to ck / ck ) is the point at which ck and ck cross; the input reference level for signals other than ck / ck , is v ref . 13. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, ce 0.3 v ddq is recognized as low. 14. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz).
A48P4616B (january, 2014, version 1.0) 51 amic technology, corp. 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter , but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge . a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progr ess on the bus, dqs will be transitioning fr om high-z to logic low. if a previous write was in progress, dqs could be high, low, or trans itioning from high to low at this time, depending on t dqss . 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. t xprd should be 200 t clk in the condition of the unstable ck operation during the power down mode. 19. for command/address and ck & ck slew rate > 1.0v/ns. 20. min (t cl ,t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device. 21. t dal minimum = (t wr /t ck ) + (t rp /t ck ). for each of the terms above, if not already an integer, round to the next highest integer. 22. operating current for four bank operation: four banks are being interleaved with t rc (min), burst mode, address and control inputs on deselect edge are not changing. i out = 0ma. test pattern for -5 (200mhz, cl = 3, t ck = 5ns, bl = 4, t rrd = 2*t ck , t rcd = 3*t ck , t rc = 11*t ck ); setup; a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n read; a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n test pattern for -4 (250mhz, cl = 3, t ck = 4ns, bl = 4, t rrd = 3*t ck , t rcd = 4*t ck , t rc = 14*t ck ); setup; a0 n n a1 ra0 n a2 ra1 n a3 ra2 n n ra3 read; a0 n n a1 ra0 n a2 ra1 n a3 ra2 n n ra3 repeat the same timing with random address changing, 50% of data changing at every transfer.
A48P4616B (january, 2014, version 1.0) 52 amic technology, corp. data input (write) (timing burst length = 4) t dsl dqs dq dm din = data in for column n. 3 subsequent elements of data in are applied in programmed order following din. : don't care t dsh t dh t ds din t dh t ds data output (read) (timing burst length = 4) t dqsq t qh1 t dqsq t qh2 t dqsq t qh3 t dqsq t qh4 t hp t hp t hp t hp1 t hp2 t hp3 t hp4 ck ck dqs dq t hp is the half cycle pulse width for each half cycle clock. t hp is referenced to the clock duty cycle only and not to the data strobe (dqs) duty cycle. data output hold time from data strobe is shown as t qh . t qh is a function of the clock high or low time (t hp ) for that given clock cycle. note correlation of t hp to t qh in the diagram above (t hp1 to t qh1 . etc.). t dqsq (max) occurs when dqs is the earliest among dqs and dq signals to transition.
A48P4616B (january, 2014, version 1.0) 53 amic technology, corp. initialize and mode register sets ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ nop pre emrs mrs pre ar ar mrs act ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ code code code ra ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ code code code ra ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ba0=h ba ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ba1=l ba0=l ba1=l ba0=l ba1=l ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ high-z high-z *v tt is not applied directly to the device, however t vtd must be greater than or equal to zero to avoid device latchup. **t mrd is required before any command can be applied and 200 cycles of ck are required before a read command can be applied. the two autofresh commands may be moved to follow the first mrs, but precede the second precharge all command. t vtd v dd v ddq v tt (system*) v ref ck ck cke command dm a0-a9, a11, a12 a10 ba0, ba1 dqs dq : don't care 200us t ck t ch t cl t mrd t mrd t rp t rfc t rfc t mrd 200 cycles of ck** lvcmos low level t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih all banks all banks t is t ih power-up: v dd and ck stable extended mode register set load mode register, reset dll load mode register (with a8=l)
A48P4616B (january, 2014, version 1.0) 54 amic technology, corp. power down mode ck ck cke command valid* nop nop valid valid valid ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ addr dqs dq dm enter power down mode exit power down mode no column access are allowed to be in progress at the time power down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power down mode shown is precharge power down. if this command is an active (or if at least one row is already active), then the power down mode shown is active power down. t ck t ch t cl t xpnr / t xprd t is t ih t is t is t is t ih t is t ih : don't care
A48P4616B (january, 2014, version 1.0) 55 amic technology, corp. auto refresh mode ck ck cke command a0-a8 a9, a11, a12 a10 ba0, ba1 pre = precharge; act = active; ra = row address; ba = bank address, ar = autorefresh. nop commands are shown for ease of illustration; other valid commands may be possible at these times. dm, dq, and dqs signals are all don?t care/high-z for operation shown. : don't care dqs dq dm ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t ck t ch t cl t rp t rfc t rfc t ih t is valid valid nop pre nop nop ar nop ar nop nop act ra ra ra ba ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ all banks one bank t ih t is bank(s) t ih t is
A48P4616B (january, 2014, version 1.0) 56 amic technology, corp. self refresh mode nop ar nop valid valid ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t rp* t ck t ch t cl t ih t is t is t is t ih t is t ih t is * = device must be in the all banks idle state before entering self refresh mode. ** = t xsnr is required before any non-read command can be applied, and t xsrd (200 cycles of ck) are required before a read command can be applied. : don't care enter self refresh mode exit self refresh mode clock must be stable before exiting self refresh mode ck ck cke command addr dqs dq dm t xsrn t xsrd ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
A48P4616B (january, 2014, version 1.0) 57 amic technology, corp. read without auto precharge (burst length = 4) ck ck cke command a0-a9, a11, a12 dm do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * = don?t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. : don't care t ck t ch t cl t rp t ih t is valid nop read nop pre nop nop act nop nop nop all banks one bank valid valid t ih t ih t is col n ra t ih t is a10 ra t ih t is dis ap ba0, ba1 ba x t ih t is ba x* ba x t lz (min) t rpre cl=2 t ac (min) t dqsck (min) t rpst t hz (min) do n t lz (max) t rpre t lz (max) do n t ac (max) t dqsck (max) t hz (max) t rpst dqs dq dqs dq case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max
A48P4616B (january, 2014, version 1.0) 58 amic technology, corp. read with auto precharge (burst length = 4) ck ck cke command a0-a9, a11, a12 dm do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. en ap = enable auto precharge. act = active; ra = row address. nop commands are shown for ease of illustration; other commands may be valid at these times. : don't care t ck t ch t cl t rp t ih t is valid nop read nop nop nop nop act nop nop nop valid valid t ih t ih t is col n ra t ih t is a10 ra t ih t is en ap ba0, ba1 ba x t ih t is ba x t lz (min) t rpre cl=2 t ac (min) t dqsck (min) t rpst t hz (min) do n t lz (max) t rpre t lz (max) do n t ac (max) t dqsck (max) t hz (max) t rpst dqs dq dqs dq case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t hz (min)
A48P4616B (january, 2014, version 1.0) 59 amic technology, corp. bank read access (burst length = 4) ck ck cke command a0-a9, a11, a12 dm do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * = don?t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. : don't care t ck t ch t cl t rc t ih t is nop act nop read nop pre nop nop act nop valid t ih t is ra col n t ih t is a10 t ih t is ba0, ba1 t ih t is ba x t lz (min) t rpre cl=2 t ac (min) t dqsck (min) t rpst t hz (min) do n t lz (max) t rpre t lz (max) do n t ac (max) t dqsck (max) t hz (max) t rpst dqs dq dqs dq case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t lz (min) ra ra ra all banks one bank dis ap ba x ba x ba x* t rp t ras t rcd
A48P4616B (january, 2014, version 1.0) 60 amic technology, corp. write without auto precharge (burst length = 4) ck ck cke command a0-a9, a11, a12 t dqss = min. din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * = don?t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. : don't care t ck t ch t cl t ih t is nop write nop nop nop nop pre nop nop act valid t ih t is col n t ih t is a10 t ih t is ba0, ba1 t ih t is ba x dqs dq dm ra all banks one bank dis ap ba x* ra t wr t rp t ih ba t wpst t dsh t dqsl t dqsh t wpre t wpres t dqss din
A48P4616B (january, 2014, version 1.0) 61 amic technology, corp. write with auto precharge (burst length = 4) ck ck cke command a0-a9, a11, a12 t dqss = min. din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. en ap = enable auto precharge. act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. : don't care t ck t ch t cl t ih t is nop write nop nop nop nop nop nop nop act valid t ih t is col n t ih t is a10 t ih t is ba0, ba1 t ih t is ba x dqs dq dm ra t wr t rp ba t wpst t dsh t dqsl t dqsh t wpre t wpres t dqss din valid valid t dal en ap ra
A48P4616B (january, 2014, version 1.0) 62 amic technology, corp. bank write access (burst length = 4) ck ck cke command a0-a9, a11, a12 t dqss = min. din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * = don?t care if a10 is high at this point. pre = precharge; act = active; ra = row address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. : don't care t ck t ch t cl t ih t is nop act nop write nop nop nop nop pre nop valid t ih t is ra t ih t is a10 t ih t is ba0, ba1 t ih t is ba x dqs dq dm all banks one bank dis ap t wpst t dsh t dqsl t dqsh t wpre t wpres t dqss din col n ra t ras ba x ba x* t wr t rcd
A48P4616B (january, 2014, version 1.0) 63 amic technology, corp. write dm operation (burst length = 4) ck ck cke command a0-a9, a11, a12 din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din (the second element of the 4 is masked). dis ap = disable auto precharge. * = don?t care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. t dqss = min. : don't care t ck t ch t cl t ih t is nop write nop nop nop nop pre nop nop act valid t ih t is t ih t is a10 ba0, ba1 dqs dq dm ra col n t ih t is all banks dis ap ra one bank t ih t is ba x ba x* ba t wpst t dsh t dqsl t dqsh t wpres t dqss din t wr t rp
A48P4616B (january, 2014, version 1.0) 64 amic technology, corp. ordering information speed part no. org. clock(mhz) comments package A48P4616Bv-5f 66pin tsop pb-free A48P4616Bv-5uf 16m x 16 200 ddr400 66pin tsop pb-free note: -u is for industrial operating temperature range -40oc to +85oc.
A48P4616B (january, 2014, version 1.0) 65 amic technology, corp. package information tsop 66l type ii (10.16 x 22.22mm) outline dimensions unit: mm c b e 1 33 66 34 d zd e a 2 a c detail "a" e 1 l a 1 detail "a" d 0.10 c dimensions in mm symbol min nom max a - - 1.20 a 1 0.05 - 0.15 a 2 0.95 1.00 1.05 b 0.22 - 0.38 c 0.12 - 0.21 d 22.12 22.22 22.32 e 11.56 11.76 11.96 e 1 10.06 10.16 10.26 l 0.40 0.50 0.60 e 0.65 bsc 0 - 8 zd 0.71 ref notes: 1. dimension d does not include mold protrusions or gate burrs. 2. dimension e 1 does not include interlead mold protrusions. 3. dimension b does not include damber protrusion / intrusion. 4. all dimensions and tolerances take reference to jedec ms-024 fc.

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