ver 3.1 oct 03, 2001 tel: 886-3-5788833 http://www.gmt.com.tw 1 g261 global mixed-mode technology inc. low voltage differential (lvd) scsi 27 line regu- lator set features ? scsi spi-2 (ultra 2) lvd scsi 27 line low volt- age differential regulator ? 4.0v to 5.25v operation ? integrated regulator set for lvd scsi ? differential failsafe bias applications ? scsi cable ? scsi card ? disk array ? industrial pc ? pos description the g261 lvd regulator set is designed to provide the correct reference voltages and bias currents for lvd termination resistor networks (475 ? , 121 ? ,and 475 ? ) the device also provides a 1.3v output for diffsense signaling. with the proper resistor net- work, the g261 solution will meet the common mode impedance, differential mode impedance, differential bias voltage and common mode voltage requirements of spi-2 (ultra2). this device contains two sink / source reference volt- age regulators, a 1.3v buffered output and protection features. the protection features include thermal shutdown and active current limiting circuitry. the g261 is offered in 16pin sop. ordering information part temp. range pin-package G261P1 -40 c~80 c 8 pin sop pin configuration reg2 hspgnd hspgnd reg1 2 3 4 8 7 6 5 8 pin sop termpwr hsgnd hsgnd diffsense 1 reg2 hspgnd hspgnd reg1 2 3 4 8 7 6 5 8 pin sop termpwr hsgnd hsgnd diffsense 1
ver 3.1 oct 03, 2001 tel: 886-3-5788833 http://www.gmt.com.tw 2 g261 global mixed-mode technology inc. absolute maximum ratings termpwr?????.???.??????.??6v package dissipation????????.????..1w junction temperature????..??.-55 c to 150 c storage temperature???????-65 c to 150 c recommended operating conditions termpwr voltage??.??????4.0v to 5.25v electrical characteristics unless otherwise specified these specifications apply for ta= 0 to 70 ,termpwr=5v. parameter test conditions min typ max umits termpwr supply current section termpwr supply current no load 6 10.0 ma termpwr voltage 4.0 5.25 v regulator section 1.75 volt regulator reg1( 50ma) 1.7 1.75 1.8 v 1.3 volt regulator diffsense, no load 1.2 1.3 1.4 v 0.75 volt regulator reg2( 50ma) 0.7 0.75 0.8 v 1.75 volt regulator source current -50 ma 1.75 volt regulator sink current 50 ma 1.75 sink current limit 600 ma 1.75 source current limit -600 ma 1.3 volt regulator source current diffsense, gnd -5 -15 ma 1.3 volt regulator sink current diffsense, 2.4v 10 200 a 0.75 volt regulator source current -50 ma 0.75 volt regulator sink current 50 ma 0.75 current limit 600 ma 0.75 current limit -600 ma block diagram ref 1.75v ref 0.75v ref 1.3v 5ma source/10a sink 1.75v 50mv 50ma source/sink trmpwr 4.0v to 5.25v pgnd 0.75v 50mv 50ma source/sink 1.3v 0.1v diffsense reg1 reg2 source/sink regulator ref 1.75v ref 0.75v ref 1.3v 5ma source/10a sink 1.75v 50mv 50ma source/sink trmpwr 4.0v to 5.25v pgnd 0.75v 50mv 50ma source/sink 1.3v 0.1v diffsense reg1 reg2 source/sink regulator
ver 3.1 oct 03, 2001 tel: 886-3-5788833 http://www.gmt.com.tw 3 g261 global mixed-mode technology inc. application information figure 1. lvd scsi discrete resistor stack table1. resistor network v.s standard outputs specification 107.3 ? diff 100 ? to 110 ? 112.9mv diff bias 100mv to 125mv 237 ? common mode 100 ? to 300 ? 1.25v common mode 1.2v to 1.30v application note: the resistor network, along with the 1.75v and 0.75v references will give the correct dif- ferential impedance, bias voltage, common mode impedance and common mode voltage as show in table 1. layout guideline: 1. for stable operation, the 1f capacitor on termpwr pin and 4.7f capacitors on reg1 and reg2 pins must be placed within 0.25 inch of their respective pins. 2. the pcb trace length form lx- and lx+ to the connector pins (all 27pairs) must be of equal length, in order to minimize the signal skew among these pairs. in addition, these traces must be as short as possible, in order to minimize capacitance. ref 1.3v source/sink regulator 50 ma source/sink termpwr 50 ma source/sink diffsense reg1 reg2 source 5 to 15ma ref 1.75v ref 0.75v source/sink regulator 4.7f 4.7f 121 1% 121 1% l1- l1+ l27- l27+ 475 1% 475 1% 475 1% pgnd 475 1% 1.3v 0.1v 1.75v 50mv 0.75v 50mv 1f diffsense: source only from termpwr to diffsens pin ref 1.3v source/sink regulator 50 ma source/sink termpwr 50 ma source/sink diffsense reg1 reg2 source 5 to 15ma ref 1.75v ref 0.75v source/sink regulator 4.7f 4.7f 121 1% 121 1% l1- l1+ l27- l27+ 475 1% 475 1% 475 1% pgnd 475 1% 1.3v 0.1v 1.75v 50mv 0.75v 50mv 1f diffsense: source only from termpwr to diffsens pin
ver 3.1 oct 03, 2001 tel: 886-3-5788833 http://www.gmt.com.tw 4 g261 global mixed-mode technology inc. package information 8-pin sop note: 1.package body sizes exclude mold flash and gate burrs 2.dimension l is measured in gage plane 3.tolerance 0.10mm unless otherwise specified 4.controlling dimension is millimeter converted inch dimensions are not necessarily exact. dimension in mm dimension in inch symbol min. nom. max. min. nom. max. a 1.35 1.60 1.75 0.053 0.063 0.069 a1 0.10 ----- 0.25 0. 004 ----- 0. 010 a2 ----- 1.45 ----- ----- 0. 057 ----- b 0.33 ----- 0.51 0. 013 ----- 0. 020 c 0.19 ----- 0.25 0. 007 ----- 0. 010 d 4.80 ----- 5.00 0. 189 ----- 0. 197 e 3.80 ----- 4.00 0. 150 ----- 0. 157 e ----- 1.27 ----- ----- 0. 050 ----- h 5.80 ----- 6.20 0. 228 ----- 0. 244 l 0.40 ----- 1.27 0. 016 ----- 0. 050 y ----- ----- 0.10 ----- ----- 0. 004 0o ----- 8o 0o ----- 8o taping specification gmt inc. does not assume any res ponsibility for use of any circuitry described, no circuit patent licenses are implied and gmt inc. reserves the right at any t ime without notice to change said circuitry and specifications. d e h 7 (4x) a1 a2 a e b y c l d e h 7 (4x) a1 a2 a e b y c l feed direction typical sop package orientation feed direction typical sop package orientation
|
