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low power, 24-bit, 31.25 ksps, sigma-delta adc with true rail-to-rail buffers data sheet AD7172-4 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015C2016 analog devices, inc. all rights reserved. technical support www.analog.com features fast and flexible output rate: 1.25 sps to 31.25 ksps channel scan data rate of 6.21 ksps/channel (161 s settling) performance specifications 17.2 noise free bits at 31.25 ksps 24 noise free bits at 5 sps inl: 2 ppm of fsr 85 db rejection of 50 hz and 60 hz with 50 ms settling user configurable input channels 4 fully differential channels or 8 single-ended channels crosspoint multiplexer true rail-to-rail analog and reference input buffers internal or external clock power supply avdd1 = 3.0 v to 5.5 v, avdd2 = iovdd = 2 v to 5.5 v split supply with avdd1 and avss at 2.5 v or 1.65 v adc current: 1.5 ma temperature range: ?40c to +105c 3- or 4-wire serial digital interface (schmitt trigger on sclk) serial port interface (spi), qspi-, microwire-, and dsp- compatible applications process control: plc/dcs modules temperature and pressure measurement medical and scientific multichannel instrumentation chromatography general description the AD7172-4 is a low noise, low power, multiplexed, - analog- to-digital converter (adc) with 4- or 8-channel (fully differential/ single-ended) inputs for low bandwidth signals. the AD7172-4 has a maximum channel scan rate of 6.21 ksps (161 s) for fully settled data. the output data rates range from 1.25 sps to 31.25 ksps. the AD7172-4 integrates key analog and digital signal condition- ing blocks to allow users to configure an individual setup for each analog input channel in use via the spi. integrated true rail-to- rail buffers on the analog inputs and reference inputs provide easy to drive high impedance inputs. the digital filter allows simult aneous 50 hz and 60 hz rejection at a 27.27 sps output data rate . the user can switch between different filter options according to the demands of each channel in the application, with further digital processing functions such as offset and gain calibration registers, which are configurable on a per channel basis. general-purpose input/outputs (gpios) control external multiplexers synchronous to the adc conversion timing. the specified temperature range is ?40c to +105c. the AD7172-4 is in a 5 mm 5 mm, 32-lead lfcsp. note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only. functional block diagram avdd1 avdd avss avss pdsw gpio0 gpio1 gpo2 gpo3 xtal1 xtal2/clkio dgnd ref? ref+ avdd2 regcap a ain0/ref2? a in1/ref2+ ain7 ain8 - ? adc 1.8v ldo 1.8v ldo iovdd regcapd serial interface and control digital filter AD7172-4 xtal and internal clock oscillator circuitry cs sclk din dout/rdy sync error i/o and external mux control 12676-001 rail-to-rail reference input buffers rail-to-rail analog input buffers crosspoint multiplexer figure 1.
ad7172- 4 data sheet rev. a | page 2 of 61 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specificatio ns ..................................................................................... 4 timing characteristics ................................................................ 7 timing diagrams .......................................................................... 7 absolute maximum ratings ............................................................ 8 ther mal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 noise performance and resolution .............................................. 17 getting started ................................................................................ 18 power supplies ............................................................................ 19 digital communication ............................................................. 19 ad7172 - 4 reset .......................................................................... 20 configuration overview ........................................................... 20 circuit description ......................................................................... 26 buffered analog input ............................................................... 26 crosspoint multiplexer .............................................................. 26 ad7172 - 4 reference .................................................................. 27 buffered r eference input ........................................................... 28 clock source ............................................................................... 28 digital filters ................................................................................... 29 sinc5 + sinc1 filter ..................................................................... 29 sinc3 filter ................................................................................... 29 single cycle set tling ................................................................... 30 enhanced 50 hz and 60 hz rejection filters ......................... 33 operating modes ............................................................................ 35 continuous conversion mode ................................................. 35 continuous read mode ............................................................. 36 single c onversion mode ........................................................... 37 standby and power - down modes ............................................ 38 calibration ................................................................................... 38 digital interface .............................................................................. 39 checksum p rotection ................................................................. 39 crc calculation ......................................................................... 40 integrated functions ...................................................................... 42 general - purpose input/output ................................................ 42 external multiplexer control ................................................... 42 delay ............................................................................................ 42 16- bit/24 - bit conversions ......................................................... 42 dout_reset ........................................................................... 42 synchronization .......................................................................... 42 error flags ................................................................................... 43 data_stat ............................................................................... 43 iostrength ........................................................................... 43 grounding and layout .................................................................. 44 register summary .......................................................................... 45 register det ails ............................................................................... 47 communications register ......................................................... 47 status register ............................................................................. 48 adc mode register ................................................................... 49 interface mode register ............................................................ 50 register check ............................................................................ 51 data register ............................................................................... 51 gpio configuration register ................................................... 52 id register ................................................................................... 53 channel register 0 ..................................................................... 54 channel re gister 1 to channel register 7 .............................. 55 setup configuration register 0 ................................................ 56 setup configuration register 1 to setup configuration register 7 ..................................................................................... 57 filter configuration register 0 ................................................. 58 filter configuration register 1 to filter configuration register 7 ..................................................................................... 59 offset register 0 ......................................................................... 59 offset register 1 to offset register 7 ....................................... 59 gain register 0 ............................................................................ 60 gain registe r 1 to gain register 7 ........................................... 60 outline dimensions ....................................................................... 61 ordering guide .......................................................................... 61
draft data sheet ad7172- 4 rev. a | page 3 of 61 revision history 5 /16 rev. 0 to rev. a moved revision history ................................................................... 3 changes to table 5 ............................................................................ 9 changes to figure 18 and figure 19 ............................................. 13 changes to power supplies section .............................................. 19 5 /1 5 revision 0 : initial version
AD7172-4 data sheet rev. a | page 4 of 61 specifications avdd1 = 3.0 v to 5.5 v, avdd2 = iovdd = 2 v to 5.5 v, avss = dgnd = 0 v, ref+ = 2.5 v, ref? = avss, mclk = internal master clock = 2 mhz, t a = t min to t max (?40c to +105c), unless otherwise noted. table 1 . parameter test conditions/comment s min typ max unit adc speed and performance output data rate (odr) 1.25 31,250 sps no missing codes 1 excluding sinc3 filter 15 ksps 24 bits resolution see table 6 and table 7 noise see table 6 and table 7 accuracy integral nonlinearity (inl) 2 5 .2 ppm of fsr offset error 2 internal short 75 v offset drift internal short 230 nv/c gain error 2 avdd1 = 5 v 5 45 ppm of fsr gain drift 0.2 0.5 ppm/c rejection power supply rejection avdd1, avdd2, v in = 1 v 98 db common - mode rejection v in = 0.1 v at dc 95 db at 50 hz, 60 hz 1 20 hz output data rate (postfilter), 50 hz 1 hz and 60 hz 1 hz 120 db normal mode rejection 1 50 hz 1 hz and 60 hz 1 hz internal clock, 20 sps odr (postfilter) 71 90 db external clock, 20 sps odr (postfilter) 85 90 db analog inputs differential input range v ref = (ref+) ? (ref?) v ref v absolute voltage limits 1 input buffers disabled avss ? 0.05 avdd1 + 0.05 v input buffers enabled avss avdd1 v analog input current input buffers disabled input current 6 a/v input current drift 0.45 n a/v/c input buffers enabled input current 5 .5 na input current drift 0.1 na/c crosstalk 1 khz input ?120 db reference inputs differential input range v ref = (ref+) ? (ref?) 1 2.5 avdd1 v absolute voltage limits 1 input buffers disabled avss ? 0.05 avdd1 + 0.05 v input buffers enabled avss avdd1 v refin input current input buffers disabled input current 9 a/v input current drift external clock 0.75 n a/v/c internal clock 1 na/v/c input buffers enabled input current 100 na input current drift 2.5 na/c normal mode rejection 1 see the rejection parameter common - mode rejection 95 db burnout currents source/sink current analog input buffers must be enabled 10 a
data sheet ad7172- 4 rev. a | page 5 of 61 parameter test conditions/comment s min typ max unit g pio (gpio0, gpio1) with respect to avss input mode leakage current 1 ?10 +10 a floating state output capacitance 5 pf output voltage 1 high, v oh i source = 200 a avss + 4 v low, v ol i sink = 800 a avss + 0.4 v input voltage 1 high, v ih avss + 3 v low, v il avss + 0.7 v clock internal clock frequency 2 mhz accuracy ?2. 6 % +2.5% % duty cycle 50 % output voltage low, v ol 0.4 v high, v oh 0.8 iovdd v crystal frequency 14 16 16.384 mhz startup time 10 s external clock (clkio) 2 2.048 mhz duty cycle 1 30 50 70 % logic inputs input voltage 1 high, v inh 2 v iovdd < 2.3 v 0.65 iovdd v 2.3 v iovdd 5.5 v 0.7 iovdd v low, v inl 2 v iovdd < 2.3 v 0.35 iovdd v 2.3 v iovdd 5.5 v 0.7 v hysteresis 1 iovdd 2.7 v 0.08 0.25 v iovdd < 2.7 v 0.04 0.2 v leakage currents ?10 +10 a logic output (dout/ rdy ) output voltage 1 high, v oh iovdd 4.5 v, i source = 1 ma 0.8 iovdd v 2.7 v iovdd < 4.5 v, i source = 500 a 0.8 iovdd v iovdd < 2.7 v, i source = 200 a 0.8 iovdd v low, v ol iovdd 4.5 v, i sink = 2 ma 0.4 v 2.7 v iovdd < 4.5 v, i sink = 1 ma 0.4 v iovdd < 2.7 v, i sink = 400 a 0.4 v leakage current floating state ?10 +10 a output capacitance floating state 10 pf system calibration 1 full - scale (fs) calibration limit 1.05 fs v zero - scale calibration limit ?1.05 fs v input span 0.8 fs 2.1 fs v power requirements power supply voltage avdd1 to avss 3.0 5.5 v avdd2 to avss 2 5.5 v avss to dgnd ?2.75 0 v iovdd to dgnd 2 5.5 v iovdd to avss for avss < dgnd 6.35 v
ad7172- 4 data sheet rev. a | page 6 of 61 parameter test conditions/comment s min typ max unit power supply currents all outputs unloaded, digital inputs connected to iovdd or dgnd full operating mode avdd1 current avdd1 = 5 v typical, 5.5 v maximum ain and ref buffers disabled 0.23 0.2 9 ma ain and ref buffers enabled 1. 7 2 .15 ma each buffer: ain and ref 0.38 ma avdd1 = 3.3 v typical, 3.6 v maximum 1 ain and ref buffers disabled 0.15 0. 2 ma ain and ref buffers enabled 1.4 5 1. 9 ma each buffer: ain and ref 0.33 ma avdd2 current 1 1.1 ma iovdd current external clock 0.33 0.5 ma internal clock 0.61 0.82 ma external crystal 0.98 ma standby mode ldo on 32 a power - down mode full power - down including ldo 1 10 a power dissipation full operating mode unbuffer ed, external clock ; avdd1 = 3.3 v, avdd2 = 2 v, iovdd = 2 v 3.16 mw unbuffered, external clock; all supplies = 5 v 7.8 mw unbuffered, external clock ; all supplies = 5.5 v 10.4 mw fully buffer ed, internal clock; avdd1 = 3.3 v, avdd2 = 2 v, iovdd = 2 v 8 mw fully buffered, internal clock; all supplies = 5 v 1 6.6 mw fully buffered, internal clock ; all supplies = 5.5 v 2 2 .4 mw standby mode a ll supplies = 5 v 160 w power - down mode full power - down, all supplies = 5 v 5 w full power - down, all supplies = 5.5 v 55 w 1 specification is not production tested but is supported by characterization data at initial product release . 2 following a system or internal zero - scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. a system full - scale ca libration reduces the gain error to the order of the noise for the programme d output data rate.
data sheet AD7172-4 rev. a | page 7 of 61 timing characteristi cs iovdd = 2 v to 5.5 v, dgnd = 0 v, input logic 0 = 0 v, input logic 1 = iovdd, c load = 20 pf, unless otherwise noted. table 2. parameter limit at t min , t max unit test conditions/comments 1 , 2 sclk t 3 25 ns min sclk high pulse width t 4 25 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 15 ns max iovdd = 4.75 v to 5.5 v 40 ns max iovdd = 2 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 12.5 ns max iovdd = 4.75 v to 5.5 v 25 ns max iovdd = 2 v to 3.6 v t 5 2.5 ns min bus relinquish time after cs inactive edge 20 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 5 10 ns min sclk inactive edge to dout/ rdy high/low write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 8 ns min data valid to sclk edge setup time t 10 8 ns min data valid to sclk edge hold time t 11 5 ns min cs rising edge to sclk edge hold time 1 sample tested during initial release to ensure compliance. 2 see figure 2 and figure 3 . 3 th is parameter is defined as the time required for the output to cross the v ol or v oh limits. 4 the sclk active edge is the falling edge of sclk. 5 dout/ rdy retur ns high after a read of the data register. in single conversion mode and continuous conversion mode, the same data can be read again, if required, while dout/ rdy is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. if the continuous read feature is enabled, the digital word can be read only once. timing diagrams t 2 t 3 t 4 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb 12676-003 figure 2 . read cycle timing diagram i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 12676-004 figure 3 . write cycle timing diagram
ad7172- 4 data sheet rev. a | page 8 of 61 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating avdd1, avdd2 to avss ?0.3 v to +6.5 v avdd1 to dgnd ?0.3 v to +6.5 v iovdd to dgnd ?0.3 v to +6.5 v iovdd to avss ?0.3 v to +7.5 v avss to dgnd ?3.25 v to +0.3 v analog input voltage to avss ?0.3 v to avdd1 + 0.3 v reference input voltage to avss ?0.3 v to avdd1 + 0.3 v digital input voltage to dgnd ?0.3 v to iovdd + 0.3 v digital output voltage to dgnd ?0.3 v to iovdd + 0.3 v analog input/digital input current 10 ma operating temperature range ?40c to +105c storage temperature range ?65c to +150c maximum junction temperature 150c lead soldering, reflow temperature 260c esd rating (hbm) 4 kv stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specifi cation is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for a device soldered on a jedec test board for surface - mount packages. table 4 . thermal resistance package type ja unit 32- lead, 5 mm 5 mm lfcsp 1 - layer jedec board 138 c/w 4 - layer jedec board 63 c/w 4 - layer jedec board with 9 t hermal v ias 41 c/w esd caution
data sheet AD7172-4 rev. a | page 9 of 61 pin configuration and function descriptions 24 ain3 23 ain2 22 gpo2 21 gpio1 20 gpio0 19 regcapd 18 dgnd 17 iovdd 1 2 3 4 5 6 7 8 ain0/ref2? ain1/ref2+ dnc regcapa avss avdd1 avdd2 pdsw 9 10 11 12 13 14 15 16 xtal1 xtal2/clkio dout/rdy din sclk cs error sync 32 31 30 29 28 27 26 25 ref+ ref? gpo3 ain8 ain7 ain6 ain5 ain4 AD7172-4 top view (not to scale) 12676-002 notes 1. dnc = do not connect. 2. solder the exposed pad to a similar pad on the pcb under the exposed pad to confer mechanical strength to the package and for heat dissipation . the exposed pad must be connected to avss through this pad on the pcb. figure 4 . pin configuration table 5 . pin function descriptions pin no. mnemonic type 1 description 1 ain0/ref2? ai analog input 0/reference 2 negative input terminal. a reference can be applied between the ref2+ and ref2? pins . ref2? can span from avss to avdd1 ? 1 v. analog inpu t 0 is selectable through the cross point multiplexer . reference 2 can be selected through the ref _selx bits in the setup configuratio n (setupconx) register s. 2 ain1/ref2+ ai analog input 1/reference 2 positive input terminal . a reference can be applied between the ref2+ and ref2? pins . ref2+ can span from avdd1 to avss + 1 v. analog input 1 is selectable through the crosspoint multiplexer . reference 2 can be selected through the ref_selx bits in the setup configuration (setupconx) register s. 3 dnc do not connect. do not connect to this pin . 4 regcapa ao analog ldo regulator output. decouple this pin to avss using a 1 f capacitor. 5 avss p negative analog supply. this supply ranges from 0 v to ?2.75 v and is nominally set to 0 v. 6 avdd1 p analog supply voltage 1. this voltage ranges from 3.0 v minimum to 5.5 v maximum with respect to avss. 7 avdd2 p analog supply voltage 2. this voltage ranges from 2 v to avdd1 with respect to avss. 8 pdsw ao power - down switch connected to avss. this pin is controlled by the pdsw bit in the gpiocon register. 9 xtal1 ai input 1 for crystal. 10 xtal2/clkio ai/di input 2 for crystal /clock input or output. see the clocksel bit s ettings in the adcmode register in table 28 for more information. 11 dout/ rdy do serial data output/data ready output. dout/ rdy is a dual purpose pin . this pin is a serial data output pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or contr ol registers. the data - word/control word information is placed on the dout/ rdy pin on the sclk falling edge and is valid on the sclk rising edge. when cs is high, the dout/ rdy output is tristated. when cs is low, and a register is not being read, dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can be used as an interrupt to a processor, indicating that valid data is available. 12 din di serial data input to the input shift register on the adc. data in this shift register is transferred to the control registers in the adc, with the register address (ra) bits of the communications register identifying the appropriate register. data is clocked in on the rising edge of sclk. 13 sclk di serial clock input. this serial clock input is for data t ransfers to and from the adc. the sclk pin has a schmitt trigger ed input, making the interface suitable for opto - isolated applications.
AD7172-4 data sheet rev. a | page 10 of 61 pin no. mnemonic type 1 description 14 cs di chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus. cs can be hardwired low, allowing the adc to operate in 3 - wire mode with the sclk, din, and dout pin s interfac ing with the device. whe n cs is high, the dout/ rdy output is tristated. 15 error di/o this pin can be used in one of the following three modes: active low error input mode: t his mode sets the adc_error bit in the status r egister. active low, open - drain error output mode : t he status register error bits are mapped to the error pin. the error pins of multiple devices can be wired together to a common pull - up resistor so that an error on any device can be observed. general - purpose output mode : t he status of the pin is controlled by the err_dat bit in the gpiocon register. the pin is referenced between iovdd and dgnd, as opposed to the avdd1 and avss levels used by the gpio 0 and gpio 1 pins. the error pin has an active pull - up in this case. 16 sync di synchronization input. this pin a llows synchroniz ation of the digital filters and analog modulators when using multiple ad7172 -4 devices. 17 iovdd p digital i nput /o utput supply voltage. the iovdd voltage ranges from 2 v to 5 v. iov dd is independent of avdd1 and avdd2. for example, iovdd can be operated at 3.3 v when avdd1 or avdd2 equa ls 5 v, or vice versa. if avss is set to ?2.5 v, the voltage on iovdd must not exceed 3. 6 v. 18 dgnd p digital ground. 19 regcapd ao digital ldo regulator output. this pin is for decoupling purposes only. decouple this pin to dgnd using a 1 f capacitor. 20 gpio0 i/o general - purpose input/output. 0 the l ogic input/output on this this pin is referred to the avdd1 and avss supplies. 21 gpio1 i/o general - purpose input/output 1 . the l ogic input/output on this this pin is referred to the avdd1 and avss supplies. 22 gpo2 o general - purpose output. the l ogic output on this this pin is referred t o the avdd1 and avss supplies. 23 ain2 ai analog input 2. analog inpu t 2 is s electable through the crosspoint multiplexer. 24 ain3 ai analog input 3. analog inpu t 3 is s electable through the crosspoint multiplexer. 25 ain4 ai analog input 4. analog inpu t 4 is s electable through the crosspoint multiplexer. 26 ain5 ai analog input 5. analog inpu t 5 is s electable through the crosspoint multiplexer. 27 ain6 ai analog input 6. analog inpu t 6 is s electable through the crosspoint multiplexer. 28 ain7 ai analog input 7. analog inpu t 7 is s electable through the crosspoint multiplexer. 29 ain8 ai analog input 8. analog inpu t 8 is s electable through the crosspoint multiplexer. 30 gpo3 o general - purpose output. the logic output on this this pin is referred to the avdd1 and avss supplies. 31 ref? ai reference 1 input negative terminal. ref? can span from avss to avdd1 ? 1 v. reference 1 can be selected through the ref_selx bits in the setup configuration (setupconx ) register s. 32 ref+ ai reference 1 input positive terminal. a reference can be applied between ref+ and ref?. ref+ can span from avdd1 to avss + 1 v. reference 1 can be selected through the ref_selx bits in the setup configuration (setupconx) register s. ep p exposed pad. solder t he exposed pad to a similar pad on the printed circuit board (pcb) under the exposed pad to confer mechanical strength to the package and for heat dissipation. the exposed pad must be connected to avss through this pad on the pcb. 1 ai is analog input, ao is analog o utput , di/o is bidirectional digital input/output, do is digital output, di is digital inpu t, and p is power s upply , i/o is input/output, and o is output .
data sheet ad7172- 4 rev. a | page 11 of 61 typical performance characteristics avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, t a = 25c, unless otherwise noted. 0 200 400 600 800 1000 adc code sample number 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 12676-205 figure 5 . noise (analog input buffers disabled, v ref = 5 v, output data rate = 1.25 sps) 0 200 400 600 800 1000 100 300 500 700 900 adc code sample number 8388460 8388465 8388470 8388475 8388480 8388485 8388490 8388495 8388500 8388505 8388510 12676-206 figure 6 . noise (analog input buffers disabled, v ref = 5 v, output data rate = 2.6 ksps) 0 200 400 600 800 1000 100 300 500 700 900 adc code sample number 8388440 8388450 8388460 8388470 8388480 8388490 8388500 8388510 8388520 8388530 8388540 12676-207 figure 7 . noise (analog input buffers disabled, v ref = 5 v, output data rate = 31.25 ksps) occurence adc code 0 1200 1000 800 600 400 200 8388480 8388482 8388484 8388486 8388488 8388490 8388492 12676-208 figure 8 . histogram (analog input buffers disabled, v ref = 5 v, output data rate = 1.25 sps) occurence adc code 0 140 120 100 80 60 40 20 8388465 8388467 8388469 8388471 8388473 8388475 8388477 8388479 8388481 8388483 8388485 8388487 8388489 8388491 8388493 8388495 8388497 8388499 8388501 8388503 8388505 12676-209 figure 9 . histogram (analog input buffers disabled, v ref = 5 v, output data rate = 2.6 ksps) occurence adc code 0 100 80 60 40 20 90 70 50 30 10 8388446 8388449 8388452 8388455 8388458 8388461 8388464 8388467 8388470 8388473 8388476 8388479 8388482 8388485 8388488 8388491 8388494 8388497 8388500 8388503 8388506 8388509 8388512 8388515 8388518 8388521 8388524 8388527 8388530 8388533 12676-210 figure 10 . histogram (analog input buffers disabled, v ref = 5 v, output data rate = 31.25 ksps)
ad7172- 4 data sheet rev. a | page 12 of 61 0 200 400 600 800 1000 adc code sample number 8388481 8388483 8388485 8388487 8388489 8388491 8388493 8388495 12676-2 1 1 figure 11 . noise (analog input buffers enabled, v ref = 5 v, output data rate = 1.25 sps) 0 200 400 600 800 1000 100 300 500 700 900 adc code sample number 8388460 8388470 8388480 8388490 8388500 8388510 8388520 12676-212 figure 12 . noise (analog input buffers enabled, v ref = 5 v, output data rate = 2.6 ksps) 0 200 400 600 800 1000 100 300 500 700 900 adc code sample number 8388400 8388420 8388440 8388460 8388480 8388500 8388520 8388540 8388560 12676-213 figure 13 . noise (analog input buffers enabled, v ref = 5 v, output data rate = 31.25 ksps) occurence adc code 0 1200 1000 800 600 400 200 8388482 8388484 8388486 8388488 8388490 8388494 8388492 12676-214 figure 14 . histogram (analog input buffers enabled, v ref = 5 v, output data rate = 1.25 sps) occurence adc code 0 120 100 80 60 40 20 8388462 8388464 8388466 8388468 8388470 8388472 8388474 8388476 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 8388494 8388496 8388498 8388500 8388502 8388504 8388506 8388508 8388510 8388512 8388514 8388516 12676-215 figure 15 . histogram (analog input buffers enabled, v ref = 5 v, output data rate = 2.6 ksps) occurence adc code 0 120 100 80 60 40 20 8388422 8388430 8388438 8388446 8388454 8388462 8388470 8388478 8388486 8388494 8388502 8388510 8388518 8388526 8388534 8388542 12676-216 figure 16 . histogram (analog input buffers enabled, v ref = 5 v, output data rate = 31.25 ksps)
data sheet ad7172- 4 rev. a | page 13 of 61 noise (v rms) frequency (mhz) 0 0.000002 0.000004 0.000006 0.000008 0.000010 0.000012 0.000014 0.000016 0.000018 0.000020 1000 201000 401000 601000 801000 1001000 1201000 1401000 1601000 1801000 analog input buffers off analog input buffers on 12676-218 figure 17 . n oise vs. external master clock frequency, analog input buffers on and off 1 10 100 1k 10k 100k 1m cmrr (db) v in frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 12676-224 figure 18 . common - mode rejection ratio (cmrr) vs. v in frequency (v in = 0.1 v, output data rate = 31.25 ksps) 10 20 30 40 50 60 70 cmrr (db) v in frequency (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 12676-225 figure 19 . common - mode rejection ratio (cmrr) vs. v in frequency (v in = 0.1 v, 10 hz to 70 hz, output data rate = 20 sps, enhanced filter) 1 10 100 1k 10k 100k 100m 10m 1m psrr (db) v in frequency (hz) ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 12676-226 figure 20 . power supply rejection ratio (psrr) vs. v in frequency ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 inl (ppm/fs) v in (v) ?6 ?4 ?2 0 2 4 6 12676-227 crystal buffers off crystal buffers on clk buffers off clk buffers on 2.5v reference, analog input buffers off 2.5v reference, analog input buffers on 5v reference, analog input buffers off 5v reference, analog input buffers on figure 21 . integral nonlinearity (inl) vs. v in (differential input) occurence inl (ppm) 0 35 30 25 20 15 10 5 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 12676-228 figure 22 . inl distribution histogram ( differential input, a ll input buffers enabled, v ref = 2.5 v ex ternal, 100 u nits)
ad7172- 4 data sheet rev. a | page 14 of 61 occurence inl (ppm) 0 40 35 30 25 20 15 10 5 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 12676-229 figure 23 . inl distribution histogram (differential input, a ll input buffers disabled, v ref = 2.5 v external, 100 units) occurence inl (ppm) 0 50 45 40 35 30 25 20 15 10 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 12676-230 figure 24 . inl distribution histogram (a ll input buffers enabled, differential input, v ref = 5 v external, 100 units) occurence inl (ppm) 0 40 35 30 25 20 15 10 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 12676-231 figure 25 . inl distribution histogram (a ll input buffers disabled, differential input, v ref = 5 v external, 100 units) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 inl (ppm) temperature (c) 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 a in buffers on a in buffers off 12676-232 figure 26 . inl vs. temperature (differential input, v ref = 2.5 v external) occurence frequency (mhz) 0 35 30 25 20 15 10 5 1. 9 96 1. 9 97 1. 9 98 1. 9 99 2.00 2. 0 01 2. 0 02 2. 0 03 12676-233 figure 27 . internal oscillator frequency/accuracy distribution histogram (100 units) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 frequency (hz) temperature (c) 1.95 1.96 1.97 1.98 1.99 2.00 2.01 12676-234 figure 28 . internal oscillator frequency vs. temperature
data sheet ad7172- 4 rev. a | page 15 of 61 occurence offset (v) 0 30 25 20 15 10 5 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 12676-236 figure 29 . offset error distribution histogram (internal short, 100 units) occurence offset drift (nv/c) 0 14 10 12 8 6 4 2 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 110 100 80 70 90 12676-237 figure 30 . offset error drift distribution histogram (internal short, 100 units) occurence gain error (ppm of fsr) 0 25 20 15 10 5 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 6 5 4 12676-238 figure 31 . gain error distribution histogram (a ll input buffers enabled, 100 units) occurence gain error (ppm of fsr) 0 25 20 15 10 5 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 6 5 4 12676-239 figure 32 . gain error distribution histogram (a ll input buffers disabled, 100 units) occurence gain drift (ppm/c) 0 35 30 25 20 15 10 5 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 12676-240 figure 33 . gain drift distribution histogram (a ll i nput buffers enabled, 100 units) occurence gain drift (ppm/c) 0 30 25 20 15 10 5 ?0.05 0 0.05 0.10 0.15 0.20 0.25 12676-241 figure 34 . gain drift distribution histogram (a ll input buffers disabled, 100 units)
ad7172- 4 data sheet rev. a | page 16 of 61 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 current (a) temperature (c) 0 700 600 500 400 300 200 100 12676-243 figure 35 . current consumption vs . temperature (standby mode) 9.5 10.5 10.4 10.3 10.2 10.1 10.0 9.9 9.8 9.7 9.6 occurence current (a) 0 45 40 35 30 25 20 15 10 5 12676-245 figure 36 . burnout current distribution histogram (100 units) input current (na) input voltage (v) ?10 10 5 0 ?5 ?5.00 ?4.62 ?4.29 ?3.96 ?3.63 ?3.30 ?2.97 ?2.64 ?2.31 ?1.98 ?1.65 ?1.32 ?990.00m ?660.00m ?330.00m 0 330.00m 660.00m 990.00m 1.32 1.65 1.98 2.31 2.64 2.97 3.30 3.63 3.96 4.29 4.62 5.00 ?40c, ain? ?40c, ain+ +25c, ain? +25c, ain+ +85c, ain? +85c, ain+ +105c, ain? 12676-246 figure 37 . analog inp ut current vs. input voltage (v cm = 2.5 v) ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 current (na) temperature (c) ?15 15 10 5 0 ?5 ?10 ain+ = avdd1 ? 0.2v ain? = avss + 0.2v ain+ = avdd1 ain? = avss 12676-247 figure 38 . analog input current vs. temperature
data sheet AD7172-4 rev. a | page 17 of 61 noise performance and resolution table 6 and table 7 show the rms noise, peak - to - peak noise, effective resolution , and the noise free (peak - to - peak) resolutio n of the ad7172 -4 for various output data rates and filters. the numbers given are for the bipolar input range with a 5 v reference. these numbers are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a single channel. it is important to note that the peak - to - peak resolution is calculated based on the peak - to - peak noise. the peak - to - peak resolution represents the resolution for which there is no code flicker. table 6 . rms noise and peak -to - peak resolution vs. output data rate us ing the sinc5 + sinc1 filter (default) 1 output data rate (sps) rms noise (v rms) effective resolution (bits) peak - to - peak noise (v p - p) peak - to - peak resolution (bits) input buffers disabled 31,250 8.2 20.2 66 17.2 15,625 7.0 20.4 52 17.5 10,417 6.0 20.7 45 17.8 1007 2.2 22.2 15 19.3 59.52 0.48 24 3.2 21.6 49.68 0.47 24 3.1 21.6 16.63 0.25 24 1.6 22.6 1.25 0.088 24 0.32 24 input buffers enabled 31,250 9.5 20 74 17 15,625 8.2 20.2 63 17.3 10,417 7.1 20.4 53 17.5 1007 2.6 21.9 16 19.3 59.52 0.62 24 3.6 21.4 49.68 0.53 24 3.3 21.5 16.63 0.32 24 1.7 22.2 1.25 0.089 24 0.35 24 1 selected rates only, 1000 samples. table 7 . rms noise and peak -to - peak resolution vs. output data rate u sing the sinc3 filter 1 output data rate (sps) rms noise (v rms) effective resolution (bits) peak - to - peak noise (v p - p) peak - to - peak resolution (bits) input buffers disabled 31,250 211 15.5 1600 12.5 15,625 27.2 18.5 205 15.6 10,417 7.9 20.3 57 17.4 1008 1.6 22.6 11 19.8 59.98 0.38 24 2.5 21.9 50 0.35 24 2.3 22 16.67 0.21 24 1.1 23.1 1.25 0.054 24 0.27 24 input buffers enabled 31,250 212 15.5 1600 12.5 15,625 27.7 18.5 210 15.5 10,417 8.5 20.2 63 17.3 1008 1.8 22.4 13 19.6 59.98 0.45 24 2.8 21.8 50 0.44 24 2.5 22 16.67 0.24 24 1.2 23 1.25 0.073 24 0.29 24 1 selected rates only, 1000 samples.
ad7172- 4 data sheet rev. a | page 18 of 61 getting started the ad7172 - 4 offers the user a fast settling, high resolution, multiplexed adc with high levels of configurability , including the following features: ? four fully differential or eight single - ended analog inputs. ? a c rosspoint multiplexer that selects any analog input c ombination as the input signals to be converted, routing them to the modulator positive or negative input. ? true rail - to - rail buffered analog and reference inputs. ? fully differential input s or single - ended input s relative to any analog input. ? per channel co nfigurability up to eight different setups can be defined. a separate setup can be mapped to each of the channels. each setup allows the user to configure whether the buffers are enabled or disabled, gain and offset correction, filter type, output data rat e, and refer ence source selection . the ad7172 - 4 includes two separate linear reg ulator blocks for both the analog and digital circuitry. the analog ldo regulator regulates the avdd2 supply to 1.8 v, supplying the adc core. tie the avdd1 and avdd2 supplies together for the easiest connection. if there is already a clean analog supply r ail in the system in the range of 2 v (minimum) to 5.5 v (maximum), the user can choose to connect this supply to th e avdd2 input, allowing lower power dissipation. dgnd AD7172-4 iovdd regcapd avss regcapa avdd2 avdd1 xtal1 31 32 29 28 27 2 1 9 10 11 12 13 17 18 19 6 7 4 5 6 8 5 3 1 4 7 2 ref? ref+ 4.7f 0.1f 0.1f v out gnd nc v in 0.1f 4.7f vin 0.1f adr44xbrz iovdd avdd2 0.1f avdd1 0.1f cx1 16mhz cx2 0.1f 1f 0.1f 1f optional external crystal circuitry capacitors clkin optional external clock input ain0/ref2? ain1/ref2+ ain6 ain7 ain8 xtal2/clkio dout/rdy din sclk dout/rdy din sclk cs 14 cs error 15 error sync 16 sync 12676-040 see the buffered analog input section for further details. figure 39 . typical connection diagram
data sheet ad7172- 4 rev. a | page 19 of 61 the linear regulator for the digital iovdd supply performs a similar function, regulating the input voltage applied at the iovdd pin to 1.8 v for the internal digital filtering. the serial interface signals always operate from the iovdd supply at the pin ; mean ing, if 3.3 v is applied to the iovdd pin, the interface logic inputs and outputs operate at this level. the ad7172 - 4 can be used across a wide variety of applications, providing high resolution and accuracy. a sample of these scenarios is as follows: ? fast scanning of analog input channels using the internal multiplexer ? fast scanning of analog input channels u sing an external multiplexer with automatic control from the gpios ? high resolution at lower speeds in either channel scanning or adc per channel applications ? single adc per channel: the fast low latency output allows further application specific filtering in external micro - controller s , dsp s , or fpga s power supplies the ad7172 - 4 has thr ee independent power supply pins: avdd1, avdd2, and iovdd. avdd1 powers the crosspoint multiplexer and integrated analog a nd reference input buffers. avdd1 is referenced to avss, and avdd1 ? avss = 3.3 v o r 5 v. av dd1 and avss can be a single 3.3 v or 5 v supply , or a 1.65 v or 2.5 v split supply. the split supply operation allows true bipolar inputs. when using split supplies, consider the absolute maximum ratings (see the absolute maximum ratings section). avdd2 powers the internal 1.8 v analog ldo regulator. this regulator powers the adc core. avdd2 is referenced to avss, and av dd2 to avss can range from 5.5 v (maximum) to 2 v (minimum). iovdd power s the internal 1.8 v digital ldo regulator. this regulator powers the digital logic of the adc. iovdd sets the voltage levels for the spi interface of the adc. iovdd is refer - enced to dgnd, and iovdd to dgnd can vary from 5.5 v (maximum) to 2 v (minimum). there are no specific requirements for a power supply sequence on the ad7172 - 4 . when all power supplies are stable, a device reset is required; see the ad7172 - 4 reset section for how to reset the device. recommended linear regulators the adp7118 provide s the positive supply rails, creating either a single 5 v or 3.3 v , or dual avdd1/iovdd , depending on the required supply configuration. the adp7118 can operate from input voltages up to 20 v. adp7118 ldo 5v: avdd1 adp7118 ldo 3.3v: avdd2/iovdd 12v input 12676-100 figure 40 . single s upply l inear r egulator the adm660 and adp7182 generate a clean negative rail for avss in the bipolar configuration to provide optimal converter performance. adp7118 ldo +2.5v: avdd1/avdd2 adp7118 ldo +3.3v: iovdd adp7182 ldo adm660 ldo ?2.5v: avss 5v input ?5v 12676-101 figure 41 . bipolar ad7172 - 4 s upply r ails table 8 . recommended power m anagement devices product description adp7118 20 v, 200 ma, l ow n oise, cmos ldo regulator adp7182 ?28 v, ?200 ma, l ow n oise, l inear r egulator adm660 cmos s witched capacitor v o ltage c onverter digital communicatio n the ad7172 - 4 has a 3 - or 4 - wire spi interface that is compatible with qspi?, microwire, and dsps. the interface operates in spi mode 3 and can be operated with cs tied low. in spi mode 3 , the sclk pin idles high, the falling edge of sclk is the drive edge, and the rising edge of sclk is the sample edge. this means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. drive edge sample edge 12676-052 figure 42 . spi mode 3 sclk edges accessing the adc register map the communications register controls access to the full register map of the adc. this register is an 8 - bit write only register. on power - up or after a reset, the digit al interface defaults to a state where it is expecting a write to the communications register; therefore, all communication begins by writing to the communications register. the data written to the communications register determines which register is being accessed and if the next operation is a read or write. the ra bits ( bits [5:0] in register 0x00 ) determine the specific register to which the read or write operation applies. when the read or write operation to the selected register is complete, the interface returns to its default state, where it expects a write operation to the communications register.
ad7172- 4 data sheet rev. a | page 20 of 61 figure 43 and figure 44 illustrate writing to and reading from a register by first writing the 8 - bit command to the communications register, followed by the data for that register. din sclk cs 8-bit command 8 bits, 16 bits, or 24 bits of data command data 12676-053 figure 43 . writing to a register (8 - bit command with register address followed b y data 8, 16, or 24 b its; data length on din is dependent on the register selected ) din sclk cs 8-bit command 8 bits, 16 bits, or 24 bits output command dat a dout/rd y 12676-054 figure 44 . reading from a register (8 - bit co mmand with register address followed by data of 8, 16, 24 bits; data length on dout / rdy is dependent on the register selected) reading the id register is the recommended method for verifying correct communication with the device. the id register is a read only register and contains the valu e 0x205x for the ad7172 - 4 . the communications register and the id register details are described in table 9 and table 10. ad7172 - 4 reset after a power - up cycle and when the power supplies are stable , a device reset is required. in situations where interface synchro - nization is lost , a device reset is also required. a write operation of at least 64 serial clock cycles with din high re turns the adc to its default state by resetting the entire device, including the register contents. alternatively, if cs is being used with the digital interface, returning cs high sets the digital interface to its default state and halts any serial interface operation. configuration overvi ew after power - on or reset, the ad7172 - 4 default configuration is as follows: ? channel configuration. ch0 is enabled, ain0 is selected as the positive input, and ain1 is selected as the negative input. setu p 0 is selected. ? setup configuration. t he analog input buffers are disabled and t he reference input buffers are also disabled. the ref pins are selected as the reference source. ? filter configuration. th e sinc5 + sinc 1 filter is selected and the maximum output data rate of 31.25 ksps is selected. ? adc mode. continuous conversion mode and the internal oscillator are enabled. ? interface m ode. crc and data + status outp ut are disabled. note that only a few of the register setting options are shown; this list is just an example. for full register information, see the register details s ection. fig ure 45 shows an overview of the suggested flow for changing the adc configuration, divided into the following three blocks: ? channel configur ation (see box a in fig ure 45) ? setup configuration (see box b in fig ure 45) ? adc mode and interface mode configuration (see box c in fig ure 45) channel configuration the ad7172 - 4 has eight independent channels and eight independent s etups. the user can select any of the analog input pairs on any channel, as well as any of the eight setups for any channel, giving the user full flexibility in the channel configuration. this also allows per channel configuration when using differential inputs and single - end ed inputs because each channel can have its own dedicated setup. channel registers the channel registers select which of the nine analog input pins (ain0 to ain8) are used as either the positive analog input (ain+) or the negative analog input (ain?) for t hat channel. this register also contains a channel enable/disable bit and the setup selection bits, which are used to select which of the eight availa ble setups to use for this setup channel. when the ad7172 - 4 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order , from channel 0 to channel 7. if a channel is disabled, it is skipped by the sequencer. details of the channel register for channel 0 are shown in table 11.
data sheet ad7172- 4 rev. a | page 21 of 61 adc mode and interface mode configuration select adc operating mode, clock source, enable crc, data + status, and more setup configuration 8 possible adc setups select filter order, output data rate, and more channel configuration select positive and negative input for each adc channel select one of 8 setups for adc channel a b c 12676-044 fig ure 45 . suggested adc configuration flow table 9 . communications register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w table 10 . id register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x07 id [15:8] id[15:8] 0x205x r [7:0] id[7:0] table 11 . channel register 0 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x10 ch0 [15:8] ch_en0 setup_sel0 reserved ainpos0[4:3] 0x8001 rw [7:0] ainpos0[2:0] ainneg0
ad7172- 4 dat a sheet rev. a | page 22 of 61 adc setups the ad7172 - 4 has eight independent setups. each setup consists of the following four registers: ? setup configuration register ? filter configuration register ? gain register ? offset register for example, setup 0 consists of setup configuration register 0, filter configuration register 0, gain register 0, and offset register 0. figure 46 sho ws the grouping of these registers the setup is selectable from the channel registers (see the channel configuration section), which allows each chann el to be assigned to on e of eight separate setups. table 12 through table 15 show the four registers that are associated with setup 0. this structure is repeated for setup 1 to setup 7 . setup configuration registers the setup configuration registers allow the user to select the output coding of the adc by selecting between bipolar mode and unipolar mode . in bipolar mode, the adc accepts negative differential input voltages, and the output coding is offset binary. in unipolar mode, the adc accepts only positive differe ntial voltages, and the coding is straight binary. in either case, the input voltage must be within the avdd1/ avss supply voltages. the user can selec t the reference source using th e s e register s . three options are available: a reference connected between t he ref+ and ref? pins , b etween ref2+ and ref2? pins , or using av dd1 ? avs s. the analog input and reference input buffers can also be enabled or disabled using th e s e register s. filter configuration registers the filter configuration register s select which digital filter is used at the output of the adc modulator. the order of the filter and the output data rate are selected by setting the bits in the s e register s . for more information, see the digital filters section. setup config registers filter config registers offset registers gain registers* select peripheral functions for adc channel select digital filter type and output data rate analog input buffers reference input buffers burnout reference source 31.25ksps to 1.25sps sinc5 + sinc1 sinc3 enhanced 50/60 sinc3 map gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 12676-045 figure 46 . adc setup register grouping table 12 . setup configuration register 0 reg. name b its bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] reserved bi_unipolar0 refbuf0+ refbuf0? ainbuf0+ ainbuf0? 0x1000 rw [7:0] burnout_en0 reserved ref_sel0 reserved table 13 . filter configuration r egister 0 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x28 filtcon0 [15:8] sinc3_map0 reserved enhfilten0 enhfilt0 0x0500 rw [7:0] reserved order0 odr0 table 14 . gain register 0 reg. name bits bit s 23:0 reset rw 0x38 gain0 [23:0] gain0[23:0] 0x5xxxx0 rw table 15 . offset register 0 reg. name bits bit s 23:0 reset rw 0x30 offset0 [23:0] offset0[23:0] 0x800000 rw
data sheet ad7172- 4 rev. a | page 23 of 61 gain registers the gain register s are 24- bit register s that hold the gain calibration coefficient for the adc. the gain registers are read/write registers. these registers are configured at power - on with factory calibrated coefficients. therefore, every device has different default coefficients. the default value is automatically overwritten if the user initiates a system full - scale cali bration or writes to a gain register. for more information on calibration, see the operating modes section. offset registers the offset register s hold the offset calibration coefficient for the adc. the power - on reset value of the offset register s is 0x800000. the offset register s a re 24 - bit read/write register s . the power - on reset value is automatically overwritten if the user initiates an internal or system zero - scale calibration or if the user writes to an offset register. adc mode and interface mode configuration the adc mode register and the interface mode register configure the core peripherals for use by the ad7172 - 4 and the mode for the digital interface. adc mode register the adc mode reg ister primarily set s the conversion mode of the adc to either continuous or single conversion. the user can also select the standby and power - down modes, as well as any of the c alibration modes. in addition, this register contains the clock source select b its the reference select bits are contained in the setup configuration registers (see the adc setups section for more informatio n). the details of thi s register are shown in table 16. interface mode register the interface mode register configures the digital interface operation. this register allows the user to control data - word length, crc enable, data plus status read, and continuous read mode. the details of this register are shown in table 17 . for more information, see the digital interface section. table 16 . adc m ode register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adcmode [15:8] reserved hide_delay sing_cyc reserved delay 0x2000 rw [7:0] reserved mode clocksel reserved table 17 . interface mode register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x02 ifmode [15:8] reserved alt_sync iostrength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en reserved wl16
ad7172- 4 data sheet rev. a | page 24 of 61 understanding configuration flexibility the most straightforward implementation of the ad7172 - 4 is to use four differenti al inputs with adjacent analog inputs and run all of them with the same setup, gain correction, and offset correction register s . in this case, the user selects the following differential inputs: ain0/ain1, ain2/ain3, ain4/ain5, and ain6/ain7. in figure 47 , the registers shown in black font must be programmed for such a configuration. the registers that are shown in gray font are redundant in this configu ration. programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks. an alternative way to implement these four fully differential inputs is to take advantage of four of the eight ava ilable setups. motivation for doing this includes having a different speed/noise requirement on each of the differential inputs, or a specific offset or gain correction may be needed for each channel. figure 48 shows how each of the differential inputs can use a separate setup, allowing full flexibility in the configuration of each channel. setup config registers channel registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input parts enable the channel select setup 0 select digital filter type and output data rate analog input buffers reference input buffers burnout reference source 31.25ksps to 1.25sps sinc5 + sinc1 sinc3 sinc3 map enhanced 50/60 gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 0x14 ch4 0x15 ch5 0x16 ch6 0x17 ch7 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 12676-046 figure 47 . four fully differential inputs, using a single setup (setupcon0 , filtcon0, gain0 , offset0) setup config registers channel registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input parts enable the channel select setup 0 select digital filter type and output data rate analog input buffers reference input buffers burnout reference source 31.25ksps to 1.25sps sinc5 + sinc1 sinc3 sinc3 map enhanced 50/60 gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 0x14 ch4 0x15 ch5 0x16 ch6 0x17 ch7 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 12676-047 figure 48 . four fully differential inputs with one setup per channel
data sheet ad7172- 4 rev. a | page 25 of 61 figure 49 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. in this example, three differential inputs and two single - ended inputs are required. the single - ended inputs are the ain4/ain8 and ain7/ain8 combinations. the differential input pairs are ain0/ain1 and ain2/ain3 , both using setup 0 , and ain5/ain6 using setup 2. the two single - ended input pairs are set up as diagnostics , and in this example use separate set ups , namely setup 1 and setup 4. given that five setups are selected for use, the setupcon0 to setupcon4 registe rs are pro - g rammed as required, and the filtcon0 to filtcon4 registers are programmed as required . o ptiona l gain and offset correction can be employed on a per setup basis by programming gain0 and gain1 and offset0 and offset1. in the example shown in figure 49 , the ch0 to ch4 registers are used. setting the msb in each of these registers, the ch_en0 to ch_en4 bits enable the five combinations via the crosspoint mux. when the ad7172 - 4 converts, the sequencer transitions in ascending sequential order from ch0 t hrough ch4 before looping back to ch0 to repe at the sequence. setup config registers channel registers filter config registers offset registers gain registers* select peripheral functions for adc channel select analog input parts enable the channel select setup 0 select digital filter type and output data rate analog input buffers reference input buffers burnout reference source 31.25ksps to 1.25sps sinc5 + sinc1 sinc3 sinc3 map enhanced 50/60 gain correction optionally programmed per setup as required (*factory calibrated) offset correction optionally programmed per setup as required 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 setupcon3 setupcon5 setupcon6 setupcon7 setupcon4 setupcon0 setupcon2 setupcon1 filtcon3 filtcon5 filtcon6 filtcon7 filtcon4 filtcon0 filtcon2 filtcon1 gain3 gain5 gain6 gain7 gain4 gain0 gain2 gain1 offset3 offset5 offset6 offset7 offset4 offset0 offset2 offset1 0x10 ch0 0x11 ch1 0x12 ch2 0x13 ch3 0x14 ch4 0x15 ch5 0x16 ch6 0x17 ch7 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 12676-048 figure 49 . mixed differential and single - ended configuration using multiple shared setups
ad7172- 4 data sheet rev. a | page 26 of 61 circuit description buffered analog inpu t the ad7172 - 4 has true rail - to - rail, integrated, precision unity - gain buffers on both adc analo g inputs. the buffers provide high input impedance with only 5 .5 na typical input current, allowing high impedance sources to be c onnected directly to the analog inputs. the buffers fully drive the internal adc switch capacitor sampling network, simplifying the analog front - end circuit requireme nts while consuming a very efficient 0. 3 8 ma typical per buffer. each analo g input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f nois e of the buffer. the 1/f noise profile of the adc and buffer combined is shown in figure 50. 0.1 1 10 100 1k 10k amplitude (db) frequency (hz) ?250 ?200 ?150 ?100 ?50 0 12676-255 figure 50 . shorted input fast fourier transform (fft), analog input buffers enabled the analog input buffers do not suffer from linearity degradation when operating at the rails, unlike many discrete amplifiers. when operating at or close to the avdd1 and avss supply rails, there is an increase in inp ut current. this increase is most notable at higher temperatures. figure 37 and figure 38 show the input current for various conditions. with the analog input bu ffers disabled, the average input current to the ad7172 - 4 changes linearl y with t he differential input voltage at a rate of 6 a / v. crosspoint multiplex er there are nine analog input pins: ain0 to ain8. each of these pins connects to the internal crosspoint multiplexer. the crosspoint multiplexer enables any of these inputs to be confi gured as an input pair, either single - ended or fully differential. the ad7172 - 4 c an have up to eight active channels. when more than one channel is enabled, the channels are automatically sequenced in order from the lowest enabled channel number to the highest enabled channel number. the output of the multiplexer is connected to the in put of the integrated true rail - to - rail buffers. these buffers can be bypassed and the multiplexer output can be directly connected to the switched capacitor input of the adc. the simplified analog input circuit is shown in figure 51. ain0 ain1 a vdd1 a vss a vss a vss a vdd1 a vss ain2 a vdd1 ain4 a vdd1 ain3 a vdd1 a vss ?1 cs1 cs2 +in ?in ?2 ?2 ?1 12676-056 figure 51 . simplified analog input circuit the cs1 and cs2 capacitors have a magnitude in the order of a number of picofarads each. this capacitance is the combination of both the sampling capacitance and the parasitic capacitance. fully differential inputs because the ain0 to ain8 analog inputs are connected to a crosspoint multiplexer, any combination of signals c an create an analog input pair. this allows the user to select four fully differential inputs or eight single - ended inputs. if four fully differential input paths are connected to the ad7172 - 4 , using adjacent analog inputs for the differential input pair, such as ain2/ain3, is recommended. this is due to the relative locations of thes e pins to each other. decouple a ll analog inputs to avss. single - ended inputs the user can also choose to measure eight different single - ended analog inputs. in this case, each of the analog inputs is converted as the difference between the single - ended in put to be measured and a set analog input common pin. because there is a crosspoint multiplexer, the user can set any of the analog inputs as the common pin. an example of such a scenario is to connect the ain4 pin to avss and then select this input when c onfiguring the crosspoint multiplexer. w hen using the ad7172 - 4 with single - ended inputs, inl degrade s.
data sheet ad7172- 4 rev. a | page 27 of 61 ad7172 - 4 reference the ad7172 - 4 offers th e user the option of either supplying a reference to the ref or ref2 pin s of the device or using av dd1 C avs s . select the reference source to be used by the analog input by setting the ref_selx bits (bits[5:4]) in the setup configuration registers appropriately. the structure of the setup configuration 0 register is shown in table 18 . the ad7172- 4 defaults on power - up to use the ref+ and ref? reference inputs, ref+ and ref ? . standard low noise, low drift voltage references, such as the adr445 , adr444 , and adr441 , are recommended for use. apply the reference to the ad7172 - 4 reference pins as shown in figure 52 . decouple the output of the reference to avss. as shown in figure 52, the adr441 output is decoupled with a 0.1 f capacitor at its output for stability purposes. the output is then connected to a 4 .7 f capacitor, which acts as a reservoir for any dynamic charge required by the adc, and followed by a 0.1 f decoupl ing capacitor at the ref+ input. this capacitor is placed as close as possible to the ref+ and ref? pins. the ref? pin is connected direc tly to the avss potential. 31 32 ref? ref+ 4.7f 0.1f 1 1 1 1 1 0.1f 0.1f 3v to 18v adr441 2 2.5v v ref AD7172-4 1 all decoupling is to avss. 2 any of the adr44x family of references can be used. the adr441 enables reuse of the 3.3v analog supply needed for avdd1 to power the reference v in . 12676-159 figure 52 . adr441 c onnected to a d7172 - 4 ref pins table 18 . setup configuration 0 register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] reserved bi_unipolar0 refbuf0+ refbuf0? ainbuf0+ ainbuf0? 0x1000 rw [7:0] burnout_en0 reserved ref_sel0 reserved table 19 . adc mode register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adcmode [15:8] r eserved hide_delay sing_cyc reserved delay 0x2 000 rw [7:0] r eserved mode clocksel reserved
AD7172-4 data sheet rev. a | page 28 of 61 buffered reference input the AD7172-4 has true rail-to-rail, integrated, precision unity gain buffers on both adc reference inputs. the buffers provide the benefit of providing high input impedance and allowing high impedance external sources to be directly connected to the reference inputs. the integrated reference buffers can fully drive the internal reference switch capacitor sampling network, simplifying the reference circuit requirements while consuming a very efficient 0.38 ma typical per buffer. each reference input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. when using a reference, such as the adr445 , adr444 , or adr441 , these buffers are not required because these references, with proper decoupling, can drive the reference inputs directly. clock source the AD7172-4 uses a nominal master clock of 2 mhz. the AD7172-4 can source its sampling clock from one of three sources: ? an internal oscillator ? an external crystal (use a 16 mhz crystal automatically divided internally to set the 2 mhz clock) ? an external clock source all output data rates listed in the data sheet relate to a master clock rate of 2 mhz. using a lower clock frequency from, for instance, an external source scales any listed data rate propor- tionally. to achieve the specified data rates, particularly rates for rejection of 50 hz and 60 hz, use a 2 mhz clock. the source of the master clock is selected by setting the clocksel bits (bits[3:2]) in the adc mode register as shown in table 19. the default operation on power-up and reset of the AD7172-4 is to operate with the internal oscillator. it is possible to fine tune the output data rate and filter notch at low output data rates using the sinc3_mapx bit. see the sinc3 filter section for more information. internal oscillator the internal oscillator runs at 16 mhz and is internally divided down to 2 mhz for the modulator and can be used as the adc master clock. the internal oscillator is the default clock source for the AD7172-4 and is specified with an accuracy of ?2.6% to +2.5%. there is an option to allow the internal clock oscillator to be output on the xtal2/clkio pin. the clock output is driven to the iovdd logic level. this option can affect the dc performance of the AD7172-4 due to the disturbance introduced by the output driver. the extent to which the performance is affected depends on the iovdd voltage supply. higher iovdd voltages create a wider logic output swing from the driver and affect performance to a greater extent. this effect is further exaggerated if the iostrength bit is set at higher iovdd levels (see table 29 for more information). external crystal if higher precision, lower jitter clock sources are required, the AD7172-4 can use an external crystal to generate the master clock. the crystal is connected to the xtal1 and xtal2/clkio pins. a recommended crystal for use is the fa-20h, a 16 mhz, 10 ppm, 9 pf crystal from epson-toyocom that is available in a surface-mount package. as shown in figure 53, insert two capacitors (cx1 and cx2) from the traces connecting the crystal to the xtal1 and xtal2/clkio pins. these capacitors allow circuit tuning. connect these capacitors to the dgnd pin. the value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the xtal1 and xtal2/clkio pins. therefore, the values of these capacitors differ depending on the pcb layout and the crystal employed. 9 10 cx1 cx2 xtal1 x tal2/clki o 1 decouple to dgnd. AD7172-4 1 1 12676-160 figure 53. external crystal connections the external crystal circuitry can be sensitive to the sclk edges, depending on the sclk frequency, iovdd voltage, crystal circuitry layout, and the crystal used. during crystal startup, any disturbances caused by the slck edges may cause double edges on the crystal input, resulting in invalid conversions until the crystal voltage has reached a high enough level such that any interference from the sclk edges is insufficient to cause double clocking. this double clocking can be avoided by ensuring that the crystal circuitry has reached a sufficient voltage level after startup before applying any sclk. due to the nature of the crystal circuitry, it is therefore recommended that empirical testing of the circuit be performed under the required conditions, with the final pcb layout and crystal, to ensure correct operation. external clock the AD7172-4 can also use an externally supplied clock. in systems where this is desirable, the external clock is routed to the xtal2/clkio pin. in this configuration, the xtal2/ clkio pin accepts the externally sourced clock and routes it to the modulator. the logic level of this clock input is defined by the voltage applied to the iovdd pin.
data sheet ad7172- 4 rev. a | page 29 of 61 digital filters the ad7172 - 4 has three flexible filter options to allow optimization of noise, settling time, and rejection: ? the s inc5 + sinc1 filter ? the s inc3 filter ? enhanced 50 hz and 60 hz rejection filters sinc1 sinc5 sinc3 50hz and 60hz postfilter 12676-058 figure 54 . digital filter block diagram the filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. each channel can use a different setup and therefore, a different filter and output data rate. see the register details section for more information. sinc5 + sinc1 filter the sinc5 + sinc1 filter is targeted at multiplexed applications and achieves sing le cycle settling at output data rates of 2.6 ksps and l ess . the sinc5 block output is fixed at the maximum rate of 31.25 ksps, and the sinc1 block output data rate can be varied to control the final adc output data rate. figure 55 shows the frequency domain response of the sinc5 + sinc1 filter at a 50 sps output data rate . the sinc5 + sinc1 filter has a slow roll - off ov er frequency and narrow notches. 0 ?120 0 150 100 50 filter gain (db) frequency (hz) ?100 ?80 ?60 ?40 ?20 12676-059 figure 55 . sinc5 + sinc1 filter response at 50 sps odr the output data rates with the accompanying settling time and rms noise for the sinc5 + sinc1 filter are shown in table 20 and table 21. sinc3 filter the sinc3 filter achieves the best single - channel noise performance at lower rates and is, therefore, most suitable for single - channel applications. the sinc3 filter always has a settling time equal to t settle = 3/ output data rate figure 56 shows the frequency domain filter response for the sinc3 filter. the sinc3 filter has good roll - off over frequency and has wide notches for good notch frequency rejection. 0 ?120 0 150 100 50 filter gain (db) frequency (hz) ?100 ?80 ?60 ?40 ?20 ?110 ?90 ?70 ?50 ?30 ?10 12676-060 figure 56 . sinc3 filter response the output data rates with the accompanying settling time and rms noise for the sinc3 filter are shown in table 22 and table 23 . it is possible to fine tune the output data rate for the sinc3 filter by setting the sinc3_mapx bit in the filter configuration registers. i f this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. all other options are eliminated. the data rate when on a single channel can be calculated using the following equation: 4:0] filtconx[1 f rate data output mod = 32 where: f mod is the modulator rate (mclk/2) and is equal to 1 mhz. filtconx[14:0] are the contents on the filter configuration registers , excluding the msb. for example, an output data rate of 50 sps can be achieved with sinc3_mapx enabled by setting the filtconx[14:0] bits to a value of 625.
AD7172-4 data sheet rev. a | page 30 of 61 single cycle settlin g the ad7172 -4 can be configured by setting the sing_cyc bit in the adc mode register so that only fully settled data is output, thus effectively putting the adc into a single cycle settling mode. thi s mode achieves single cycle settling by reducing the output data rate to be equal to the settling time of the adc for the selected o utput data rate. this bit has no effect with the sinc5 + sinc1 filter at output data rates of 2.6 ksps and l ess. figure 57 shows a step on the analog input with single cycle settling mode disabled and the sinc3 filter selected. the analog input requires at least three cycle s after the step change for the output to reach the final settled value. 1/odr analog input fully settled adc output 12676-061 figure 57 . step input w ithout single cycle settling figure 58 shows the same step on the analog input but with single cycle settling enabled. the analog input requires at least a single cycle for the output to be fully settled. the output data rate, as indicated by the rdy signal, is now reduced to equal the settling time of the filter at the selected output data rate. t settle analog input fully settled adc output 12676-062 figure 58 . step input with single cycle settling table 20 . output data rate, settling time, and noise using the sinc5 + sinc1 filter with input buffers disabled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling time 1 notch frequency (hz) noise (v rms) effective resolution with 5 v reference (bits) noise (v p - p) 2 peak - to - peak resolution with 5 v reference (bits) 31,250 6211 161 s 31,250 8.2 20.2 66 17.2 15,625 5181 193 s 15,625 7.0 20.4 52 17.5 10,417 4444 225 s 10,417 6.0 20.7 45 17.8 5208 3115 321 s 5208 4.5 21.1 33 18.2 2597 2597 385 s 3906 3.9 21.3 29 18.4 1007 1007 993 s 1157 2.2 22.2 15 19.3 503.8 503.8 1.99 ms 539 1.5 22.6 10 19.9 381 381 2.63 ms 401 1.3 22.9 9.1 20.1 200.3 200.3 4.99 ms 206 0.88 23.3 6.1 20.6 100.2 100.2 9.99 ms 102 0.64 23.8 4.2 21.2 59.52 59.52 16.8 ms 59.98 0.48 24 3.2 21.6 49.68 49.68 20.13 ms 50 0.47 24 3.1 21.6 20.01 20.01 49.98 ms 20 0.27 24 1.7 22.4 16.63 16.63 60.13 ms 16.67 0.25 24 1.6 22.6 10 10 100 ms 10 0.2 24 1.1 23.1 5 5 200 ms 5 0.14 24 0.75 24 2.5 2.5 400 ms 2.5 0.091 24 0.32 24 1.25 1.25 800 ms 1.25 0.088 24 0.32 24 1 the settling time is rounded to the nearest microsecond. this is reflected in the output data rate and channel switching rate. channel switching rate = 1 settling time. 2 1000 samples .
data sheet AD7172-4 rev. a | page 31 of 61 table 21 . output data rate, settling time, and noise using the sinc5 + sinc1 filter with input buffers enabled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling time 1 notch frequency (hz) noise (v rms) effective resolution with 5 v reference (bits) noise (v p - p) 2 peak - to - peak resolution with 5 v reference (bits) 31,250 6211 161 s 31,250 9.5 20 74 17 15,625 5181 193 s 15,625 8.2 20.2 63 17.3 10,417 4444 225 s 10,417 7.1 20.4 53 17.5 5208 3115 321 s 5208 5.3 20.9 39 18 2597 2597 385 s 3906 4.7 21 29 18.4 1007 1007 993 s 1157 2.6 21.9 16 19.3 503.8 503.8 1.99 ms 539 1.8 22.4 12 19.7 381 381 2.63 ms 401 1.6 22.6 11 19.8 200.3 200.3 4.99 ms 206 1.1 23.1 7.5 20.3 100.2 100.2 9.99 ms 102 0.75 23.6 5.1 21 59.52 59.52 16.8 ms 59.98 0.62 24 3.6 21.4 49.68 49.68 20.13 ms 50 0.53 24 3.3 21.5 20.01 20.01 49.98 ms 20 0.32 24 1.8 22.4 16.63 16.63 60.13 ms 16.67 0.32 24 1.7 22.5 10 10 100 ms 10 0.25 24 1.2 23 5 5 200 ms 5 0.18 24 0.83 23.5 2.5 2.5 400 ms 2.5 0.11 24 0.35 24 1.25 1.25 800 ms 1.25 0.089 24 0.35 24 1 the settling time is rounded to the nearest microsecond. this is reflected in the outpu t data rate and channel switching rate. channel swit ching rate = 1 settling time. 2 1000 samples .
AD7172-4 data sheet rev. a | page 32 of 61 table 22 . output data rate, settling time, and noise using the sinc3 filter with input buffers disabled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling time 1 notch frequency (hz) noise (v rms) effective resolution with 5 v reference (bits) noise (v p - p) 2 peak - to - peak resolution with 5 v reference (bits) 31,250 10,309 97 s 31,250 211 15.5 1600 12.5 15,625 5,181 193 s 15,625 27.2 18.5 205 15.6 10,417 3,460 289 s 10,417 7.9 20.3 57 17.4 5,208 1,733 577 s 5,208 3.7 21.4 27 18.5 2,604 867.3 1.15 ms 2,604 2.5 21.9 17 19.2 1,008 335.9 2.98 ms 1,008 1.6 22.6 11 19.8 504 167.98 5.95 ms 504 1.1 23.1 7.5 20.3 400.6 133.5 7.49 ms 400.6 0.99 23.3 6.7 20.5 200.3 66.67 14.98 ms 200.3 0.68 23.7 4.6 21 100.2 33.39 29.95 ms 100.2 0.47 24 3.1 21.6 59.98 19.99 50.02 ms 59.98 0.38 24 2.5 21.9 50 16.67 60 ms 50 0.35 24 2.3 22 20.01 6.67 149.95 ms 20.01 0.21 24 1.2 23 16.67 5.56 180 ms 16.67 0.21 24 1.1 23.1 10 3.33 300 ms 10 0.18 24 0.83 23.5 5 1.67 600 ms 5 0.18 24 0.56 24 2.5 0.83 1.2 sec 2.5 0.16 24 0.41 24 1.25 0.42 2.4 sec 1.25 0.054 24 0.27 24 1 the settling time is rounded to the nearest microsecond. this is reflected in the output data rate and channel switching rate. channel switching r ate = 1 settling time . 2 1000 samples . table 23 . output data rate, settling time, and noise using the sinc3 filter with input buffers enabled default output data rate (sps); sing_cyc = 0 and single channel enabled 1 output data rate (sps/channel); sing_cyc = 1 or with multiple channels enabled 1 settling time 1 notch frequency (hz) noise (v rms) effective resolution with 5 v reference (bits) noise (v p - p) 2 peak - to - peak resolution with 5 v reference (bits) 31,250 10,309 97 s 31,250 212 15.5 1600 12.5 15,625 5,181 193 s 15,625 27.7 18.5 210 15.5 10,417 3,460 289 s 10,417 8.5 20.2 63 17.3 5,208 1,733 577 s 5,208 4.3 21.2 28 18.4 2,604 867.3 1.15 ms 2,604 3.0 21.7 20 19 1,008 335.9 2.98 ms 1,008 1.8 22.4 13 19.6 504 167.98 5.95 ms 504 1.3 22.9 8.9 20.1 400.6 133.5 7.49 ms 400.6 1.2 23 8.2 20.2 200.3 66.67 14.98 ms 200.3 0.82 23.5 5.6 20.8 100.2 33.39 29.95 ms 100.2 0.57 24 3.8 21.3 59.98 19.99 50.02 ms 59.98 0.45 24 2.8 21.8 50 16.67 60 ms 50 0.44 24 2.5 22 20.01 6.67 149.95 ms 20.01 0.26 24 1.3 22.9 16.67 5.56 180 ms 16.67 0.24 24 1.2 23 10 3.33 300 ms 10 0.19 24 0.91 23.4 5 1.67 600 ms 5 0.12 24 0.62 24 2.5 0.83 1.2 sec 2.5 0.098 24 0.45 24 1.25 0.42 2.4 sec 1.25 0.073 24 0.29 24 1 the settling time is rounded to the nearest microsecond. this is reflected in the output data rate and channel switching rate. channel switching rate = 1 settling time. 2 1000 samples .
data sheet AD7172-4 rev. a | page 33 of 61 enhanced 50 h z and 60 h z rejection filters the enhanced filters provide rejection of 50 hz and 60 hz simultaneously and allow the user to trade off settling time and rejection. these filters can operate up to 27.27 sps or can reject up to 90 db of 50 hz 1 hz and 60 hz 1 hz interference. these filters are operated by postfiltering the output of the sinc5 + sinc1 filter. for this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters to achieve the specified settling time and noise performance. table 24 shows the output data rates with the accompanying settling time, rejection, and rms noise. figure 59 to figure 66 show the frequency domain plots of the responses from the enhanced filters. table 24 . enhanced filters output data rate, noise, settling time, and rejection using the enhanced filters output data rate (sps) settling time (ms) simultaneous rejection of 50 hz 1 hz and 60 hz 1 hz(db) 1 noise (v rms) peak - to - peak resolution (bits) comments 27.27 36.67 47 0.45 21.4 see figure 59 and figure 62 25 40.0 62 0.44 21.4 see figure 60 and figure 63 20 50.0 85 0.41 21.7 see figure 61 and figure 64 16.667 60.0 90 0.417 21.7 see figure 65 and figure 66 1 maste r clock = 2 .00 mhz. 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 12676-063 figure 59 . 27.27 sps odr, 36.67 ms settling time 0 ?100 0 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 600 100 200 300 400 500 12676-065 figure 60 . 25 sp s odr, 40 ms settling time 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 12676-067 figure 61 . 20 sps odr, 50 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12468-064 figure 62 . 27.2 7 sps odr, 36.67 ms settling tim e ( 40 hz to 70 hz )
ad7172- 4 data sheet rev. a | page 34 of 61 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12676-066 figure 63 . 25 sps od r, 40 ms settling time (40 hz to 70 hz) 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12676-068 figure 64 . 20 sps odr, 50 ms settling time (40 hz to 70 hz) 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 12676-069 figure 65 . 16.667 sps odr, 60 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 12676-070 figure 66 . 16.667 sps odr, 60 ms settling time (40 hz to 70 hz)
data sheet ad7172- 4 rev. a | page 35 of 61 operating modes the ad7172 - 4 has a number of operating modes that can be set from the adc mode register and interface mode register (see table 28 and table 29 ). these modes are as follows and are described in the following sections : ? continuous conversion mode ? continuous read mode ? single conversion mode ? standby mode ? power - down mode ? calibration modes (three) continuous conversio n mode continuous conversion mode is the default power - up mode. the ad7172 - 4 converts continuously, and the rdy bit in the status register goes low each time a conversion is complete. if cs is low, the rdy output also goes low when a conversion is complete. to read a conversion, write to the communications register to indicat e that the next operation is a read of the data register. when the data - word h as been read from the data register, the dout/ rdy pin goes high. the user can read this register additional times, if required. however, ensure that the data register is not being accessed at the completion of the next conversion; ot herwise, the new conversion word is lost. when several channels are enabled, the adc automatically sequences through the enabled channels, performing one conversion on each channel. when all the channels have been converted, the sequence starts again with the first channel. the channels are converted in order from the lowest enabled channel to the highest enabled channel. the data register is updated as soon as each conversion is available. the rdy output pulses low each time a conversion is available. the user can then read the c onversion while the adc converts the next enabled channel . if the data_stat bit in the interface mode register is set to 1, the contents of the stat us register, along with the conversion data, are output each time the data register is read. the status register indicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x44 0x44 data data 12676-071 figure 67 . continuous conversion mode
ad7172- 4 data sheet rev. a | page 36 of 61 continuous read mode in continuous read mode, it is not required to write to the communications register before reading adc data; apply only the required number o f sclks after the rdy ou tput goes low to indicate the end of a conversion. when the conversion is read, the rdy output returns high until the next conversion is available. in this mode, the d ata can be read only once. e nsure that the data - word is read befor e the next conversion is complete. if the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the ad7172 - 4 to read the data - word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output se rial register. the adc must be configured for continuous conversion mode to use continuous read mode. to enable continuous read mode, set the contread bit in the interface mode register. when this bit is set, the only serial interface operations possible a re reads from the data register. to exit con - tinuous read mode, issue a dummy read of the adc data register command (0x44) while the rdy output is low. alternatively, apply a software reset, that is, 64 sclks with cs = 0 and din = 1. this resets the adc and all register contents. these are the only commands that the interface recognizes after it is placed in continuous read mode. hold din low in continuous read mode until an instruction is to be written to the device. if multiple adc channels are enabled, each channel is output in turn, with the status bits being appended to the data if the data_stat bit is set in the interface mode register. the status register indicates the channel to which the conversion corresponds. din sclk dout/rd y cs 0x02 data data data 0x0080 12676-072 figure 68 . continuous read mode
data she et ad7172- 4 rev. a | page 37 of 61 single conversion mo de in single conversion mode, the ad7172 - 4 performs a single conversion and is placed in standby mode after the conversion is complete . the rdy output goes low to indicate the completion of a conversion . when the data - word has been read from the data register, the rdy output goes high. the data register can be read several times, if required, even when the rdy output has gone high. if several channels are enabled, the adc automatically sequences through the enabled channels and performs a conversion on each channel. when a conversion is started, the rdy output go es high and remains high until a valid conversion is available and cs is low. when the conversion is available, the rdy output goes low. the adc then selects the next channel and begins a conversion. the user can re ad the present conversion while the next conversion is being performed. when the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. when the adc has performed a single conver sion on each of the selected channels, it returns to standby mode. if the data_stat bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read . the two lsbs of the status register indicate the channel to which the conversion corresponds . din sclk dout/rdy cs 0x01 0x44 data 0x8010 12676-073 figure 69 . single conversion mode
ad7172- 4 data sheet rev. a | page 38 of 61 standby and power - down modes in standb y mode, most blocks are powered down. the ldo regulator s remain active so that the registers maintain their contents. the crystal oscillator remains active if selected. to power down the clock in standby mode, set the clocksel bits in the adc mode register to 00 (internal oscillator mode ). in power - down mode, all blocks are powered down, including the ldo regulator s. a ll registers lo se their contents, and the gpio outputs are placed in three - state. to prevent accidental entry to power - down mode, the adc must first be placed in standby mode. exiting power - down mode requires 64 sclks with cs = 0 and din = 1, that is, a serial interface reset. a delay of 500 s is recommended before issuing a subsequent serial interface command to allow the ldo regulator to power up. calibration the ad7172 - 4 allows a two - point calibration to be performed to eliminate any offset and gain errors. three calibration modes are used to eliminate these offset and gain errors on a per setup basis: ? internal zero - scale calibration mode ? system zero - scale calibration mode ? system full - scale calibration mode there is no internal full - scale calibration mode b e cause this is calibrated in the factory at the time of production. only one channel can be active during calibration. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the default value of the offset register is 0x800000, and the nomi nal value of the gain register is 0x555555. the calibration range of the adc gain is from 0.4 v ref to 1.05 v ref . the following equations show the calculations that are used . in unipolar mode, the ideal relationship that is, not taking into account the adc gain error and offset error is as follows: 2 400000 x 0 ) 0 80000 x 0 ( 2 75 . 0 23 ? ? ? ? ? ? ? ? = gain offset v v data ref in in bipolar mode, the ideal relationship ? that is, not taking into account the adc gain error and offset error ? is as follows: 800000 x 0 400000 x 0 ) 800000 x 0 ( 2 0.75 23 + ? ? ? ? ? ? ? ? = gain offset v v data ref in to start a calibration, write the rel evant value to the mode bits in the adc mode register. the dout/ rdy pin and the rdy bit in the status register go high when the calibration initiates. when the calibration is complete, the contents of the corre sponding offset or gain register are updated, the rdy bit in the status register is reset and the rdy output pin returns low (if cs is low), and the ad7172 - 4 reverts to standby mode. during an internal offset calibration, the selected positive analog input pin is disconnected, and both modulator inputs are connected internally to the selected negative analog input pin. therefore , it is necessary to ensure that the voltage on the select ed negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. however, for s ystem calibrations the system zero - scale (offset) and system full - scale (gain) voltages must be applied to the adc pins before initiating the calibration modes. as a result, errors external to the adc are removed. from an operational point of view, treat a calibration like another adc conversion. an offset calibration, if required, must always be performed before a full - scale cali bration. set the system software to monitor the rdy bit in the status register or the rdy output to determine the end of a calibration via a polling sequence or an interrupt driven routine. all calibrations req uire a time equal to the settling time of the selected filter and output data rate to be completed. an internal offset calibration, system zero - scale calibration, and system full - scale calibration can be performed at any output data rate. using lower outpu t data rates results in better calibration accuracy and is accurate for all output data rates. a new offset calibration is required for a given channel if the reference source for that channel is changed. the offset error is typically 75 v and an offset calibration reduces the offset error to the order of the noise. the gain error is factory calibrated at ambient temperature. following this calibration, the gain error is typically 5 ppm of fsr. the ad7172 - 4 provides the user with access to the on - chip calibration registers, allowing the microprocessor to read the calibration coeffici ents of the device and to write its own calibration coefficients. a read or write of the offset and gain registers can be performed at any time except during an internal or self calibration.
data sheet ad7172- 4 rev. a | page 39 of 61 digital interface the programmable functions of the ad7172 - 4 are controlled via the spi. the serial interface of the ad7172 - 4 consists of four signals: cs , din, sclk, and dout/ rdy . the din input transfer s data into the on - chip registers, and the dout output access e s data from the on - chip registers. sclk is the serial clock input for the device, and all data transfers (either on the din input or on the dout output) occur with respect to the sclk signal. the dout/ rdy pin also functions as a dat a ready signal, with the output going low if cs is low when a new data - word is available in the data register. the rdy output is reset high when a read operation from the data register is complete. the rdy output also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. take care to avoid reading from the data register when the rdy output is about to go low. the best method to ensure that no data read occurs is to always monitor the rdy output . s tart reading the data register as soon as the rdy output goes l ow , and ensure a sufficient sclk rate, such that the read is completed before the next conversion result . cs is used to select a d evice. cs can decode the ad7172 - 4 in systems where seve ral components are connected to the serial bus. figure 2 and figure 3 show timing diagrams for interfacing to the ad7172 - 4 using cs to decode the device. figure 2 shows the timing for a read operation from the ad7172 - 4 , and figure 3 shows the timing for a write operation to the ad7172 - 4 . it is possible to read from the data register several times even though the rdy output returns high after the first read operation. however, take care to ensure that the read operations are complete before the next output update occurs. in continuous read mode, the data register can be read only once. operate t he serial interface in 3 - wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy pins are used to communicate with the ad7172 - 4 . the end of the conversion can also be monitored using the rdy bit in the status register. the ad7172 - 4 can be reset by writing 64 sclks with cs = 0 and din = 1. a reset returns the interface to the state in which it expects a write to the communications register. this operation resets the contents of all registers to their power - on values. following a reset, allow a period of 500 s before addressing the serial interface. checksum protection the ad7172 - 4 has a checksum mode that can improve interface robustness. using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. if an error occurs during a register write, the crc_error bit is set in the status register. however, to e nsure that the register write i s successful, read back the register and verify the checksum. for crc checksum calculations during a write operation, the following polynomial is always used: x 8 + x 2 + x + 1 during read operations, the user can select between this polynomial and a simpler exclusive or ( xor ) function. the xor function requires less time to process on the host microcontroller than the polynomial - based checksum. the crc_en bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple xor check. the checksum is appended to the end of each read and write transaction. the checksum calculation for the write transaction is calculated using the 8 - bit command word and the 8 - bit to 24- bit data. for a read transaction, the checksum is calculated using the command word and the 8 - bit to 32 - bit data output. figure 70 and figure 71 show spi write and read transactions, res pectively. 8-bit command 8-bit crc up to 24-bit input cs data crc cs din sclk 12676-074 figure 70 . spi write transaction with crc 8-bit command 8-bit crc up to 32-bit output cmd data crc cs din sclk dout/ rdy 12676-075 figure 71 . spi read transaction with crc if checksum protection is enabled when continuous read mode is active, an implied read data command of 0x44 before every data transmission must be accounted for when calculating the checksum value. this implied read data command ensures a nonzero checksum value even if the adc data equals 0x000000.
ad7172- 4 data sheet rev. a | page 40 of 61 crc calculation polynomial the checksum, which is eight bits wide, is generated using the polynomial x 8 + x 2 + x + 1 to generate the checksum, the data is left shifted by eight bits to create a number ending in eight logic 0s. the polynomial is aligned so that the msb is adjacent to the leftmost logic 1 of the data. an xor function is applied to the data to produce a new, shorter number. the polynomial is again aligned so that its msb is adjacent to the leftmost logic 1 of the new result, and the procedure is repeated. this process repeats until the original data is reduced to a value less than the polynomial. this is the 8 - bit checksum. example of a polynomial crc calculation 24- bit word: 0x654321 ( 8 - bit command and 16 - bit data) an example of generating the 8 - bit checksum using the polynomial based checksum is as follows: initial value 011001010100001100100001 01100101010000110010000100000000 left shifted eight bits x 8 + x 2 + x + 1 = 100000111 polynomial 100100100000110010000100000000 xor result 100000111 polynomial 100011000110010000100000000 xor result 100000111 polynomial 11111110010000100000000 xor result 100000111 polynomial value 1111101110000100000000 xor result 100000111 polynomial value 111100000000100000000 xor result 100000111 polynomial value 11100111000100000000 xor result 100000111 polynomial value 1100100100100000000 xor result 100000111 polynomial value 100101010100000000 xor result 100000111 polynomial value 101101100000000 xor result 100000111 polynomial value 1101011000000 xor result 100000111 polynomial value 101010110000 xor result 100000111 polynomial valu e 1010001000 xor result 100000111 polynomial value 10000110 checksum = 0x86
data sheet ad7172- 4 rev. a | page 41 of 61 xor calculation the checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an xor of the bytes. example of an xor calculation 24- bit word: 0x654321 ( 8 - bit command and 16 - bit data) using the previous example, divide into three bytes: 0x65, 0x43, and 0x21 01100101 0x65 01000011 0x43 00100110 xor result 00100001 0x21 00000111 crc
ad7172- 4 data sheet rev. a | page 42 of 61 integrated functions the ad7172 - 4 has integrated functions that improve the usefulness of a number of applications as well as serve diagnostic purposes in safety conscious applications. general - purpose i nput /o utput the ad7172 - 4 has two digital gpio pins (gpio0 and gpio1) and two general - purpose digital output pins (gpo2 and gpo3). as the naming convention suggests, the gpio0 and gpio1 pins can be configured as inputs or outputs, but gpo2 and gpo3 are outputs only. the gpio x and gpo x pins are enabled using the follo wing bits in the gpiocon register: ip_en0, ip_en1 (or op_en0, op_en1) for gpio0 and gpio1, and op_en2_3 for gpo2 and gpo3. when the gpio0 pin or the gpio1 pin is enabled as an input, the logic level at the pin is contained in the gp_data0 or gp_data1 bit, respectively. when the gpio0, gpio1, gpo2, or gpo3 pin is enabled as an output, the gp_data0, gp_data1, gp_data2, or gp_dat a3 bit, respectively, determine the logic level output at the pin. the logic levels for these pins are referenced to avdd1 and avs s. the error pin can also be used as a general - purpose output. when the err_en bits in the gpiocon register are set to 11, the error pin operates as a general - purpose output. in this configuration, the err_dat bit in the gp iocon register determines the logic level output at the pin. the logic level for the pin is referenced to iovdd and dgnd. all general - purpose outputs have an active pull - up. external multiplexer control if an external multiplexer is used to increase the c hannel count, the multiplexer logic pins can be controlled via the ad7172 - 4 gpiox pins. with the mux_io bit, the gpiox timing is controlled by the adc; therefore, the channel change is synchronized with the adc, eliminating any need for external synchronization. delay it is possible to insert a programmable delay before the ad7172 - 4 begins to take samples. this delay allows an external amplifier or multipl exer to settle and can also alleviate the specification requirements for the external amplifier or multiplexer. eight programmable settings, ranging from 0 s to 8 ms, can be set using the delay bits in the adc mode register (register 0x01, bits[10:8]). if a delay greater than 0 s is selected and the hide_delay bit in the adc mode register is set to 0, this delay is added to the conversion time, regardless of the selected output data rate. when using the sinc5 + sinc1 filter, it is possible to hide this de lay such that the output data rate remains the same as the output data rate without the delay enabled. if the hide_delay bit is set to 1 and the selected delay is less than half of the conversion time, the delay can be absorbed by reducing the number of av erages the digital filter performs, which keeps the conversion time the same but can affect the noise performance. the effect on the noise performance depends on the delay time compared to the conversion time. it is possible to absorb the delay only for o utput data rates less than 2.6 ksps with the exception of the following four rates, which cannot absorb any d elay: 381 sps , 59.5 2 sps, 49. 68 sps, an d 16.66 sps. 16- bit/24 - bit conversions by default, the ad7172 - 4 generates 24 - bit conversions. however, the width of the conversions can be reduced to 16 bits. setting the wl16 bit in the i nterface mode register to 1 rounds all data conversions to 16 bits. clearing this bit sets the width of the data conversions to 24 bits. dout_reset the serial interface uses a shared dout/ rdy pin. by default, this pin outputs the rdy signal. during a data read, this pin outputs the data from the register being read. after the read is complete, the pin reverts to outputting the rdy signal after a short fixed period of time (t 7 ). however, this time may be too short for some microcontrollers and can be extended until the cs pin is brought high by setting the dout_reset bit in the interface mode register to 1. this setting means that cs must frame each read operation and compete the serial interface transaction. synchronization normal synchronization when the sync_en bit in the gpiocon register is set to 1, the sync pin functions as a synchronization input. the sync input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the device . this feature allow s the user to start to gather samples of the analog input from a known point, the rising edge of the sync input. the sync input must be low for at least one master clock cycle to ensure that synchronization occurs. i f multiple ad7172 - 4 devices are operated from a common maste r clock, they can be synchronized so that their analog inputs are sampled simultaneously. this synchronization is typic ally completed after each ad7172 - 4 device has performed its own calibration or has calibration coefficients loaded into its calibration registers. a falling edge on the sync input resets the digital filter and the analog modulator and places the ad7172 - 4 into a consistent known state. while the sync input is low, the ad7172 - 4 is maintained in this known state. on the sync input rising edge, the modulator and filter are taken out of this reset state, and on the next master clock edge, the device starts to gather input samples again. the device is taken out of reset on the master clock falling edge following the sync input low to high transition. therefore, when multiple devices are being synchronized, take the sync input high on the master clock rising edge to ensure that all devices are released on the master clock falling edge. if the sync in put is not taken high in sufficient time, a difference of one master
data sheet ad7172- 4 rev. a | page 43 of 61 clock cycle between the devices is possible; that is, the instant at which conversions are available differs from device to device by a maximum of one master clock cycle. the sync input can also be used as a start conversion command for a single channel when in normal synchronization mode. in this mode, the rising edge of the sync input starts a conversion, and the falling edge of the rdy output indicates when the conversion is complete. the settling time of the filter is required for each data register update. after the conversion is complete, bring the sync input low in preparation for the next conversion start signal . alternate synchronization in alternate synchronization mode, the sync input operates as a start conversion command when several channels of the ad7172 - 4 are enabled. setting the alt_sync bit in the interface mode register to 1 enables an alternate synchronization scheme. when the sync input is taken low, the adc completes the conversion on the current channel, selects the next channel in the sequence , and then waits until the sync input is taken high to start the conversion. the rdy output goes low w hen the conversion is c omplete on the current channel, and the data register is updated with the corresponding conversion. therefore, the sync input does not interfere with the sampling on the currently selected channel but allows the use r to control the instant at which the conversion begins on the next channel in the sequence. alternate synchronization mode can be used only when several channels are enabled. it is not recommended to use this mode when a single channel is enabled. error f lags the status register contains three error bits ( adc_error, crc_error, and reg_error ) that flag errors with the adc conversion, errors with the crc check, and errors caused by changes in the registers, respectively. in addition, the error output can indicate that an error has occurred. adc_error the adc_error bit in the status register flags any errors that occur during the conversion process. the flag is set when an over - range or underrange result is output from the adc. the adc also o utputs all 0s or all 1s when an undervoltage or overvoltage occurs. this flag is reset only when the overvoltage or undervoltage is removed. this flag is not reset by a read of the data register. crc_error if the crc value that accompanies a write operatio n does not correspond with the information sent, the crc_error flag is set. the flag is reset when the status register is explicitly read. reg_error the re g _error flag is used in conjunction with the reg_check bit in the interface mode register. when the reg_check bit is set, the ad7172 - 4 monitors the values in the on - chip registers. if a bit changes, the reg_error bit is set to 1 . therefore, for writes to the on - chip registers, set the reg_check bit to 0. when the registers have been up dated, the reg_check bit can be set to 1. the ad7172 - 4 c alculates a checksum of t he on - chip registers. if one of the register values has changed, the reg_error bit is set to 1 . if an error is flagged, the reg_check bit must be set to 0 to clear the reg_error bit in the status register. the register check function does not monitor the d ata register, status register, or interface mode register. error input/output t h e error pin functions as an error input/output pin or as a general - purpose output pin. the err_en bits in the gpiocon register determine the function of the pin. w hen err_en is set to 10, the error pin functions as an open - drain error output. the three error bits in the status register (adc_error, crc_error, and reg_error) are ored, inverted, and mapped to the error output. therefore, the error output indicates that an error has occurred. the status register must be read to identify the error source. when err_en is set to 01, the error pin functions as an error input. the error output of another component can be connected to the ad7172 - 4 error input so that the ad7172 - 4 indicates when an error occurs on either itself or the external component. the value on the error input is inverted and ored with the errors from the adc conversion, and the result is indicated via the adc_error bit in the status register. the value of the error input is reflected in the err_dat bit in the gpio onfiguration register. the error input/output is disabled when err_en is set to 00. when the err_en bits are set to 11, the error pin operates as a general - pur pose output. data_stat the contents of the status register can be appended to each con - version on the ad7172 - 4 using the data_stat bit in the ifmode register . this function is useful if several channels are enabled. each time a conversion is output, the contents of the status register are appended. the two lsbs of the status register i ndicate to which channel the conversion corresponds. in addition, the user can determine if any errors are being flagged by the error bits. iostrength the serial interface can operate with a power supply as low as 2 v. however, at this low voltage, the do ut/ rdy pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board or if the sclk frequency is high. the iostrength bit in the interface mode register increases the drive strength of the dout/ rdy pin.
ad7172- 4 data sheet rev. a | page 44 of 61 grounding and layout the analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common - mode voltages. the high common - mode rejection of the device removes common - mode noise on these inputs. the analog and digital su pplies to the ad7172 - 4 are independent and connected to separate pins to minimize coupling between the analog and digital sections of the device. the digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. the digital filter also removes noise from the anal og and reference inputs, provided that these noise sources do not saturate the analog modulator. as a result, the ad7172 - 4 is more immune to noise interference than a conventional high resolution converter. however, because the resolution of the ad7172 - 4 is high and the noise levels from the converter are so low, take care with regard to grounding and layout. the pcb that houses the adc must be designed such that t he analog and digital sections are separated and confined to certain areas of the board. a minimum etch technique is generally best for ground planes because it results in the best shielding. in any layout, the user must consider the flow of currents in th e system, ensuring that the paths for all return currents are as close as possible to the p aths the currents took to reach their destinations . avoid running digital lines under the device because this couples noise onto the die . al low the analog ground pla ne to run under the ad7172 - 4 to prevent noise coupling. the power supply lines to the ad7172 - 4 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. avoid crossover of digital and analog signals. run traces on opposite sides of the board at right angles to each other. this techni que reduces the effects of feed through on the board. a microstrip technique is by far the best but is not always possible with a double - sided board. good decoupling is important when using high resolution adcs. the ad7172 - 4 has three p ower supply pins : av dd1, av dd2, and iovdd. the avdd1 and avdd2 pins are referenced to avss, and the iovdd pin is referenced to dgnd. decouple avdd1 and avdd2 with a 10 f capacitor in parallel with a 0.1 f capacitor to avss on each pin. place the 0.1 f c apacitor as close as possible to the device on each supply, ideally right up against the device. decouple iovdd with a 10 f capacitor in parallel with a 0.1 f capacitor to dgnd. decouple all analog inputs to a vss. d ecouple the ref and ref 2 pins to avss . the ad7172 - 4 also has two on - board ldo regulators , one that regulates the avdd2 supply and one that regulates the iovdd supply. for the regc a pa pin, use 1 f and 0.1 f capacitors to avss. similarly, for the regcapd pin, use 1 f and 0.1 f capac itors to dgnd . if using the ad7172 - 4 for split supply operation, a separate plane must be used for avss.
data sheet ad7172- 4 rev. a | page 45 of 61 register summary table 25 . register summary reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w 0x00 status [7:0] rdy adc_error crc_error reg_error reserved channel 0x80 r 0x01 adcmode [15:8] reserved hide_delay sing_cyc reserved delay 0x2000 rw [7:0] reserved mode clocksel reserved 0x02 ifmode [15:8] reserved alt_sync iostrength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en reserved wl16 0x03 regcheck [23:0] register_check[23:0] 0x000000 r 0x04 data [23:0] data[23:0] 0x000000 r 0x06 gpiocon [15:8] reserved pdsw op_en2_3 mux_io sync_en err_en err_dat 0x0800 rw [7:0] gp_data3 gpdata2 ip_en1 ip_en0 op_en1 op_en0 gp_data1 gp_data0 0x07 id [15:8] id[15:8] 0x205x r [7:0] id[7:0] 0x10 ch0 [15:8] ch_en0 setup_sel0 reserved ainpos0[4:3] 0x8001 rw [7:0] ainpos0[2:0] ainneg0 0x11 ch1 [15:8] ch_en1 setup_sel1 reserved ainpos1[4:3] 0x0001 rw [7:0] ainpos1[2:0] ainneg1 0x12 ch2 [15:8] ch_en2 setup_sel2 reserved ainpos2[4:3] 0x0001 rw [7:0] ainpos2[2:0] ainneg2 0x13 ch3 [15:8] ch_en3 setup_sel3 reserved ainpos3[4:3] 0x0001 rw [7:0] ainpos3[2:0] ainneg3 0x14 ch4 [15:8] ch_en4 setup_sel4 reserved ainpos4[4:3] 0x0001 rw [7:0] ainpos4[2:0] ainneg4 0x15 ch5 [15:8] ch_en5 setup_sel5 reserved ainpos5[4:3] 0x0001 rw [7:0] ainpos5[2:0] ainneg5 0x16 ch6 [15:8] ch_en6 setup_sel6 reserved ainpos6[4:3] 0x0001 rw [7:0] ainpos6[2:0] ainneg6 0x17 ch7 [15:8] ch_en7 setup_sel7 reserved ainpos7[4:3] 0x0001 rw [7:0] ainpos7[2:0] ainneg7 0x20 setupcon0 [15:8] reserved bi_unipolar0 refbuf0+ refbuf0 - ainbuf0+ ainbuf0? 0x1000 rw [7:0] burnout_en0 reserved ref_sel0 reserved 0x21 setupcon1 [15:8] reserved bi_unipolar1 refbuf1+ refbuf1? ainbuf1+ ainbuf1? 0x1000 rw [7:0] burnout_en1 reserved ref_sel1 reserved 0x22 setupcon2 [15:8] reserved bi_unipolar2 refbuf2+ refbuf2? ainbuf2+ ainbuf2? 0x1000 rw [7:0] burnout_en2 reserved ref_sel2 reserved 0x23 setupcon3 [15:8] reserved bi_unipolar3 refbuf3+ refbuf3? ainbuf3+ ainbuf3? 0x1000 rw [7:0] burnout_en3 reserved ref_sel3 reserved 0x24 setupcon4 [15:8] reserved bi_unipolar4 refbuf4+ refbuf4? ainbuf4+ ainbuf4? 0x1000 rw [7:0] burnout_en4 reserved ref_sel4 reserved 0x25 setupcon5 [15:8] reserved bi_unipolar5 refbuf5+ refbuf5? ainbuf5+ ainbuf5? 0x1000 rw [7:0] burnout_en5 reserved ref_sel5 reserved 0x26 setupcon6 [15:8] reserved bi_unipolar6 refbuf6+ refbuf6? ainbuf6+ ainbuf6? 0x1000 rw [7:0] burnout_en6 reserved ref_sel6 reserved 0x27 setupcon7 [15:8] reserved bi_unipolar7 refbuf7+ refbuf7? ainbuf7+ ainbuf7? 0x1000 rw [7:0] burnout_en7 reserved ref_sel7 reserved 0x28 filtcon0 [15:8] sinc3_map0 reserved enhfilten0 enhfilt0 0x0500 rw [7:0] reserved order0 odr0 0x29 filtcon1 [15:8] sinc3_map1 reserved enhfilten1 enhfilt1 0x0500 rw [7:0] reserved order1 odr1 0x2a filtcon2 [15:8] sinc3_map2 reserved enhfilten2 enhfilt2 0x0500 rw [7:0] reserved order2 odr2 0x2b filtcon3 [15:8] sinc3_map3 reserved enhfilten3 enhfilt3 0x0500 rw [7:0] reserved order3 odr3 0x2c filtcon4 [15:8] sinc3_map3 reserved enhfilten4 enhfilt4 0x0500 rw [7:0] reserved order4 odr4 0x2d filtcon5 [15:8] sinc3_map3 reserved enhfilten5 enhfilt5 0x0500 rw [7:0] reserved order5 odr5 0x2e filtcon6 [15:8] sinc3_map3 reserved enhfilten6 0x0500 rw [7:0] reserved order6 odr6
ad7172- 4 data sheet rev. a | page 46 of 61 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x2f filtcon7 [15:8] sinc3_map3 reserved enhfilten7 enhfilt7 0x0500 rw [7:0] reserved order7 odr7 0x30 offset0 [23:0] offset0[23:0] 0x800000 rw 0x31 offset1 [23:0] offset1[23:0] 0x800000 rw 0x32 offset2 [23:0] offset2[23:0] 0x800000 rw 0x33 offset3 [23:0] offset3[23:0] 0x800000 rw 0x34 offset4 [23:0] offset5[23:0] 0x800000 rw 0x35 offset5 [23:0] offset6[23:0] 0x800000 rw 0x36 offset6 [23:0] offset6[23:0] 0x800000 rw 0x37 offset7 [23:0] offset7[23:0] 0x800000 rw 0x38 gain0 [23:0] gain0[23:0] 0x5xxxx0 rw 0x39 gain1 [23:0] gain1[23:0] 0x5xxxx0 rw 0x3a gain2 [23:0] gain2[23:0] 0x5xxxx0 rw 0x3b gain3 [23:0] gain3[23:0] 0x5xxxx0 rw 0x3c gain4 [23:0] gain4[23:0] 0x5xxxx0 rw 0x3d gain5 [23:0] gain5[23:0] 0x5xxxx0 rw 0x3e gain6 [23:0] gain6[23:0] 0x5xxxx0 rw 0x3f gain7 [23:0] gain7[23:0] 0x5xxxx0 rw
data sheet ad7172- 4 rev. a | page 47 of 61 register details communications regis ter address: 0x00, reset: 0x00, name: comms all access to the on - chip registers must start with a write to the communications register. this write determines what register is accessed next and whether th e operation is a write or a read. table 26 . bit descriptions for comms bits bit name settings description reset access 7 wen this bit must be low to begin communications with the adc. 0x0 w 6 r/ w this bit determines if the command is a read or write operation. 0x0 w 0 write command 1 read command [5:0] ra the register address bits determine which register is to be read from or written to as part of the current communication. 0x00 w 000000 status register 000001 adc mode register 000010 interface mode register 000011 register check register 000100 data register 000110 gpio configuration register 000111 id register 010000 channel r egister 0 010001 channel r egister 1 010010 channel r egister 2 010011 channel r egister 3 010100 channel r egister 4 010101 channel r egister 5 010110 channel r egister 6 010111 channel r egister 7 100000 setup configuration register 0 100001 setup configuration register 1 100010 setup configuration register 2 100011 setup configuration register 3 100100 setup configuration register 4 100101 setup configuration register 5 100110 setup configuration register 6 100111 setup configuration register 7 101000 filter configuration register 0 101001 filter configuration register 1 101010 filter configuration register 2 101011 filter configuration register 3 101100 filter configuration register 4 101101 filter configuration register 5 101110 filter configuration register 6 101111 filter configuration register 7 110000 offset register 0 110001 offset register 1 110010 offset register 2 110011 offset register 3 110100 offset register 4 110101 offset register 5 110110 offset register 6 110111 offset register 7 111000 gain register 0 111001 gain register 1 111010 gain register 2 111011 gain register 3 111100 gain register 4 111101 gain register 5 111110 gain register 6 111111 gain register 7
ad7172- 4 data sheet rev. a | page 48 of 61 status register address: 0x00, reset: 0x80, name: status the status register is an 8 - bit register that contains adc and serial interface status information. it can optionally be appended to the data register by setting the data_stat bit in the interface mode register. table 27 . bit descriptions for status bits bit name settings description reset access 7 rdy the status of rdy is output to the dout/ rdy pin whenever cs is low and a register is not being read. this bit goes low when the adc has written a new result to the data register. in adc calibration modes, this bit goes low when the adc has written the calibration result. rdy is brought high automatically by a read of the data register. 0x1 r 0 new data result available 1 awaiting new data result 6 adc_error this bit by default indicates if an adc overrange or underrange has occurred. the adc result is clamped to 0xffffff for overrange errors and 0x000000 for underrange errors. this bit is updated when the adc result is written and is cleared at the next update after removing the overrange or underrange conditio n. 0x0 r 0 no error 1 error 5 crc_error this bit indicates if a crc error has taken place during a register write. for register reads, the host microcontroller determines if a crc error has occurred. this bit is cleared by a read of this register. 0x0 r 0 no error 1 crc error 4 reg_error this bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. the check is activated by setting the reg_check bit in the interface mode register. this bit is cleared by clearing the reg_check bit. 0x0 r 0 no error 1 error 3 reserved these bits are reserved. 0x0 r [2:0] channel these bits indicat e which channel was active for the adc conversion whose result is cur rently in the data register. this may be different from the channel currently being converted. the mapping is a direct map from the channel register; therefore, channel 0 results in 0x0 a nd channel 7 results in 0x7. 0x0 r 000 channel 0 001 channel 1 010 channel 2 011 channel 3 100 channel 4 101 channel 5 110 channel 6 111 channel 7
data sheet ad7172- 4 rev. a | page 49 of 61 adc mode register address: 0x01, reset: 0x2000, name: adcmode the adc mode register controls the operating mode of the adc and the master clock selection. a write to the adc mode register resets the filter and the rdy bits and starts a new conversion or calibration. table 28 . bit descriptions for adcmode bits bit name settings description reset access 15 re served reserved 0x0 rw 14 hide_delay if a programmable dela y is set using the delay bits, this bit allows the delay to be hidden by absorb ing the delay into the conversion time for selected data rates with the sinc5 + sinc1 filter. see the delay section for more information. 0x0 rw 0 enabled 1 disabled 13 sing_cyc this bit can be used when only a single channel is active to set the adc to only output at the settled filter data rate. 0x1 rw 0 disabled 1 enabled [12:11] reserved these bits are reserved; set these bits to 0. 0x0 r [10:8] delay these bits allow a programmable delay to be added after a channel switch to allow settling of external circuitry before the adc starts processing its input. 0x0 rw 000 0 s 001 32 s 010 128 s 011 320 s 100 800 s 101 1.6 ms 110 4 ms 111 8 ms 7 reserved this bit is reserved; set this bit to 0. 0x0 r [6:4] mode these bits control the operating mode of the adc. see the operating modes section for more information. 0x0 rw 000 continuous conversion mode 001 single conversion mode 010 standby mode 011 power - down mode 100 internal offset calibration 110 system offset calibration 111 system gain calibration [3:2] clocksel this bit is used to select the adc clock source. selecting internal oscillator also enables the internal oscillator. 0x0 rw 00 internal oscillator 01 internal oscillator output on the xtal2/clkio pin 10 external clock input on the xtal2/clkio pin 11 external crystal on the xtal1 and xtal2/clkio pins [1:0] reserved these bits are reserved; set these bits to 0. 0x0 r
ad7172- 4 data sheet rev. a | page 50 of 61 interface mode register address: 0x02, reset: 0x0000, name: ifmode the interface mode register configures various serial interface options. table 29 . bit descriptions for ifmode bits bit name settings description reset access [15:13] reserved these bits are reserved; set these bits to 0. 0x0 r 12 a lt_ sync this bit enables a different behavior of the sync pin to allow the use of sync as a control for conversions when cycling channels (see the description of the sync_en bit in the gpio configuration register section for details). 0x0 rw 0 disabled 1 enabled 11 iostrength this bit controls the drive strength of the dout/ rdy pin. set this bit when reading from the serial interface at high speed with a low iovdd supply and moderate capacitance. 0x0 rw 0 disabled (default) 1 enabled [10:9] reserved these bits are reserved; set these bits to 0. 0x0 r 8 dout_reset see the dout_reset section for more information. 0x0 rw 0 disabled 1 enabled 7 contread this en ables a continuous read of the adc data register. the adc must be configured in conti nuous conversion mode to use continuous read. for more details, see the operating modes section. 0x0 rw 0 disabled 1 enabled 6 data_stat this enables th e status register to be appended to the data register when read so that the channel and status information are transmitted with the data. this is the only way to en sure tha t the channel bits read from the status register correspond to the da ta in the data register. 0x0 rw 0 disabled 1 enabled 5 reg_check this bit enables a register integrity checker, which can be used to monitor any change in the value of the user registers. to use this feature, configure all other registers as desired, with this bit cleared. then write to this register to set the reg_check bit to 1. if the contents of any of the registers change, the reg_error bit is set in the status register. to clear the error, set the reg_check bit to 0. neither the interfac e mode register nor the adc data or status registers are included in the registers that are checked. if a register must have a new value written, this bit must first be cleared; otherwise, an error is flagged when the new register contents are written. 0x0 rw 0 disabled 1 enabled 4 reserved this bit is reserved; set this bit to 0. 0x0 r [3:2] crc_en enables crc protection of register reads/writes. crc increases the number of bytes in a serial interface transfer by one. see the crc calculation section for more details. 0x00 rw 00 disabled 01 xor checksum enabled for register read transactions; register writes still use crc with these bits set 10 crc checksum enabled for read and write transactions 1 reserved this bit is reserved; set this bit to 0. 0x0 r
data sheet ad7172- 4 rev. a | page 51 of 61 bits bit name settings description reset access 0 wl16 this bit c hanges the adc data register to 16 bits. the adc is not reset by a write to the interface mode register; therefore, the adc result is not rounded to the correct word length immediately after writing to th is bit . the first new adc result is correct. 0x0 rw 0 24 - bit data 1 16- bit data register check address: 0x03, reset: 0x000000, name: regcheck the register check register is a 24 - bit checksum calculated by exclusively or'ing the contents of the user registers. the reg_check bit in the interface mode register must be set for this register to operate; otherwise, the register reads 0. table 30 . bit descriptions for regcheck bits bit name settings description reset access [23:0] register_check this register contains the 24 - bit checksum of user registers when the reg_check bit is set in the interface mode register. 0x000000 r data register address: 0x04, reset: 0x000000, name: data the data register contains the adc conversion result. the encoding is offset binary, or it can be changed to unipolar by the bi_unipolarx bit s in the setup configuration registers. reading the data register brings the rdy bit and the rdy output high if they are low. the adc result can be read multiple times; however, because the rdy output has been brought high, it is not possible to know if another adc result is imminent. after the command to read the adc register is received, the adc does not write a new result i nto the data register. table 31 . bit descrip tions for data bits bit name settings description reset access [23:0] data this register contains the adc conversion result. if data_stat is set in the interface mode register, the status register is appended to this register when read, making this a 32- bit register. if wl16 is set in the interface mode register, this register is reduced to 16 bits. 0x000000 r
ad7172- 4 data sheet rev. a | page 52 of 61 gpio configuration r egister address: 0x06, reset: 0x0800, name: gpiocon the gpio configuration register controls the general - purpose input/out put pins of the adc. table 32 . bit descriptions for gpiocon bits bit name settings description reset access 15 reserved these bits are reserved; set these bits to 0. 0x0 r 14 pdsw this bit enables/disables the power - down switch function. setting the bit allows the pin to sink current. this function can be used for bridge sensor applications where the switch controls the power - up/power - down of the bridge . 0x0 rw 13 op_en2_3 this bit enables the gpo2 and gpo3 pins. outputs are re ferenced between avdd1 and avss. 0x0 rw 12 mux_io this bit allows t he adc to control an external multiplexer, using gpio0/gpio1/ gpo2 in sync with the internal channel sequencing. the analog inpu t pins used for a channel can still be selected on a per channel basis. therefore, it is possible to have a 8 - channel multiplexer in front of each analog input pair (ain0/ain1 to ain6/ain7) , giving a total of 32 differential channels. however, only 8 channels at a time can be automatically sequen ced. following t he sequence of 8 channels, the user must employ an spi command to change the selected analog input pair before it sequences through the next 8 channels suppli ed by the external multiplexer. 0x0 rw there is a delay function that allows extra time for the analog input to settle, in conjunction with any switching from an external multiplexer (see the delay bits in the adc mode register section). 11 sync_en this bit enables the sync pin as a sync input. when the pin is low, this bit holds the adc and filter in reset until the sync pin goes high. an alternative operation of the sync pin is available when the alt_sync bit in the interface mode register is set. this mode only works when multiple channels are enabled. in this case, a low on the sync pin does not immediately reset the filter/modulator. instead, if the sync pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. bringing sync high begins the next conversion. this alternative sync mode allow s sync to be used while cycling through channels. 0x1 rw 0 disabled. 1 enabled. [10:9] err_en these bits enable the error pin as an error input/output. 0x0 rw 00 disabled. 01 error is an error input. the (inverted) readback state is or'ed with other error sources and is available in the adc_error bit in the status register. the error pin state can also be read from the err_dat bit i n this register. 10 error is an open - drain error output. the status register error bits are or'ed, inverted, and mapped to the error pin. the error pins of multiple devices can be wi red together to a common pull - up resistor so that an error on any device can be observed. 11 error is a general - purpose output. the status of the pin is controlled by the err_dat bit in this register. this output is referenced between iovdd and dgnd, as opposed to the avdd1 and avss levels used by the gpio pins. the error pin has an active pull - up in this case. 8 err_dat this bit determines the logic level at the error pin if the pin is enabled as a general - purpose output. this bit reflects the readback status of the pin if the pin is enabled as an input. 0x0 rw 7 gp_data3 this bit is the write data for gpo3. 0x0 w 6 gp_data2 this bit is the write data for gpo2. 0x0 w 5 ip_en1 this bit turns gpio1 into an input. inputs are referenced to avdd1 or avss. 0x0 rw 0 disabled. 1 enabled.
data sheet ad7172- 4 rev. a | page 53 of 61 bits bit name settings description reset access 4 ip_en0 this bit turns gpio0 into an input. inputs are referenced to avdd1 or avss. 0x0 rw 0 disabled. 1 enabled. 3 op_en1 this bit turns gpio1 into an output. outputs are referenced between avdd1 and avss. 0x0 rw 0 disabled. 1 enabled. 2 op_en0 this bit turns gpio0 into an output. outputs are referenced between avdd1 and avss. 0x0 rw 0 disabled. 1 enabled. 1 gp_data1 this bit is the readback or write data for gpio1. 0x0 rw 0 gp_data0 this bit is the readback or write data for gpio0. 0x0 rw id register address: 0x07, reset: 0x205x , name: id the id register returns a 16 - bit id. for the ad7172 - 4 , this id is 0x205x . table 33 . bit descriptions for id bits bit name settings description reset access [15:0] id the id register returns a 16 - bit id code that is specific to the adc. 0x205x r 0x205x ad7172 -4
ad7172- 4 data sheet rev. a | page 54 of 61 channel register 0 address: 0x10, reset: 0x8001, name: ch0 the channel registers are 16 - bit registers that select which channels are currently active, which inputs are selected for each channel, and which setup is used to configure the adc for that channel. table 34 . bit descriptio ns for ch0 bits bit name settings description reset access 15 ch_en0 this bit enables channel 0. if more than one channel is enabled, the adc automatically sequences between them. 0x1 rw 0 disabled 1 enabled (default) [14:12] setup_sel0 these bits identify which of the eight setups are used to configure the adc for this channel. a setup comprises a set of four registers: the setup configuration register , the filter configuration register, the offset register, and the gain register. all channels can use the same setup, in which case the same 2 - bit value must be written to these bits on all active channels, or up to eight channels can be configured differently. 0x0 rw 000 setup 0 001 setup 1 010 setup 2 011 setup 3 100 setup 4 101 setup 5 110 setup 6 111 setup 7 [11:10] reserved these bits are reserved; set these bits to 0. 0x0 r [9:5] ainpos0 these bits select which input is connected to the positive input of the adc for this channel. 0x0 rw 00000 ain0 (default) 00001 ain1 00010 ain2 00011 ain3 00100 ain4 00101 ain5 00110 ain6 00111 ain7 01000 ain8 10011 ((avdd1 ? avss)/5)+ (analog input buffers must be enabled) 10100 ((avdd1 ? avss)/5)? (analog input buffers must be enabled) 10101 ref+ 10110 ref? [4:0] ainneg0 these bits select which input is connected to the negative input of the adc for this channel. 0x1 rw 00000 ain0 00001 ain1 (default) 00010 ain2 00011 ain3 00100 ain4 00101 ain5 00110 ain6 00111 ain7 01000 ain8 10011 ((avdd1 ? avss)/5)+ 10100 ((avdd1 ? avss)/5)? 10101 ref+ 10110 ref?
data sheet ad7172- 4 rev. a | page 55 of 61 channel register 1 t o channel register 7 address: 0x11 to 0x17, reset: 0x0001, name: ch1 to ch7 the remaining seven channel registers share the same layout as channel register 0. table 35 . ch1 t o ch 7 r egister map reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x11 ch1 [15:8] ch_en1 setup_sel1 reserved ainpos1[4:3] 0x0001 rw [7:0] ainpos1[2:0] ainneg1 0x12 ch2 [15:8] ch_en2 setup_sel2 reserved ainpos2[4:3] 0x0001 rw [7:0] ainpos2[2:0] ainneg2 0x13 ch3 [15:8] ch_en3 setup_sel3 reserved ainpos3[4:3] 0x0001 rw [7:0] ainpos3[2:0] ainneg3 0x14 ch4 [15:8] ch_en4 setup_sel4 reserved ainpos4[4:3] 0x0001 rw [7:0] ainpos4[2:0] ainneg4 0x15 ch5 [15:8] ch_en5 setup_sel5 reserved ainpos5[4:3] 0x0001 rw [7:0] ainpos5[2:0] ainneg5 0x16 ch6 [15:8] ch_en6 setup_sel6 reserved ainpos6[4:3] 0x0001 rw [7:0] ainpos6[2:0] ainneg6 0x17 ch7 [15:8] ch_en7 setup_sel7 reserved ainpos7[4:3] 0x0001 rw [7:0] ainpos7[2:0] ainneg7
ad7172- 4 data sheet rev. a | page 56 of 61 setup configuration register 0 address: 0x20, res e t: 0x1000 , n ame: setupcon0 the setup configuration registers are 16 - bit registers that configure the reference selection, input buffers, and output coding of the adc. table 36 . bit descriptions for setupcon0 bits bit name settings description reset access [15:13] reserv ed these bits are reserved; set these bits to 0. 0x0 r 12 bi_unipolar0 this bit sets the output coding of the adc for setup 0. 0x1 rw 0 unipolar coded output 1 bipolar coded output (offset binary) 11 refbuf0+ this bit enables or disables the ref+ input buffer. 0x0 rw 0 ref+ buffer disabled 1 ref+ buffer enabled 10 refbuf0? this bit enables or disables the ref? input buffer. 0x0 rw 0 ref? buffer disabled 1 ref? buffer enabled 9 ainbuf0+ this bit enables or disables the ain+ input buffer. 0x0 rw 0 ain+ buffer disabled 1 ain+ buffer enabled 8 ainbuf0? this bit enables or disables the ain? input buffer. 0x0 rw 0 ain? buffer disabled 1 ain? buffer enabled 7 burnout_en0 this bit enables a 10 a current source on the positive analog input selected and a 10 a current sink on the negative analog input selected. the burnout currents are useful in diagnosis of an open wire, whereby the adc result goes to full scale. enabling the burnout currents duri ng measurement results in an o ffset voltage on the adc. the best strategy for diagnosing an open wire is turning on the burnout currents at intervals, before or after precision measurements. 0x00 r 6 reserved these bits are reserved; set these bits to 0. 0x00 r [5:4] ref_sel0 these bits allow the user to select the reference source for adc conversion on setup 0. 0x0 rw 00 external r eference supplied to the ref+ and ref ? pins. 01 external r eference 2 supplied to ain1/ref2+ and ain0/ref2 ? pins. 11 avdd1 ? avss. this can be used to as a diagnostic to validate other reference values. [3:0] reserved these bits are reserved; set these bits to 0. 0x0 r
data sheet ad7172- 4 rev. a | page 57 of 61 setup configuration register 1 to setup configuration regist er 7 address: 0x21 to 0x27, reset: 0x 1000 , name: setupcon1 to setupcon7 the remaining seven setup co nfiguration registers share the same layout as setup configuration register 0. table 37 . setupcon1 to setupcon 7 reg ister map reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x21 setupcon1 [15:8] reserved bi_unipolar1 refbuf1+ refbuf1? ainbuf1+ ainbuf1? 0x1000 rw [7:0] burnout_en1 reserved ref_sel1 reserved 0x22 setupcon2 [15:8] reserved bi_unipolar2 refbuf2+ refbuf2? ainbuf2+ ainbuf2? 0x1000 rw [7:0] burnout_en2 reserved ref_sel2 reserved 0x23 setupcon3 [15:8] reserved bi_unipolar3 refbuf3+ refbuf3? ainbuf3+ ainbuf3? 0x1000 rw [7:0] burnout_en3 reserved ref_sel3 reserved 0x24 setupcon4 [15:8] reserved bi_unipolar4 refbuf4+ refbuf4? ainbuf4+ ainbuf4? 0x1000 rw [7:0] burnout_en4 reserved ref_sel4 reserved 0x25 setupcon5 [15:8] reserved bi_unipolar5 refbuf5+ refbuf5? ainbuf5+ ainbuf5? 0x1000 rw [7:0] burnout_en5 reserved ref_sel5 reserved 0x26 setupcon6 [15:8] reserved bi_unipolar6 refbuf6+ refbuf6? ainbuf6+ ainbuf6? 0x1000 rw [7:0] burnout_en6 reserved ref_sel6 reserved 0x27 setupcon7 [15:8] reserved bi_unipolar7 refbuf7+ refbuf7? ainbuf7+ ainbuf7? 0x1000 rw [7:0] burnout_en7 reserved ref_sel7 reserved
ad7172- 4 data sheet rev. a | page 58 of 61 filter configuration register 0 address: 0x28, reset: 0x0500, name: filtcon0 the filter configuration registers are 16 - bit registers that configure the adc data rate and filter options. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the sequence. table 38 . bit descriptions for filtcon0 bits bit name settings description reset access 15 sinc3_map0 if this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for setup 0. all other options are eliminated. this allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. the data rate whe n on a single channel equals f mod /(32 filtcon0[14:0]). 0x0 rw [14:12] reserved these bits are reserved; set these bits to 0. 0x0 r 11 enhfilten0 this bit enables various postfilters for enhanced 50 hz and 60 hz rejection for setup 0. the order0 bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. 0x0 rw 0 disabled 1 enabled [10:8] enhfilt0 these bits select between various postfilters for enhanced 50 hz and 60 hz rejection for setup 0. 0x5 rw 010 27 sps, 47 db rejection, 36.7 ms settling 011 21.25 sps, 62 db rejection, 40 ms settling 101 20 sps, 86 db rejection, 50 ms settling 110 16.67 sps, 92 db rejection, 60 ms settling 7 reserved this bit is reserved; set this bit to 0. 0x0 r [6:5] order0 these bits control the order of the digital filter that processes the modulator data for setup 0. 0x0 rw 00 sinc5 + sinc1 (default) 11 sinc3 [4:0] odr0 these bits control the output data rate of the adc and, therefore, the settling time and noise for setup 0. rates shown are for the sinc5 + sinc 1 filter. see table 20 to table 23. 0x0 rw 00000 31,250 00001 31,250 00010 31,250 00011 31,250 00100 31,250 00101 31,250 00110 15,625 00111 10,417 01000 5208 01001 2597 01010 1007 01011 503.8 01100 381 01101 200.3 01110 100.2 01111 59.52 10000 49.68 10001 20.01 10010 16.63 10011 10 10100 5 10101 2.5 10110 1.25
data sheet ad7172- 4 rev. a | page 59 of 61 filter configuration register 1 to filter configuration regist er 7 address: 0x29 to 0x2f, reset: 0x0500, name: filtcon1 to filtcon7 the remaining seven filter configuration registers share the same layout as filter configuration register 0. table 39 . filtcon1 to filtcon7 register map reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x29 filtcon1 [15:8] sinc3_map1 reserved enhfilten1 enhfilt1 0x0500 rw [7:0] reserved order1 odr1 0x2a filtcon2 [15:8] sinc3_map2 reserved enhfilten2 enhfilt2 0x0500 rw [7:0] reserved order2 odr2 0x2b filtcon3 [15:8] sinc3_map3 reserved enhfilten3 enhfilt3 0x0500 rw [7:0] reserved order3 odr3 0x2c filtcon4 [15:8] sinc3_map4 reserved enhfilten4 enhfilt4 0x0500 rw [7:0] reserved order4 odr4 0x2d filtcon5 [15:8] sinc3_map5 reserved enhfilten5 enhfilt5 0x0500 rw [7:0] reserved order5 odr5 0x2e filtcon6 [15:8] sinc3_map6 reserved enhfilten6 enhfilt6 0x0500 rw [7:0] reserved order6 odr6 0x2f filtcon7 [15:8] sinc3_map7 reserved enhfilten7 enhfilt7 0x0500 rw [7:0] reserved order7 odr7 offset register 0 address: 0x30, reset: 0x800000, name: offset0 the offset (zero - scale) registers are 24 - bit registers that compensate for any offset error in the adc or in the system. table 40 . bit descriptions for offset0 bits bit name settings description reset access [23:0] offset0 offset calibration coefficient for setup 0. 0x800000 rw offset register 1 to offset register 7 address: 0x31 to 0x33, reset: 0x800000, name: offset1 to offset7 the remaining seven offset registers share the same layout as offset register 0. table 41 . offset1 to offset 7 re gister map reg. name bits reset rw 0x31 offset1 [23:0] offset1[23:0] 0x800000 rw 0x32 offset2 [23:0] offset2[23:0] 0x800000 rw 0x33 offset3 [23:0] offset3[23:0] 0x800000 rw 0x34 offset4 [23:0] offset4[23:0] 0x800000 rw 0x35 offset5 [23:0] offset5[23:0] 0x800000 rw 0x36 offset6 [23:0] offset6[23:0] 0x800000 rw 0x37 offset7 [23:0] offset7[23:0] 0x800000 rw
ad7172- 4 data sheet rev. a | page 60 of 61 gain register 0 address: 0x38, reset: 0x5xxxx0, name: gain0 the gain (full - scale) registers are 24 - bit registers that compensate for any gain error in the adc or in the system. table 42 . bit descriptions for gain0 bits bit name settings description reset access [23:0] gain0 gain calibration coefficient for setup 0. 0x5xxxx0 rw gain register 1 to g ain register 7 address: 0x39 to 0x3f, reset: 0x5xxxx0, name: gain1 to gain7 the remaining seven gain registers share the same layout as gain register 0. table 43 . gain 1 to gain 7 register map reg. name bits reset rw 0x39 gain1 [23:0] gain1[23:0] 0x5xxxx0 rw 0x3a gain2 [23:0] gain2[23:0] 0x5xxxx0 rw 0x3b gain3 [23:0] gain3[23:0] 0x5xxxx0 rw 0x3c gain4 [23:0] gain4[23:0] 0x5xxxx0 rw 0x3d gain5 [23:0] gain5[23:0] 0x5xxxx0 rw 0x3e gain6 [23:0] gain6[23:0] 0x5xxxx0 rw 0x3f gain7 [23:0] gain7[23:0] 0x5xxxx0 rw
data sheet AD7172-4 rev. a | page 61 of 61 outline dimensions compliant to jedec standards mo-220-whhd. 1 0.50 bsc 3.50 ref bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.65 3.50 sq 3.45 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 04-02-2012-a figure 72. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-11) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7172-4bcpz ?40c to +105c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-11 AD7172-4bcpz-rl ?40c to +105c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-11 AD7172-4bcpz-rl7 ?40c to +105c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-11 1 z = rohs compliant part. ?2015C2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12676-0-5/16(a)

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