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1 tft-lcd supplies + dvr + v com amplifier ISL98665 the ISL98665 is an integrated power management ic (pmic) for tft-lcds used in notebooks, tablet pcs, and monitors. the device integrates a boost converter for generating avdd, an ldo for v logic , and a second boost converter for v gh . vgl is generated by a charge pump driven by the switch node of the avdd boost. the ISL98665 also includes a high performance v com amplifier and a v com calibrator, with integrated eeprom. the avdd boost converter features a 2.5a fet with adjustable switching frequency ranging from 310khz to 1.2mhz. the soft-start time and compensation are adjustable by external components. v gh boost converter features a 1.2a fet and temperature compensation. the ldo is able to deliver 360ma for driving the voltage rail required by external digital circuitry. the ISL98665 provides a 7-bit resolution, current sink v com calibrator with i 2 c interface, and a v com amplifier. the output of the v com is powered up with the voltage at the last programmed eeprom setting. features ? 2.2v to 5.5v input ? 2.5a, 0.15 ? integrated avdd boost fet ? 1.2a integrated boost for up to 37.5v v gh with temperature compensation ? ldo able to deliver 360ma ? adjustable boost switching frequency from 310khz to 1.2mhz ? integrated high output current v com amplifier ? dvr (digital variable resistor) - wiper position stored in 7-bit nonvolatile memory and recalled on power-up - endurance, 1,000 data changes per bit ? uvlo, ovp, ocp, and otp protection ? 28 ld, 4x5mm tqfn package ? pb-free (rohs compliant) applications ? lcd notebook, tablet, and monitor pin configuration ISL98665 (28 ld 4x5 tqfn) top view lx2 lx1 pgnd4 pgnd3 sda scl pos neg vout pgnd1 pgnd2 lxp comp fb freq agnd1 en vin lout ss rset nc vgh agnd2 rntc comp2 1 2 3 4 5 6 7 22 21 20 19 18 17 16 28 27 26 25 24 23 9 1011121314 avdd 8 fbp 15 thermal pad caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. june 27, 2013 fn8564.0
ISL98665 2 fn8564.0 june 27, 2013 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 application/block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 avdd boost operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v gh boost operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v gh temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 boost component selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 rectifier diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 linear regulator (ldo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 vcom amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ISL98665 dvr memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register description: access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register description: ivr and wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 initial v com setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 determination of rset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 determination of r1 and r2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 final transfer function for dvr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vgl charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 overcurrent protection (ocp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 over-temperature protection (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power-on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ISL98665 3 fn8564.0 june 27, 2013 application/block diagram note: component designators in this application di agram match with the evaluation board schematic. lx2 avdd comp pgnd4 avdd d1 vin vin scl sda avdd boost controller register vgh boost controller eeprom vout avdd lxp pgnd2 rntc dvr vcom rset c1 c2 c6 c7 l1 c9 r1 r11 r8 r12 d3 r18 r17 rntc c17 c15 c10 d2 l2 ldo controller lx1 pgnd3 ss fb lout freq vlogic fbp comp2 en avdd pos neg pgnd1 vgl vgh osc vgh vlogic c11 c12 c21 c13 c24 c23 c20 c22 r5 r15 r14 r16 c25 r28 r2 r3 r18 z1 thermal pad agnd2 agnd1 avdd r22
ISL98665 4 fn8564.0 june 27, 2013 pin descriptions pin# symbol description 1 comp avdd boost converter compensation pin. connect a series resistor and capacitor between this pin and agnd to optimize transient response and stability. for more information refer to ?compensation? on page 12. 2 fb avdd boost converter feedback. connect to the center of a vo ltage divider between avdd and agnd to set the avdd voltage. for more information refer to ?avdd boost operation? on page 10. 3 freq boost converter frequency adjustment pin. connect this pin wi th a resistor to agnd set the boost frequency. refer to ?swit ching frequency selection? on page 10 for more information. 4 agnd1 analog ground 1. 5 en ic enable pin. enables all the ISL98665 outputs. 6 vin ic input supply and ldo input. need to connect decoupling capacitor close to vin pin. 7 lout ldo output. connect at least one 1f capacitor to gnd for stable operation. 8 avdd dvr and v com amplifier voltage analog supply. place a 0.47f capacitor close to the avdd pin. 9posv com amplifier non-inverting input. 10 neg v com amplifier inverting input. 11 vout v com amplifier output. 12 pgnd1 v com amplifier ground. 13 pgnd2 vgh power ground. 14 lxp vgh boost converter switching node. 15 fbp vgh boost converter feedback . connect to the center of a voltage divider between vgh and agnd to set the vgh voltage. refe r to ?v gh boost operation? on page 10 for more information. 16 comp2 vgh boost converter compensation pin. connect a series re sistor and capacitor between this pin and agnd to optimize transient response and stability. refer to ?com pensation? on page 12 for more information. 17 rntc temperature compensation pin. refer to ?v gh temperature compensation? on page 11 for the connection of this pin. 18 agnd2 analog ground 2. 19 vgh power supply for eeprom programming; vgh ovp sensing pin. 20 nc not connected. 21 rset dvr sink current adjustment pin; connect a resistor between this pin and agnd to set the resolution of the dvr output vol tage. 22 ss avdd boost converter soft-start. connect a capacitor between this pin and gnd to set the soft-start time. refer to ?soft-st art? on page 10 for more information. 23 scl i 2 c clock high impedance input. 24 sda i 2 c bidirectional data high impedance input/open-drain output. 25, 26 pgnd3, pgnd4 avdd boost power ground. 27, 28 lx1, lx2 avdd boost converter switching node 1 and 2. thermal pad connect to ground plane on pcb to maximize thermal performance. ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL98665irtz 98665 irtz -40 to +105 28 ld 4x5 tqfn l28.4x5c ISL98665irt-evz ISL98665 evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, wh ich is rohs compliant and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see device information page for ISL98665 for more information on msl please see techbrief tb363 .
ISL98665 5 fn8564.0 june 27, 2013 absolute maximum rating s thermal information vgh and lxp to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +45v lx1, lx2, avdd, pos, neg, and vout to agnd . . . . . . . . . . -0.3 to +18v voltage between agnd and pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v all other pins to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 1kv latch up (tested per jesd78; class ii, level a) . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 28 ld 4x5 tqfn package (notes 4, 5). . . . 39 9 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature during soldering . . . . . . . . . . . . . . . . . . . . . . . . +260c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient operating temperature . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2v to 5.5v avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 16v v gh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 37.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = en = 3.3v, avdd = 8v, v ldo = 1.89v, v gh =21v. t a = +25c, unless otherwise specified . boldface limits apply over the operating te mperature range, -40c to +105c. symbol parameter test conditions min (note 6) typ max (note 6) units general v in v in supply voltage range 2.2 3.3 5.5 v i s_dis v in supply currents when disabled v in < uvlo 390 500 a i s v in supply currents en = 3.3v, overdrive avdd and v gh 1.3 1.6 ma i en enable pin current en = 3.3v 3 a logic input characteristics v il low voltage threshold en, scl, sda 0.60 v v ih high voltage threshold en, scl, sda 1.2 v r il pull-down resistor en 0.75 1.15 1.55 m ? internal oscillator f osc switching frequency freq resistor = 10k ? 1.1 1.2 1.3 mhz freq resistor = 20k ? 550 600 650 khz avdd boost regulator avdd_rng avdd output voltage range 1.1*v in 16 v davdd/ diout avdd load regulation 10ma < i load < 250ma, t a = +25c 0.2 % davdd/ dv in avdd line regulation i load = 150ma, 2.2v < v in < 5.5v, t a = +25c 0.2 % v fb avdd feedback voltage i load = 100ma 1.188 1.200 1.212 v i fb input bias current fb pin 200 na r ds(on)_avdd switch on-resistance 150 190 m ? i lim_avdd switch current limit 2.0 2.5 3.0 a
ISL98665 6 fn8564.0 june 27, 2013 avdd_d max max duty cycle freq = 600khz 88 93 % v gh boost regulator v gh _rng v gh output voltage range 1.1* avdd 37.5 v i lim_vgh v gh switch current limit 0.8 1.2 1.6 a dv gh / di out load regulation 2ma < i load < 50ma, t a = +25c 0.2 % dv gh / dv in line regulation 2.2v < v in < 5.5v, i load = 5ma, t a = +25c 0.2 % r ds(on)_vgh v gh boost switch on resistance 0.6 0.8 ? v gh _d max maximum duty cycle freq = 600khz 90 94 % i fbp input bias current fbp pin 200 na v fbp v gh feedback voltage vrntc < 0.608v, v gh < 37.5v 0.592 0.608 0.622 v vrntc > 1.215v, v gh < 37.5v 1.188 1.215 1.239 v 0.608v < vrntc < 1.215v, v gh < 37.5v vrntc v hys_tcomp temperature compensation hysteresis 20 mv i rntc rntc current 200 na ldo regulator dv ldo / dv in line regulation i load = 1ma, 2.2v < v in < 5.5v, t a = +25c 0.3 % dv ldo / di out load regulation 1ma < i load < 300ma, t a = +25c 0.3 % v do dropout voltage v in = 2.2v, i load = 250ma 200 300 mv i lim_ldo current limit output drops by 5% 250 360 ma v ldo ldo output voltage i load = 50ma, t a = +25c 1.89 v v com amplifier i s_com v com block supply current avdd = 8v 0.7 1.35 ma v os offset voltage v pos = v neg = 0.5*avdd 15 mv i l input leakage current v pos = v neg = 0.5*avdd 0 1 a cmir common mode input voltage range 0avdd v cmrr common-mode rejection ratio v pos = v neg from 2v to 6v 60 75 db psrr power supply rejection ratio 8v < avdd < 12v v pos = v neg = 0.5*avdd 70 85 db v oh output voltage swing high i out (source) = 0.1ma avdd - 0.015 avdd - 0.005 v i out (source) = 75ma avdd - 1.74 avdd - 1.28 v v ol output voltage swing low i out (sink) = 0.1ma gnd + 0.001 gnd + 0.006 v i out (sink) = 75ma gnd + 0.94 gnd + 1.4 v electrical specifications v in = en = 3.3v, avdd = 8v, v ldo = 1.89v, v gh =21v. t a = +25c, unless otherwise specified . boldface limits apply over the operating temperat ure range, -40c to +105c. (continued) symbol parameter test conditions min (note 6) typ max (note 6) units
ISL98665 7 fn8564.0 june 27, 2013 i sc output short circuit current v out = avdd, v out shorted to gnd (sourcing) 135 180 ma v out = gnd, v out shorted to avdd (sinking) 170 220 ma sr slew rate rising, 0.5v v out +5.5v, r l = 10k ? || c l = 10pf to agnd 35 v/s falling, +5.5v v out 0.5v, r l = 10k ? || c l = 10pf to agnd 35 bw bandwidth (-3db) a v 1, r l = 10k ? || c l = 10pf to agnd 20 mhz v com calibrator (dvr) rset vr rset voltage resolu tion (note 7) 7 bits rset dnl rset differential nonlinearity t a = +25c, (note 8) 1 lsb rset zse rset zero-scale error t a = +25c, (note 8) 2 lsb rset fse rset full-scale error t a = +25c, (note 8) 8 lsb i rset rset current capability 105 a avdd to rset avdd to rset voltage attenuation 1.20 v/v fault detection threshold v uvlo undervoltage lock out threshold v in rising 1.85 2.0 2.15 v hysteresis 0.2 v ovp avdd avdd boost overvoltage protection avdd rising (note 9) 15.4 15.9 16.4 v hysteresis 1.3 v ovp vgh v gh boost overvoltage protection v gh rising 38 39 40 v t off thermal shutdown all channels temperature rising 150 c hysteresis 40 c power sequence t ss v logic v logic soft-start time 0.45 ms i ss avdd boost soft-start current at start-up 4a v ss soft-start voltage end of soft-start ramp 1 v t delay v gh delay from avdd start-up finish to v gh start v gh = 37.5v 2.5 ms t ss v gh v gh soft-start time v gh = 37.5v 33 ms eeprom eeprom endurance t a = +25c, 1 kcyc eeprom retention t a = +25c, 88 khrs notes: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. temperature limits established by characterization and are not production tested. 7. established by design. not a parametric spec. 8. compliance to limits is assure d by characterization and design. 9. boost will stop switching as soon as boost output reaches ovp threshold. electrical specifications v in = en = 3.3v, avdd = 8v, v ldo = 1.89v, v gh =21v. t a = +25c, unless otherwise specified . boldface limits apply over the operating temperat ure range, -40c to +105c. (continued) symbol parameter test conditions min (note 6) typ max (note 6) units
ISL98665 8 fn8564.0 june 27, 2013 typical performance curves figure 1. avdd efficiency vs i_a vdd figure 2. avdd load regulation figure 3. avdd line regulation figure 4. avdd transient response figure 5. v gh efficiency vs i_ v gh figure 6. v gh load regulation 76 78 80 84 86 88 0 50 100 150 200 250 efficiency (%) i_a vdd (ma) f osc = 600khz 82 f osc = 1.2mhz 90 f osc = 310khz v in = 3.3v, avdd = 8v inductor = nrs5010t, 10h diode = pmeg2005 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01 10 60 110 160 210 260 load regulation (%) i_a vdd (ma) f osc = 600khz f osc = 1.2mhz f osc = 310khz v in = 3.3v, avdd = 8v -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 2.2 2.7 3.2 3.7 4.2 4.7 5.2 a vdd boost v in (v) line regulation (%) f osc = 1.2mhz f osc = 310khz f osc = 600khz v in = 3.3v, avdd = 8v, i_a vdd = 150ma a vdd ripple = .200mv/div, i_a vdd = 100ma/div 2ms/div v in = 3.3v, avdd = 8v, i_a vdd = 50ma-250ma 50 55 60 65 70 75 80 85 90 0 5 10 15 20 25 30 35 40 45 50 efficiency (%) i_v gh (ma) f osc = 1.2mhz f osc = 600khz f osc = 310khz avdd = 8v, v gh = 21v inductor = nrs5010t, 10h diode = pmeg4005 -0.018 -0.016 -0.014 -0.012 -0.010 -0.008 -0.006 0.004 0.002 0.000 0 5 10 15 20 25 30 35 40 45 50 f osc = 600khz f osc = 1.2mhz f osc = 310khz i_v gh (ma) load regulation (%) v in = 8v, v gh = 21v
ISL98665 9 fn8564.0 june 27, 2013 figure 7. v gh line regulation figure 8. v gh transient response figure 9. v gh transient response figure 10. l do load regulation figure 11. l do line regulation figure 12. v com large signal transient response typical performance curves (continued) -0.002 0.000 0.002 0.004 0.006 0.008 0.010 0.012 0.014 0.016 0 2 4 6 8 10 12 14 16 18 20 f osc = 600khz line regulation (%) v gh boost v in (v) f osc = 1.2mhz f osc = 310khz ic_v in = 3.3v, v gh = 21v i_v gh = 5ma ic_v in = 3.3v, avdd = 8v, v gh = 21v i_v gh = 2ma-20ma v gh ripple= 200mv/div, i_v gh = 10ma/div 2ms/div v in = 3.3v, avdd = 8v v gh = 37.5v i_v gh = 2ma-20ma v gh ripple = 200mv/div, i_v gh = 10ma/div 2ms/div -0.300 -0.250 -0.200 -0.150 -0.100 -0.050 0.000 0 50 100 150 200 250 300 load regulation (%) i_ldo (ma) v in = 3.3v -0.300 -0.250 -0.200 -0.150 -0.100 -0.050 0.000 2.0 2.5 3.0 3.5 4.0 4.5 5 5.5 6.0 v in (v) line regulation (%) i ldo = 1ma input = 1v/div, output = 1v/div input signal output signal 500ns/div
ISL98665 10 fn8564.0 june 27, 2013 applications information enable control the ISL98665 is enabled when th e en pin voltage is high and v in is above rising uvlo. all output channels in ISL98665 are shut down when the enable pin is pulled down. switching frequency selection the ISL98665 switching frequency can be adjusted from 310khz to 1.2mhz by connecting a resistor between freq pin and agnd. a lower switching frequency redu ces power dissipation at very light load conditions but more easily allows discontinuous conduction mode. higher switching frequency allows for smaller external components - inductor and output capacitors. higher switching frequency will get higher efficiency for a given v in and loading range, depending on v in , v out and external components, as shown in figure 1. the calculation of the switching frequency is shown in equation 1 f sw is the desired boost switching frequency, and r fsw is the setting resistor (see r 8 in application diagram on page 3). figure 13 shows the relationship between the switching frequency and the frequency setting resistance. avdd boost operation the avdd boost converter is a current mode pwm converter operating at frequency ranging from 310khz or 1.2mhz. it can operate in both discontinuous conduction mode (dcm) at light load and continuous conduction mode (ccm). in continuous conduction mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. the voltage conversion ratio in contin uous current mode is given by equation 2: d is the duty cycle of the switching mosfet. the boost regulator uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. a comp arator looks at the peak inductor current cycle-by-cycle and terminates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal refe rence voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k ? is recommended. the boost converter output voltage is determined by equation 3: r 2 and r 3 are the feedback resistor values as shown in the ?application/block diagram? on page 3. the current through the mosfet is limited to 2.5a peak. this restricts the maximum output current (average) based on equation 4: eff is the efficiency of the avdd boost converter, i l is the peak-to-peak inductor ripple current, and is set by equation 5: where f sw is the switching frequency. soft-start the soft-start is provided by an internal current source of 4a to charge the external soft-start capacitor. the ISL98665 ramps up the current limit from 0a up to the full value, as the voltage at the ss pin ramps from 0v to 1v. hence, the soft-start time shown in figure 24 on page 21 is 5.5ms when the soft-start capacitor is 22nf, and 11.8ms for 47nf. v gh boost operation the vgh boost converter is a current mode pwm converter operating at frequency ranging fr om 310khz or 1.2mhz, which is the same with avdd boost switching frequency. it can operate in both discontinuous conduction mode (dcm) at light load and continuous conduction mode (ccm) at heavy load. the vgh boost regulator uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. a comp arator looks at the peak inductor current cycle-by-cycle and terminates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal refe rence voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for (eq. 1) f sw 1.14 10 10 () r fsw -------------------------------- = frequency (khz) figure 13. a vdd switching frequency vs resistance 0 200 400 600 800 1000 1200 1400 5 10 15 20 25 30 35 40 45 50 55 resistance (k ? ) (eq. 2) v avdd v in ------------------- - 1 1d ? ------------- = v avdd r 2 r 3 + r 3 -------------------- - v fb = (eq. 3) i omax i lmt i l 2 -------- ? ?? ?? v in v o --------- xeff = (eq. 4) i l v in l --------- d f sw ---------- = (eq. 5)
ISL98665 11 fn8564.0 june 27, 2013 noise being coupled into the feed back pin. the boost converter output voltage is determined by equation 6: where r 14 and r 15 are feedback resistors as shown in the ?application/block diagram? on page 3 the current through the mosfet is limited to 1.2a peak. in continuous conduction mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by equation 7: where d is the duty cycle of the switching mosfet, v in is the input voltage of v gh boost. in most applications, v in of the v gh boost converter is connected to the avdd. for most of the applications, the v gh boost converter operates in discontinuous conduction mode. the operation of boost converter in dcm is much more complicated than in ccm. the voltage conversion ratio is now a function not only of the duty cycle d, but also of the boost inductance, the switching frequency and the loading. in dcm, the volt age conversion ratio is given by equation 8. where f s is the switching frequency, v in is the input voltage of v gh boost, i out is the loading of v gh boost converter. v gh temperature compensation temperature compensation is integrated in ISL98665 to adjust v gh output voltage in order to compensate the amorphous silicon (a-si) shift register driving capability over temperature. a voltage divider with a ntc thermistor between avdd and ground should be used to determine the rntc voltage, as shown in figure 14. r 17 and r 18 can be adjusted to select the temperature range, based on the selection of the ntc thermistor. the v gh feedback voltage (thus v gh output voltage) is adjusted by the rntc voltage, which is varied by the ntc thermistor resistance at different temperatur e, as shown in figure 15. when the v gh voltage is below the ovp threshold, if rntc voltage is below 0.608v at higher temperature, the v gh feedback voltage is fixed at 0.608v. if rntc voltage is above 1.215v at lower temperature, the v gh feedback voltage is fixed at 1.215v. if rntc voltage is between 0.608v and 1.215v, the v gh feedback voltage follows rntc voltage. once v gh output voltage is above ovp threshold, the v gh output voltage will be regulated at 37.5v no matter what rntc voltage is. boost component selection input capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converter. a ceramic capacitor is recommended. the voltage rating of the input ca pacitor should be larger than the maximum input voltage. some input capacitors are recommended in table 1. inductor the boost inductor is a critical part that influences the output voltage ripple, transient respon se, and efficiency. values of 3.3h to 10h are used to match the internal slope compensation. if boost converter operates in ccm, the inductor must be able to handle the follo wing average and peak currents shown in equations 9 and 10: v gh r 14 r 15 + r 14 --------------------------- - v fbp = (eq. 6) v gh v in ------------ 1 1d ? ------------- = (eq. 7) (eq. 8) v gh v in ------------ 1 v in xd 2 i out x2xlxf s ------------------------------------ + = rntc r18 r17 ntc vlogic figure 14. rntc circuit table 1. boost converter input capacitor recommendation capacitor size mfg part number 10f/10v 0603 tdk c1608x5r1a106m 10f/16v 0805 tdk c2012x5r1c106k/0.85 figure 15. vfbp/vrntc vs temperature notes: 10. above fbp vs temperature curve is only true when v gh = vfbp*(ru+rl) / rl < ovp where ru is the upper resistance ( r 15 in ?application/block diagram? on page 3) and rl is the lower resistance ( r 14 in application diagram on page 3) in the fbp resistor ladder from v gh to agnd. 11. when v gh reach ovp, v gh boost regulates at 37.5v, regardless rntc voltage. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -20 -10 0 10 20 30 40 50 60 v o l t a g e ( v ) temperature (c) vrntc vfb 1.215v 0.608v r 17 = 5.11k , r 18 = 28k ntc = ncp15xm472
ISL98665 12 fn8564.0 june 27, 2013 where i l can be calculated using equation 5. if boost converter operates in dcm, the inductor must be able to handle the following average and peak currents shown in equations 11 and 12: some inductors are recommended in table 2 for different design considerations. rectifier diode a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode should be higher than the maximum output voltage. the rectifier diode must meet the output current and peak inductor current requirements. table 3 shows some recommendations for boost converter diode. output capacitor the output capacitor supplies curren t to the load during transient conditions directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: 1. the voltage drop due to the inductor ripple current flowing through the esr of the output capacitor. 2. charging and discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in equation 13 assumes the effective value of the capacitor at a particular voltage and not the manufacturer?s stated value, measured at 0v. it is recommended to use one or two 10f x5r 25v or equivalent ceramic output capacitors for avdd boost output and 4.7f x5r 50v or equivalent ceramic output capacitors for v gh boost output. table 4 shows some selections of output capacitors. compensation the boost converters of the isl 98665 can be compensated by an rc network connected from the comp pins to ground. for avdd, 15nf and 5.5k rc network is used in the demo board. for v gh , 15nf and 28k rc network is used in the demo board. the larger value resistor and lower value capacitor can lower the transient overshoot, however, at the expense of the stability of the loop. linear regulator (ldo) the ISL98665 includes an ldo wi th fixed output voltage of 1.89v. it can supply current up to 350ma. the efficiency of the ldo depends on the difference between input voltage and output voltage (equation 14) by assuming ldo quiescent current is much lower than ldo output current: the less difference between input and output voltage, the higher efficiency it is. ceramic capacitors are recommended for the ldo input and output capacitors. an output capacitor within the 1f to 4.7f range is recommended. larger capacitors help to reduce noise and deviation during transient lo ad change. some capacitors are recommended in table 5. table 2. boost converter inductor recommendation inductor dimensions (mm) mfg part number note 10h/ 4apeak 8.3x8.3x4.5 sumida cdrh8d43-100nc efficiency optimization 6.8h/ 1.8apeak 5.0x5.0x2.0 tdk plf5020t-6r8m1r8 10h/ 0.9a 5.0x5.0x1.0 taiyo yuden nrs5010t100mmgf pcb space/profile optimization table 3. boost converter rectifier diode recommendation diode v r /i avg rating package mfg avdd pmeg2010er 20v/1a sod123w nxp mss1p2u 20v/1a microsmp vishay v gh bas52-02v 45v/0.75a sod523f infineon db2j501 50v/0.2a sod323 panasonic (eq. 9) i lavg i out eff ------------- x vout v in ----------------- - = i lpk i lavg i l 2 -------- + = (eq. 10) (eq. 11) i lavg i out eff ------------- x vgh v in ------------- = i lpk v in l --------- d f s ---- = (eq. 12) table 4. boost output capacitor recommendation capacitor size mfg part number avdd 4.7f/25v 0805 tdk c2012x5r1e475k 10f/25v 0805 murata grm21br61e106ka73l v gh 4.7f/50v 0805 tdk c2012x5r1h475m 1f/50v 0603 tdk cga3e3x5r1h105k v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s ---- + = (eq. 13) % () v ldo_in v ldo_out ----------------------------- - ?? ?? ?? 100% = (eq. 14)
ISL98665 13 fn8564.0 june 27, 2013 v com amplifier the v com amplifier is designed to control the voltage on the back plane of an lcd display. this plane is capacitively coupled to the pixel drive voltage, which alternately cycles positive and negative at the line rate for the display. thus, the amplifier must be capable of sourcing and sinking pulses of current, which can occasionally be quite large (in the range of 100ma for typical applications). the ISL98665 v com amplifier is capable of rail-to-rail output swings and can drive wide range of capacitive loads. as load capacitance increases, the -3db bandwidth of the device will decrease and the peaking will increase. when driving large capacitive loads, an isolation resistor (typically between 1 and 10 ) should be placed in series with the output. the positive input of the v com amplifier (pos) is controlled by the dvr dac. however, if the dvr dac calibration function is not required, the v com amplifier can be used as an independent operational amplifier. leave the rset pin floating to disable the dvr dac function. i 2 c serial interface the ISL98665 uses a standard i 2 c interface bus for communication. the two-wire interface links a master(s) and uniquely addressable slave devi ces. the dvr of the ISL98665 operates as a slave device in all applications. the master generates clock signals and is re sponsible for initiating data transfers. the serial clock is on the scl line and the serial data (bi-directional) is on the sda line. the ISL98665 supports clock rates up to 400khz (fast-mode), and is backwards compatible with standard 100khz clock rates (standard-mode). the sda and scl lines must be high when the bus is not in use. an external pull-up resistor (typically 2.2k ? to 4.7k ? ) is required for sda and scl. the ISL98665 meets standard i 2 c timing and interface specifications, see table 6 and figure 16, which show the standard timing definition s and specifications for i 2 c communication. table 5. ldo output capacitor recommendation capacitor size mfg part number 1f/10v 0603 tdk c1608x7r1a105k 1f/6.3v 0603 murata grm188r70j105k 2.2f/6.3v 0603 tdk c1608x7r0j225k table 6. i 2 c timing and interface specifications symbol parameter min typ max units f scl scl frequency 400 khz t in pulse width suppression ti me at sda and scl inputs 50 ns t aa scl falling edge to sda output data valid 480 ns t buf time the bus must be free before the start of a new transmission 480 ns t low clock low time 480 ns t high clock high time 400 ns t su:sta start condition set-up time 480 ns t hd:sta start condition hold time 400 ns t su:dat input data set-up time 40 ns t hd:dat input data hold time 0 ns t su:sto stop condition set-up time 400 ns t hd:sto stop condition hold time for read, or volatile only write 400 ns t wp non-volatile write cycle time 25 ms c scl capacitive on scl 5 pf c sda capacitive on sda 5 pf
ISL98665 14 fn8564.0 june 27, 2013 protocol conventions data states on the sda line ca n change only during scl low periods. the sda state changes during scl high are reserved for indicating start and stop conditions (see figure 16). on power-up of the ISL98665, the sda pin is in the input mode. all i 2 c interface operations must be gin with a start condition, which is a high-to-low transition of the sda while scl is high. the dvr continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 16). a start condition is ignored during the power-up sequence and during internal non-volatile write cycles. all the i 2 c interface must be terminated by a stop condition, which is a low-to-high transition of sda while scl is high (see figure 16). a stop condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. a stop condition during a write operation to a non-volatile writ e byte, initiates an internal non-volatile write cycle. the device enters its standby state when the internal non-volatile write cycle is completed. an ack (acknowledge) is a software convention used to indicate a successful data transfer. the transm itting device, ei ther master or slave, releases the sda bus after tr ansmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 17). the ISL98665 dvr responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful receipt of an address byte. the ISL98665 also respond with an ack after re ceiving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. a valid identification byte contains 28h as the seven msbs. the lsb is in the read/write bit. its value is "1" for a read operation, and "0" for a write operation (see table 7). write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition (see figure 17). afte r each of the three bytes, the ISL98665 responds with an ack. when the write transaction is completed, the master should generate a stop condition. a stop condition also acts as a protection of non-volatile memory. a valid identification byte, address byte, and total number of scl pulses act as a pr otection of both volatile and non-volatile registers. during a write sequence, the data byte is loaded into an internal shift register as it is received. the data byte is transferred to the wr or to the acr respectively, at the falling edge of the scl pulse that loads the last bit (lsb) of the data byte. read operation a read operation consists of a th ree byte instruction followed by one or more data bytes (see figure 19). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to "0", an address byte, a second start, and a second identi fication byte with the r/w bit set to "1". after each of the three bytes, the ISL98665 responds with an ack; then the isl986 65 transmits the data byte. the master then terminates the re ad operation (i ssuing a stop condition) following the la st bit of the data byte. t su:sta start t hd:sta t r t f t su:dat t hd:dat stop start t buf t su:sto v ih v il v ih v il sda scl t r t f figure 16. i 2 c timing definition table 7. identification byte format 0101000r/w (msb) (lsb)
ISL98665 15 fn8564.0 june 27, 2013 ISL98665 dvr memory description the ISL98665 contains one non-volatile byte known as the initial value register (ivr). it is accessed by the i 2 c interface at address 00h. the ivr contains the value that is loaded into the volatile wiper register (wr) at power-up. the volatile wr, and the non-volatile ivr of the dvr are accessed with the same address 00h. the access control register (acr) determines which byte at address 00h is accessed (ivr or wr). the volatile acr must be set as follows: when the acr is 00h, which is the default at power-up: ? a read operation to address 00h outputs the value of the non-volatile ivr. ? a write operation to address 00h writes the identical values to the wr and ivr of the dvr. when the acr is 80h: ? a read operation to address 00h outputs the value of the volatile wr. ? a write operation to address 00h only writes to the volatile wr. it is not possible to write to the ivr without writing the same value to the wr. 00h and 80h are the only values that should be written to address 02h. all other values are reserved and must not be written to address 02h. register description: access control the access control register (acr) is volatile and is at address 02h. the msb of acr decides which byte is accessed at register 00h as shown in the following. all other bits of acr should be zero (0). ? 00h = nonvolatile ivr ? 80h = volatile wr all other bits of he acr should be written 0 or 1. power-up default for this address is 00h. register description: ivr and wr the output of the dvr is controlled directly by the wr. writes and reads can be made directly to this register to control and monitor without any non-volatile memory ch anges. this is done by setting address 02h to data 80h, then writing the data. the non-volatile ivr stores the power-up value of the dvr output. on power -up, the contents of the ivr are transferred to the wr. to write to the ivr, first address 02h is set to data 00h, then the data is written. writing a new value to the ivr register will set a new power- up position for the wiper. also, writing to this register will load the same value into the wr as the ivr. therefore, if a new value is loaded into the ivr, not only will the non-volatile ivr change, but the wr will also contain the same value after the write, and the wiper position will change. reading from the ivr will not change the wr, if its contents are different. figure 20 gives examples to show writing to ivr/wr and reading from ivr/wr. note: if the data byte is to be written only to wr, when the write transaction is completed, the devi ce enters its standby state. if the data byte is to be written al so to non-volatile memory (ivr), when the write transaction is completed, the ISL98665 begins its internal write cycle to non-volatile memory. during the internal non-volatile write cycle, the devi ce ignores transitions at the sda and scl pins and the sda output is at a high impedance state. when the internal non-volatile write cycle is completed, the ISL98665 enters its standby state. table 8. register map address (hex) non-volatile volatile 02 - acr 01 reserved 00 ivr wr note: wr: wiper register, ivr: initial value register.
ISL98665 16 fn8564.0 june 27, 2013 sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 17. acknowledge response from receiver s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the slave a c k 00 11 a c k write signal at sda 0000 00 0 00 0 0 x figure 18. byte write sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 00 11 s t o p a c k 01 0 11 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 00 0 000 00 000 0 00 x figure 19. read sequence
ISL98665 17 fn8564.0 june 27, 2013 initial v com setting the ISL98665 provides the ability to reduce the flicker of a tft-lcd panel during panel produc tion test and alignment. it offers an i 2 c programmable adjustment, which can be used to set the panel v com voltage. the device has a 128-step ?digital variable resistor? (dvr) control that adjusts an internal voltage that ultimately controls the sink curre nt (iset) output of the dvr_out node. the dvr_out pin is connected to an external voltage divider so that the device will have the capability to scale the voltage by increasing the dvr_out sink-current. the resistor on the set pin (r set ) determines the maximum (full scale) allowable sink-current, which determines the adjustment resolution (step size), as shown in figure 21. note: that r 1 in figure 21 corresponds to r 11 in the ?application/block diagram? on page 3. the r 2 in figure 21 corresponds to r 12 in the ?application/block diagram? on page 3. writing ? a ? new ? value ? to ? the ? ivr write ? to ? acr ? first 01010000a00000010a00000000a then, ? write ? to ? ivr 01010000a00000000a0d7d6d5d4d3d2d1a note ? that ? the ? wr ? will ? also ? reflect ? this ? new ? value ? since ? both ? registers ? get ? writen ? at ? the ? same ? time d1:lsb, ? d7:msb writing ? a ? new ? value ? to ? wr ? only write ? to ? acr ? first 01010000a00000010a10000000a then, ? write ? to ? wr 01010000a00000000a0d7d6d5d4d3d2d1a note ? that ? the ? ivr ? value ? will ? not ? change d1:lsb, ? d7:msb reading ? from ? ivr write ? to ? the ? acr ? first 01010000a00000010a00000000a then ? set ? the ? ivr ? address 01010000a00000000a read ? from ? the ? ivr 01010001a0d7d6d5d4d3d2d1 example ? 2 reading ? from ? the ? wr write ? to ? the ? acr ? first 01010000a00000010a10000000a then ? set ? the ? wr ? address 01010000a00000000a read ? from ? the ? wr 01010001a0d7d6d5d4d3d2d1 figure 20. example of write and read sequence for v com amplifier r set - + rset dvr_dac avdd r 1 r 2 avdd i set pos v out neg dvr_out figure 21. dvr_output circuit connection example
ISL98665 18 fn8564.0 june 27, 2013 figure 22, shows the relationship between the 7-bit dvr dac register value and the dvr?s tap position. the taps are generated from a resistor string between avdd and gnd. note: that a register value of 0 register value of 0 selects the first step of the resistor string. the output voltage of the internal dvr string is given in equation 15. r figure 23, shows the schematic of the dvr_out current sink. the combination of amplifier a1, transistor q1, and resistor r set forms a voltage-controlled current source, with the voltage determined by the dvr setting. the initial register value is at 64d by default. the wr value is set back to 64d if any error occurs during i 2 c read or write communication. when writing to the eeprom, v gh needs to be higher than 12v when avdd is 8v. outside these conditions, writing operations may not to be successful. the external r set resistor sets the full-scale (maximum) sink current that can be pulled from the dvr_out node (i set ). the i set can be up to 105 a maximum (this limit is set by the size of the internal metal interconnects). the relationship between the i set and the register value is shown in equation 16. the maximum value of i set can be calculated by substituting the maximum register value of 0 into equation 16, resulting in equation 17: equation 15 can also be used to calculate the unit sink current step size per register code, resulting in equation 18: determination of r set the ultimate goal for the dvr dac is to generate an adjustable voltage between two endpoints, v com_min and v com_max , with a fixed power supply voltage, avdd. this is accomplished by choosing the correct values for r set , r 1 and r 2 . the exact value of r set is not critical. r set values range from 3k to more than 100k will work under most conditions. equation 17 can be used to calculate the minimum value r set . larger r set values reduce quiescent power, since r 1 and r 2 are proportional to r set . equation 19 limits the minimum value for r set , which is based on the 105 a maximum output current sink. determination of r 1 and r 2 with avdd, v com (min) and v com (max) known and r set chosen per the above requirements, r 1 and r 2 can be determined using equations 20 and 21: v dvr 127 registervalue ? 128 ---------------------------------------------------------- - ?? ?? a vdd 20 --------------- - ?? ?? = (eq. 15) a vdd 19r r 126 125 124 0 1 2 3 register value (decimal) a vdd 20 v dvr 127 figure 22. dvr dac - simplified schematic i set v dvr r set --------------- - 127 registervalue ? 128 ---------------------------------------------------------- - ?? ?? a vdd 20 --------------- - ?? ?? 1 r set --------------- ?? ?? == (eq. 16) i set max () 127 128 --------- - a vdd 20r set ---------------------- = (eq. 17) i step a vdd 128 () 20 () r set () ----------------------------------------------- = (eq. 18) avdd r set v dvr rset pos/ dvr_out i set r 1 r 2 v sat v rset = v dvr = i set * r set q1 a1 v com vout neg gnd a2 i set v com amplifier figure 23. dvr current sink circuit r set avdd 20 105 () a ----------------------------------- - > (eq. 19) r 1 20.16 r set v com max () v com min () ? v com max () ----------------------------------------------------------------------- - ?? ?? ?? ? = (eq. 20) r 2 20.16 r set v com max () v com min () ? a vdd v com max () ? ----------------------------------------------------------------------- - ?? ?? ?? ? = (eq. 21)
ISL98665 19 fn8564.0 june 27, 2013 final transfer function for dvr the voltage at pos/dvr_out can be calculated from equation 22: with amplifier a2 (v com amplifier) in the unity-gain configuration (v out tied to neg as shown in figure 23), then pos = neg = v out . note: there can be a minor variance between pos and v out voltages due to the v com amplifier offset, refer to the v com amplifier ?v os ? specification in the ?electrical specifications table? on page 6. vgl charge pump an external charge pump driven by the avdd boost switching node can be used to generate vgl, as shown on the ?application/block diagram? on page 3. the number of the charge pump stages can be calculated using equation 23. where n is the number of the charge pump stages, v d is the forward voltage drop of one schottky diode used in the charge pump. v d is varied with forward current and ambient temperature, so it should be the maximum value in the datasheet of the diode chosen according to max forward current and lowest temperature in the application condition. once the number of the charge pump stages is determined, the maximum current that the charge pump can deliver can be calculated using equation 24: where f sw is the switching frequency of the avdd boost, c fly is the flying capacitance (c22 in ?a pplication/block diagram? on page 3). i vgl is the loading of vgl. fault protection overcurrent protection (ocp) the boost overcurrent protection limits the boost mosfet current on a cycle-by-cycle basis. when the mosfet current reaches the current limit threshold, the cu rrent pwm switching cycle is terminated and the mosfet is turned off for the remainder of that cycle. overcurrent protection does not disable any of the regulators. once the fault is removed (mosfet current falls below current limit), the ic will continue with normal operation. undervoltage lockout (uvlo) if the input voltage (v in ) falls below the falling uvlo, all the channels will be disabled. all the rails will restart with normal soft-start operation when the v in input voltage is applied again (v in > rising uvlo). refer to the ?electrical specifications table? on page 5 for the uvlo specifications. overvoltage protection (ovp) the avdd boost overvoltage protection monitors the avdd voltage through avdd pin. when the avdd pin voltage exceeds the ovp level, the avdd boost converter stops switching. no other channel faults out when avdd ovp happens. the v gh boost overvoltage protection monitors the v gh voltage through the vgh pin. when the vgh pin voltage exceeds the ovp level, the v gh boost converter regulates the output voltage at 37.5v. no other channel faults out when v gh ovp happens. over-temperature protection (otp) the ISL98665 has a hysteretic over-temperature protection threshold set at +150c (typ). if th is threshold is reached, all the channels are disabled immediately. when temperature falls by +40c (typ) then all the regulators automatically re-start. power on/off sequence when v in rising exceeds rising uvlo and en is high, v logic starts up with a 0.45ms soft-start time. avdd boost converter also starts up. the soft-start time of avdd depends on the capacitance on the ss pin. the 2.5ms after avdd soft-start is completed, the vgh boost converter starts up. the typical soft- start time of v gh is 33ms. at power off, when v in reaches falling uvlo, all channels shut down. the detailed power on/off sequence is shown in figure 24. v dvrout a vdd r 2 r 1 r 2 + -------------------- - ?? ?? ?? 1 127 registervalue ? 128 ---------------------------------------------------------- - r 1 20r set ---------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 22) (eq. 23) vgl headroom nxavdd 2xnxv d ? vgl ? 0 > = (eq. 24) vgl nx avdd ? 2xv d i vgl f sw xc fly () ----------------------------- - ++ ?? ?? ?? =
ISL98665 20 fn8564.0 june 27, 2013 layout recommendation the device's performance, including efficiency, output noise, transient response and control loop stability, is affected by the pcb layout. the pcb layout is critical, especially at high switching frequency. following are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and thick as possible to minimize parasitic inductance and resistance. 2. the input bypass capacitor should be connected to the vin pin with the smallest trace possible. 3. loops with large ac amplitudes and fast slew rate should be made as small as possible. 4. the feedback network should sense the output voltage directly from the point of load. minimize feedback track lengths to avoid switching noise pick-up. 5. digital input pins and en, should be isolated from the high di/dt and dv/dt signals. otherwis e, it may cause a glitch on those inputs. 6. i 2 c signals, if not used, should be tied to v in . 7. analog ground (agnd) and po wer ground (pgnd) should be separated on pcb. the agnd is a quite ground plane with no large currents flowing through it for all the low-current sensitive analog and digital si gnals. the compensation and feedback components, soft start capacitors and bias input bypass capacitors need to be connected to agnd. agnd should be on a clearer layer and kept away from the noise. the pgnd plane carries high currents, all the power components should be connected to pgnd. agnd and pgnd should be connected to each other on the pcb at a single point. it is crucial to connect these two grounds at the location very close to the ic. 8. the power ground (pgnd) should be connected at the ISL98665 exposed die plate area. 9. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissipation to the surrounding air. a demo board is available to illustrate the proper layout implementation.
ISL98665 21 fn8564.0 june 27, 2013 power-on/off sequence vin uvlo en uvlo vlogic avdd vgl vgh 2.5ms vss pull to gnd charging vss cap with 4a vss=vin en = h vss = vin vgh soft-start = 33ms avdd soft-start vlogic soft-start = 0.45ms vss = 1v, avdd soft-start finish figure 24. power-on/off sequence
ISL98665 22 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8564.0 june 27, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change june 27, 2013 fn8564.0 initial release
ISL98665 23 fn8564.0 june 27, 2013 package outline drawing l28.4x5c 28 lead thin quad flat no-lead plastic package rev 0, 9/08 typical recommended land pattern detail "x" top view bottom view side view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 5.00 (4x) 0.15 6 pin 1 index area 23 pin #1 index area 28 2.50 24x 0.50 exp. dap 8 1 22 14 28x 0.400 9 6 3.50 max 0.80 see detail "x" seating plane 0.08 0.10 c c c ( 4.80 ) ( 3.50 ) ( 28 x 0.60) (28x .250) ( 24x 0.50) ( 3.80 ) ( 2.50) 2.50 0.10 28x 0.25 a mc b 4 3.50 exp. dap 15 side view unless otherwise specified, tolerance : decimal 0.05 the configuration of the pin #1 identifier is optional, but must dimensioning and tolerancing conform to amse y14.5m-1994. 3. 6. 2. dimensions are in millimeters. 1. notes: be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. dimensions in ( ) for reference only. dimension applies to the metallized terminal and is measured 4. tiebar shown (if present) is a non-functional feature. between 0.15mm and 0.30mm from the terminal tip. 5.

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