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october 2015 docid027717 rev 2 1 / 12 this is information on a product in full production. www.st.com STW65N80K5 n - channel 800 v, 0.07 typ., 46 a mdmesh? k5 power mosfet in a to - 247 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STW65N80K5 800 v 0.08 46 a 446 w ? industrys lowest r ds(on) x area ? industrys best figure of merit (fom) ? ultra low gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description this very high voltage n - channel power mosfet is designed using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic reducti on in on - resistance and ultra - low gate charge for applications requiring superior power density and high efficiency. table 1: device summary order code marking package packing STW65N80K5 65n80k5 to - 247 tube t o-247 1 2 3
contents STW65N80K5 2 / 12 docid027717 rev 2 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 to - 247 package information ................................ ............................. 9 5 revision history ................................ ................................ ............ 11
STW65N80K5 electrical ratings docid027717 rev 2 3 / 12 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d drain current (continuous) at t case = 25 c 46 a drain current (continuous) at t case = 100 c 30 i dm (1) drain current (pulsed) 184 a p tot total dissipation at t case = 25 c 446 w dv/dt (2) peak diode recovery voltage slope 4.5 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 t stg storage temperature - 55 to 150 c t j operating junction temperature notes: (1) pulse width is limited by safe operating area. (2) i sd 46 a, di/dt=100 a/s; v ds peak < v (br)dss , v dd = 80% v (br)dss . (3) v ds 640 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 0.28 c/w r thj - amb thermal resistance junction - ambient 50 table 4: avalanche characteristics symbol parameter value unit i ar (1) avalanche current, repetitive or not repetitive 16 a e as (2) single pulse avalanche energy 700 mj notes: (1) pulse width limited by t jmax . (2) starting t j = 25 c, i d = i ar , v dd = 50 v.
electrical characteristics STW65N80K5 4 / 12 docid027717 rev 2 2 electrical characteristics (t case = 25 c unless otherwise specified) table 5: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 800 v i dss zero gate voltage drain current v gs = 0 v, v ds = 800 v 1 a v gs = 0 v, v ds = 800 v, t case = 125 c 50 i gss gate - body leakage current v ds = 0 v, v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 23 a 0.07 0.08 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 3230 - pf c oss output capacitance - 310 - c rss reverse transfer capacitance - 3 - c oss(eq) (1) equivalent output capacitance v ds = 0 to 640 v, v gs = 0 v - 734 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 1.9 - q g total gate charge v dd = 640 v, i d = 46 a, v gs = 10 v (see figure 14: "test circuit for gate charge behavior" ) - 92 - nc q gs gate - source charge - 18 - q gd gate - drain charge - 65 - notes: (1) c oss(eq) is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 400 v, i d = 23 a r g = 4.7 , v gs = 10 v (see figure 13: "test circuit for resistive load switching times" and figure 18: "switching time waveform" ) - 34 - ns t r rise time - 30 - t d(off) turn - off delay time - 90 - t f fall time - 10 -
STW65N80K5 electrical characteristics docid027717 rev 2 5 / 12 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 46 a i sdm (1) source - drain current (pulsed) - 184 a v sd (2) forward on voltage v gs = 0 v, i sd = 46 a - 1. 5 v t rr reverse recovery time i sd = 46 a, di/dt = 100 a/s, v dd = 60 v (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 650 ns q rr reverse recovery charge - 20 c i rrm reverse recovery current - 60 a t rr reverse recovery time i sd = 46 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 845 ns q rr reverse recovery charge - 28 c i rrm reverse recovery current - 66 a notes: (1) pulse width is limited by safe operating area. (2) pulse test: pulse duration = 300 s, duty cycle 1.5%. table 9: gate - source zener diode symbol parameter test conditions min. typ. max. unit v (br)gso gate - source breakdown voltage i gs = 1 ma, i d = 0 a 30 - - v the built - in back - to - back zener diodes are specifically designed to enhance the esd performance of the device. the zener voltage facilitates efficient and cost - effective device integrity protection, thus eliminating the need for additional external componentry.
electrical characteristics STW65N80K5 6 / 12 docid027717 rev 2 2.1 electrical characteristics (cu rves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STW65N80K5 elec trical characteristics docid027717 rev 2 7 / 12 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : maximum avalanche energy vs temperature
test circuits STW65N80K5 8 / 12 docid027717 rev 2 3 test circuits figure 13 : test circuit for resistive load switching times figure 14 : test circuit for gate charge behavior figure 15 : test circuit for inductive load switching and diode recovery times figure 16 : unc lamped inductive load test circuit figure 17 : unclamped inductive waveform figure 18 : switching time waveform
STW65N80K5 package information docid027717 rev 2 9 / 12 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 to - 247 package information figure 19 : to - 247 packa ge outline
package information STW65N80K5 10 / 12 docid027717 rev 2 table 10: to - 247 package mechanical data dim. mm. min. typ. max. a 4.85 5.15 a1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 d 19.85 20.15 e 15.45 15.75 e 5.30 5.45 5.60 l 14.20 14.80 l1 3.70 4.30 l2 18.50 ?p 3.55 3.65 ?r 4.50 5.50 s 5.30 5.50 5.70
STW65N80K5 revision history docid027717 rev 2 11 / 12 5 revision history table 11: document revision history date revision changes 21 - may - 2015 1 first release. 02 - oct - 2015 2 text and formatting changes throughout document. datasheet status promoted from preliminary to production data. on cover page: - updated title description and features table. updated sections - electrical ratings and electrical characteristics. add ed section - electrical characteristics (curves).
STW65N80K5 12 / 12 docid027717 rev 2 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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