this is information on a product in full production. march 2014 docid022192 rev 3 1/10 10 ESDAVLC8-4BN4 4-line very low capacitance transil? array for esd protection datasheet ? production data figure 1. functional diagram (top view) features ? stand-off voltage: 3 v ? very low capacitance: 4.5 pf ? small package: 1.0 x 0.8 mm ? very thin package: 0.40 mm max ? low leakage current: 50 na at 25 c benefits ? high esd robustness of the equipment ? suitable for high speed interface complies with the following standards: ? iec 61000-4-2: ? 15 kv (air discharge) ? 8 kv (contact discharge) ? mil std 883g- method 3015-7: class3b: ? >25 kv (human body model) applications where transient overvoltage protection and electrical overstress protection in sensitive equipment is required, such as: ? communication systems ? cellular phone handsets and accessories ? video equipment description the ESDAVLC8-4BN4 is monolithic array designed to protect up to 4 lines against esd transients. it has been designed specifically for the protection of the high speed interface of integrated circuits in portable equipment and miniaturized electronics devices. the qfn-4l package minimizes pcb space. tm: transil is a trademark of stmicroelectronics. qfn-4l gnd i/o1 i/o2 i/o3 i/o4 www.st.com
characteristics ESDAVLC8-4BN4 2/10 docid022192 rev 3 1 characteristics figure 2. electrical characteristics (definitions) note: for component test in its final application, the minimum clamping voltage has to be 20 v on v br1 (gnd to i/o) and 25 v on v br2 (i/o to gnd). table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp peak pulse voltage, iec 61000-4-2, level 4 (contact discharge) 16 kv p pp peak pulse power dissipation (8/20 s) (1) t j initial = t amb 1. for a surge greater than the maximum values, the diode will fail in short-circuit. gnd to i/o i/o to gnd 45 32 w i pp peak pulse current (8/20 s) 1.6 a t j maximum junction temperature range -40 to 125 c t stg storage temperature range -55 + 150 c table 2. electrical characteristics (values, t amb = 25 c) symbol test conditions min. typ. max. unit v br1 i r = 1 ma, gnd to i/o 8.5 11 14 v v br2 i r = 1 ma, i/o to gnd 14.5 17 20 v i rm v rm = 3 v 50 na v cl i pp = 1 a, 8/20 s, gnd to i/o 20 v i pp = 1 a, 8/20 s, i/o to gnd 28 cv i/o = 0 v, f = 1 mhz, v osc = 30 mv 4.5 5.5 pf r d dynamic resistance, pulse width 100 ns i/o to gnd 0.36 gnd to i/o 0.28 symbol parameter v = breakdown voltage i = leakage current @ v v = stand-off voltage i = peak pulse current br rm rm rm pp v = clamping voltage cl
docid022192 rev 3 3/10 ESDAVLC8-4BN4 characteristics figure 3. peak pulse power versus initial junction temperature (8/20 s waveform) figure 4. peak pulse power versus exponential pulse duration p pp (w) 0 20 40 60 80 100 25 35 45 55 65 75 85 95 105 115 125 135 145 8/20 s direct reverse t (c) j p (w) pp 1 10 100 10 100 1000 t j =25 c direct reverse t (s) p figure 5. clamping voltage versus peak pulse current (typical values, 8/20 s waveform) figure 6. junction capacitance versus reverse voltage applied (typical values) i (a) pp 0.1 1.0 10.0 10 20 30 8/20s tj initial = 25 c direct reverse v (v) cl c(pf) 0.0 1.0 2.0 3.0 4.0 5.0 0123456 f=1 mhz v osc =30mv rms vr=0v t j =25 c direct reverse v r (v) figure 7. esd response to iec 61000-4-2 (+8 kv contact discharge) on each channel figure 8. esd response to iec 61000-4-2 (-8 kv contact discharge) on each channel 10 v/div 20 ns/div 10 v/div 20 ns/div
characteristics ESDAVLC8-4BN4 4/10 docid022192 rev 3 figure 9. s21 attenuation measurement figure 10. analog crosstalk measurement -30.00 1.0 m 10.0 m 100.0 m 1.0 g -25.00 -20.00 -15.00 -10.00 -5.00 0.00 db 100.0 k f/hz 100.0k 1.0m 10.0m 100.0m 1.0g -100.00 -90.00 -80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00 db f/hz figure 11. leakage current versus junction temperature (typical values) figure 12. tlp measurement i r (na) 0.01 0.10 1.00 10.00 25 35 45 55 65 75 85 95 105 115 125 v r =v rm=3 v direct reverse t j (c) i pp (a) 0 5 10 15 20 25 0 5 10 15 20 25 v cl (v) gnd to i/o i/o to gnd
docid022192 rev 3 5/10 ESDAVLC8-4BN4 package information 2 package information ? epoxy meets ul94, v0 ? lead-free package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 13. qfn- 4l dimension definitions table 3. qfn- 4l dimension values ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.31 0.38 0.40 0.012 0.015 0.016 a1 0.00 0.02 0.05 0.00 0.0008 0.002 b 0.10 0.15 0.20 0.004 0.006 0.008 d 0.70 0.80 0.90 0.028 0.031 0.035 d2 0.50 0.58 0.65 0.020 0.023 0.026 e 0.35 0.40 0.45 0.014 0.016 0.018 e 0.90 1.00 1.10 0.035 0.039 0.043 e2 0.15 0.20 0.25 0.006 0.008 0.010 l 0.18 0.23 0.28 0.007 0.009 0.011 l1 0.00 -- 0.05 0.00 -- 0.002 a a1 d e d2 e e2 l1 b l 1 4 2 3 index area
package information ESDAVLC8-4BN4 6/10 docid022192 rev 3 note: product marking may be rotated by multiples of 90 for assembly plant differentiation. in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. figure 16. tape and reel specifications figure 14. footprint dimensions (in mm) figure 15. marking 0.4 0.43 0.2 0.18 0.17 0.58 0.58 1.4 b dot identifying pin a1 location user direction of unreeling all dimensions are typical values in mm 4.0 2.0 2.0 8.0 1.75 3.5 ? 1.55 0.63 0.89 0.22 1.07 b b b b b b b
docid022192 rev 3 7/10 ESDAVLC8-4BN4 recommendation on pcb assembly 3 recommendation on pcb assembly 3.1 stencil opening design reference design ? stencil opening thickness: 100 m ? stencil opening for leads: opening to footprint ratio is 100%. figure 17. recommended stencil window position 3.2 solder paste 1. halide-free flux qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste is recommended. 3. offers a high tack force to resist component movement during high speed. 4. solder paste with fine particles: powder particle size is 20-45 m. 180 m footprint footprint t=100 m and opening ratio is 100% 580 m 200 m 430 m stencil window
recommendation on pcb assembly ESDAVLC8-4BN4 8/10 docid022192 rev 3 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks and open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 3.5 reflow profile figure 18. st ecopack ? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
docid022192 rev 3 9/10 ESDAVLC8-4BN4 ordering information 4 ordering information figure 19. ordering information scheme 5 revision history table 4. ordering information order code marking package weight base qty delivery mode ESDAVLC8-4BN4 b (1) 1. the marking can be rotated by multiples of 90 to differentiate assembly location qfn-4l 1.17 mg 10000 tape and reel esda vlc 8 4 b n4 esd array very low capacitance package 8 = 8.5 volts min 4 = 4 lines b = bidirectional breakdown voltage number of lines direction n4 = qfn-4l table 5. document revision history date revision changes 06-sep-2011 1 initial release. 25-sep-2012 2 updated ecopack statement. 25-mar-2014 3 for table 2 added maximum values for v br1 and v br2 , and the note following the table.updated values for dynamic resistance in table 2 and added figure 12 .
ESDAVLC8-4BN4 10/10 docid022192 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com
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