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general description the max3992 is a 10gbps clock and data recovery (cdr) with equalizer ic for xfp optical transmitters. the max3992 and the max3991 (cdr with limiting amplifier) form a signal conditioner chipset for use in xfp trans- ceiver modules. the chipset is xfi compliant and offers multirate operation for data rates from 9.95gbps to 11.1gbps. the max3992 recovers the data for up to 12 inches of fr-4 and one connector without the need for a stand- alone equalizer. the phase-locked loop is optimized for jitter tolerance in sonet, ethernet, and fibre-channel applications. low jitter generation of 4mui rms leaves adequate margin for meeting sonet jitter requirements at the optical output. an ac-based power detector asserts the loss-of-signal (los) output when the input signal is removed. an exter- nal reference clock, with frequency equal to 1/64 or 1/16 of the serial data rate, is used to aid in frequency acqui- sition. a loss-of-lock (lol) indicator is provided to indi- cate the lock status of the receiver pll. the max3992 is available in a 4mm x 4mm, 24-pin qfn package. it consumes 356mw from a single +3.3v sup- ply and operates over a 0c to +85? temperature range. applications 9.95gbps to 11.1gbps optical xfp modules sonet oc-192/sdh stm-64 xfp transceivers 10.3gbps/11.1gbps ethernet xfp transceivers 10.5gbps fibre-channel xfp transceivers 10gbps dwdm transceivers 10gbps xfp copper modules high-speed backplane interconnects features ? multirate operation from 9.95gbps to 11.1gbps ? span up to 300mm (12in) fr4 with one connector ? low-output jitter generation: 4mui rms ? low-output deterministic jitter: 4.6ps p-p ? xfi-compliant input interface ? los indicator ? lol indicator ? power dissipation: 356mw max3992 10gbps clock and data recovery with equalizer ________________________________________________________________ maxim integrated products 1 19-3496; rev 0; 11/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin- package pkg code MAX3992UTG 0? to +85? 24 qfn t2444-4 MAX3992UTG+* 0? to +85? 24 qfn t2444-4 v cc 1 gnd 2 sdi- 3 sdi+ 4 gnd 5 v cc 6 v cc 18 gnd 17 sdo- 16 sdo+ 15 gnd 14 v cc 13 sclko+ 7 sclko- 8 fctl2 9 pol 10 v cc 11 cfil 12 vth 24 fctl1 23 refclk- 22 refclk+ 21 los 20 lol 19 max3992 4mm x 4mm qfn* *the exposed pad must be connected to circuit-board ground for proper thermal and electrical performance. top view pin configuration typical application circuit appears at end of data sheet. * future product? ontact factory for availability. + denotes lead-free package.
max3992 10gbps clock and data recovery with equalizer 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc ..............................................-0.5v to +4.0v input voltage levels (sdi+, sdi-, refclk+, refclk-) ....................................(v cc - 1.0v) to (v cc + 0.5v) cml output voltage (sdo+, sdo-, sclko+, slcko-) ......................................(v cc - 1.0v) to (v cc + 0.5v) voltage at (cfil, lol, vth, pol, los, fctl1, fctl2) ..............................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +85 c) 24-pin qfn (derate 20.8mw/ c above +85 c) .........1355mw junction temperature range .............................-40 c to+150 c storage temperature range...............-55 c to +150 c lead temperature (soldering, 10s) ....+300 c electrical characteristics (see table 1 for operating conditions. typical values at v cc = +3.3v, t a = +25?, unless otherwise noted.) parameter sym b o l conditions min typ max units supply current i cc 108 145 ma data input specification (sdi) single-ended input resistance r se 42 50 58 ? differential input resistance r d 84 100 116 ? single-ended input resistance matching ? % 0.1ghz to 5.5ghz (note 1) 15 differential-input return loss sdd11 5.5ghz to 12ghz (note 1) 6 db differential to common-mode conversion scd11 0.1ghz to 15ghz 17 db common-mode input return loss scc11 0.1ghz to 15ghz 7 db reference clock specification (refclk) single-ended input resisitance 84 100 116 ? differential input resistance 168 200 232 ? cml output specification (sdo) sdo?differential output swing (note 2) 575 650 725 mv p-p sdo?output common-mode voltage rl = 50 ? to v cc v cc - 0.16 v sclko?differential output 380 mv p-p single-ended output resistance 42 50 58 ? differential output resistance r o 84 100 116 ? single-ended output resistance matching ? % 0.1ghz to 5.5ghz (note 1) 13 differential-output return loss sdd22 5.5ghz to 12ghz (note 1) 8 db rise/fall time (20% to 80%) (note 2) 18 23 30 ps power-down assert time (note 3) 50 ?
max3992 10gbps clock and data recovery with equalizer _______________________________________________________________________________________ 3 electrical characteristics (continued) (see table 1 for operating conditions. typical values at v cc = +3.3v, t a = +25?, unless otherwise noted.) parameter sym b o l conditions min typ max units jitter specification 120khz < f 8mhz (notes 2, 4) 0.05 0.25 jitter peaking j p f 120khz (notes 2, 4) 0.03 db jitter transfer bandwidth j bw (notes 2, 4) 5.6 8.0 mhz f = 400khz 2.2 >2.8 ( n ote 5) f = 4mhz 0.4 0.55 sinusoidal jitter tolerance (notes 2, 4, 6) f = 80mhz 0.4 0.45 ui p-p jitter generation (notes 2, 4, 7) 4 6.9 mui rms serial-data output deterministic jitter dj prbs 2 7 - 1 (note 2) 4.6 13 ps p-p pll acquisition/lock specification acquisition time figures 1, 2 (note 2) 200 ? lol assert time figure 1 (note 2) 90 ? maximum frequency pullin time (note 8) 2 ms frequency difference at which lol is asserted ? f/f refclk ? f = | f vco / n - f refclk | , n = 16 or 64 651 ppm frequency difference at which lol is deasserted ? f/f refclk ? f = | f vco / n - f refclk | , n = 16 or 64 500 ppm loss-of-signal (los) specification vth control voltage range vth 150 500 mv los gain factor vth/ v los_assert 10 v/v minimum los assert voltage v los_assert 15 mv maximum los assert voltage v los_assert 50 mv los gain-factor accuracy (notes 2, 9) -1.5 +1.5 db los hysteresis (notes 2, 10) 3.5 3.7 3.9 db los gain-factor stability (note 2) overtemperature and supply -10 +10 % los assert time figure 2 (note 2) 3 90 s los deassert time figure 2 (note 2) 90 ? vth input current -5 +5 ? lvttl input/output specification (lol, los, fctl1, fctl2) input high voltage v ih 2.0 v input low voltage v il 0.8 v input current -30 +30 ? output high voltage v oh sourcing 30? v cc - 0.5 v output low voltage v ol sinking 1ma 0.4 v
max3992 10gbps clock and data recovery with equalizer 4 _______________________________________________________________________________________ electrical characteristics (continued) (see table 1 for operating conditions. typical values at v cc = +3.3v, t a = +25?, unless otherwise noted.) note 1: measured with 100mv p-p differential amplitude. note 2: guaranteed by design and characterization. note 3: measured from the time that the fctl1 input goes high with fctl2 = 0, to the time when the supply current drops to less than 40% of the nominal value. note 4: measured with prbs = 2 31 - 1. note 5: measurement limited by test equipment. note 6: jitter tolerance is for ber 10 -12 , measured with additional 0.1vi deterministic jitter through 15 inches of fr4. (see typical operating characteristics 1.) note 7: measured with 50khz to 80mhz sonet filter. note 8: applies on power-up or after standby. note 9: over process, temperature and supply. note 10: hysteresis is defined as 20log(v los-deassert /v los-assert ). table 2. serial data rate and reference clock frequency application data rate (rb) (g bps) /16 reference clock frequency (mhz) /64 reference clock frequency (mhz) oc-192 sonet ?sdh64 9.95328 622.08 155.52 oc-192 sonet over fec 10.664 666.5 166.625 itu g.709 10.709 669.3125 167.328125 10gbps ethernet, ieee 802.3ae 10.3125 644.53125 161.1328125 10gbps ethernet over itu g.709 11.09573 693.483125 173.3707813 10gbps fibre channel 10.51875 657.421875 164.355469 table 1. operating conditions (unless otherwise noted, fctl1 = fctl2 = 0.) parameter symbol conditions min typ max units supply voltage v cc 3.0 3.6 v ambient temperature t a 0 +85 ? input data rate rb (see table 2) gbps differential input voltage to transmission line v d 0 to 12 inches fr-4 400 1000 mv p-p output load resistance rl rl is ac-coupled 50 ? refclk?differential input voltage swing 300 1600 mv p-p refclk duty cycle 30 70 % rb / 16 refclk frequency f refclk rb / 64 ghz refclk accuracy relative to rb / 16 or rb / 64 -100 +100 ppm f refclk = rb / 64 1200 refclk rise/fall times (20% to 80%) f refclk = rb / 16 300 ps refclk random jitter noise bandwidth < 100mhz 10 ps rms note: the part should be in standby mode when data rates are being switched.
max3992 10gbps clock and data recovery with equalizer _______________________________________________________________________________________ 5 figure 1. tx lol assert and pll acquisition time lol acquisition time lol assert time *assert and acquisition time are defined with a valid reference clock applied. 651ppm 500ppm ? f/f refclk figure 2. los assert/deassert time los los deassert time data input power los assert time lol acquisition time
max3992 10gbps clock and data recovery with equalizer 6 _______________________________________________________________________________________ t ypical operating characteristics (v cc = 3.3v, t a = +25 c, unless otherwise noted.) normalized bit time (ui) max3992 input (15in fr-4) max3992 toc01 differential signal amplitude (mv) -500 -50 50 500 00.3 5 0.65 1 recovered reference signal prbs 2 31 -1 15in fr-4 max3992 toc02 differential signal amplitude (100mv/div) normalized bit time (ui) 0 1 0 6 4 2 8 10 12 14 16 020 10 30 40 50 jitter generation vs. power-supply white noise amplitude (bw < 100khz) max3992 toc03 noise amplitude (mv rms ) jitter generation (mui rms ) prbs 2 31 -1 power-supply induced output jitter vs. ripple frequency max3992 toc04 frequency (hz) jitter generation (ps p-p/ mv p-p ) 1m 100k 10k 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0 1k 10m sinusoidal jitter tolerance 12in fr-4 2 31 -1 prbs data max3992 toc05 frequency (hz) jitter tolerance (u| p-p ) 10m 1m 100k 1 10 100 0.01 1k 10k 100m tolerance exceeds modulation capabilities of test equipment xfi telecom mask 0.1 jitter transfer max3992 toc06 frequency (hz) jitter transfer (db) 10m 1m 10k 100k -18 -15 -12 -9 -6 -3 0 3 -21 1k 100m 80 110 100 90 120 130 140 -10 30 20 010 40506 0708090 max3992 supply current vs. temperature max3992 toc07 temperature ( c) supply current (ma) differential s11 sdd11 max3992 toc08 frequency (hz) sdd11 (db) 10g 1g 100m -35 -30 -25 -20 -15 -10 -5 0 5 10 -40 10m 100g xfi mask
max3992 10gbps clock and data recovery with equalizer _______________________________________________________________________________________ 7 t ypical operating characteristics (continued) (v cc = 3.3v, t a = +25 c, unless otherwise noted.) common mode s11 scc11 max3992 toc09 frequency (hz) scc11 (db) 10g 1g 100m -35 -30 -25 -20 -15 -10 -5 0 -40 10m 100g xfi mask differential to common mode s11 scd11 max3992 toc10 frequency (hz) scd11 (db) 10g 1g 100m -50 -40 -30 -20 -10 0 -60 10m 100g xfi mask pin name function 1, 6, 11, 13, 18 v cc +3.3v power supply 2, 5, 14, 17 gnd supply ground 3 sdi- negative serial input, cml 4 sdi+ positive serial input, cml 7 sclko+ positive clock output, cml. see table 3 for information about enabling the sclko output (for use in device testing). 8 sclko- negative clock output, cml. see table 3 for information about enabling the sclko output (for use in device testing). 9 fctl2 function control input 2, ttl. see table 3 for more information. 10 pol data polarity control input, ttl. connect to v cc or leave open to maintain the same polarity as the input. connect to gnd to invert the polarity of the data. 12 cfil loop-filter capacitor connection. connect a 0.047? capacitor between cfil and v cc . 15 sdo+ positive serial data output, cml 16 sdo- negative serial data output, cml 19 lol lock status indicator, ttl. this output goes high to indicate the receiver is out of lock. 20 los receiver loss-of-signal indicator, ttl . this output goes high when the input signal is removed. 21 refclk+ positive reference clock input, digital. the refclk inputs are designed to be ac-coupled to the reference clock source. refclk?have a 200 ? differential impedance. see the detailed description section for more information. see table 2. pin description
max3992 detailed description the max3992 clock and data recovery with equalizer recovers data from the xfi interface. it consists of an equalizer with los power detector and a data retimer with lol indicator. an optional recovered clock may also be enabled for performance testing. equalizer the sdi inputs of the max3992 accept serial nrz data from xfi standard interfaces. when signals from 400mv p-p to 1000mv p-p are applied to a transmission line from 0 to 12 inches of fr-4, the equalizer restores them for recovery by the cdr. the equalizer removes most of the deterministic jitter caused by frequency dependent skin effect and dielectric losses, as well as connector loss. pll retimer the integrated pll recovers a synchronous clock that is used to retime the input data. connect a 0.047? capacitor between cfil and v cc to provide pll damp- ening. the external reference connected to refclk aids in frequency acquisition. because the reference clock is only used for frequency acquisition, an extremely low jitter generation can be achieved from a low-quality reference clock. the reference clock should be within ?00ppm of the bit rate divided by 16 or 64. 10gbps clock and data recovery with equalizer 8 _______________________________________________________________________________________ figure 3. functional diagram functional diagram max3992 vth equalizer vco dff dq cml cml phase/ frequency detector lol detector los lol functional control cfil cml sdi+ sdi- refclk+ refclk- sdo+ sdo- sclko+ sclko- fctl1 fctl2 pll 200 ? pol pin description (continued) pin name function 22 refclk- negative reference clock input, digital. the refclk inputs are designed to be ac-coupled to the reference clock source. refclk?have a 200 ? differential impedance. see the detailed description section for more information. see table 2. 23 fctl1 function control input 1, ttl. see table 3 for more information. 24 vth los threshold input, analog. a voltage applied to this input sets the los assert threshold. the los power detector can be disabled if vth is connected to v cc , which forces los low. ep exposed pad supply ground. the exposed pad must be soldered to the circuit-board ground for proper thermal and electrical performance. the max3992 uses exposed-pad variation t2444-4 in the package outline drawing. see the exposed-pad package.
loss-of-lock monitor the lol output indicates that the frequency difference between the recovered clock and the reference clock is excessive. lol may assert due to excessive jitter at the data input, incorrect frequency, or loss of input data. the lol detector monitors the frequency difference between the recovered clock and the reference clock. the lol output is asserted high when the frequency difference exceeds 650ppm. loss-of-signal monitor the los output indicates a loss of input data. set vth >500mv. when the input signal is removed (<50mv), los will be asserted high. reference clock input the refclk inputs are internally terminated and self- biased to allow ac-coupling. the input impedance is 100 ? single-ended (200 ? differential). the refclk inputs of the max3991 and max3992 should be con- nected close together in parallel. the impedance look- ing into the parallel combination is 100 ? differential. this allows both the max3991 and max3992 to easily interface with one reference clock without using addi- tional components. see figure 4. design procedure modes of operation the max3992 has a standby mode and jitter test mode in addition to its normal operating mode. standby is used to conserve power. in the standby mode, the power consumption of the max3992 falls below 40% of the normal-operation power consumption. the jitter test mode enables the sclk outputs to clock a bert when testing jitter generation, jitter transfer, and jitter toler- ance. the fctl1 and fctl2 ttl inputs are used to select the mode of operation as shown in table 3. serial data rate and reference clock frequency input configuration the sdi inputs of the max3992 are current-mode logic (cml) compatible. the inputs have internal 50 ? terminations for minimum external components. see figure 5 for the input structure. for additional informa- tion on logic interfacing, refer to maxim application note hfan 1.0: introduction to lvds, pecl, and cml. output configuration the max3992 uses cml for its high-speed digital out- puts (sdo and sclko ). the configuration of the out- put circuit includes internal 50 ? back terminations to v cc . see figure 6 for the output structure. cml outputs may be terminated by 50 ? to v cc , or by 100 ? differen- tial impedance. the relation of the output polarity to input can be reversed using the pol pin. for additional infor- mation on logic interfacing, refer to maxim application note hfan 1.0: introduction to lvds, pecl, and cml. max3992 10gbps clock and data recovery with equalizer _______________________________________________________________________________________ 9 max3991 max3992 max3992 200 ? 200 ? 200 ? 50w 50w reference clock 50w 50w reference clock transceiver termination transmitter-only termination 200 ? figure 4. reference clock termination
max3992 applications information exposed pad (ep) package the exposed pad, 24-pin qfn incorporates features that provide a very low thermal-resistance path for heat removal from the ic. the pad is electrical ground on the max3992 and must be soldered to the circuit board for proper thermal and electrical performance. layout considerations for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground con- nections short, and use multiple vias where possible. use controlled-impedance transmission lines to inter- face with the max3992 high-speed inputs and outputs. power-supply decoupling should be placed as close to v cc as possible. to reduce feedthrough, take care to isolate the input signals from the output signals. 10gbps clock and data recovery with equalizer 10 ______________________________________________________________________________________ table 3. functional control fctl1 fctl2 description 00 normal operation, serial clock output disabled. 10 standby power-down mode. 01 normal operation, serial clock output disabled. 11 serial clock output enabled for jitter testing. figure 5. cml input model sdi+ sdi- v cc 50 ? 50 ? figure 6. cml output model vcc gnd sdo+ sdo- 50 ? 50 ? figure 7. polarity (pol) function (sdi+) - (sdi-) (sdo+) - (sdo-) pol = vcc (sdo+) - (sdo-) pol = gnd
max3992 10gbps clock and data recovery with equalizer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. chip information transistor count: 10,300 process: sige bipolar substrate: soi package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim- ic.com/packages.) (qfn 4mm x 4mm x 0.8mm, pack- age code: t2444-4) max3975 max3992 max3991 driver lol lol los fctl vth los fctl vth xfi reference 30-pin connector tosa pol 2 2 pol 2-wire interface refclk+ refclk- refclk+ refclk- sdi+ sdo+ sdi- sdo- cfil v cc gnd sdo+ sdo- sdi+ sdi- cfil v cc v cc gnd n.c. n.c. v cc 0.047 f 0.047 f rosa 50 ? transmission line *future product. ds1862* controller t ypical application circuit

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