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sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 1 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 description ................................ ................................ ................................ ................................ ................................ .......... 3 features ................................ ................................ ................................ ................................ ................................ .............. 3 pin configuration ................................ ................................ ................................ ................................ ................................ 4 pin description ................................ ................................ ................................ ................................ ................................ .... 6 special function register (sfr) ................................ ................................ ................................ ................................ ........ 8 function description ................................ ................................ ................................ ................................ ......................... 10 1. general features ................................ ................................ ................................ ................................ ..................... 10 1.1. embedded flash ................................ ................................ ................................ ................................ ......... 10 1.2. io pads ................................ ................................ ................................ ................................ ....................... 10 1.3. instruction timing selection ................................ ................................ ................................ ......................... 10 1.4. reset ................................ ................................ ................................ ................................ ........................ 11 1.4.1. hardware reset functi on ................................ ................................ ................................ ............. 11 1.4.2. software reset function ................................ ................................ ................................ .............. 11 1.4.3. time access key register (takey) ................................ ................................ ................................ 12 1.4.4. software reset register (swres) ................................ ................................ ................................ . 12 1.4.5. example of software reset ................................ ................................ ................................ ............. 12 1.5. clocks ................................ ................................ ................................ ................................ ......................... 12 2. instruction set ................................ ................................ ................................ ................................ .......................... 13 3. memory structure ................................ ................................ ................................ ................................ ..................... 17 3.1. program memory ................................ ................................ ................................ ................................ ........ 17 3.2. data memory ................................ ................................ ................................ ................................ ............... 18 3.2.1. data memory - lower 128 byte (00h to 7fh) ................................ ................................ .................. 18 3.2. 2. data memory - higher 128 byte (80h to ffh) ................................ ................................ ................ 18 4. cpu engine ................................ ................................ ................................ ................................ ............................. 19 4.1. accumulator ................................ ................................ ................................ ................................ ................ 1 9 4.2. b register ................................ ................................ ................................ ................................ ................... 19 4.3. program status word ................................ ................................ ................................ ................................ .. 20 4.4. stack pointer ................................ ................................ ................................ ................................ ............... 20 4.5. data pointer ................................ ................................ ................................ ................................ ................ 20 4.6. data pointer 1 ................................ ................................ ................................ ................................ ............. 21 4.7. interface control register ................................ ................................ ................................ ............................. 21 5. gpio ................................ ................................ ................................ ................................ ................................ ........ 22 6. timer 0 and timer 1 ................................ ................................ ................................ ................................ ................. 23 6.1. timer/counter mode control register (tmod) ................................ ................................ ............................. 23 6.2. timer/counter control register (tcon) ................................ ................................ ................................ ....... 24 6.3. t0 t1 signal swapping ................................ ................................ ................................ .......................... 24 7. serial interface 0 ................................ ................................ ................................ ................................ ...................... 25 7.1. mode 0 ................................ ................................ ................................ ................................ ........................ 26 7.2. mode 1 ................................ ................................ ................................ ................................ ........................ 26 7.3. mode 2 ................................ ................................ ................................ ................................ ........................ 27 7.4. mode 3 ................................ ................................ ................................ ................................ ........................ 27 7.5. multiprocessor communication of serial interface 0 ................................ ................................ ................... 27 7.6. baud rate generator ................................ ................................ ................................ ................................ .... 28 7.6.1. serial interface 0 modes 1 and 3 ................................ ................................ ................................ ... 28 7.7. clock source for baud rate ................................ ................................ ................................ .......................... 28 8. watchdog timer ................................ ................................ ................................ ................................ ........................ 29 9. interrupt ................................ ................................ ................................ ................................ ................................ .... 32 9.1. priority leve l structure ................................ ................................ ................................ ................................ .. 34 10. power management unit ................................ ................................ ................................ ................................ . 36 10.1. idle mode ................................ ................................ ................................ ................................ ................ 36 1 0.2. stop mode ................................ ................................ ................................ ................................ ............... 36 11. iic function ................................ ................................ ................................ ................................ ...................... 37 12. lvi C low voltage interrupt ................................ ................................ ................................ ............................. 41 13. in - system programming (internal isp) ................................ ................................ ................................ ........... 42 13.1. isp service program ................................ ................................ ................................ ............................... 42 13.2. lock bit (n) ................................ ................................ ................................ ................................ ............. 42 13.3. program the isp service program ................................ ................................ ................................ ......... 43
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 2 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 13.4. initiate isp service program ................................ ................................ ................................ ................... 43 13.5. isp register C takey, ifcon, ispfah, ispfal, ispfd and ispfc ................................ .................... 43 operating conditions ................................ ................................ ................................ ................................ ........................ 46 dc characteristics ................................ ................................ ................................ ................................ ............................ 46
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 3 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 product list sm 39 r 04g1 w 14np , SM39R04G1w14op, SM39R04G1w10mp description the original 8052 had 12 - clock architecture. a machine cycle needed 12 clocks and most instructions were either one or two machine cycles. thus except for the mul and div instructions, the 8052 used either 12 or 24 clocks for each instruction. furthermore, each cycle in the 8052 used two memory fetches. in many cases the second fetch was dummy, and extra clocks were wasted. the SM39R04G1 is a core of a fast single - chip 8 - bit microcontroller. it is a fully functional 8 - bit embedded controller that executes all asm51 instructions and has the same instruction set as the mcs - 51. ordering information SM39R04G1 ihhkl yymmv i: process identifier { w = 2. 7 v ~ 5.5v} hh: pin count k: package type postfix {as table below } l:pb free identifier {no text is non - pb free p is pb free} yy: year mm: month v: version identifier{ a, b,} postfix package pin / pad configuration n pdip (300 mil) page 4 o sop ( 150 mil) page 4 m msop (118 mil) page 4 contact syncmos : www.syncmos.com.tw 6f, no.10 - 2 li - hsin 1st road , sbip, hsinchu, taiwan tel: 886 - 3 - 567 - 1820 fax: 886 - 3 - 567 - 1891 features ? operating voltage: 2. 7 v ~ 5.5v ? high speed architecture of 1 clock/ma chine cycle runs up to 25 mhz. ? 1~8t modes are software programmable . ? instruction - set compatible with mcs - 51. ? internal osc with range 1mhz~ 24 mhz ? 4k bytes on - chip flash program memory. ? 256 bytes ram as standard 8052, ? one serial peripheral interfaces in ful l duplex mode. ? synchronous mode, fixed baud rate, ? 8 - bit uart mode, variable baud rate. ? 9 - bit uart mode, fixed baud rate, ? 9 - bit uart mode, variable baud rate. ? additional baud rate generator ? two 16 - bit timer/counters. (timer 0, 1) ? 1 2 gpios( 14 l pdip/sop ) ? prog rammable watchdog timer. ? one iic interface. (master/slave mode) ? on C chip flash memories support isp/iap/icp and eeprom functions. ? isp service program space configurable in n*256 byte (n=0 to 4) size. ? on - chip in - circuit emulator (ice) functions with on - chip debugger (ocd). ? emi reduction mode (ale output inhibited) . ? lvi/lvr . ? io pad esd over 4kv. ? enhance user code protection. ? external interrupt 0, 1 with four priority levels. ? power management unit for idle and power down modes.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 4 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 pin configuration notes 1. the pin reset/p3.6 factory default is reset, user must keep this pin at low during power - up. user can configure it to gpio (p3.6) by a flash programmer. 2. to avoid accidentally entering isp - mode(refer to section 13. 4 ), care must be taken not asserti ng pulse signal at p3.0 during power - up while isp active pin (14l at p3.7 10l at p3.3) are se t to high. 3. to apply icp function, sda and scl must be set to bi - direction mode if they are configured as gpio in system. i n t 0 / t 0 / r x d / p 3 . 0 p 1 . 2 / x t a l 2 p 1 . 3 / x t a l 1 i n t 1 / p 3 . 3 v s s v c c p 3 . 7 / i n t 1 / t 1 p 3 . 5 / t 1 p 3 . 4 / t 0 p 1 . 1 / s c l p 1 . 0 / s d a i n t 0 / p 3 . 2 i n t 1 / t 1 / t x d / p 3 . 1 r e s e t ( d e f a u l t ) / p 3 . 6 / i n t 0 / t 0 1 2 3 4 5 6 7 1 4 1 3 1 2 1 1 1 0 9 8 s y n c m o s s m 3 9 r 0 4 g 1 i h h n p y y m m v ( 1 4 l p d i p t o p v i e w ) i n t 0 / t 0 / r x d / p 3 . 0 i n t 1 / p 3 . 3 v s s v c c p 3 . 7 / i n t 1 / t 1 p 3 . 5 / t 1 p 3 . 4 / t 0 p 1 . 1 / s c l p 1 . 0 / s d a i n t 0 / p 3 . 2 i n t 1 / t 1 / t x d / p 3 . 1 1 2 3 4 5 6 7 1 4 1 3 1 2 1 1 1 0 9 8 s y n c m o s s m 3 9 r 0 4 g 1 i ( 1 4 l s o p t o p v i e w ) p 1 . 2 / x t a l 2 p 1 . 3 / x t a l 1 r e s e t ( d e f a u l t ) / p 3 . 6 / i n t 0 / t 0 i n t 0 / t 0 / r x d / p 3 . 0 i n t 1 / t 1 / t x d / p 3 . 1 x t a l 2 / p 3 . 2 x t a l 1 / p 3 . 3 v s s v c c p 3 . 7 / i n t 1 / t 1 r e s e t ( d e f a u l t ) / p 3 . 6 / i n t 0 / t 0 p 3 . 5 / s c l p 3 . 4 / s d a 1 2 3 4 5 1 0 9 8 7 6 s m 3 9 r ( 1 0 l m s o p ) 0 4 g 1 i
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 5 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 block diagram u a r t 0 f l a s h 4 k b y t e s s r a m 2 5 6 b y t e s i n t e r r u p t t i m e r 0 / 1 w a t c h d o g i c e i c p p o r t 1 p o r t 3 p o r t 1 p o r t 3 t 0 t 1 i i c _ s c l r x d 0 t x d 0 i n t e r f a c e c o n t r o l x t a l 1 x t a l 2 i i c _ s d a c p u i i c p 1 . 0 ( d a t a ) p 1 . 1 ( c l o c k ) m a x 8 1 0 r e s e t
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 6 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 pin description 14l pdip/sop symbol i/o description 1 p3.0/rxd /#int0 / t0 i/o bit 0 of port 3 & serial interface channel 0 receive/transmit data & ( external interrupt 0 or timer 0 external input) 2 p3.1/txd /#int1 /t1 i/o bit 1 of port 3 & seri al interface channel 0 transmit data or receive clock in mode 0 & ( external interrupt 1 or timer 1 external input) 3 xtal2/ p1.2 i/o crystal output & bit 2 of port 1 4 xtal1/ p1.3 i/o crystal input & bit 3 of port 1 5 p3.2/#int0 i/o bit 2 of port 3 & ex ternal interrupt 0 6 p3.3/#int1 i/o bit 3 of port 3 & external interrupt 1 7 vss i power supply 8 p1.0/sda i/o bit 0 of port 1 & on - chip instrumentation command and data i/o pin synchronous to oci_scl in ice and icp functions 9 p1.1/scl i/o bit 1 of po rt 1 & on - chip instrumentation clock i/o pin of ice and icp functions 10 p3.4/t0 i/o bit 4 of port 3 & timer 0 external input 11 p3.5/t1 i/o bit 5 of port 3 & timer 1 external input 12 reset (default) / p3.6 /#i nt0 /t0 i/o reset pin (default) & (bit 6 of port 3 or external interrupt 0 or timer 0 external input) 13 p3.7 /#int1 /t1 i/o bit 7 of port 3 & ( external interrupt 1 or timer 1 external input) 14 vdd i power supply the special function pin can configured as below table (can be select by sfr) signal de fault option1 option2 #int0 5 (p3.2) 1 (p3.0) 12 (p3.6) #int1 6 (p3.3) 2 (p3.1) 13 (p3.7) t0 10(p3.4) 12(p3.6) 1(p3.0) t1 11(p3.5) 13(p3.7) 2(p3.1) the reset pin can be configured as i/o port p3.6 when user use on - chip hardware reset mechanism the xtal2 can be configured as i/o port p 1.2 by icp or in isp mode. when user use oscillator (xtal1 as clock input) or on - chip rc oscillator is set to main system clock source the xtal1 can be configured as i/o port p 1.3 by icp or in isp mode when user use on - chip rc oscillator is set to main system clock source
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 7 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 10l msop symbol i/o description 1 p3.0/rxd/#int0/t0 i/o bit 0 of port 3 & serial interface channel 0 receive/transmit data & (external interrupt 0 or timer 0 external input) 2 p3.1/txd/#int1/t1 i/o bit 1 of port 3 & serial interface channel 0 transmit data or receive clock in mode 0 & (external interrupt 1 or timer 1 external input) 3 xtal2/ p3.2 i/o crystal output & pin bit 2 of port 3 4 xtal1/ p3.3 i/o crystal input & bit 3 of port 3 5 vss i power supply 6 p3.4 / s da i/o bit 4 of port 3 & on - chip instrumentation command and data i/o pin synchronous to oci_scl in ice and icp functions 7 p3.5/ scl i/o bit 5 of port 3 & & on - chip instrumentation clock i/o pin of ice and icp functions 8 reset (default) / p 3.6 /# int0 /t0 i/o reset (default) & ( bit 6 of port 3 & external interrupt 0 or timer 0 external input ) 9 p3.7 /#int1 /t1 i/o bit 7 of port 3 & external interrupt 1 or timer 1 external input 10 vdd i power supply the special function pin can configured as b elow table (can be select by sfr) signal default option1 option2 #int0 8(p3.6) 1(p3.0) 8(p3.6) #int1 9(p3.7) 2(p3.1) 9(p3.7) t0 8(p3.6) 8(p3.6) 1(p3.0) t1 9(p3.7) 9(p3.7) 2(p3.1) the reset pin can be configured as i/o port p3.6 when user use on - chip hardware reset mechanism the x tal2 can be configured as i/o port p 3.2 by icp or in isp mode. when user use oscillator (xtal1 as clock input) or on - chip rc oscillator is set to main system clock source the xtal1 can be configured as i/o port p 3.3 by icp or in isp mode when user use on - chip rc oscillator is set to main system clock source
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 8 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 special function register (sfr) a map of the special function registers is show n as below: hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex f8 iics iicctl iica1 iica2 iicrwd iicebt ff f0 b takey f7 e8 ef e0 acc ispfah ispfal ispfd ispfc lvc swres e7 d8 p3m0 p3m1 df d0 psw p1m0 p1m1 d7 c8 cf c0 ircon c7 b8 ien1 ip1 s0relh bf b0 p3 wdtc wdtk b7 a8 ien0 ip0 s0rell af a0 p1w e p3we a7 98 s0con s0buf 9f 90 p1 aux 97 88 tcon tmod tl0 tl1 th0 th1 ckcon ifcon 8f 80 sp dpl dph dpl1 dph1 pcon 87 hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin/hex note: special function registers reset values and descripti on for SM39R04G1 register location reset value description sp 81h 07h stack pointer dpl 82h 00h data pointer 0 low byte dph 83h 00h data pointer 0 high byte dpl1 84h 00h data pointer 1 low byte dph1 85h 00h data pointer 1 high byte pcon 87h 40h powe r control tcon 88h 00h timer/counter control tmod 89h 00h timer mode control tl0 8ah 00h timer 0, low byte tl1 8bh 00h timer 1, low byte th0 8ch 00h timer 0, high byte th1 8dh 00h timer 1, high byte ckcon 8eh 10h clock control register ifcon 8fh 40 h interface control register p1 90h ffh port 1 aux 91h 00h auxiliary register
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 9 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 register location reset value description s0con 98h 00h serial port 0, control register s0buf 99h 00h serial port 0, data buffer p1we a3h ffh port 1 output enable p3we a4h ffh port 3 output enable ien0 a8h 00h interrupt enable register 0 ip0 a9h 00h interrupt priority register 0 s0rell aah 00h serial port 0, reload register, low byte p3 b0h ffh port 3 wdtc b6h 04h watchdog timer control register wdtk b7h 00h watchdog timer refresh key. ien1 b8h 00h interrupt enable register 1 ip1 b9h 00h interrupt priority register 1 s0relh bah 00h serial port 0, reload register, high byte ircon c0h 00h interrupt request control register psw d0h 00h program status word p1m0 d4h 0 0h port 1 output mode 0 p1m1 d5h 00h port 1 output mode 1 p3m0 dah 00h port 3 output mode 0 p3m1 dbh 00h port 3 output mode 1 acc e0h 00h accumulator ispfah e1h ffh isp flash address - high register ispfal e2h ffh isp flash address - low register ispfd e3h ffh isp flash data register ispfc e4h 00h isp flash control register lvc e6h 2 0h low voltage control register swres e7h 00h software reset register b f0h 00h b register takey f7h 00h time access key register iics f8h 00h iic status register iicc tl f9h 04h iic control register iica1 fah a0h iic channel 1 address 1 register iica2 fbh 60h iic channel 1 address 2 register iicrwd fch 00h iic channel 1 read / write data buffer iics2 fdh 00h iic status2 register
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 10 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 function description 1. general feat ures SM39R04G1 is an 8 - bit micro - controller all of its functions and the detailed meanings of sfr will be given in the following sections 1.1. embedded flash the program can be loaded into the embedded 4 kb flash memory via its writer or in - system progra mm ing (isp) the high - quality flash has a 100k - write cycle life suitable for re - programming and data recording as eeprom 1.2. io pads the SM39R04G1 has two i/o ports: port 1 and port 3 . ports 3 are 8 - bit ports and port 1 is a 4 - bit port (the 10l msop only hav e 8 - bit port 3) .these are: quasi - bidirectional (standard 8051 port outputs), push - pull, open drain, and input - only. as description in section 5 at 14l package (dip/sop) the int0 int1 t0 t 1 signal can be configured to other i/o as below signal default op tion1 option2 #int0 5(p3.2) 1(p3.0) 12(p3.6) #int1 6(p3.3) 2(p3.1) 13(p3.7) t0 10(p3.4) 12(p3.6) 1(p3.0) t1 11(p3.5) 13(p3.7) 2(p3.1) at 10l package (msop) the int0 int1 t0 t 1 signal can be configured to other i/o as below signal default option1 opt ion2 #int0 8(p3.6) 1(p3.0) 8(p3.6) #int1 9(p3.7) 2(p3.1) 9(p3.7) t0 8(p3.6) 8(p3.6) 1(p3.0) t1 9(p3.7) 9(p3.7) 2(p3.1) the reset pin can be configured as i/o port p3.6 when user use on - chip hardware reset mechanism the xtal2 and xtal1 can be config ured as i/o port by icp or in isp mode when user use external osc or on - chip rc oscillator is set to main system clock source show as below external osc internal osc 14l package xtal1 xtal1 p1.3 xtal2 p1.2 p1.2 10l package xtal1 xtal1 p3.3 xtal2 p3.2 p3.2 all the pins on p 1 and p3 are with slew rate adjustment to reduce emi. the other way to reduce emi is to disable the ale output if unused. this is selected by its sfr. the io pads can withstand 4kv esd in human body mode guaranteeing the sm39r 04g1 s quality in hig h electro - static environments. 1.3. instruction timing selection the conventional 52 - series mcus are 12t, i.e., 12 oscillator clocks per machine cycle. SM39R04G1 is a 1 t to 8 t mcu, i.e., its machine cycle is one - clock to eight - clock. in the other words, it can execute one instruction within one clock to only eight clocks .
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 11 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 mnemonic: ckcon address: 8eh 7 6 5 4 3 2 1 0 reset - its - - - - 10h its: instruction timing select. its [6:4] instruction timing 000 1t mode 001 2t mode (defaul t) 010 3t mode 011 4t mode 100 5t mode 101 6t mode 110 7t mode 111 8t mode the default is in 2t mode, and it can be changed to another instruction timing mode if ckcon [ 6:4] (at address 8 e h) is change any time. not every instruction can be execut ed with one machine cycle. the exact machine cycle number for all the instructions are given in the next section. 1.4. reset 1.4.1. hardware reset function SM39R04G1 provides on - chip hardware reset mechanism, the reset duration is programmable by writer or isp on - chip hardware reset duration 25ms (default) 200ms 100ms 50ms 16ms 8ms 4ms 1.4.2. software reset function SM39R04G1 provides one software reset mechanism to reset whole chip. to perform a software reset, the firmware must write three specific values 55 h, aah and 5ah sequentially to the takey register to enable the software reset register (swres) write attribute. after swres register obtain the write authority, the firmware can write ffh to the swres register. the hardware will decode a reset signal that or with the other hardware reset. the swres register is self - reset at the end of the software reset procedure. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset software reset function takey time access key register f7 h takey [7:0] 00h swres software reset register e7h swres [7:0] 00h
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 12 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 1.4.3. time access key register (takey) mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h software reset register (swres) is read - only by default; software must write t hree specific values 55h, aah and 5ah sequentially to the takey register to enable the swres register write attribute. that is: mov takey, #55h mov takey, # 0 aah mov takey, #5ah 1.4.4. software reset register (swres) mnemonic: swres address: e7h 7 6 5 4 3 2 1 0 reset swres [7:0] 00h swres [7:0]: software reset register bit. these 8 - bit is self - reset at the end of the reset procedure. swres [7:0] = ffh, software reset. swres [7:0] = 00h ~ feh, mcu no action. 1.4.5. example of software reset mov takey, #55h mov ta key, # 0 aah mov takey, #5ah ; enable swres write attribute mov swres, # 0 ffh ; software reset mcu 1.5. clocks the default clock is the 12mhz on - chip rc - oscillator . this clock is used during the initialization stage. the major work of the initialization stage is to determine the clock so urce used in normal operation. the internal clock sources are from the on - chip rc - oscillator with programmable frequency outputs as table 1 - 1 the clock source can set by writer or i c p table 1 - 1: selection of clock source clock source e xternal crystal (use xtal1 and xtal2 pins ) external crystal (only use xtal1, the xtal2 define as i/o) 20mhz from on - chip rc - oscillator 16mhz from on - chip rc - oscillator 12mhz from on - chip rc - oscillator (default) 8mhz from on - chip rc - oscillator 4mhz from on - chip rc - oscillator 2mhz from on - chip rc - oscillator 1mhz from on - chip rc - oscillator
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 13 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 2. instruction set all SM39R04G1 instructions are binary code com patible and perform the same functions as they do with the industry standard 8051. the following tables give a summary of the instruction set cycles of the SM39R04G1 microcontroller core. table 2 - 1: arithmetic operations mnemonic description code bytes cy cles add a,rn add register to accumulator 28 - 2f 1 1 add a,direct add direct byte to accumulator 25 2 2 add a,@ri add indirect ram to accumulator 26 - 27 1 2 add a,#data add immediate data to accumulator 24 2 2 addc a,rn add register to accumulator with carry flag 38 - 3f 1 1 addc a,direct add direct byte to a with carry flag 35 2 2 addc a,@ri add indirect ram to a with carry flag 36 - 37 1 2 addc a,#data add immediate data to a with carry flag 34 2 2 subb a,rn subtract register from a with borrow 98 - 9f 1 1 subb a,direct subtract direct byte from a with borrow 95 2 2 subb a,@ri subtract indirect ram from a with borrow 96 - 97 1 2 subb a,#data subtract immediate data from a with borrow 94 2 2 inc a increment accumulator 04 1 1 inc rn increment register 0 8 - 0f 1 2 inc direct increment direct byte 05 2 3 inc @ri increment indirect ram 06 - 07 1 3 inc dptr increment data pointer a3 1 1 dec a decrement accumulator 14 1 1 dec rn decrement register 18 - 1f 1 2 dec direct decrement direct byte 15 2 3 dec @ri d ecrement indirect ram 16 - 17 1 3 mul ab multiply a and b a4 1 5 div divide a by b 84 1 5 da a decimal adjust accumulator d4 1 1
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 14 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 table 2 - 2: logic operations mnemonic description code bytes cycles anl a,rn and register to accumulator 58 - 5f 1 1 anl a,d irect and direct byte to accumulator 55 2 2 anl a,@ri and indirect ram to accumulator 56 - 57 1 2 anl a,#data and immediate data to accumulator 54 2 2 anl direct,a and accumulator to direct byte 52 2 3 anl direct,#data and immediate data to direct byte 5 3 3 4 orl a,rn or register to accumulator 48 - 4f 1 1 orl a,direct or direct byte to accumulator 45 2 2 orl a,@ri or indirect ram to accumulator 46 - 47 1 2 orl a,#data or immediate data to accumulator 44 2 2 orl direct,a or accumulator to direct byte 42 2 3 orl direct,#data or immediate data to direct byte 43 3 4 xrl a,rn exclusive or register to accumulator 68 - 6f 1 1 xrl a,direct exclusive or direct byte to accumulator 65 2 2 xrl a,@ri exclusive or indirect ram to accumulator 66 - 67 1 2 xrl a,#data e xclusive or immediate data to accumulator 64 2 2 xrl direct,a exclusive or accumulator to direct byte 62 2 3 xrl direct,#data exclusive or immediate data to direct byte 63 3 4 clr a clear accumulator e4 1 1 cpl a complement accumulator f4 1 1 rl a rot ate accumulator left 23 1 1 rlc a rotate accumulator left through carry 33 1 1 rr a rotate accumulator right 03 1 1 rrc a rotate accumulator right through carry 13 1 1 swap a swap nibbles within the accumulator c4 1 1
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 15 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 table 2 - 3: data transfer mnemon ic description code bytes cycles mov a,rn move register to accumulator e8 - ef 1 1 mov a,direct move direct byte to accumulator e5 2 2 mov a,@ri move indirect ram to accumulator e6 - e7 1 2 mov a,#data move immediate data to accumulator 74 2 2 mov rn,a mo ve accumulator to register f8 - ff 1 2 mov rn,direct move direct byte to register a8 - af 2 4 mov rn,#data move immediate data to register 78 - 7f 2 2 mov direct,a move accumulator to direct byte f5 2 3 mov direct,rn move register to direct byte 88 - 8f 2 3 m ov direct1,direct2 move direct byte to direct byte 85 3 4 mov direct,@ri move indirect ram to direct byte 86 - 87 2 4 mov direct,#data move immediate data to direct byte 75 3 3 mov @ri,a move accumulator to indirect ram f6 - f7 1 3 mov @ri,direct move dire ct byte to indirect ram a6 - a7 2 5 mov @ri,#data move immediate data to indirect ram 76 - 77 2 3 mov dptr,#data16 load data pointer with a 16 - bit constant 90 3 3 movc a,@a+dptr move code byte relative to dptr to accumulator 93 1 3 movc a,@a+pc move code b yte relative to pc to accumulator 83 1 3 push direct push direct byte onto stack c0 2 4 pop direct pop direct byte from stack d0 2 3 xch a,rn exchange register with accumulator c8 - cf 1 2 xch a,direct exchange direct byte with accumulator c5 2 3 xch a, @ri exchange indirect ram with accumulator c6 - c7 1 3 xchd a,@ri exchange low - order nibble indir. ram with a d6 - d7 1 3
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 16 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 table 2 - 4: program branches mnemonic description code bytes cycles acall addr11 absolute subroutine call xxx11 2 6 lcall addr16 long subroutine call 12 3 6 ret from subroutine 22 1 4 reti from interrupt 32 1 4 ajmp addr11 absolute jump xxx01 2 3 ljmp addr16 long iump 02 3 4 sjmp rel short jump (relative addr.) 80 2 3 jmp @a+dptr jump indirect relative to the dptr 73 1 2 jz rel j ump if accumulator is zero 60 2 3 jnz rel jump if accumulator is not zero 70 2 3 jc rel jump if carry flag is set 40 2 3 jnc jump if carry flag is not set 50 2 3 jb bit,rel jump if direct bit is set 20 3 4 jnb bit,rel jump if direct bit is not set 30 3 4 jbc bit,direct rel jump if direct bit is set and clear bit 10 3 4 cjne a,direct rel compare direct byte to a and jump if not equal b5 3 4 cjne a,#data rel compare immediate to a and jump if not equal b4 3 4 cjne rn,#data rel compare immed. to reg. and jump if not equal b8 - bf 3 4 cjne @ri,#data rel compare immed. to ind. and jump if not equal b6 - b7 3 4 djnz rn,rel decrement register and jump if not zero d8 - df 2 3 djnz direct,rel decrement direct byte and jump if not zero d5 3 4 nop no operation 0 0 1 1 table 2 - 5: boolean manipulation mnemonic description code bytes cycles clr c clear carry flag c3 1 1 clr bit clear direct bit c2 2 3 setb c set carry flag d3 1 1 setb bit set direct bit d2 2 3 cpl c complement carry flag b3 1 1 cpl bit complement direct bit b2 2 3 anl c,bit and direct bit to carry flag 82 2 2 anl c,/bit and complement of direct bit to carry b0 2 2 orl c,bit or direct bit to carry flag 72 2 2 orl c,/bit or complement of direct bit to carry a0 2 2 mov c, bit move direct bit to carry flag a2 2 2 mov bit,c move carry flag to direct bit 92 2 3
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 17 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 3. memory structure the SM39R04G1 memory structure follows general 8052 structure. it is 4kb program memory . 3.1. program memory the SM39R04G1 has 4kb on - chip fla sh memory which can be used as general program memory or eeprom, on which include up to 1k byte specific isp service program memory space . the address range for the 4k byte is $000 to $fff. the address range for the isp service program is $c00 to $fff. the isp service program size can be partitioned as n blocks of 256 byte (n=0 to 4). when n=0 means no isp service program space available, total 4k byte memory used as program memory. when n=1 means address $f00 to $fff reserved for isp service program. when n=2 means memory address $e00 to $fff reserved for isp service programetc . value n can be set and programmed into SM39R04G1 by the writer or icp . i t can be used to record any data as eeprom. the procedure of this eeprom application function is described i n the section 1 3 on internal isp. fig . 3 - 1: SM39R04G1 programmable flash f f f f 0 0 e 0 0 d 0 0 c 0 0 0 0 0 i s p s e r v i c e p r o g r a m s p a c e , u p t o 1 k 4 k p r o g r a m m e m o r y s p a c e n = 4 n = 3 n = 2 n = 1 n = 0
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 18 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 3.2. data memory the SM39R04G1 has 256bytes on - chip sram; 256 bytes of it are the s ame as general 8052 internal memory structure fig . 3 - 3: ram architecture 3.2.1. data memory - lower 128 byte (00h to 7fh) data memory 00h to ffh is the same as 8052. the address 00h to 7fh can be accessed by direct and indirect addressing modes. address 00h to 1fh is register area. address 20h to 2fh is memory bit area. address 30h to 7fh is for general memory area. 3.2.2. data memory - higher 128 byte (80h to ffh) the address 80h to ffh can be accessed by indirect addressing mode. address 80h to ffh is data area. h i g h e r 1 2 8 b y t e s ( a c c e s s e d b y i n d i r e c t a d d r e s s i n g m o d e o n l y ) l o w e r 1 2 8 b y t e s ( a c c e s s e d b y d i r e c t & i n d i r e c t a d d r e s s i n g m o d e ) s f r ( a c c e s s e d b y d i r e c t a d d r e s s i n g m o d e o n l y ) 0 0 7 f 8 0 f f 8 0 f f
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 19 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 4. cpu engine the SM39R04G1 engine is composed of four components: a. control unit b. arithmetic C logic unit c. memory control unit d. ram and sfr control unit the SM39R04G1 engine allows to fetch instruction from program memory and to execute using ram or sfr. the following chapter describes the main engine register. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 8051 core acc accumulator e0h acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00h b b register f0h b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h psw program status word d0h cy ac f0 rs[1:0] ov psw.1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 0 82h dpl[7:0] 00h dph data pointer high 0 83h dph[7:0] 00h dpl1 data pointer low 0 84h dpl1[7:0] 00h dph1 data pointer high 0 85h dph1[7:0] 00h aux auxiliary register 91h br g s - - pts[1:0] pints[1:0] dps 00h ifcon interface control register 8fh - cdpr - - - - - ispe 00h 4.1. accumulator acc is the accumulator register. most instructions use the accumulator to store the operand. mnemonic: acc address: e0h 7 6 5 4 3 2 1 0 reset acc.7 acc.6 acc05 acc.4 acc.3 acc.2 acc.1 acc.0 00h acc[7:0]: the a (or acc) register is the standard 8052 accumulator. 4.2. b register the b register is used du ring multiply and divide instructions. it can also be used as a scratch pad register to store temporary data. mnemonic: b address: f0h 7 6 5 4 3 2 1 0 reset b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00h b[7:0]: the b register is the standard 8052 register that serves as a second accumulator.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 20 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 4.3. program status word mnemonic: psw address: d0h 7 6 5 4 3 2 1 0 reset cy ac f0 rs [1:0] ov f1 p 00h cy: carry flag. ac: auxiliary carry flag for bcd operations. f0: general purpose flag 0 available for user. rs[1:0 ]: register bank select, used to select working register bank. rs[1:0] bank selected location 00 bank 0 00h C C C C ov: overflow flag. f1: general purpose flag 1 available for user. p: pari ty flag, affected by hardware to indicate odd/even number of one bits in the 4.4. stack pointer the stack pointer is a 1 - byte register initialized to 07h after reset. this register is incremented before push and call instruc tions, causing the stack to start from location 08h. mnemonic: sp address: 81h 7 6 5 4 3 2 1 0 reset sp [7:0] 07h sp[7:0]: the stack pointer stores the scratchpad ram address where the stack begins. in other words, it always points to the top of the s tack. 4.5. data pointer the data pointer (dptr) is 2 - bytes wide. the lower part is dpl, and the highest is dph. it can be loaded as a 2 - byte register (e.g. mov dptr, #data16) or as two separate registers (e.g. mov dpl,#data8). it is generally used to acces s the external code or data space (e.g. movc a, @a+dptr, @dptr respectively). mnemonic: dpl address: 82h 7 6 5 4 3 2 1 0 reset dpl [7:0] 00h dpl[7:0]: data pointer low 0 mnemonic: dph address: 83h 7 6 5 4 3 2 1 0 reset dph [7:0] 00h dph [7:0]: d ata pointer high 0
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 21 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 4.6. data pointer 1 the dual data pointer accelerates the moves of data block. the standard dptr is a 16 - bit register that is used to address external memory or peripherals. in the SM39R04G1 core the standard data pointer is called dptr; t he second data pointer is called dptr1. the data pointer select bit chooses the active pointer. the data pointer select bit is located in lsb of aux register (dps). the user switches between pointers by toggling the lsb of aux register. all dptr - related i nstructions use the currently selected dptr for any activity. dpl1[7:0]: data pointer low 1 mnemonic: dph1 address: 85h 7 6 5 4 3 2 1 0 reset dph1 [7:0] 00h dph1[7:0]: data pointer high 1 mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts[1:0] pints[1:0] dps 00h dps: data pointer selects register. dps = 1 is selected dptr1. 4.7. interface control register mnemonic: ifcon address: 8fh 7 6 5 4 3 2 1 0 reset - cdpr - - - - - ispe 00h cdpr: code protect (read only) ispe: isp function enable bit ispe = 1, enable isp function ispe = 0, disable isp function mnemonic: dpl1 address: 84h 7 6 5 4 3 2 1 0 reset dpl1 [7:0] 00h
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 22 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 5. gpio the SM39R04G1 has three i/o ports: port 1 and port 3. ports 3 are 8 - bit ports and port 1 is a 4 - bit port ( the 10l msop only have 8 - bit port 3) . these are: quasi - bidirectional (standard 8051 port outputs), push - pull, open drain, and input - only. two configuration registers for each port select the output type for each port pin. all i/o port pins on the SM39R04G1 may be configured by software to one of four types on a pin - by - pin basis, shown as below: mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset i/o port function register p1m0 port 1 output mode 0 d4h p1m0[3:0] 00h p1m1 po rt 1 output mode 1 d5h p1m1[3:0] 00h p3m0 port 3 output mode 0 dah p3m0[7:0] 00h p3m1 port 3 output mode 1 dbh p3m1[7:0] 00h p1we port 3 output enable a3h p1we[3:0] ffh p3we port 1 output enable a4h p 3 we[7:0] ffh pxm1.y pxm0.y port output mode 0 0 quasi - bidirectional (standard 8051 port outputs) (pull - up) 0 1 push - pull 1 0 input only (high - impedance) 1 1 open drain the reset pin can be configured as i/o port p3.6 when user use on - chip hardware reset mechanism the xtal2 and xtal1 can be configured as i/o port by icp or in isp mode when user use external osc or on - chip rc oscillator is set to main system clock source mnemonic: p1we address: a3h 7 6 5 4 3 2 1 0 reset p1.3 p1.2 p1.1 p1.0 ffh mnemonic: p3we address: a4h 7 6 5 4 3 2 1 0 reset p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh for general - purpose applications, every pin can be assigned to either high or low independently as given below: mn emonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset ports port 3 port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh port 1 port 1 90h p1.3 p1.2 p1.1 p1.0 ffh mnemonic: p1 address: 90h 7 6 5 4 3 2 1 0 reset p1 .3 p1.2 p1.1 p1.0 ffh p1. 3 ~ 0: port1 [ 3 ] ~ port1 [0] mnemonic: p3 address: b0h 7 6 5 4 3 2 1 0 reset p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh p3.7~ 0: port3 [7] ~ port3 [0]
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 23 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 6. timer 0 and timer 1 the SM39R04G1 has two 16 - bit timer/counter regis ters: timer 0 and timer 1. all can be configured for counter or timer operations. in timer mode, the timer 0 register or timer 1 register is incremented every 12 machine cycles, which means that it counts up after every 12 periods of the cl oc k signal. in counter mode, the register is incremented when the falling edge is observed at the corresponding input pin t0or t1. since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. two special function registers (tmod and tcon) are used to select the appropriate mode. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset timer 0 and 1 tl0 timer 0 , low byte 8ah tl0[7:0] 00h th0 timer 0 , high byte 8ch th0[7:0] 00h tl1 timer 1 , low byte 8bh tl1[7:0] 0 0h th1 timer 1 , high byte 8dh th1[7:0] 00h tmod timer mode control 89h gate c/t m1 m0 gate c/t m1 m0 00h tcon timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h aux auxiliary register 91h brgs - - pts[1:0] pints[1:0] dps 00h 6.1. timer/counter mode control register (tmod) mnemonic: tmod address: 89h 7 6 5 4 3 2 1 0 reset gate c/t m1 m0 gate c/t m1 m0 00h timer 1 timer 0 gate: if set, enables external gate control (pin int0 or int1 for counter 0 or 1, respectively). when int0 or int1 is h igh, and trx bit is set (see tcon register), a counter is incremented every falling edge on t0 or t1 input pin c/t: selects timer or counter operation. when set to 1, a counter operation is performed, when cleared to 0, the corresponding register will fun ction as a timer. m[1:0]: selects mode for timer/counter 0 or timer/counter 1. m1 m0 mode function 0 0 mode0 13 - bit counter/timer, with 5 lower bits in tl0 or tl1 register and 8 bits in th0 or th1 register (for timer 0 and timer 1, respectively). the 3 h igh order bits of tl0 and tl1 are hold at zero. 0 1 mode1 16 - bit counter/timer. 1 0 mode2 8 - bit auto - reload counter/timer. the reload value is kept in th0 or th1, while tl0 or tl1 is incremented every machine cycle. when tlx overflows, a value from thx is copied to tlx. 1 1 mode3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops. if timer 0 m1 and m0 bits are set to 1, timer 0 acts as two independent 8 bit timers / counters.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 24 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 6.2. timer/counter control register (tcon) mnemonic: tcon address: 88h 7 6 5 4 3 2 1 0 reset tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tf1: timer 1 overflow flag set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. tr1: timer 1 run control bit. if c leared, timer 1 stops. tf0: timer 0 overflow flag set by hardware when timer 0 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. tr0: timer 0 run control bit. if cleared, timer 0 stops. ie1: interr upt 1 edge flag. set by hardware, when falling edge on external pin int1 is observed. cleared when interrupt is processed. it1: interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt. ie0: interrupt 0 edge flag. s et by hardware, when falling edge on external pin int0 is observed. cleared when interrupt is processed. it0: interrupt 0 type control bit. selects falling edge or low level on input pin to cause interrupt. 6.3. t0 the t0 t1 signal can b e configured to other i/o mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts [1:0] pints[1:0] dps 00h package = 14 pin pts [1:0] t0 t1 0x00 p3.4 p3.5 0x01 p3.0 p3.1 0x10 p3.6 p3.7 0x11 p3.4 p3.5 package = 10 pin pts[1:0] t0 t1 0x00 p3.6 p3.7 0x01 p3.0 p3.1 0x10 p3.6 p3.7 0x11 p3.6 p3.7
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 25 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 7. serial interface 0 the serial buffer consists of two separate registers, a transmit buffer and a receive buffer. writing data to the special function register s0buf sets this data in serial out put buffer and starts the transmission. reading from the s0buf reads data from the serial receive buffer. the serial port can simultaneously transmit and receive data. it can also buffer 1 byte at receive, which prevents the receive data from being lost if the cpu reads the first byte before transmission of the second byte is completed. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset serial interface 0 pcon power control 87h smod - - - - - stop idle 40h aux auxiliary re gister 91h brgs - - pts[1:0] pints[1:0] dps 00h s0con serial port 0 control register 98h sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 00h s0buf serial port 0 data buffer 99h s0buf[7:0] 00h s0rell serial port 0 reload register low byte aah s0rel .7 s0rel .6 s0rel .5 s0rel .4 s0rel .3 s0rel .2 s0rel .1 s0rel .0 00h s0relh serial port 0 reload register high byte bah - s0rel .9 s0rel .8 00h mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts[1:0] pints[1:0] dps 00h brgs : brgs = 0 C baud rate generator use timer 1 th1 sfr. brgs = 1 C baud rate generator use s0rel sfr. mnemonic: s0con address: 98h 7 6 5 4 3 2 1 0 reset sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 00h sm0,sm1: serial port 0 mode selection. sm0 sm1 mode 0 0 0 0 1 1 1 0 2 1 1 3 the 4 modes in uart0, mode 0 ~ 3, are explained later. sm20: enables multiprocessor communication feature ren0: if set, enables serial reception. cleared by software to disable reception. tb80: the 9 th transmitted data bit in modes 2 and 3. set or cleared by the cpu depend ing on the function it performs such as parity check, multiprocessor communication etc. rb80: in modes 2 and 3, it is the 9 th data bit received. in mode 1, if sm20 is 0, rb80 is the stop bit. in mode 0, this bit is not used. must be cleared by software . ti0: transmit interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software. ri0: receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. the serial interface 0 can operate in the following 4 modes: sm0 sm1 mode description board rate 0 0 0 shift register fosc/12
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 26 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart fosc/32 or fosc/64 1 1 3 9 - bit uart variable h ere fosc is the crystal or oscillator frequency. 7.1. mode 0 pin rxd0 serves as input and output. txd0 outputs the shift clock. 8 bits are transmitted with lsb first. the baud rate is fixed at 1/12 of the crystal frequency. reception is initialized in mode 0 by setting the flags in s0con as follows: ri0 = 0 and re n0 = 1. in other modes, a start bit when ren0 = 1 starts receiving serial data. fig. 7 - 1: transmit mode 0 for serial 0 fig. 7 - 2: receive mode 0 for serial 0 7.2. mode 1 pin rxd0 serves as input, and txd0 serves as serial output. no external shift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronizes the transmissi on, 8 data bits are available by reading s0buf, and stop bit sets the flag rb80 in the special function register s0con. in mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate. fig. 7 - 3: transmit mode 1 for serial 0
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 27 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 fig. 7 - 4: receive mode 1 for serial 0 7.3. mode 2 this mode is similar to mode 1, with two differen ces. the baud rate is fixed at 1/32 (smod=1) or 1/64(smod=0) of oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (lsb first), a programmable 9 th bit, and a stop bit (1). the 9 th bit can be used to control the parit y of the serial interface: at transmission, bit tb80 in s0con is output as the 9 th bit, and at receive, the 9 th bit affects rb80 in special function register s0con. 7.4. mode 3 the only difference between mode 2 and mode 3 is that in mode 3 either internal ba ud rate generator or timer 1 can be use to specify baud rate. fig. 7 - 5: transmit modes 2 and 3 for serial 0 fig. 7 - 6: receive modes 2 and 3 for serial 0 7.5. multiprocessor comm unication of serial interface 0 the feature of receiving 9 bits in modes 2 and 3 of serial interface 0 can be used for multiprocessor communication. in this case, the slave processors have bit sm20 in s0con. when the master processor outputs slaves address, it sets the 9 th bit to 1, causing a serial port receive interrupt in all the slaves. the slave processors compare the received byte with their network address. if there is a match, the addressed slave will clear sm20 and receive the rest of the message, while other slaves will leave sm20 bit unaffected and ignore this message. after addressing the slave, the host will output the rest of the message with the 9 th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 28 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 7.6. baud rate generator 7.6.1. serial interface 0 modes 1 and 3 (a) when brgs = 0 (in sfr aux ): (b) when brgs = 1 (in sfr aux ): 7.7. clock source for baud rate the on - chip rc - oscillator frequency varies within + 3 % after factory calibration. in case of application with higher clock precision requ irement, external crystal is usually recommended clock source. ? ? th1 256 12 32 f 2 rate baud smod ? ? ? ? ? osc ? ? s0rel 2 64 f 2 rate baud 10 osc smod ? ? ? ?
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 29 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 8. watchdog timer the watch dog timer (wdt) is an 8 - bit free - running counter that generate reset signal if the counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. the wdt function can help user software recover from abnormal software condition. the wdt is different from timer0, timer1 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user should check wdtf bit of wdtc register whenever un - predicted reset happened. after an external reset the watchdog timer is disabled and all registers are set to zeros. the watchdog timer has a f ree running on - chip rc oscillator ( 250 khz 20% ). the wdt will keep on running even after the system clock has been turned off (for example, in sleep mode). during normal operation or sleep mode, a wdt time - out (if enabled) will cause the mcu to reset. the wdt can be enabled or disabled any time during the normal mode. please refer the wdte bit of wdtc register. the default wdt time - out period is approximately 16.38 ms (wdtm [3:0] = 0100b) . the wdt has selectable divider input for the time base source clock . to select the divider input, the setting of bit3 ~ bit0 (wdtm [3:0]) of watch dog timer control register (wdtc) should be set accordingly. watchdog reset time = table 8 .1 wdt time - out period wdtm [3:0] divider (2 5 0 khz rc oscillator in) time period @ 2 5 0khz 0000 1 1. 02 ms 0001 2 2. 05 ms 0010 4 4.10 ms 0011 8 8.19 ms 0100 16 16.38 ms (default) 0101 32 32.77ms 0110 64 65.54ms 0111 128 131.07ms 1000 256 262.14ms 1001 512 524.29ms 1010 1024 1.05s 1011 2048 2.10s 1100 4096 4.19s 1101 8192 8.39s 1110 16384 16.78s 1111 32768 33.55s when mcu is reset, the mcu will be read wdten control bit status. when wdten bit is set to 1, the watchdog function will be disabled no matter what the wdte bit status is . when wdten bit is clear to 0, the watchdog function will be enabled if wdte bit is set to 1 by program. user can to set wdten on the writer or i s p. the program can enable the wdt function by programming 1 to the wdte bit premise that wdten control bit i s clear to 0. after wdte set to 1, the 8 bit - counter starts to count with the selected time base source clock which set by wdtm [3:0]. it will generate a reset signal when overflows. the wdte bit will be cleared to 0 automatically when mcu been reset, eith er hardware reset or wdt reset. once the watchdog is started it cannot be stopped. user can refreshed the watchdog timer to zero by writing 0x55 to watch dog timer refresh key (wdtk) register. this will clear the content of the 8 - bit counter and let the c ounter re - start wdt m 2 250khz ? wdtclk wdtclk 256
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 30 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 to count from the beginning. the watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. when watchdog timer is overflow, the wdtf flag will set to one and automatically reset mcu. the wdtf flag can be clear by software or external reset or power on reset. fig. 8 - 1: watchdog timer block diagram mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset watchdog timer takey time access key regis ter f7h takey [7:0] 00h wdtc watchdog timer control register b6h wdtf - wdte - wdtm [3:0] 04h wdtk watchdog timer refresh key b7h wdtk[7:0] 00h mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h watchdog timer control register (wdtc ) is read - only by default; software must write three specific values 55h, aah and 5ah sequentially to the takey register to enable the wdtc write attribute. that is: mov takey, #55h mov takey, #aah mov takey, #5ah mnemonic: wdtc address: b6h 7 6 5 4 3 2 1 0 reset wdtf - wdte - wdtm [3:0] 04h wdtf: watchdog timer reset flag. when mcu is reset by watchdog, wdtf flag will be set to one by hardware. this flag clear by software or external reset or power on reset. wdte: control bit used to enable watchdog timer. the wdte bit can be used only if wdten is "0". if the wdten bit is "0", then wdt 2 5 0 k h z r c o s c i l l a t o r w d t c t a k e y ( 5 5 , a a , 5 a ) w d t m [ 3 : 0 ] w d t e n e n a b l e / d i s a b l e w d t w d t c o u n t e r w d t c l k w d t k ( 0 x 5 5 ) r e f r e s h w d t c o u n t e r p o w e r o n r e s e t e x t e r n a l r e s e t s o f t w a r e w r i t e 0 w d t f s e t w d t f = 1 c l e a r w d t f = 0 w d t t i m e - o u t r e s e t e n a b l e w d t c w r i t e a t t r i b u t e wdtm 2 1
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 31 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 can be disabled / enabled by the wdte bit. 0: disable wdt. 1: enable wdt. the wdte bit is not used if wdten is "1". that is, if the wdten bit is "1", wdt is always dis abled no matter what the wdte bit status is. the wdte bit can be read and written. wdtm [3:0]: wdt clock source divider bit. please see table 8.1 to reference the wdt time - out period. mnemonic: wdtk address: b7h 7 6 5 4 3 2 1 0 reset wdtk[7:0] 00h w dtk: watchdog timer refresh key. a programmer must write 0x55 into wdtk register, and then the watchdog timer will be cleared to zero. for example, if enable wdt and select time - out reset period is 262.14 ms. first, programming the information block op3 b it7 wdten to 0. secondly, mov takey, #55h mov takey, #aah mov takey, #5ah ; enable wdtc write attribute. mov wdtc, #28h ; set wdtm [3:0] = 1000b. set wdte =1 to enable wdt ; function. . . . mov wdtk, #55h ; clear wdt timer to 0.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 32 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 9. interrupt the sm39r04 g1 provides 7 interrupt sources with four priority levels. each source has its own request flag(s) located in a special function register. each interrupt requested by the corresponding flag could individually be enabled or disabled by the enable bits in sf rs ien0, and ien1. when the interrupt occurs, the engine will vector to the predetermined address as shown in table 9.1. once interrupt service has begun, it can be interrupted only by a higher priority interrupt. the interrupt service is terminated by a return from instruction reti. when an reti is performed, the processor will return to the instruction that would have been next when interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by setting a flag bit. thi s bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled once per machine cycle, and then samples are polled by hardware. if the sample indicates a pending interrupt when the interrupt is enabled, then interru pt request flag is set. on the next instruction cycle the interrupt will be acknowledged by hardware forcing an lcall to appropriate vector address. interrupt response will require a varying amount of time depending on the state of microcontroller when th e interrupt occurs. if microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. in other cases, the response time depends on current instruction. the fastest possible response to an interrupt is 7 machine cycles. this includes one machine cycle for detecting the interrupt and six cycles for perform the lcall. table 9 - 1: interrupt vectors interrupt request flags interrupt vector address interrupt number *(use keil c tool) ie0 C C C C C C C bout c51 users guide about interrupt function description mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset interrupt aux auxiliary register 91h brgs - - pts[1:0] pints[1:0] dps 00h ien0 interrupt enable 0 register a8h ea - - es0 et1 ex1 et0 ex0 00h ien1 interrupt enable 1 register b8h - - ieiic ielvi - - - - 00h ircon interrupt request register c0h - - iicif lviif - - - - 00h ip0 interrupt priority level 0 a9h - - ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 00h ip1 interrup t priority level 1 b9h - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 00h mnemonic: aux address: 91h 7 6 5 4 3 2 1 0 reset brgs - - pts[1:0] pints[1:0] dps 00h the in t0 int1 signal can be configured to other i/o
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 33 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 package = 14 pin pints [1:0] int0 int1 0x00 p3.2 p3.3 0x01 p3.0 p3.1 0x10 p3.6 p3.7 0x11 p3.2 p3.3 package = 10 pin pints [1:0] int0 int1 0x00 p3.6 p3.7 0x01 p3.0 p3.1 0x10 p3.6 p3.7 0x11 p3.6 p3.7 interrupt enable 0 register(ien0) mnemonic: ien0 address: a8h 7 6 5 4 3 2 1 0 reset ea - - es0 et1 ex1 et0 ex0 00h ea: ea=0 C C C C C C C C C C C C mnemonic: ien1 address: b8h 7 6 5 4 3 2 1 0 reset - - ieiic ielvi - - - - 00h ieiic: iic interrupt enable. ieiics = 0 C C C C mnemonic: ircon address: c0h 7 6 5 4 3 2 1 0 reset - - iicif lviif - - - - 00h iicif: iic interrupt flag. lviif: lvi interrupt flag.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 34 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 9.1. priority level structure all interrupt sources are combined in groups: table 9 - 2 : priority level groups groups - external interrupt 0 timer 0 interrupt - external interrupt 1 - timer 1 interrupt - serial channel 0 interrupt lvi interrupt - iic interrupt each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special fun ction register ip0 and one in ip1. if requests of the same priority level will be received simultaneously, an internal polling sequence determines which request is serviced first. mnemonic: ip0 address: a9h 7 6 5 4 3 2 1 0 reset - - ip0.5 ip0.4 ip0.3 ip 0.2 ip0.1 ip0.0 00h mnemonic: ip1 address: b9h 7 6 5 4 3 2 1 0 reset - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 00h table 9 - 3 : priority levels ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 level2 1 1 level3 (highest) table 9 - 4 : gro ups of priority bit group ip1.0, ip0.0 external interrupt 0 - ip1.1, ip0.1 timer 0 interrupt - ip1.2, ip0.2 external interrupt 1 - ip1.3, ip0.3 timer 1 interrupt - ip1.4, ip0.4 serial channel 0 interrupt lvi interrupt ip1.5, ip0.5 - iic interrupt
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 35 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 table 9 - 5 : polling sequence interrupt source sequence external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial channel 0 interrupt lvi interrupt iic interrupt polling sequence
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 36 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 10. power management unit power management unit se rves two power management modes, idle and stop, for the users to do power saving function. mnemonic: pcon address: 87h 7 6 5 4 3 2 1 0 reset smod - - - - - stop idle 4 0h stop: stop mode control bit. setting this bit turning on the stop mode. stop bit is always read as 0 idle: idle mode control bit. setting this bit turning on the idle mode. idle bit is always read as 0 10.1. idle mode setting the idle bit of pcon register invokes the idle mode. the idle mode leaves internal clocks and peripherals runnin g. power consumption drops because the cpu is not active. the cpu can exit the idle state with any interrupts or a reset. 10.2. stop mode setting the stop bit of pcon register invokes the stop mode. all internal clocking in this mode is turn off. the cpu will exit this state only if interrupt s asserted from external int0/1 and lvi or hardware reset by wdt and lvr .
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 37 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 11. iic function the iic module uses the scl (clock) and the sda (data) line to communicate with external iic interface. its speed can be selected to 400kbps (maximum) by software setting the iicbr [2:0] control bit. the iic module provided 2 interrupts (rxif, txif). it will generate start, repeated start and stop signals automatically in master mode and can detects start, repeated start and stop signa ls in slave mode. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pf. the interrupt vector is 6bh. mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset iic function iicctl iic control register f9h iicen mss mas ab_en bf_e n iicbr[2:0] 04h iics iic status register f8h - mpif laif rxif txif rxak txak rw,b b 00h iica1 iic address 1 register fah iica1[7:1] match1 or rw1 a0h iica2 iic address 2 regis ter fbh iica2[7:1] match2 or rw2 60h iicrwd iic read/write register fch iicrwd[7:0] 00h iicebt iic enaable bus transaction fdh fu_en - 00h mnemonic: iicctl address: f9h 7 6 5 4 3 2 1 0 reset iicen mss mas ab_en bf_en iicbr[2:0] 04h iicen: enable iic module iicen = 1 is enable iicen = 0 is disable. mss: master or slave mode select. mss = 1 is master mode. mss = 0 is slave mode. *the software must set this bit before setting others register. mas: master address select (master mode only) mas = 0 is to use iica1. mas = 1 is to use iica2. ab_en: arbitration lost enable bit. (master mode only) if set ab_en bit, the hardware will check arbitration lost. once arbitration lost occurred, hardware will return to idle state. if this bit is cleared, hardwa re will not care arbitration lost condition. set this bit when multi - master and slave connection. clear this bit when single master to single slave. bf_en: bus busy enable bit. (master mode only) if set bf_en bit, hardware will not generate a start condit ion to bus until bf=0. clear this bit will always generate a start condition to bus when mstart is set. set this bit when multi - master and slave connection. clear this bit when single master to single slave. iicbr[2:0]: baud rate selection (master mode on ly), where fosc is the external crystal or oscillator frequency. the default is fosc/512 for users convenience.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 38 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 011 fosc/256 100 fosc/512 101 fosc/1024 110 fosc/2048 111 fosc/4096 mnem onic: iics address: f8h 7 6 5 4 3 2 1 0 reset - mpif laif rxif txif rxak txak rw 00h mpif : the stop condition interrupt flag the stop condition occurred and this bit will be set. software need to clear this bit laif: arbitration lost bit. (master mo de only) the arbitration interrupt flag, the bus arbitration lost occurred and this bit will be set. software need to clear this bit rxif: the data receive interrupt flag (rxif) is set after the iicrwd (iic read write data buffer) is loaded with a newly r eceive data. txif: the data transmit interrupt flag (txif) is set when the data of the iicrwd (iic read write data buffer) is downloaded to the shift register. rxak: the acknowledge status indicate bit. when clear, it means an acknowledge signal has been received after the complete 8 bits data transmit on the bus. txak: the acknowledge status transmit bit. when received complete 8 bits data, this bit will set (noack) or clear (ack) and transmit to master to indicate the receive status. rw: master mode: bus busy bit if detect scl=0 or sda=0 or bus start, this bit will be set. if detect stop,this bit will be cleared. this bit can be cleared by software to return ready state. slave mode: the slave mode read (received) or wrote (transmit) on the iic bus. whe n this bit is clear, the slave module received data on the iic bus (sda).(slave mode only) fig . 1 1 - 1: acknowledgement bit in the 9 th bit of a byte transmission mnemonic: iica1 address: fah 7 6 5 4 3 2 1 0 reset iica1[7:1] match1 or rw1 a0h r/w r or r/w slave mode: iica1[7:1]: iic address registers this is the first 7 - bit address for this slave module. it will be checked when an address (from master) is received
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 39 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 match1: when iica1 matches with the received address from the master side, this b it will set to 1 by hardware. when iic bus gets or send first data , this bit will clear automatically. master mode: iica1[7:1]: iic address registers this 7 - bit address indicates the slave with which it wants to communicate. rw1: this bit will be sent out as rw of the slave side if the module has set the mstart or rstart bit. it appears at the 8 th bit after the iic address as shown in fig. 14 - 2. it is used to tell the salve the direction of the following communication. if it is 1, the module is in ma ster receive mode. if 0, the module is in master transmit mode. fig. 1 1 - 2: rw bit in the 8 th bit after iic address mnemonic: iica2 address: fbh 7 6 5 4 3 2 1 0 reset iica2[7:1] match2 or rw2 60h r/w r or r/w slave mode: iica2[7:1]: iic addres s registers this is the second 7 - bit address for this slave module. it will be checked when an address (from master) is received match2: when iica2 matches with the received address from the master side, this bit will set to 1 by hardware. when iic bus gets or send first data , this bit will clear automatically. master mode: iica2[7:1]: iic address registers this 7 - bit address indicates the slave with which it wants to communicate. rw2: this bit will be sent out as rw of the slave side if the module has set the mstart or rstart bit. it is used to tell the salve the direction of the following communication. if it is 1, the module is in master receive mode. if 0, the module is in master transmit mode. mnemonic: iicrwd address: fch 7 6 5 4 3 2 1 0 r eset iicrwd[7:0] 00h iicrwd[7:0]: iic read write data buffer. in receiving (read) mode, the received byte is stored here. in transmitting mode, the byte to be shifted out through sda stays here. mnemonic: iicebt address: fdh 7 6 5 4 3 2 1 0 reset fu_ en - - - - - - 00h master mode 00: reserved 01: iic bus module will enable read/write data transfer on sda and scl.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 40 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 10: iic bus module generate a start condition on the sda/scl, then send out address which is stored in the iica1/iica2(selected by mas control bit) 11: iic bus module generate a stop condition on the sda/scl. slave mode: 01: fu_en[7:6] should be set as 01 only. the other value is inhibited. notice: 1. fu_en[7:6] should be set as 01 before read/write data transfer for bus release; otherwise, scl will be locked (pull low). 2. fu_en[7:6] should be set as 01 after read/write data transfer for receiving a stop condition from bus master. 3. in transmit data mode ( slave mode), the output data should be filled into iicrwd before setting fu_en[7:6] as 01. 4. fu_ en[ 7:6] will be a uto - clear by hardware, so setting fu_en[7:6] repeatedly is necessary.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 41 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 12. lvi C low voltage interrupt the interrupt vector 63 h. mnemonic: lvc address: e6h 7 6 5 4 3 2 1 0 reset lvi_en lvi_vs lvrxe lvsif - - epsif - 20h lvi_en: low voltage interrupt fu nction enable bit. 0: disable low voltage detect function. 1: enable low voltage detect function. lvi_vs: low voltage interrupt level selection 0 :the level of voltage is set at lo w - level 1 :the level of voltage is set at hi - level lvrxe: external low vol tage reset function enable bit. 0: disable external low voltage reset function. 1: enable external low voltage reset function. lvsif low voltage status flag 1:the vdd voltage under lvi voltage 0:the vdd voltage above lvi voltage esp if mcu external volta ge status flag 1: means less than 3.8v(external power) 0: means more than 3.9v(external power) hi - level symbol parameter min typ max units v lvi low voltage interrupt voltage level 3.4 3.7 4.0 v v lvr low voltage reset voltage level 3.2 3.5 3.8 v notes: the v lvi always above v lvr about 0.2v. lo w - level symbol parameter min typ max units v lvi low volta ge interrupt voltage level 2.1 2.3 2.5 v v lvr low voltage reset voltage level 1.9 2.1 2.3 v notes: the v lvi always above v lvr about 0.2v.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 42 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 13. in - system programming ( internal isp) the SM39R04G1 can generate flash control signal by internal hardware circu it. users utilize flash control register, flash address register and flash data register to perform the isp function without removing the SM39R04G1 from the system. the SM39R04G1 provides internal flash control signals which can do flash program/chip erase /page erase/protect functions. user need to design and use any kind of interface which SM39R04G1 can input data. user then utilize isp service program to perform the flash program/chip erase/page erase/protect functions. 13.1. isp service program the isp servi ce program is a user developed firmware program which resides in the isp service program space. after user developed the isp service program, user then determine the size of the isp service program. user need to program the isp service program in the sm39r 04g1 for the isp purpose. the isp service programs were developed by user so that it should includes any features which relates to the flash memory programming function as well as communication protocol between SM39R04G1 and host device which output data to the SM39R04G1. for example, if user utilize uart interface to receive/transmit data between SM39R04G1 and host device, the isp service program should include baud rate, checksum or parity check or any error - checking mechanism to avoid data transmission error. the isp service program can be initiated under SM39R04G1 active or idle mode. it can not be initiated under power down mode. 13.2. lock bit (n) the lock bit n has two functions: one is for service program size configuration and the other is to lock the isp service program space from flash erase function. the isp service program space address range $c00 to $fff. it can be divided as blocks of n*256 byte. (n=0 to 4). when n=0 means no isp function, all of 4k byte flash memory can be used as program memor y. when n=1 means isp service program occupies 256 byte while the rest of 3.75k byte flash memory can be used as program memory. the maximum isp service program allowed is 1k byte when n=4. under such configuration, the usable program memory space is 3k by te. after n determined, SM39R04G1 will reserve the isp service program space downward from the top of the program address $fff. the start address of the isp service program located at $ 0c00 . please see section 3.1 program memory diagram for this isp servi ce program space structure. the lock bit n function is different from the flash protect function. the flash erase function can erase all of the flash memory except for the locked isp service program space. if the flash not has been protected, the content of isp service program still can be read. if the flash has been protected, the overall content of flash program memory space including isp service program space can not be read. table 1 3 .1 isp code area . n isp service program address 0 no isp service pro gram 1 256 bytes ( $ f 00h ~ $ f ffh ) 2 512 bytes ( $e00h ~ $ f ffh ) 3 768 bytes ( $d00h ~ $ f ffh ) 4 1.0 k bytes ( $c00h ~ $ f ffh ) isp service program configurable in n*256 byte (n= 0 ~ 4 )
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 43 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 13.3. program the isp service program after lock bit n is set and isp servic e program been programmed, the isp service program memory will be protected (locked) automatically. the lock bit n has its own program/erase timing. it is different from the flash memory program/erase timing so the locked isp service program can not be era sed by flash erase function. if user needs to erase the locked isp service program, he can do it by writer only. user can not change isp service program when SM39R04G1 was in system. 13.4. initiate isp service program to initiate the isp service program is to load the program counter (pc) with start address of isp service program and execute it. there are four ways to do so: (1) blank reset. hardware reset with first flash address blank ($0000=#ffh) will load the pc with start address of isp service program. the h ardware reset includes max810 (power on reset) and external pad reset. the hardware will issue a strobe window about 256us after hardware reset. (2) execute jump instruction can load the start address of the isp service program to pc. (3) enters isp service progr am by hardware setting. user can force SM39R04G1 enter isp service program by setting isp active pin ( 14l at p3.7 10l at p3.3), active low during hardware reset period. the hardware reset includes max810 (power on reset) and external pad reset. the hardware will issue a strobe window about 256us after hardware reset. in application system design, user sh ould take care of the setting of isp active pin (14l at p3.7 10l at p3.3), at reset period to prevent SM39R04G1 from entering isp service program. (4) enters isp service program by hardware setting, the p3.0 will be detected the two clock signals during har dware reset period. the hardware reset includes max810 (power on reset) and external pad reset. the hardware will issue a 256us strobe window to detect 2 clock signals after hardware reset. during the strobe window, the hardware will detect the status of isp active pin ( 14l at p3.7 10l at p3.3) and p3.0. if they meet one of above conditions, chip will switch to isp mode automatically. after isp service program executed, user need to reset the SM39R04G1, either by hardware reset or by wdt, or jump to the address $0000 to r e - start the firmware program. there are 6 kinds of entry mechanisms for user different applications. this entry method will select on the writer or i s p. (1) first address blank. i .e. $0000 = 0xff. and triggered by internal reset signal. (2) first address blank. i .e. $0000 = 0xff. and triggered by pad reset signal. (3) isp active pin (14l at p3.7 10l at p3.3)=0 . and triggered by internal reset signal. (4) isp active pin (14l at p3.7 10l at p3.3) =0. and triggered by pad reset signal. (5) p3.0 input 2 clocks. and triggered by internal reset signal. (6) p3.0 input 2 clocks. and triggered by pad reset signal. 13.5. isp register C takey, ifcon, ispfah, ispfal, ispfd and ispfc mnemonic description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset isp function takey time acc ess key register f7h takey [7:0] 00h ifcon interface control register 8fh - cdpr - - - - - ispe 00h ispfah isp flash address - high register e1h - ispfah [3:0] ffh ispfal isp flash address - low register e2h ispfal [7:0] ffh
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 44 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 ispfd isp flash data regist er e3h ispfd [7:0] ffh ispfc isp flash control register e4h emf1 emf2 emf3 emf4 - ispf.2 ispf.1 ispf.0 00h mnemonic: takey address: f7h 7 6 5 4 3 2 1 0 reset takey [7:0] 00h isp enable bit (ispe) is read - only by default, software must write three sp ecific values 55h, aah and 5ah sequentially to the takey register to enable the ispe bit write attribute. that is: mov takey, #55h mov takey, #aah mov takey, #5ah mnemonic: ifcon address: 8fh 7 6 5 4 3 2 1 0 reset - cdpr - - - - - ispe 00h the bit 0 ( ispe) of ifcon is isp enable bit. user can enable overall SM39R04G1 isp function by setting ispe bit to 1, to disable overall isp function by set ispe to 0. the function of ispe behaves like a security key. user can disable overall isp function to prevent software program be erased accidentally. isp registers ispfah, ispfal, ispfd and ispfc are read - only by default. software must be set ispe bit to 1 to enable these 4 registers write attribute. mnemonic: ispfah address: e1h 7 6 5 4 3 2 1 0 reset - - - - ispfah3 ispfah2 ispfah1 ispfah0 ffh ispfah [ 3 :0]: flash address - high for isp function mnemonic: ispfal address: e2h 7 6 5 4 3 2 1 0 reset ispfal7 ispfal6 ispfal5 ispfal4 ispfal3 ispfal2 ispfal1 ispfal0 ffh ispfal [7:0]: flash address - low for isp fu nction the ispfah & ispfal provide the 1 2 - bit flash memory address for isp function. the flash memory address should not include the isp service program space address. if the flash memory address indicated by ispfah & ispfal registers overlay with the is p service program space address, the flash program/page erase of isp function executed thereafter will have no effect. mnemonic: ispfd address: e3h 7 6 5 4 3 2 1 0 reset ispfd7 ispfd6 ispfd5 ispfd4 ispfd3 ispfd2 ispfd1 ispfd0 ffh ispfd [7:0]: flash da ta for isp function. the ispfd provide the 8 - bit data register for isp function.
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 45 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 mnemonic: ispfc address: e4h 7 6 5 4 3 2 1 0 reset emf1 emf2 emf3 emf4 - ispf[2] ispf[1] ispf[0] 00h emf1: entry mechanism (1) flag, clear by reset. (read only) emf2: entry mechanism (2) flag, clear by reset. (read only) emf3: entry mechanism (3) flag, clear by reset. (read only) emf4: entry mechanism (4) flag, clear by reset. (read only) ispf [2:0]: isp function select bit. ispf[2:0] isp function 000 byte progra m 001 chip protect 010 page erase 011 chip erase 100 write option 101 read option 110 erase option 111 finish flag one page of flash memory is 256 byte the option function can access the xtal1 and xtal2 configured to i/o pins select(description in section 1.2)
sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 46 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 operating conditions symbol description min. typ. max. unit. remarks ta operating temperature - 40 25 85 cc supply voltage 2. 7 5.5 v 23mhz(max) v cc supply voltage 3.0 5.5 v 25mhz(max) dc characteristics t a = - 40 to 85 , v cc = 5.0v symbol parameter valid min max units conditions vil1 input low - voltage por t 1,3 - 0.5 0.8 v vcc=5v vil2 input low - voltage res, xtal1 0 0.8 v vih1 input high - voltage port 1,3 2.0 v cc + 0.5 v vih2 input high - voltage res, xtal1 70%vcc v cc + 0.5 v vol output low - voltage port 1,3 0.4 v iol= 5.0 ma vcc=5v voh1 output high - vol tage using strong pull - up (1) port 1,3 2.4 v ioh= - 16 ma voh2 output high - voltage using weak pull - up (2) port 1,3 2.4 v ioh= - 2 80 ua iil logic 0 input current port 1,3 - 75 ua vin= 0.45v itl logical transition current port 1,3 - 650 ua vin= 2.0v ili inp ut leakage current port 1,3 10 ua 0.45v sm 3 9 r04g1 8 - bit micro - controller 4kb with isp fl as h & 256 b ram embedded specifications subject to change without notice contact your sales representatives for the most recent information. i ssfd - m 0 53 47 ver. h sm 3 9 r 04g1 0 8 / 20 1 3 t a = - 40 to 85 , v cc = 3. 0 v symbol parameter valid min max units conditions vil1 input low - voltage port 1,3 - 0.5 0.8 v vcc=3. 0 v vil2 input low - voltage res, xtal1 0 0.8 v vih1 input high - voltage port 1,3 2.0 v cc + 0.5 v vih2 input high - voltage res, xtal1 70%vcc v cc + 0.5 v vol output low - voltage port 1,3 0.4 v iol= 3. 0 ma v cc=3. 0 v voh1 output high - voltage using strong pul l - up (1) port 1,3 2.4 v ioh= - 3.2 ma voh2 output high - voltage using weak pull - up (2) port 1,3 2.4 v ioh= - 55 ua iil logic 0 input current port 1,3 - 75 ua vin= 0.45v itl logical transition current port 1,3 - 650 ua vin=1.5v ili input leakage curren t port 1,3 10 ua 0.45v 0 . 1 u f v s s

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