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november 2012 doc id 15716 rev 2 1/19 AN2985 application note steval-ifp010v3: designing with vni2140j dual high-side smart power solid-state relay ic introduction the steval-ifp010v3 demonstration board has been developed to show the vni2140j device functionalities within industrial applications such as plcs (programmable logic controllers) which drive lamps, valves, relays, and similar loads. this tool allows evaluating vni2140j features, in particular embedded self-protection, power-handling capabilities, operation and diagnostic feedback, thermal behavior and conformity to emc immunity standards. figure 1. steval-ifp010v3 a double-sided pcb allows obtaining the best trade-off between a routing solution and thermal management results. the main features of the demonstration board are: two output channels (2 x 1 a) two input channels two feedback channels for fault and open load diagnostics bidirectional opto-isolated interface for mcu safe connection ttl/cmos compatible signals for mcu direct connection leds to indicate outputs compliance to iec61000-4-4 and iec61000-4-5 standards compatibility with existing stmicroelectronics tools (ibu communication board, canic10, for example) 10.5 v to 36 v dc power supply voltage range demonstration board description www.st.com
contents AN2985 2/19 doc id 15716 rev 2 contents 1 steval-ifp010v3 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 safety precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 vni2140j - device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5.1 steval-ifp010v3 electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.2 steval-ifp010v3 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5.3 steval-ifp010v3 thermal management . . . . . . . . . . . . . . . . . . . . . . . 10 2 emc immunity tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 burst immunity test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 surge test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 appendix a steval-ifp010v3 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . 15 appendix b steval-ifp010v3 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 appendix c reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AN2985 list of tables doc id 15716 rev 2 3/19 list of tables table 1. steval-ifp010v3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. j1 and j5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. burst setup configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. burst test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. surge test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. steval-ifp010v3 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
list of figures AN2985 4/19 doc id 15716 rev 2 list of figures figure 1. steval-ifp010v3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. steval-ifp010v3 top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. steval-ifp010v3 bottom view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. steval-ifp010v3 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. j1 connector pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. j5 connector pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. steval-ifp010v3 pcb copper heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. thermal map in steady-state condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 10. thermal map in demagnetization condition (1 hz repetitive cycling on 1.2 h 48 w load) . 11 figure 11. steady-state thermal behavior, 3d simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 12. repetitive demagnetization thermal behavior, 3d simulation (1 hz repetitive cycling on 48 w 1.2 h load) 11 figure 13. burst timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. surge standard timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. steval-ifp010v3 component layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16. steval-ifp010v3 copper top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 17. steval-ifp010v3 copper bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AN2985 steval-ifp010v3 demonstration board doc id 15716 rev 2 5/19 1 steval-ifp010v3 demonstration board 1.1 safety precautions the board must be used only by expert technicians. the copper areas around the vni2140j device have a heat sink function, visible in the top layer layout view, refer to figure 8 . in case of short-circuit, current limitation or hard demagnetization, the steval-ifp010v3 board, or part of it, might reach a very high temperature with consequent danger. no specific protections are implemented for a reverse dc accidental connection. remember that an electrolytic capacitor is connected to the supply bus, therefore a reverse continuous dc voltage applied to it may produce a dangerous explosion. warning: st assumes no responsibility for any consequences which may result from the improper use of this tool. 1.2 description the steval-ifp010v3 demonstration board is composed of two main sections: an opto-isolated interface for input and status signals a two-channel self-protected power stage section with stmicroelectronics transil? diode protection. the demonstration board consists of a double-sided fr4 printed circuit board with 35 m copper plating. the pcb dimensions are 52 mm x 68 mm. the top and bottom view are shown in figure 3 and 4 , respectively. 1.3 vni2140j - device overview the vni2140j is a monolithic two-channel driver featuring a very low supply current. the ic, which uses stmicroelectronics vipower technology, is intended for driving loads with one side connected to ground. active channel current limitation, combined with thermal shutdown (independent for each channel) and automatic restart, protect the device against overload. the main features of the vni2140j ic are: output current: 1 a per channel shorted load protections for each channel junction overtemperature protection for thermal independence of the channels case overtemperature protection and restart are not simultaneous for the two channels protection against ground disconnection current limitation undervoltage shutdown
steval-ifp010v3 demonstration board AN2985 6/19 doc id 15716 rev 2 open load in off state and short to vcc detection open drain diagnostic outputs 3.3 v cmos/ttl compatible inputs fast demagnetization of inductive loads conforms to iec 61131-2 figure 2. block diagram active current limitation avoids that the system power supply drops in case of a shorted load. in overload condition, the channel turns off and back on automatically after the ic temperatures decreases below a threshold set by a temperature hysteresis so that junction temperature is controlled. if this condition makes the case temperature reach the case temperature limit (t csd ), overloaded channels are turned off (i.e. the channels for which junction temperature has exceeded the junction protection threshold, t jsd , and has not fallen below the junction protection reset threshold, t jr ). these channels restart, non-simultaneously, only when the case temperature decreases below the case protection reset threshold (t cr ). non- overloaded channels continue to operate normally. the open drain diagnostic outputs indicate related channel overtemperature conditions. 1.4 electrical characteristics the electrical characteristics of the vni2140j demonstration board (steval-ifp010v3) are given in ta b l e 1 . !-v
AN2985 steval-ifp010v3 demonstration board doc id 15716 rev 2 7/19 table 1. steval-ifp010v3 electrical characteristics parameter value comments min typ max operating condition ambient operating temperature 85 c if the vni2140j junction temperature exceeds 180 c, the device shuts down power supply dc mains voltage range 10.5 v 36 v dc insulated voltage 5 v from eval communication board supply current on vdd 300 a all channels are off 1.9 ma 3.8 ma all channels are on, vin = 5 v output stage output channel (on) current limitation 1 a 2 a internally limited v cc = 24 v; r load < 10 m dv/dt (on) turn-on voltage slope 3 v/s i out = 0.5 a, resistive load dv/dt (off) turn-off voltage slope 4 v/s i out = 0.5 a, resistive load demagnetization protection output voltage on inductive turn-off v cc -45 v cc -50 v cc -52 i out = 0.5 a; l load >= 1 mh
steval-ifp010v3 demonstration board AN2985 8/19 doc id 15716 rev 2 1.5 circuit description the main components and functions of the module are indicated below: power section l6562a controller fot delay current setting leds dimming auxiliary power open / short-circuit protection figure 3. steval-ifp010v3 top view figure 4. steval-ifp010v3 bottom view !-v
AN2985 steval-ifp010v3 demonstration board doc id 15716 rev 2 9/19 1.5.1 steval-ifp010v3 electrical schematic figure 5. steval-ifp010v3 schematic !-v & q) & q) & q) & x) 7 7 *1' 28 7 28 7 9gf 0 09,7(% ' 607$& & q) & q) 7 7 $% - *1'',6&7(67 7 7 $% - 9ff',6&7(67 &855(17352%( $% - '/ /(' '/ /(' ,1 ,1 9'' 67$7 67$7 ,1 ,1 9'' 67$7 67$7 ,1 ,1 9'' 67$7 67$7 25 - (9$/&200%2$5' - &$1 0 09,7(% ,& 7/3) ,& 7/3) ,& 7/3) ,& 7/3) 5 . 5 . 5 . 5 . 5 . 5 . 5 . 5 . 5 . 5 . 5 . 5 . ,q 'ldj 'ldj ,q *1' 2xw 2xw 2xw 2xw 9ff 7$% 9ff 9ff ,& 91,- ,/)251,725(+$5,&+,(67281$6267,78=,21('(/9$ /25(',5( 5'$$.
steval-ifp010v3 demonstration board AN2985 10/19 doc id 15716 rev 2 1.5.2 steval-ifp010v3 connectors the demonstration board is equipped with input and output connectors. specifically, there are two input header connectors (j5 and j1), one two-channel output channel connector (m1) and a supply voltage connector (m2). both input connectors, j5 and j1, provide the same bidirectional signals guaranteeing the maximum compatibility with existing stmicroelectronics tools such as the industrial communication board (see an2451) and similar products. figure 6. j1 connector pinout figure 7. j5 connector pinout 1.5.3 steval-ifp010v3 thermal management the steval-ifp010v3 pcb has two heatsinks: approximately 2 sq. cm on the top layer and 3 sq.cm on the bottom layer, thermally interconnected through 9 vias, as shown in figure 8 . in a steady-state condition low r ds(on) ensures a very low dissipation but, in current limitation and in fast demagnetization, the power dissipation is much higher, requiring a low thermal resistance through the device exposed tab, soldering space, top layer, vias and bottom layer path. a 25 m copper (10 oz/sq. ft) thickness and 0.3 mm diameter for the vias are used according to eia/jesd51-5. table 2. j1 and j5 pin descriptions j1 - pin number j5 - pin number signal type 11 1 vdd 5/3.3 v supply voltage 23 2 gnd signal ground 9 3 in1 input channel 1 13 4 in2 input channel 2 6 7 stat1 status channel 1 25 8 stat2 status channel 2 !-v !-v
AN2985 steval-ifp010v3 demonstration board doc id 15716 rev 2 11/19 figure 8. steval-ifp010v3 pcb copper heatsink figure 9 and 11 show the steval-ifp010v3 temperature map with all channels permanently switched on, 48 loads, 24 v supply voltage and ambient temperature of 25 c. the ic temperature increase is only about a few degrees. figure 10 and 12 show a similar map when the ic is cycling at 1 hz, 50% duty cycle, 48 , 1.2 h loads, 24 v supply voltage and ambient temperature of 25 c. in particular figure 11 and 12 show a 3d thermal modelization of the device. !-v figure 9. thermal map in steady-state condition figure 10. thermal map in demagnetization condition (1 hz repetitive cycling on 1.2 h 48 load) !-v !-v figure 11. steady-state thermal behavior, 3d simulation figure 12. repetitive demagnetization thermal behavior, 3d simulation (1 hz repetitive cycling on 48 1.2 h load) !-v !-v
emc immunity tests AN2985 12/19 doc id 15716 rev 2 2 emc immunity tests the steval-ifp010v3 has been tested according to emc immunity standards iec61000-4-4 (fast transient burst) and iec61000-4-5 (high energy surge). a fast transient burst test has been performed all channels. each channel under test cycles on and off at 1 hz, duty cycle 50%, on two 48 load resistors at 24 v dc supply voltage. a burst signal was applied using an ultra-compact simulator with an internal capacitive coupling clamp tool. 2.1 test conditions ambient temperature: 25.5 c ambient humidity: 46% mains voltage power supply: 24 vdc dc insulated voltage: 5 vdc loads: 4 x 48 power resistor 2.2 burst immunity test ta b l e 3 shows the burst setup configuration used to perform this test. figure 13 shows the standard timing waveform applied during the burst test. table 3. burst setup configuration test level condition pulse time rt 5 ns 30% pulse duration td 50 ns 30% source impedance zq = 50 20% polarity positive / negative burst duration ( td ) 15 ms 20 % at burst frequency ( f )5 khz burst period ( tr ) 300 ms 20 % duration time (t) 5 min
AN2985 emc immunity tests doc id 15716 rev 2 13/19 figure 13. burst timing waveform ta b l e 4 shows the results of a burst test. normal performance has been observed when applying two different disturbance levels on the output ports and vcc main voltage power supply. 2.3 surge test a high energy surge test was performed in differential mode. a high surge signal was injected on the dut (device under test) through a 42 decoupling resistor. the test consisted of three positive and three negative discharges with a repetition rate of 1 discharge per minute. figure 14 shows the standard timing waveform applied on the dut. table 4. burst test results burst standard test routines level voltag e level (kv) acceptance criteria (1) 1. classification of the test: (criteria a): normal performance (criteria b): temporary degradation or loss of function or performance with automatic return to normal operation (criteria c): temporary degradation or loss of function with external intervention to recover normal operation (criteria d): degradation or loss of function, need replacement of damaged components to recover normal operation. iec 61000-4-4 level 1 0.5 a iec 61000-4-4 level 2 1 a iec 61000-4-4 level 3 2 a iec 61000-4-4 level 4 4 a !-v
emc immunity tests AN2985 14/19 doc id 15716 rev 2 figure 14. surge standard timing waveform ta b l e 5 below shows normal performance of the device. table 5. surge test results surge standard test routines level voltage level (kv) acceptance criteria (1) 1. classification of the test: (criteria a): normal performance (criteria b): temporary degradation or loss of function or performance with automatic return to normal operation (criteria c): temporary degradation or loss of function with external intervention to recover normal operation (criteria d): degradation or loss of function, need substitution of damaged components to recover normal operation. iec 61000-4-5 level 1 0.5 a iec 61000-4-5 level 2 1 a iec 61000-4-5 level 3 2 a !-v
AN2985 steval-ifp010v3 bill of material doc id 15716 rev 2 15/19 appendix a steval-ifp010v3 bill of material table 6. steval-ifp010v3 bill of material designator part type description c1 10 nf ceramic capacitor c2 10 nf ceramic capacitor c3 100 nf ceramic capacitor c4 47 f 50 v electrolytic capacitor c5 4.7 nf ceramic capacitor c6 4.7 nf ceramic capacitor d1 sm15t39ac st transil? diode dl1 led led dl2 led led ic1 vni2140j st high-side driver ic ic2 tlp281f opto-coupler ic3 tlp281f opto-coupler ic4 tlp281f opto-coupler ic5 tlp281f opto-coupler j1 header 34-pin eval communication board connector j3 gnd disc. test jumper j4 vcc disc. test jumper j5 header 34-pin 14.p plug m1 2-way connector screw drive connector m2 2-way connector screw drive connector r1 22 k resistor r2 22 k resistor r3 47 k resistor r4 47 k resistor r5 1 k resistor r6 1 k resistor r7 10 k resistor r8 10 k resistor r9 10 k resistor r10 10 k resistor r11 220 k resistor r12 220 k resistor
steval-ifp010v3 pcb layout AN2985 16/19 doc id 15716 rev 2 appendix b steval-ifp010v3 pcb layout figure 15. steval-ifp010v3 component layer figure 16. steval-ifp010v3 copper top layer figure 17. steval-ifp010v3 copper bottom layer !-v !-v
AN2985 reference documents doc id 15716 rev 2 17/19 appendix c reference documents 1. an1351 2. an2684
revision history AN2985 18/19 doc id 15716 rev 2 revision history table 7. document revision history date revision changes 17-nov-2009 1 initial release. 07-nov-2012 2 updated steval-ifp010v2 with steval-ifp010v3 and updated figure.
AN2985 doc id 15716 rev 2 19/19 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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