integrated circuit systems, inc. general description features ics9158-03 block diagram 9158-03 rev d 7/28/98 applications frequency generator and integrated buffer the ics9158-03 is a low-cost frequency generator designed specifically for desktop and notebook pc applications. eight copies of the cpu clock are available. each high drive (40ma) output is capable for driving a 30pf load and has a typical duty cycle of 50/50. the clock outputs are skew-controlled to within 250ps. the ics9158-03 makes a gradual transition between frequencies, so that it meets the intel cycle-to-cycle timing specification for 486 and pentium? systems. ? 8 skew-free, high drive cpu/bus clocks ? up to 100 mhz output ? 250ps skew between all outputs ? outputs can drive up to 30pf load and 40ma ? 5010% duty cycle ? compatible with 486 and pentium cpus ? on-chip loop filter components ? 4 .5v - 5.5v supply range ? 24-pin soic package ? ideal for risc or cisc systems such as 486, pentium, powerpc?, etc. requiring multiple cpu and bus clocks. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9158-03 pin configuration 24-pin soic functionality (assuming 14.318 mhz input.) vdd=5v10% or 3.3v10%, temp=0-70c peripheral clocks fs2 fs1 fs0 clk2a (mhz) clk12(a-c) (mhz) clk1(a-d) (mhz) 000321616 001323216 010321616 011323216 1 0 0 502525 1 0 1 505025 1 1 0 66.67 33.33 33.33 1 1 1 60 60 30 oe clk2a clk12(a-c) clk12(a-d) 40mhz (pin 6) 24mhz (pin 7) ref (pin 18) 1 runs runs runs 39.92 23.95 14.31818 0 tristatetristatetristatetristatetristatetristate
3 ics9158-03 pin descriptions for ics9158-03 pin number pin name type description 1 clk1a out clk1a clock output 2 x2 out crystal connection 3 x1 in crystal connection 4 vdd pwr digital power supply (+5v) 5 gnd pwr digital ground 6 40 mhz out 40 mhz clock output 7 24 mhz out 24 mhz floppy disk/combination i/o clock output 8 clk1b out clk1b clock output 9 agnd pwr analog ground 10 oe in output enable. tristates all outputs when low. 11 clk12b out clk12b clock output 12 gnd pwr digital ground 13 clk1c out clk1c clock output 14 clk1d out clk1d clock output 15 fs2 in cpu clock frequency select 2 16 avdd pwr analog power supply (+5v) 17 clk12a out clk12a clock output 18 ref out 14.31818 mhz clock output 19 gnd pwr digital ground 20 vdd pwr digital power supply (+5v) 21 clk12c out 2x cpu clock output 22 clk2a out cpu clock output 23 fs1 in cpu clock frequency select 1 24 fs0 in cpu clock frequency select 0
4 ics9158-03 electrical characteristics at 5v absolute maximum ratings avdd, vdd referenced to gnd . . . . . . . . . . . . . . . . 7v operating temperature under bias. . . . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +150c voltage on i/o pins referenced to gnd. . . . . . . . . . . gnd -0.5v to vdd +0.5v power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 watts stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il 0.8 v input high voltage v ih 2.0 v input low current i il v in =0v (pull-up) -20 a input high current i ih v in =v dd -5 5 a output low voltage v ol i ol =20.0ma 0.25 0.4 v output high voltage 1 v oh i oh =-30ma 2.4 3.5 v output low current 1 i ol v ol =0.8v 45 65 ma output high current 1 i oh v oh =2.0v -55 -35 ma supply current i dd no load, 66 mhz 67 100 ma output frequency change over supply and temperature 1 f d with respect to typical frequency 0.002 0.01 % short circuit current 1 i sc each output clock 25 56 ma pull-up resistor value 1 r pu input pin 680 k w input capacitance 1 c i except x1, x2 8 pf load capacitance 1 c l pins x1, x2 20 pf v dd = +5v10%, t a =0c to 70c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production.
5 ics9158-03 electrical characteristics ( continued ) note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units output rise time, 0.8 to 2.0v (note 1) tr 30pf load - 1 2.0 ns rise time, 20% to 80% vdd (note 1) tr 30pf load - 2.5 3 ns output fall time, 2.0 to 0.8v 1 tf 30pf load - 0.5 2.0 ns fall time, 80% to 20% vdd 1 tf 30pf load - 1.5 3.0 ns duty cycle 1 dt 30pf load 45/55 48/52 55/45 % jitter, one sigma 1 tj1s as compared with clock period 0.5 2.0 % jitter, absolute tjab -5 2 5 % jitter, absolute tjab 25-66mhz clocks -250 250 ps input frequency fi 14.318 mhz clock skew between clk2a, clk1(a-d) and clk12(a-c) outputs tsk -250 100 250 ps frequency transition time 1 tft from 4 to 50 mhz 13 20 ms v dd = +5v10%, t a =0c to 70c unless otherwise stated
6 ics9158-03 v dd = +3.3v10%, t a =0c to 70c unless otherwise stated electrical characteristics at 3.3v note 1: parameter is guaranteed by design and characterization. not 100% tested in production. dc characteristics parameter symbol test conditions min typ max units input low voltage v il 0.2 vdd v input high voltage v ih 0.7 vdd v input low current i il v in =0v(pull-up) -10 a input high current i ih v in =v dd -5 a output low voltage v ol i ol =10ma 0.1v dd v output high voltage 1 v oh i oh =-5ma 0.85v dd v output low current 1 i ol v ol =0.2v dd 20 30 ma output high current 1 i oh v oh =0.7v dd -15 -10 ma supply current i dd no load, 66 mhz 43 70 ma output frequency change over supply and temperature 1 f d with respect to typical frequency 0.002 0.01 % short circuit current 1 i sc each output clock 25 56 ma pull-up resistor value 1 r pu input pin 900 kw input capacitance 1 c i except x1, x2 8 pf load capacitance 1 c l pins x1, x2 20 pf ac characteristics parameter symbol test conditions min typ max units output rise time, 0.8 to 2.0v 1 t r 30pf load - 1 2.5 ns rise time, 20% to 80% v dd 1 t r 30pf load - 2.5 4.0 ns output fall time, 2.0 to 0.8v 1 t f 30pf load - 0.5 2.5 ns fall time, 80% to 20% v dd 1 t f 30pf load - 1.5 4.0 ns duty cycle 1 d t 30pf load 40/50 44/46 50/40 % jitter, one sigma 1 t j1s as compared with clock period 0.5 2.0 % jitter, absolute 1 t jab 25% jitter, absolute 1 t jab 25-66 mhz clocks 300 ps input frequency f i 14.318 mhz clock skew window between clk2a, clk1(a-d) cpu and clk12(a-c) outputs 1 t sk 100 250 ps frequency transition time 1 t ft from 4 to 50 mhz 13 20 ms
7 ics9158-03 ordering information ics9158-03cw24 example: ics xxxx-ppp w package type w=(soic) 300mil pattern number (2 or 3 digit number for parts with rom code patterns) device type (consists of 3 or 4 digit numbers) prefix ics, av=standard device; gsp=genlock device 24 lead soic lead count 24l dimension l 0.604 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
|
