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1/66 ste2004 july 2004 1 features 102 x 65 bits display data ram programmable mux rate programmable frame rate x,y programmable carriage return dual partial display mode row by row scrolling n-line inversion automatic data ram blanking procedure selectable input interface: ? i 2 c bus fast and hs-mode (read and write) 68000 & 8080 parallel interfaces (read and write) 3-lines and 4-lines spi interface (read and write) 3-lines 9 bit serial interface (read and write) fully integrated oscillator requires no external components cmos compatible inputs fully integrated configurable lcd bias voltage generator with: selectable multiplication factor (up to 5 x ) effective sensing for high precision output eight selectable temperature compensation coefficients designed for chip-on-glass (cog) applications. low power consumption, suitable for battery operated systems logic supply voltage range from 1.7 to 3.6v high voltage generator supply voltage range from 1.75 to 4.5v display supply voltage range from 4.5 to 14.5v backward compatibility with ste2001/2 2 description the ste2004 is a low power cmos lcd control- ler driver. designed to drive a 65 rows by 102 col- umns graphic display, it provides all necessary functions in a single chip, including on-chip lcd supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. ste2004 features six standard interfaces (3-lines serial, 3-lines spi, 4-lines spi, 68000 parallel, 8080 parallel & i 2 c) for ease of interfacing with the host micro-controller table 1. order codes part numbers type ste2004die1 bumped wafers STE2004DIE2 bumped dice on waffle pack 102 x 65 single chip lcd controller / driver figure 1. block diagram column drivers row drivers data latches 65 x 102 ram display control logic scroll logic data register instruction register co to c101 r0 to r64 vsense slave res vdd1,2 clock timing generator bias voltage generator high voltage generator reset test shift register vlcd v ss sel1,2 ext icon_mode vssaux sao sdin/sda_in sda_out sclk/scl db0 to db7 9 bit serial d/c cs sa1 sdout e/wr r/w- rd i2c bus 3 & 4 line spi parallel 8080 parallel 68k sel 0 sel 1 sel 2 test_vref test_mode lr0047 osc osc_in osc_out fr_in fr_out master slave sync vlcdsense rev. 4
ste2004 2/66 table 2. pin description n pad type function r0 to r64 1-6 109-141 o lcd row driver output c0 to c101 6-107 o lcd column driver output v ss 192-203 gnd ground pads. v dd1 156-163 supply ic positive power supply v dd2 164-171 supply internal generator supply voltages. v lcd 205-209 supply voltage multiplier output v lcdsense 204 supply voltage multiplier regulation input. v lcdout sensing for output voltage fine tuning v sense_slave 145 supply voltage reference for slave charge pump v ssaux 190-177- 147 o ground reference for pins configuration v dd1aux 142 o vdd1 reference for pins configuration sel1,2,3 152 153 154 i interface mode selection - cannot be left floating ext_set 151 i extended instruction set selection - cannot be left floating icon_mode 155 i extended instruction set selection - cannot be left floating sdout 180 o serial & spi data output - if unused must be left floating sdin - sdain 179 i sdin - serial & spi interface data input - cannot be left floating i sdain - i 2 c bus data in - cannot be left floating sclk - scl 181 i sclk - serial & spi interface clock - cannot be left floating i scl - i 2 c bus clock - cannot be left floating sda_out 178 o i 2 c bus data out if unused must be left floating sa0 149 i i 2 c slave address bit 0 - cannot be left floating sa1 148 i i 2 c slave address bit 1- cannot be left floating db0 to db7 182-189 i/o parallel interface 8 bit data bus - cannot be left floating r/w - rd 175 i r/w - 68000 series parallel interface read & write control input - cannot be left floating ird - 8080 series parallel interface read enable clock input - cannot be left floating e / wr 176 i e - 68000 series parallel interface read & write clock input - cannot be left floating sel3 sel2 sel1 interface gnd / vssaux gnd / vssaux gnd / vssaux i 2 c gnd / vssaux gnd / vssaux vdd1 spi 4-lines 8 bit gnd / vssaux vdd1 gnd / vssaux spi 3-lines 8 bit gnd / vssaux vdd1 vdd1 serial 3-lines 9 bit vdd1 gnd / vssaux gnd / vssaux parallel 8080-series vdd1 gnd / vssaux vdd1 parallel 68000-series ext pad config instruction set selected gnd or vssaux basic vdd1 extended icon mode pad config icon mode status gnd or vssaux disbled vdd1 enabled
3/66 ste2004 e / wr 176 i wr - 8080 series parallel interface - write enable clock input - cannot be left floating res 172 i reset input. active low. d/c 174 i interface data/command selector- cannot be left floating cs 173 i serial & parallel interfaces enable. when low the incoming data are clocked in. cannot be left floating test_mode 191 i test pad - 50 kohm internal pull-down must be connected to vss/vssaux test_vref 146 o test pad - must be left floating oscin 144 i oscillator input: oscout 210 o internal/external oscillator out - if unused must be left floating fr_out 211 o master slave frame inversion synchronization. if unused must be left floating fr_in 143 i master slave frame inversion synchronization. cannot be left floating m/s 100 i master/ slave configuration bit:- cannot be left floating table 2. pin description (continued) n pad type function osc_in configuration high internal oscillator enabled low internal oscillator disabled external scillator internal oscillator disabled m/s pin osc_out fr_out fr_in charge pump high enabled enabled disabled auxvsense disabled low enabled enabled enabled charge pump in slave mode or ext power
ste2004 4/66 figure 2. chip mechanical drawing ste2004 col 0 vlcdsense (0,0) x y d/c cs res col 101 col 50 col 51 row 6 osc_out row 27 row 38 row 59 mark_1 mark_4 mark_3 mark_2 d0 d1 d2 d3 d4 d5 d6 d7 vssaux vssaux e - wr r/w - rd lr0048 sdaout sdin - sdain sclk - scl sdout sa1 sel2 sel3 vssaux m/s sa0 sel1 vlcd vss test_mode vdd1 vdd2 test vref fr_out vsense_slave vdd1_aux osc_in fr_in row 32 row 37 row 5 row 0 row64/icon row63 row60 row31 row28 icon ext_set
5/66 ste2004 figure 3. improved alth & plesko driving method v ss v 5 v 4 v 3 v 2 v lcd v ss v 5 v 4 v 3 v 2 v lcd row 0 r0 (t) row 1 r1 (t) v ss v 5 v 4 v 3 v 2 v lcd v ss v 5 v 4 v 3 v 2 v lcd col 0 c0 (t) col 1 c1 (t) v 3 - v ss 0v v 3 - v ss v lcd - v ss v ss - v 5 0v v 4 - v 5 v ss - v lcd v 4 - v lcd v ss - v 5 0v v 4 - v 5 v ss - v lcd v 4 - v lcd v state1 (t) v lcd - v 2 v 3 - v ss frame n frame n + 1 0 1 2 3 4 5 6 7 8 9 64 0v v 3 - v ss v lcd - v ss v state2 (t) v lcd - v 2 ..... ....... 0 1 2 3 4 5 6 7 8 9 64 ..... ....... ? v 1 (t) ? v 2 (t) ? v 1 (t) = c1(t) - r0(t) ? v 2 (t) = c1(t) - r1(t) d00in1154
ste2004 6/66 3 circuit description 3.1 supplies voltages and grounds v dd2 is supply voltages to the internal voltage generator (see below). if the internal voltage generator is not used, this should be connected to v dd1 pad. v dd1 supplies the rest of the ic. v dd1 supply voltage could be different form v dd2 . 3.2 internal supply voltage generator the ic has a fully integrated (no external capacitors required) charge pump for the liquid crystal display supply voltage generation. the multiplying factor can be programmed to be: auto, x5, x4, x3, x2, using the ?set cp multiplication? command. if auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition. this make possible to have an input voltage that chang- es over time and a constant v lcd voltage. the output voltage (v lcd ) is tightly controlled through the v l- cdsense pad. for this voltage, eight different temperature coefficients (tc, rate of change with temperature) can be programmed using tc1 & tc0 or t2, t1 and t0 bits. this will ensure no contrast degradation over the lcd operating range. an external supply could be connected to v lcd to supply the lcd without using the internal generator. in such event the internal voltage generator must be programmed to zero (prs = [0;0], vop = 0 - reset con- dition) and the charge pump (cp[0;0]) set to 5x or auto mode. 3.3 oscillator a fully integrated oscillator (requires no external components) is present to provide the clock for the dis- play system. when used the osc pad must be connected to v dd1 pad. an external oscillator could be used and fed into the osc pin.if an external oscillator is used, it must be always present when ste2004 is not in power down mode. an oscillator out is provided on the oscout pad to cascade two or more drivers. 3.4 master/slave mode ste2004 support the master slave working mode for both control logic and charge pump. this function allows to drive matrix such as 204x65 or 102x130 using two synchronized ste2004 and the internal charge pump of both device. if m/s is connected to vdd1, the driver is configured to work in master mode. when ste2004 is in master mode the vsense_slave pin is disabled and is possible to control the vlcd value using vop bits. the master time generator outputs on fr_out and on osc_out the relevant timing references. if m/s is connected to gnd, the driver is configured to work in slave mode. when ste2004 is in slave mode, the vlcd configuration set by vop registers and the thermal compensation slope set by tc register are neglected. the vlcd value generated is equal to the voltage value present on vsense_slave pin so the slave configuration can follow the master configuration. the only recognized configuration is vop=0 that forces the charge pump to be in off state whatever is the value of vsense_aux. to synchronize the master & slave timing circuits, the slave driver fr_in pad must be connected to mas- ter driver fr_out pad and slave driver osc_in pad must be connected to the master driver osc_out pad (fig. 4). this connection ensure a synchronization at both frame level (r0 on the master is driven together with the slave r0 driver) and at oscillator level (same frame frequency on the master and on the slave). if the synchronization at frame level is not required, fr_in pin must be connected tovdd1 or to vdd1_aux (fig. 5). during power up procesure, master device must be forced to exit from power down before the slave de- vice. to enter in powerdown mode, slave device must be forced in power down state before master de- vice. v dd2 2vlcd ? n4 + () ------------------------ - 200mv +
7/66 ste2004 figure 4. master slave logic connection with frame synchronization figure 5. master slave logic conn ection without frame synchronization 3.5 bias levels to properly drive the lcd, six (including vlcd and vss) different voltage (bias) levels are generated. the ratios among these levels and vlcd, should be selected according to the mux ratio (m). they are established to be (fig. 6): figure 6. bias level generator thus providing an 1/(n+4) ratio, with n calculated from: for m = 65, n = 5 and an 1/9 ratio is set. for m = 49, n =4 and an 1/8 ratio is set. the ste2004 provides three bits (bs0, bs1, bs2) for programming the desired bias ratio as shown below: oscout lr0219 ste2004 vdd1aux ste2004 frout oscin frin oscin frin oscout frout oscout lr022 0 ste2004 vdd1aux ste2004 frout oscin frin oscout frout vdd1aux oscin frin v lcd n3 + n4 + ------------ - v lcd , n2 + n4 + ------------ - v lcd , 2 n4 + ------------ - v lcd , 1 n4 + ------------ - v lcd ,v ss , r v lcd v ss v lcd v lcd v lcd v lcd n + 3 n + 4 r nr r r n + 2 n + 4 2 n + 4 1 n + 4 d00in115 0 nm3 ? =
ste2004 8/66 table 3. the following table bias level for m = 65 and m = 49 are provided: table 4. 3.6 lcd voltage generation the lcd voltage at reference temperature (to = 27c) c an be set using the vop register content according to the following formula: v lcd (t=to) = v lcd o = (ai+v op b) (i=0,1,2) with the following values: note that the three prs values produce three adjacent ranges for vlcd. if the v op register and prs bits are set to zero the internal voltage generator is switched off. the proper value for the vlcd is a function of the liquid crystal threshold voltage (vth) and of the mul- tiplexing rate. a general expression for this is: for mux rate m = 65 the ideal v lcd is: v lcd(to) = 6.85 v th than: bs2 bs1 bs0 n 0007 0016 0105 0114 1003 1012 1101 1110 symbol m = 65 (1/9) m = 49 (1/8) v1 v lcd v lcd v2 8/9*v lcd 7/8*v lcd v3 7/9*v lcd 6/8*v lcd v4 2/9*v v lcd 2/8*v lcd v5 1/9 *v lcd 1/8*v lcd v6 v ss v ss symbol value unit note ao 2.95 v prs = [0;0] a1 6.83 v prs = [0;1] a2 10.71 v prs = [1;0] b 0.0303 v to 2 7 c v lcd 1m + 21 1 m -------- - ? ?? ?? ? ----------------------------------- - v th ? = v op 6.85 v th a i ? ? () 0.03 ---------------------------------------- - =
9/66 ste2004 3.7 temperature coefficients as the viscosity, and therefore the contrast, of the lcd are subject to change with temperature, there's the need to vary the lcd voltage with temperature. ste2004 provides the possibility to change the vlcd in a linear fashion against temperature with eight different temperature coefficient selectable through t2, t1 and t0 bits. only four of them are available through basic instruction set. table 5. table 6. figure 7. finally, the v lcd voltage at a given (t) temperature can be calculated as: v lcd (t) = v lcd o [1 + (t-to) tc] name tc1 tc0 value unit tc0 0 0 -0.0 10 -3 1/ c tc2 0 1 -0.7 10 -3 1/c tc3 1 0 -1.05 10 -3 1/c tc6 1 1 -2.1 10 -3 1/c name t2 t1 t0 value unit tc0 0 0 0 -0.0 10 -3 1/ c tc1 0 0 1 -0.35 10 -3 1/c tc2 0 1 0 -0.7 10 -3 1/c tc3 0 1 1 -1.05 10 -3 1/c tc4 1 0 0 -1.4 10 -3 1/c tc5 1 0 1 -1.75 10 -3 1/c tc6 1 1 0 -2.1 10 -3 1/c tc7 1 1 1 -2.3 10 -3 1/c 00h 01h 02h 03h 04h 05h ?. 7fh 00h 01h 02h 7ch 7dh 7eh 03h 04h 7dh 7eh 7fh 05h ?. 7ch a 1 a 1 b a 0 + b prs = [0;0] prs = [0;1] v o v lcd 00h 01h 02h 03h 04h 7dh 7eh 7fh 05h 7ch prs = [1;0] ?. a 2
ste2004 10/66 3.8 display data ram the ste2004, provides an 102x65 bits static ram to store display data. this is organized into 9 (bank0 to bank8) banks with 102 bytes. one of these banks can be used for icons. ram access is accomplished in either one of the bus interfaces provided (see below). allowed addresses are x0 to x101 (horizontal) and y0 to y8 (vertical). when writing to ram, four addressing mode are provided: normal horizontal (mx=0 and v=0), having the column with address x= 0 located on the left of the mem- ory map. the x pointer is increased after each byte written. after the last column address (x=x-car- riage), y address pointer is set to jump to the following bank and x restarts from x=0. (fig. 8) normal vertical (mx=0 and v=1), having the column with address x= 0 located on the left of the memory map. the y pointer is increased after each byte written. after the last y bank address (y=y-carriage), x address pointer is set to jump to next column and y restarts from y=0 (fig. 9). mirrored horizontal (mx=1 and v=0), having the column with address x= 0 located on the right of the memory map. the x pointer is increased after each byte written. after the last column address (x=x- carriage), y address pointer is set to jump to the next bank and x restarts from x=0 (fig. 10). mirrored vertical (mx=1 and v=1), having the column with address x= 0 located on the right of the mem- ory map. the y pointer is increased after each byte written. after the last y bank address (y=y-car- riage), the x pointer is set to jump to next column and y restarts from y=0 (fig. 11). after the last allowed address (x;y)=(x-carriage; y-carriage), the address pointers always jump to the cell with address (x;y) = (0;0) (fig. 12,13,14 & 15). data bytes in the memory could have the msb either on top (d0 = 0, fig.16) or on the bottom (d0=1, fig. 17). the ste2004 provides also means to alter the normal output addressing. a mirroring of the display along the x axis is enabled setting to a logic one my bit.this function doesn't affect the content of the memory map. it is only related to the memory read process. when icon mode=1 the icon row is not mirrored with my and is not scrolled. when icon mode=0 the icon row is like an other graphic line and is mirrored and scrolled. three are the multiplex ratio available when the partial display mode is disabled (mux 33, mux 49 and mux 65). only a subset of writable rows are output on row drivers in mux 33,49 & 65 mode. when y-carriagemux/8 lines only 33, 49 lines are visualized. it is possible to select which lines of ddram are connected on the output drivers using the scrolling func- tion (range: 0-y-carriage*8). when y-carriage>mux/8 lines, the icon row is moved in ddram to the first row of the bank correspondant to y-carriage return value, being always connected on the same output driver. when my=0 , the icon row is output on r64 in mux 65 mode, on r56 in mux 49 and on r48 in mux33. when my=1 , and icon mode=0 , the icon row is output on r0 whatever is the mux rate.
11/66 ste2004 figure 8. automatic data ram writing sequence with v=0 and data ram normal format (mx=0) 1 figure 9. automatic data ram writing sequence with v=1 and data ram normal format (mx=0) 1 figure 10. automatic data ram writing sequence with v=0 and data ram mirrored format (mx=1) 1 figure 11. automatic data ram writing sequence with v=1 and data ram mirrored format (mx=1) 1 1. x carriage=101; y-carriage = 8 0123 9899100101 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 lr0049 01 0123 9899100101 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 lr0050 3210 98 99 100 101 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 lr0051 10 32 98 99 100 101 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 lr005 2
ste2004 12/66 figure 12. automatic data ram writing sequence with x-y carriage return (v=0; mx=0) figure 13. automatic data ram writing sequence with x-y carriage return (v=1; mx=0) figure 14. automatic data ram writing sequence with x-y carriage return (v=0; mx=1) figure 15. automatic data ram writing sequence with x-y carriage return (v=1; mx=1) bank 0 bank 1 bank 2 y carr bank 7 bank 8 0123 98 99 100 101 x carr lr005 3 bank 0 bank 1 bank 2 y carr bank 7 bank 8 0123 x carr 98 99 100 101 lr005 4 bank 0 bank 1 bank 2 y carr bank 7 bank 8 0 1 2 3 98 99 100 101 x carr lr0055 bank 0 bank 1 bank 2 y carr bank 7 bank 8 0 1 2 3 x carr 98 99 100 101 lr005 6
13/66 ste2004 figure 16. data ram byte organization with d0 = 0 figure 17. data ram byte organization with d0 = 1 0 msb lsb 1 2 3 98 99 100 101 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 lr005 7 lsb msb 0123 9899100101 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 lr005 8
ste2004 14/66 figure 18. memory rows vs. row drivers mapping icon_mode=1 and mux 65 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r63 r62 r61 r60 r59 r58 r57 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r31 r30 r29 r28 r27 r26 r25 r24 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 r63 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r64 r64 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0268
15/66 ste2004 figure 19. memory rows vs. row drivers mapping icon_mode=0 and mux 65 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r63 r62 r61 r60 r59 r58 r57 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r31 r30 r29 r28 r27 r26 r25 r24 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 r63 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r64 r64 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 40h lr0269
ste2004 16/66 figure 20. memory rows vs. row drivers mapping icon_mode=1, y-carriage<=6 and mux 49 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r49 r50 r51 r52 r53 r54 r55 r56 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0270
17/66 ste2004 figure 21. memory rows vs. row drivers mapping icon_mode=0, y-carriage<=6 and mux 49 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r49 r50 r51 r52 r53 r54 r55 r56 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0271
ste2004 18/66 figure 22. memory rows vs. row drivers mapping icon_mode=0, y-carriage=7, scrolling pointer>07h and mux 49 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r49 r50 r51 r52 r53 r54 r55 r56 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0275
19/66 ste2004 figure 23. memory rows vs. row drivers mapping icon_mode=1, y-carriage=7, scrolling pointer>07h and mux 49 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0276 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output r48 r49 r50 r51 r52 r53 r54 r55 r56 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0
ste2004 20/66 figure 24. memory rows vs. row drivers mapping icon_mode=1, y-carriage=8, scrolling pointer<10h and mux 49 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r49 r50 r51 r52 r53 r54 r55 r56 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0273
21/66 ste2004 figure 25. memory rows vs. row drivers mapping icon_mode=0, y-carriage=8, scrolling pointer<10h and mux 49 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r56 r55 r54 r53 r52 r51 r50 r49 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 r23 r22 r21 r20 r19 r18 r17 r16 normal direction reverse direction row output r48 r49 r50 r51 r52 r53 r54 r55 r56 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 lr0274
ste2004 22/66 figure 26. memory rows vs. row drivers mapping icon_mode=1, y-carriage<=4 and mux33 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0272
23/66 ste2004 figure 27. memory rows vs. row drivers mapping icon_mode=0, y-carriage<=4 and mux 33 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 0 0 0 0 0 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 0 1 0 0 0 1 1 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 0 1 1 0 0 1 1 1 page 0 page 1 page 2 page 3 page 6 page 7 x address 00h 01h 02h 06h 03h 04h 05h 5fh 60h 61h 65h 62h 63h 64h 00h y address d3 d a t a d2 d1 d0 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r47 r46 r45 r44 r43 r42 r41 r40 r39 r38 r37 r36 r35 r34 r33 r32 normal direction reverse direction row output c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 col output normal direction reverse direction line address scrolling pointer d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 0 page 4 20h 21h 22h 23h 24h 25h 26h 27h d5 d4 d7 d6 d1 d0 d3 d2 0 1 0 1 page 5 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh page 8 1 0 0 0 d0 r48 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 y-carriage c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l 0 101 1 2 3 4 5 6 100 99 98 97 96 95 c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l c o l lr0272
ste2004 24/66 figure 28. row drivers vs. lcd panel interconnection in mux65 mode figure 29. row drivers vs. lcd panel interconnection in mux49 mode mux 65 ste2004 column drivers row drivers row drivers icon r 2 r 1 r 0 r 4 r 3 r 5 r 6 r10 r 9 r 8 r12 r11 r 7 r13 r14 r18 r17 r16 r20 r19 r15 r21 r22 r26 r25 r24 r28 r27 r23 r29 r30 r31 r35 r34 r33 r37 r36 r32 r38 r39 r43 r42 r41 r45 r44 r40 r46 r47 r51 r50 r49 r53 r52 r48 r54 r55 r59 r58 r57 r61 r60 r56 r62 r63 r64 lr0109 mux 49 ste2004 column drivers row drivers row drivers icon r 2 r 1 r 0 r 4 r 3 r 5 r 6 r10 r 9 r 8 r12 r11 r 7 r13 r14 r18 r17 r16 r20 r19 r15 r21 r22 r26 r25 r24 r28 r27 r23 r29 r30 r31 r35 r34 r33 r37 r36 r32 r38 r39 r43 r42 r41 r45 r44 r40 r46 r47 r51 r50 r49 r53 r52 r48 r54 r55 r59 r58 r57 r61 r60 r56 r62 r63 r64 lr0108
25/66 ste2004 figure 30. row drivers vs. lcd panel interconnection in mux33 mode mux 33 ste2004 column drivers row drivers row drivers icon r 2 r 1 r 0 r 4 r 3 r 5 r 6 r10 r 9 r 8 r12 r11 r 7 r13 r14 r18 r17 r16 r20 r19 r15 r21 r22 r26 r25 r24 r28 r27 r23 r29 r30 r31 r35 r34 r33 r37 r36 r32 r38 r39 r43 r42 r41 r45 r44 r40 r46 r47 r51 r50 r49 r53 r52 r48 r54 r55 r59 r58 r57 r61 r60 r56 r62 r63 r64 lr0107
ste2004 26/66 4 bus interfaces to provide the widest flexibility and ease of use the ste2004 features six different methods for interfacing the host controller. to select the desired interface the sel1, sel2 and sel3 pads need to be connected to a logic low (connect to gnd) or a logic high (connect to vdd). all the i/o pins of the unused inter- faces must be connected to gnd. all interfaces are working while the ste2004 is in power down. table 7. 4.1 i 2 c interface the i 2 c interface is a fully complying i 2 c bus specification, selectable to work in both fast (400khz clock) and high speed mode (3.4mhz). this bus is intended for communication between different ics. it consists of two lines: one bi-directional for data signals (sda) and one for clock signals (scl). both the sda and scl lines must be connected to a positive supply voltage via an active or passive pull-up. the following protocol has been defined: - data transfer may be initiated only when the bus is not busy. - during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, de- fine the start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock signal is high, defines the stop condition. data valid: the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited. the information is transmit- ted byte-wide and each receiver acknowledges with the ninth bit. by definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". the device that controls the message is called "master". the devices that are controlled by the master are called "slaves" acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked sel3 sel2 sel1 interface note 000 i 2 c read and write; fast and high speed mode 0 0 1 spi 4 lines 8 bit read and write 0 1 0 spi 3 lines 8 bit read and write 0 1 1 serial 3 lines 9 bit read and write 1 0 0 parallel 8080-series read and write 1 0 1 parallel 68000-series read and write
27/66 ste2004 out of the slave transmitter. the device that acknowledges has to pull down the sda_in line during the acknowledge clock pulse. of course, setup and hold time must be taken into account. a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition. connecting sda_in and sda_out together the sda line become the standard data line. having the ac- knowledge output (sdaout) separated from the serial data line is advantageous in chip-on-glass (cog) applications. in cog applications where the track resistance from the sdaout pad to the system sda line can be significant, a potential divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track resistance. it is possible that during the acknowledge cycle the ste2004 will not be able to create a valid logic 0 level. by splitting the sda input from the output the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is nec- essary to minimize the track resistance from the sdack pad to the system sda line to guarantee a valid low level. to be compliant with the i 2 c-bus hs-mode specification the ste2004 is able to detect the special se- quence "s00001xxx". after this sequence no acknowledge pulse is generated. since no internal modification are applied to work in hs-mode, the device is able to work in hs-mode with- out detecting the master code. figure 31. bit transfer and start,stop conditions definition figure 32. acknowledgment on the i 2 c-bus 4.1.1 communication protocol the ste2004 is an i 2 c slave. the access to the device is bi-directional since data write and status read are allowed. four are the device addresses available for the device. all have in common the first 5 bits (01111). the two least significant bit of the slave address are set by connecting the sa0 and sa1 inputs to a logic 0 or to a logic 1. to start the communication between the bus master and the slave lcd driver, the master must initiate a start condition. following this, the master sends an 8-bit byte, on the sda bus line (most significant bit first). this consists of the 7-bit device select code, and the 1-bit read/write designator (r/w ). all slaves with the corresponding address acknowledge in parallel, all the others will ignore the i 2 c-bus transfer. data line stable data valid change of data allowed start condition stop condition clock data lr006 9 start clock pulse for acknowledgement data output by receiver sclk from master data output by transmitter lr007 0 1 msb lsb 289
ste2004 28/66 4.1.2 writing mode. if the r/w bit is set to logic 0 the ste2004 is set to be a receiver. after the slaves acknowledge one or more command word follows to define the status of the device. a command word is composed by three bytes. the first is a control byte which defines the co and d/c values, the second and third are data bytes. the co bit is the command msb and defines if after this com- mand will follow two data bytes and an other command word or if will follow a stream of data (co = 1 com- mand word, co = 0 stream of data). the d/c bit defines whether the data byte is a command or ram data (d/c = 1 ram data, d/c = 0 command). if co =1 and d/c = 0 the incoming data byte is decoded as a command, and if co =1 and d/c =1, the following data byte will be stored in the data ram at the location specified by the data pointer. every byte of a command word must be acknowledged by all addressed units. after the last control byte, if d/c is set to a logic 1 the incoming data bytes are stored inside the ste2004 display ram starting at the address specified by the data pointer. the data pointer is automatically up- dated after every byte written and in the end points to the last ram location written. every byte must be acknowledged by all addressed units. 4.1.3 reading mode. if the r/w bit is set to logic 1 the chip will output data immediately after the slave address. if the d/c bit during the last write access, is set to a logic 0, the byte read is the status byte. figure 33. communication protocol 4.2 serial interfaces ste2004 can feature three different serial synchronized interfaces with the host controller. it is possible to select a 3-lines spi, a 4-lines spi or 3-line 9 bits serial interface. 4.2.1 4-lines spi interface ste2004 4-lines serial interface is a bidirectional link between the display driver and the application supervisor. it consists of four lines: one/two for data signals (sdi n, sout), one for clock signals (sclk), one for the pe- ripheral enable (cs ) and one for mode selection (sd/c ). the serial interface is active only if the cs line is set to a logic 0. when cs line is high the serial peripheral power consumption is zero. while cs pin is high the serial interface is kept in reset. the ste2004 is always a slave on the bus and receive the communication clock on the sclk pin from the mas- ter. information are exchanged byte-wide. during data transfer, the data line is sampled on the positive sclk edge. sd/c line status indicates whether the byte is a command (sd/c =0) or a data (sd/c =1); sd/c line is read on lr0008 s s 01111 0 a0a driver ack write mode read mode r/w r/w slave address co driver ack command word control byte msb........lsb co last n> 0 byte driver ack driver ack driver ack a 1 dc control byte data byte a dc control byte a 0 data byte a p s s 01111 0 a1a driver ack master ack p driver slave address s 01111 0 a r / w control byte c o d c 000 a s 1 a s 1 a s 1 a h [1] h [0] h e
29/66 ste2004 the eighth sclk clock pulse during every byte transfer. if cs stays low after the last bit of a command/data byte, the serial interface expects the msb of the next byte at the next sclk positive edge. a reset pulse on res pin interrupts the transmission. no data is written into the data ram and all the internal registers are cleared. if cs is low after the positive edge of res , the serial interface is ready to receive data. throughout sdout can be read the driver i 2 c slave address or the status byte. the command sequence that allows to read i 2 c slave address or status byte is reported in fig. 34 & 35. sdout is in high impedance in steady state and during data write. it is possible to short circuit sdout and sdin and read i2c address or status byte without any additional lines. figure 34. 4-lines serial bus protocol - one byte transmission figure 35. 4-lines serial bus protocol - several byte transmission figure 36. 4-lines serial bus protocol - i2c address or status byte read msb lsb d/c cs sdin sclk lr0071 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 d/c cs sdin sclk lr0072 db7 db6 db5 db4 db3 db2 db1 db0 don't care cs sdin sclk high-z db1 db0 high-z don't care don't care don't care don't care don't care don't care don't care command write data read db7 db6 db5 db4 db3 db2 sdout high-z db1 db0 high-z db7 db6 db5 db4 db3 db2 id number status byte lr00076 d/c
ste2004 30/66 figure 37. 4-lines spi reading sequence 4.2.2 3-lines spi interface the ste2004 3-lines serial interface is a bidirectional link between the display driver and the application supervisor. it consists of three lines: one/two for data signals (sdin,sdout), one for clock signals (sclk) and one for peripheral enable (cs ). if the r/w bit is set to logic 0 the ste2004 is set to be a receiver. one or more command word follows to define the status of the device. a command word is composed by two bytes. the first is a control byte which defines co, d/c , r/w h[1;0] and he values, the second is a data byte (fig 39). the co bit is the command msb and defines if after this command will follow one data byte and an other command word or if will follow a stream of commands or a steam of ddram data (co = 1 command word, co = 0 stream of data). the d/c bit defines whether the data byte is a command or ddram data (d/c = 1 ram data, d/c = 0 command). the h[1;0] bits define the instruction set page if he bit =1. if he bit is set to 0 h[1;0] values are neglected and it is possible to update the instruction set page number using only the related instruction in the instruction set. if co =1 and d/c = 0 the incoming data byte is decoded as a command, and if co =1 and d/c =1, the following data byte will be stored in the data ram at the location specified by the data pointer. after the last control byte, if d/c is set to a logic 1 the incoming data bytes are stored inside the ste2004 display data ram starting at the address specified by the data pointer. the data pointer is automatically updated after every byte written and in the end points to the last ram location written. throughout sdout can be read the driver i 2 c slave address or the status byte. the command sequence that allows to read i 2 c slave address or the status byte is reported in fig. 39 & 40. if the r bit is set to logic 0 and d/c=0, the i 2 c slave address is read; if the r bit is set to logic 1 and d/ c=0, the the i 2 c slave address is read sdout is in high impedance in steady state and during data write. it is possible to short circuit sdout and sdin and read i 2 c address or status byte without any additional line. reading sequence write a "00000000" instruction source 8 pulses on sclk and read the id number or the status byte on sdout end of reading sequence sdout buffer configured in high impedence lr0078 sdout buffer becomes active (low impedence) 1 note: 1) these data are not read by the display diver 2) sdin and sdout can be short circuited if the processor can configure serial output buffers in high impedence during data read .
31/66 ste2004 figure 38. 3-lines serial interface protocol in writing mode figure 39. 3-lines spi interface protocol in reading mode write mode command word control byte msb........lsb co last n> 0 byte data byte control byte 0 data byte control byte c o d c 00 h [1] control byte r / w h [0] h e data byte control byte co 1 0 data byte control byte msb........lsb last n> 0 byte data byte = command if d/c=0 data byte = ddram data if d/c=1 data byte control byte 0 data byte control byte msb........lsb last n> 0 byte 0 1 transferred only commands transferred only ddram data lr0002 db7 db6 db5 db4 db3 db2 db1 db0 don't care cs sdin sclk high-z db1 db0 high-z don't care don't care don't care don't care don't care don't care don't care command write data read db7 db6 db5 db4 db3 db2 co=1 d/c=0 "command" r/w=1 "read" sdout high-z db1 db0 high-z db7 db6 db5 db4 db3 db2 id-number status byte lr0077
ste2004 32/66 figure 40. 3-lines spi reading sequence 4.2.3 3-lines 9 bits serial interface the ste2004 3-lines serial interface is a bidirectional link between the display driver and the application supervisor. it consists of three lines: one/two for data signals (sdin, sdout), one for clock signals (sclk) and one for peripheral enable (cs ). the serial interface is active only if the cs line is set to a logic 0. when cs line is high the serial peripheral power consumption is zero. while cs pin is high the serial interface is kept in reset. the ste2004 is always a slave on the bus and receive the communication clock on the sclk pin from the master. information are exchanged word-wide. the word is composed by 9 bit. the first bit is named sd/c and indicates whether the following byte is a command (sd/c =0) or data byte (sd/c =1). during data trans- fer, the data line is sampled on the positive sclk edge. if cs stays low after the last bit of a command/data byte, the serial interface expects the sd/c bit of the next word at the next sclk positive edge. a reset pulse on res pin interrupts the transmission. no data is written into the data ram and all the in- ternal registers are cleared. if cs is low after the positive edge of res , the serial interface is ready to receive data. throughout sdout can be read only the driver i 2 c slave address or the status byte. the command sequence that allows to read i 2 c slave address or status byte is reported in fig. 43 & 44. sdout is in high impedance in steady state and during data write. it is possible to short circuit sdout and sdin and read i 2 c address or status byte without any additional line. reading sequence set co bit =1, d/c bit =0 r/w bit =1 source 8 pulses on sclk and read the id-number or the status byte on sdout end of reading sequence sdout buffer configured in high impedence lr0079 sdout buffer become active (low impedence) 1 note: 1) these data are not read by the display diver 2) sdin and sdout can be short circuited if the processor can configure serial output buffers in high impedence during data read .
33/66 ste2004 figure 41. 3-lines serial bus protocol - one byte transmission figure 42. 3-lines serial bus protocol - several byte transmission figure 43. 3-lines serial interface protocol in reading mode figure 44. 3-lines serial reading sequence msb sd/c cs sdin sclk lr0073 lsb db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 d/c cs sdin sclk lr007 4 d/c db7 db6 d/c db7 db6 db5 db4 db3 db2 db1 db0 cs sdin sclk high-z db1 db0 high-z don't care don't care don't care don't care don't care don't care don't care command write data read db7 db6 db5 db4 db3 db2 sd/c sdout high-z db1 db0 high-z db7 db6 db5 db4 db3 db2 id-number status byte don't care lr0075 db7 sd/c reading sequence write a "00000000" instruction source 9 pulses on sclk and read the id number or the status byte on sdout end of reading sequence sdout buffer configured in high impedence lr0080 sdout buffer becomes active (low impedence) 1 note: 1) these data are not read by the display diver 2) sdin and sdout can be short circuited if the processor can configure serial output buffers in high impedence during data read .
ste2004 34/66 4.3 parallel interface the ste2004 selectable parallel interfaces are 68000-series and 8080-series. they are both an 8-bits bi- directional link between the display driver and the application supervisor. throughout both parallel interfaces can be read the i 2 c driver slave address or the status byte. 4.3.1 68000-series parallel interface if cs is low after the positive edge of res , the 68000 parallel interface is ready to receive or transmit data. while cs pin is high the 68000 parallel interface is kept in reset. 4.3.2 write mode if r/w line is set to 0 data are latched on e falling edge. 4.3.3 read mode when r/w line is set to 1, data are output on d0-d7 bus on e rising edge. data bus is set in high imped- ance mode when e is set to logic 0. accordingly to r bit value i2c address or status byte is output on d0-d7 bus. figure 45. 68000-series parallel interface protocol - one byte transmission figure 46. 68000-series parallel interface bus protocol - several bytes transmission d/c cs d0 to d7 e r/w lr0004 d/c cs d0 to d7 e r/w lr0081
35/66 ste2004 figure 47. 68000-series parallel interface protocol in reading mode figure 48. 68000-series parallel interface protocol in reading mode (several bytes) 4.3.4 8080-series parallel interface if cs is low after the positive edge of res , the 8080 parallel interface is ready to receive or transmit data. while cs pin is high the 8080 parallel interface is kept in reset. write mode data are latched on wr rising edge. read mode data are output on d0-d7 bus on rd rising edge. data bus is set in high impedance mode when rd is set to logic 1. accordingly to r bit value i2c address or status byte is output on d0-d7 bus. figure 49. 8080-series parallel bus protocol - one byte transmission d/c cs d0 to d7 e r/w lr008 2 d/c cs d0 to d7 e r/w lr0046 note 1) data bus is configured in high impedence mode after evry rd rising edge 2) always the same data is output on d0-d7 d/c cs d0 to d7 wr rd lr008 3
ste2004 36/66 figure 50. 8080-series parallel bus protocol - several bytes transmission figure 51. 8080-series parallel interface protocol in reading mode figure 52. 8080-series parallel interface protocol in reading mode (several bytes) d/c cs wr d0 to d7 rd lr008 4 d/c cs rd d0 to d7 wr lr008 5 d/c cs rd d0 to d7 wr note 1) data bus is configured in high impedence mode after every rd rising edge 2) always the same data is output on d0-d7 lr0045
37/66 ste2004 5 instruction set two different instructions formats are provided: - with d/c set to low : commands are sent to the control circuitry. - with d/c set to high : the data ram is addressed. two different instruction set are embedded: the ste2001-like instruction set and the extended instruction set. to select the ste2001-like instruction set the ext pad has to be connected to a logic low (connect to gnd). to select the he extended instruction the ext pad has to be connected to a logic high (connect to vdd1). the instructions have the syntax summarized in table 1 (basic-set) and table 2 (extended set) 5.1 reset (res ) at power-on, all internal registers are configured with the default value. the ram content is not defined. a reset pulse on res pad (active low) re-initialize the internal registers content (see tables 3,4,5,&6). every on-going communication with the host controller is interrupted, applying a reset pulse. after the power-on, the software reset instruction can be used to re-load the reset configuration into the internal registers. the default configurations is: a memory blank instruction can be executed to clear the ddram content. 5.2 p ower down (pd = 1) when at power down, all lcd outputs are kept at v ss (display off). bias generator and v lcd generator are off (v lcdout output is discharged to v ss , and then is possible to disconnect v lcdout ). the internal oscillator is in off state. an external clock can be provided. the ram contents is not cleared. 5.3 memory blanking procedure this instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly gener- ated in memory when starting up the device. this instruction substitutes (102x8) single "write" instruc- tions. it is possible to program "memory blanking procedure" only under the following conditions: - pd bit = 0 no instruction can be programmed for a period equivalent to 102x8 internal write cycles (102x8x1/fclock). the start of memory blanking procedure will be between one and two fclock cycles from the last active edge (e fallig edge for the parallel interface, last sclk rising edge for the serial & spi interfaces, last scl rising edge for the i 2 c interface). 5.4 checker board procedure this instruction allows to fill the memory with "checker-board" pattern. it is mainly intended to developers, who can now simply obtain complex module test configuration by means of a single instruction. it is pos- sible to program "checker board procedure" only under the following conditions: - pd bit = 0 - horizontal addressing (v = 0) - normal instruction set (h[1:0] = 0) - normal display (mx = my = 0) - display blank (e = d = 0) - address counter x[6: 0] = 0 and y[4: 0] = 0 - temperature coefficient (tc[1: 0] = 0) - bias system (bs[2: 0] = 0) - multiplexing ratio (m[1:0]=0 - mux 65) - frame rate (fr[1:0]=?75hz?) - power down (pd = 1) - dual partial display disabled (pe=0) - v op =0 - y-carriage=8 - x-carriage=101
ste2004 38/66 no instruction can be programmed for a period equivalent to 102x8 internal write cycles (102x8x1/fclock). the start of checker-board procedure will be between one and two fclock cycles from the last active edge (e falling edge for the parallel interface, last sclk rising edge for the serial & spi interfaces, last scl rising edge for the i 2 c interface). 5.5 scrolling function the ste2004 can scroll the graphics display in units of raster-rows. the scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. the scroll function doesn't affect the data ram content. it is only related to the visualization process. the information output on the drivers is related to the row reading sequence (the 1st row read is output on r0, the 2nd on r1 and so on). scrolling means reading the matrix starting from a row that is sequentially in- creased or decreased. after every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. the offset range changes in accordance with mux rate. after 64th/65th scrolling commands in mux 65 mode, or after the 48th/49th scrolling com- mands in mux 49 mode, or after 32nd/33rd scrolling command in mux 33 mode, the offset between the memory address and the memory scanning pointer is again zero (cyclic scrolling). a reset scrolling pointer instruction can be executed to force to zero the offset between the memory ad- dress and the memory scanning pointer if icon mode =1, the icon row is not scrolled. if icon mode=0 the last row is like a general purpose row and it is scrolled as other lines. i f the dir bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. if the dir bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up. table 8. 5.6 dual partial display if the pe bit is set to a logic one the dual partial display mode is enabled. eight partial display modes are available. the offset of the two partial display zones is row by row pro- grammable. the icon row is accessed last in each partial display frame. two sets of register for the hv-generator parameters are provided (prs[1:0], vop[6:0], bs[2:0], cp[2:0].). this allows switching from normal mode to partial display mode only with one instruction. the hv gener- ator is automatically re configured using the parameters related to the enabled mode. the parameters of the two sets of registers with the same function are located in the same position of the instruction set. the registers related to the normal mode are accessible when normal mode (pe=0) is selected, the others are accessible when the partial display mode is enabled (pe=1). to setup prs[1:0], vop[6:0], bs[2:0], cp[2:0] values the instruction flow proposed in fig. 54 must be followed. to setup partial display sectors start address and partial display mode no particular instruction flow has to be followed. mux rate icon mode description icon row driver with my=0 mux 33 1 icon row not scrooled r48 mux 33 0 33 line graphic matrix r48 mux 49 1 icon row not scrooled r56 mux 49 0 49 line graphic matrix r56 mux 65 1 icon row not scrooled r64 mux 65 0 65 line graphic matrix r64
39/66 ste2004 figure 53. dual partial display enabling instruction flow figure 54. dual partial display mode configuration or duty change table 9. partial display configurations pdc 2 pdc 1 pdc 0 section 1 section2 reset state 0 0 0 0 8 + icon row 0 0 1 8 0 + icon row 0 1 0 8 8 + icon row 0 1 1 0 16 + icon row 000 1 0 0 16 0 + icon row 1 0 1 8 16 + icon row 1 1 0 16 8 + icon row 1 1 1 16 16 + icon row enable dual partial display end of enabling dual partial display set pe=1 optional1 set 1st sector start address set 2nd sector start address setup partial display configuration set driver in power down(pd=1) set driver in partial display mode (pe=1) end of partial display config. set prs[1:0], vop[6:0], bs[2:0], cp[2:0] for partial display operation set driver in normal mode (pe=0) set partial display configuration (pdc[2:0]) set 1st sector start address set 2nd sector start address optional
ste2004 40/66 6id-number the ste2004 allows to program a driver identification number (id-number). this make possible to easily manage on one platform more than one lcd module with different configuration parameters. four are the device id-numbers programmable: 00111100, 00111101, 0011110 & 0011111. all have in common the first 6 bits (001111). the two least significant bit could be set connecting the sa0 and sa1 inputs to a vss or vdd1. the driver id-number can be read through all communication interfaces. the way to read-out the id-num- ber changes according the interface selected. the readout protocol for each interface is described in the bus interfaces paragraph. table 10. ste2001/2-like instruction set instruction d/c r / w description b7 b6 b5 b4 b3 b2 b1 b0 h=0 or h=1 read commnad0000000000 read i 2 c address or status byte (with 3-lines serial & 4-lines spi only) function set 0 0 0 0 1 mx my pd v h[0] power down management; entry mode; status byte 0 1 pd bsy 0 demxmydo (i 2 c interface only) id code 0 1 0 01 111id1id0 write data 1 0 d7 d6 d5 d4 d3 d2 d1 d0 writes data to ram h=0 memory blank 0000000001starts memory blank procedure scroll 000000001dir scrolls by one row up or down v lcd range setting 000000010 prs [0] v ldc programming range selection display control 0000001d0e select display configuration set cp factor 0000010s2s1s0 charge pump multiplication factor set ram y 0 0 0 1 0 0 y3 y2 y1 y0 set horizontal (y) ram address set ram x 0 0 1 x6x5x4x3x2x1x0 set vertical (x) ram address h=1 checker board 0000000001starts checker board procedure duty 000000001 mux selects duty factor tc select 00000001tc1tc0 set temperature coefficient for v ldc data order 0000001do 00 bias ratios 0000010bs2bs1bs0 set desired bias ratios reserved 00 01xxxxxx not to be used set v op 001 op6 op5 op4 op3 op2 op1 op0 v op register write instruction
41/66 ste2004 table 11. extended instruction set instruction d/c r/w description b7 b6 b5 b4 b3 b2 b1 b0 h independent instructions read command0000000000 read i 2 c address or status byte (with 3-lines serial & 4-lines spi only) 00001mxmypdh[1]h[0] page selector, power down management; entry mode status byte 0 1 pd bsy 0 demxmydo id code 0 1 0 01 111id1id0 write data 1 0 d7 d6 d5 d4 d3 d2 d1 d0 writes data to ram h=[0;0] ram commands memory blank 0000000001 starts memory blank procedure scroll 000000001dir scrolls by one row up or down v lcd range setting 00000001 prs [1] prs [0] v ldc programming range selection display control 0000001d0e select display configuration set cp factor 0000010s2s1s0 charge pump multiplication factor set ram y 000100y3y2y1y0 set horizontal (y) ram address set ram x 0 0 1 x6x5x4x3x2x1x0 set vertical (x) ram address h=[0;1] checker board 0000000001 starts checker board procedure 000000001v vertical addressing mode tc select 00000001tc1tc0 set temperature coefficient for v ldc data order 0000001do00 msb position bias ratios 0000010bs2bs1bs0 set desired bias ratios read mode, 000100r000 set v op 001 op6 op5 op4 op3 op2 op1 op0 v op register write instruction h=[1;0] driver control 0000000001 software reset display control 000000001pe partial enable 00000001fr1fr0 frame rate control 0000001 0 m[1] m[0] mux ratio partial mode 0000010 pdc 2 pdc 1 pdc 0 partial display config 0001 pd y 5 pd y 4 pd y 3 pd y 2 pd y 1 pd y 0 1 st sector start address 001 pd y 6 pd y 5 pd y 4 pd y 3 pd y 2 pd y 1 pd y 0 2 nd sector start address h=[1;1] 0000000001 scrolling pointer reset 000000001 x not used 00000001xx not used 0000001t2t1t0 set temperature coefficient for v ldc 000001 nw3nw2nw1nw0 n-line inversion 000100 yc-3 yc-2 yc-1 yc-0 y-carriage return 001 xc-6 xc-5 xc-4 xc-3 xc-2 xc-1 xc-0 x carriage return
ste2004 42/66 table 12. explanations of table 3 & 4 symbols table 13. page selection table 14. display mode table 15. frame rate control table 16. vlcd range selection bit 0 1 reset state dir scroll by one down scroll by one up h[0] select page 0 select page 1 0 pd device fully working device in power down 1 v horizontal addressing vertical addressing 0 mx normal x axis addressing x axis address is mirrored. 0 my image is displayed not vertically mirrored image is displayed vertically mirrored 0 do msb on top msb on bottom 0 pe partial display disabled partial display enabled 0 mux mux 65 mode mux 33 mode 0 r read id-number / i2c address read status byte 0 h[1] h[0] description reset state 00page 0 0 1 page 1 page 0 10page 2 11page 3 d e description reset state 0 0 display blank 0 1 all display segments on e=0 1 0 normal mode d=0 1 1 inverse video mode fr[1] fr[0] description reset state 00 65hz 0 1 70hz 75hz 10 75hz 11 80hz prs[1] prs[0] description reset state 0 0 2.94 0 1 6.78 10 10.62 11 10.62
43/66 ste2004 table 17. multiplexing ratio table 18. temperature coefficient table 19. table 20. charge pump multiplication factor m[1] m[0] description reset state 00 49 0 1 65 01 10 33 1 1 not allowed t2 t1 t0 description reset state 0 0 0 vlcd temperature coefficient 0 0 0 1 vlcd temperature coefficient 1 0 1 0 vlcd temperature coefficient 2 0 1 1 vlcd temperature coefficient 3 000 1 0 0 vlcd temperature coefficient 4 1 0 1 vlcd temperature coefficient 5 1 1 0 vlcd temperature coefficient 6 1 1 1 vlcd temperature coefficient 7 tc1 tc0 description reset state 0 0 vlcd temperature coefficient 0 0 1 vlcd temperature coefficient 2 00 0 1 vlcd temperature coefficient 3 1 1 vlcd temperature coefficient 6 cp2 cp1 cp0 description reset state 000 multiplication factor x2 0 0 1 multiplication factor x3 0 1 0 multiplication factor x4 0 1 1 multiplication factor x5 000 100 not used 101 not used 110 not used 111 automatic
ste2004 44/66 table 21. bias ratio table 22. y carriage return register table 23. partial display configuration table 24. n-line inversion bs2 bs1 bs0 description reset state 0 0 0 bias ratio equal to 7 0 0 1 bias ratio equal to 6 0 1 0 bias ratio equal to 5 0 1 1 bias ratio equal to 4 000 1 0 0 bias ratio equal to 3 1 0 1 bias ratio equal to 2 1 1 0 bias ratio equal to 1 1 1 1 bias ratio equal to 0 y-c[3] y-c[2] y-c[1] y-c[0] description reset state 0 0 0 0 y-carriage =0 0 0 0 1 y-carriage =1 0 0 1 0 y-carriage =2 0 0 1 1 y-carriage =3 1000 0 1 0 0 y-carriage =4 .... 0 1 1 0 y-carriage =6 0 1 1 1 y-carriage =7 1 0 0 0 y-carriage =8 pd2 pd1 pd0 section 1 section2 reset state 0 0 0 0 8 + icon row 0 0 1 8 0 + icon row 0 1 0 8 8 + icon row 0 1 1 0 16 + icon row 000 1 0 0 16 0 + icon row 1 0 1 8 16 + icon row 1 1 0 16 8 + icon row 1 1 1 16 16 + icon row nw3 nw2 nw1 nw0 description reset state 0000 0-line inversion (frame inversion) 0001 2-line inversion 0010 3-line inversion 0 0 1 1 4-line inversion 0000 :::: : 1110 15-line inversion 1111 16-line inversion
45/66 ste2004 figure 55. i2c interface interconnection in master/ slave mode figure 56. i3-lines spi & 3-lines serial inte rfaces interconnection in master slave mode figure 57. 4-lines spi interface interconnection in master slave mode sdain lr0214 ste2004 ste2004 scl sdaout note: master and slave i2c aaddress must be different sdain scl sdaout scl sda res res res sdout lr021 5 ste2004 ste2004 sclk sdin sdout sclk sdin sclk slave cs master cs sd cs res cs res res sdout lr021 6 ste2004 ste2004 sclk sdin sdout sclk sdin sclk slave cs master cs sd d/c cs res d/c cs res res d/c
ste2004 46/66 figure 58. 8080-series & 68000-series interface interconnection in master slave mode figure 59. host processor interconnection with i2c interface lr021 7 ste2004 ste2004 d7-d0 res slave cs master cs d7-d0 8 lines 8 lines e-wr rw-rd d/c cs res d7-d0 e-wr rw-rd d/c cs res e-wr rw-rd d/c vdd1 / vssaux vdd1 / vssaux digital vdd ste2004 p d/c cs res d0 d1 d2 d3 d4 d5 d6 d7 vssaux vssaux e - wr r/w - rd vsense_slave vdd1_aux osc_in fr_in sdin-sdain sdout sdaout sclk -scl sa1 sel2 sel3 vssaux m/s sa0 sel1 vss test_mode vdd1 vdd2 test vref vssaux vdd1 analog vdd lr011 0 icon vdd1 / vssaux vdd1 / vssaux ext_set
47/66 ste2004 figure 60. host processor interconnection with 4-line spi interface figure 61. host processor interconnection with 3-line spi interface digital vdd ste2004 p d/c cs res d0 d1 d2 d3 d4 d5 d6 d7 vssaux vssaux e - wr r/w - rd sdin-sdain sdout sdaout sclk-scl sel2 sel3 sel1 vss test_mode vdd1 vdd2 lr0111 vdd1 analog vdd vssaux icon vdd1 / vssaux vdd1 / vssaux vdd1 / vssaux vsense_slave vdd1_aux osc_in fr_in sa1 vssaux m/s sa0 test vref vdd1 vdd1 / vssaux ext_set digital vdd ste2004 p d/c cs res d0 d1 d2 d3 d4 d5 d6 d7 vssaux vssaux e - wr r/w - rd sdin-sdain sdout sdaout sclk-scl sel2 sel3 sel1 vss test_mode vdd1 vdd2 lr011 2 vssaux analog vdd vdd1 vssaux icon vdd1 / vssaux vdd1 / vssaux vdd1 / vssaux vsense_slave vdd1_aux osc_in fr_in sa1 vssaux m/s sa0 test vref vdd1 vdd1 / vssaux ext_set
ste2004 48/66 figure 62. host processor interconnection with 3-line serial interface figure 63. host processor interconnection with 8080-series parallel interface digital vdd ste2004 p d/c cs res d0 d1 d2 d3 d4 d5 d6 d7 vssaux vssaux e - wr r/w - rd sdin-sdain sdout sdaout sclk-scl sel2 sel3 sel1 vss test_mode vdd1 vdd2 lr011 3 analog vdd vdd1 vssaux vdd1 icon vdd1 / vssaux vdd1 / vssaux vdd1 / vssaux vsense_slave vdd1_aux osc_in fr_in sa1 vssaux m/s sa0 test vref vdd1 vdd1 / vssaux ext_set digital vdd ste2004 p d/c cs res d0 d1 d2 d3 d4 d5 d6 d7 vssaux vssaux e - wr r/w - rd sdin-sdain sdout sdaout sclk-scl sel2 sel3 sel1 vss test_mode vdd1 vdd2 lr011 4 analog vdd vssaux vdd1 vssaux icon vdd1 / vssaux vdd1 / vssaux vdd1 / vssaux vsense_slave vdd1_aux osc_in fr_in sa1 vssaux m/s sa0 test vref vdd1 vdd1 / vssaux ext_set
49/66 ste2004 figure 64. host processor interconnection with 6800 digital vdd ste2004 p d/c cs res d0 d1 d2 d3 d4 d5 d6 d7 vssaux vssaux e - wr r/w - rd sdin-sdain sdout sdaout sclk-scl sel2 sel3 sel1 vss test_mode vdd1 vdd2 vdd1 analog vdd vssaux lr011 5 vdd1 icon vdd1 / vssaux vdd1 / vssaux vdd1 / vssaux vsense_slave vdd1_aux osc_in fr_in sa1 vssaux m/s sa0 test vref vdd1 vdd1 / vssaux ext_set
ste2004 50/66 figure 65. application schematic using the internal lcd voltage generator and two separate supplies figure 66. application schematic using the internal lcd voltage generator and a single supply v dd2 v dd1 vdd2 i/o vdd1 vss vlcdsense vlcd v ss 65 x 102 display 32 102 33 1 f1 f 1 f v dd vdd2 i/o vdd1 vss vlcdsense vlcd v ss 32 33 1 f 65 x 102 display 102 1 f
51/66 ste2004 figure 67. power-on timing diagram vdd1 res cs sclk sdin d/c e lr020 8 vdd2 r/w d0 - d7 host osc out, fr_out (driver) sdout - sda out oscin, fr_in (host) scl- sdain hi-z d0 - d7 driver hi-z reset acceptance time booster off power on internal reset t vdd t logic(res) tw(res)
ste2004 52/66 figure 68. power-off timing diagram vdd1 res clk-scl sdin-sdain d/c e cs lr020 7 vdd2 r/w d0 - d7 host osc out fr_out (driver) sdout sda-out oscin (host) d0 - d7 driver hi-z fr_in t vdd hi-z reset table loaded
53/66 ste2004 figure 69. initialization with built-in booster setup normal display mode configuration set driver in power down(pd=1) set driver in normal display mode (pe=0) end of normal display mode config. set operative voltage for normal display operation ( vop[6:0] - prs[1;0]) switch "on" booster and display control logic (pd=0) lr021 8 set bias raio for normal display operation (bs[2:0]) set temperature compensation for normal display operation (t[2:0] or tc[1:0]) set multiplexing rate m[1:0) set charge pump for normal display operation (cp[1:0])
ste2004 54/66 figure 70. data ram to display mapping table 25. test pin configuration test pin pin configuration test_vref open test_mode gnd glass top view display data ram icor row lcd display data ram = "0" display data ram = "1" bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 d00in1155
55/66 ste2004 table 26. absolute maximum ratings table 27. electrical characteristics symbol parameter value unit v dd1 supply voltage range - 0.5 to + 5 v v dd2 supply voltage range - 0.5 to + 7 v v lcd lcd supply voltage range - 0.5 to + 15 v i ss supply current - 50 to +50 ma v i input voltage (all input pads) -0.5 to v dd1 + 0.5 v i in dc input current - 10 to + 10 ma i out dc output current - 10 to + 10 ma p tot total power dissipation (t j = 85c) 300 mw p o power dissipation per output 30 mw t j operating junction temperature -40 to + 85 c t stg storage temperature - 65 to 150 c dc operation (v dd1 = 1.7 to 3.6 v; v dd2 = 1.75 to 4.5 v; vss1,2 = 0v; vlcd = 4.5 to 15 v; tamb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit supply voltages v dd1 supply voltage note 9 1.7 3.6 v v dd2 v v dd2 supply voltage lcd voltage internally generated 1.75 4.5 v v lcd lcd supply voltage lcd voltage supplied externally 4.5 14.5 v lcd supply voltage internally generated; note 1 4.5 14.5 v i(v dd1 ) supply current v dd1 = 2.8v; v lcd = 10v; f sclk = 0;t amb = 25c; parallel port; note 3,8. 15 20 30 a supply current write mode v dd2 = 2.8v; v lcd = 10v; f sclk = 1mhz;t amb = 25c; osc_in=gnd; note8. 100 120 a i(v dd2 ) voltage generator supply current with v op = 0 and prs = [0:0] with external v lcd 1 a v dd2 = 2.8v; v lcd = 10v; f sclk =0; t amb = 25c; no display load; 5x charge pump; note 2,3,6, 60 100 a i(v dd1,2 ) total supply current v dd2 = 2.8v; v lcd = 10v; 5x charge pump; f sclk = 0; t amb = 25c; no display load; note 2, 3, 6 80 130 a power down mode with internal or external vlcd. note 4 310 a i(v ldcin ) external lcd supply voltage current v dd =2.8v; v lcd =10v;no display load; f sclk = 0; t amb = 25c; note 3. 23 a logic outputs v 0h high logic level output voltage ioh=-500 a 0.8v dd1 v dd1 v v ol low logic level output voltage iol=+500 a v ss 0.2v dd1 v
ste2004 56/66 notes: 1. the maximum possible v lcd voltage that can be generated is dependent on voltage, temperature and (display) load. 2. internal clock 3. when f sclk = 0 there is no interface clock. 4. power-down mode. during power-down all static currents are switched-off. 5. if external v lcd , the display load current is not transmitted to i dd 6. tolerance depends on the temperature; (typically zero at t amb = 27c), maximum tolerance values are measured at the temper- ature range limit. 7. for tc0 to tc7 8. data byte writing mode 9. vdd1<=vdd2 logic inputs v il logic low voltage level v ss 0.3 v dd1 v v ih logic high voltage level 0.7 v dd1 v dd2 v i in input current v in = v ss1 or v dd1 -1 1 a logic inputs/outputs v il logic low voltage level v ss 0.3 v dd1 v v ih logic high voltage level 0.7 v dd1 v dd1 + 0.5 v column and row driver r row row output resistance 3k 5k kohm r col column output resistance 5k 10k kohm v col column bias voltage accuracy no load -50 +50 mv v row row bias voltage accuracy -50 +50 mv lcd supply voltage v lcd lcd supply voltage accuracy; internally generated v dd = 2.8v; v lcd = 10v; fsclk=0; t amb =25 c; no display load;note 2, 3, 6 & 7, vop=69h, prs=2hex -1.8 +1.8 % tc0 temperature coefficient -0.0 10 -3 1/c tc1 -0.35 10 -3 1/c tc2 -0.7 10 -3 1/c tc3 -1.05 10 -3 1/c tc4 -1.4 10 -3 1/c tc5 -1.75 10 -3 1/c tc6 -2.1 10 -3 1/c tc7 -2.3 10 -3 1/c dc operation (continued) (v dd1 = 1.7 to 3.6 v; v dd2 = 1.75 to 4.5 v; vss1,2 = 0v; vlcd = 4.5 to 15 v; tamb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit table 23 electrical characteristics (continued)
57/66 ste2004 figure 71. reset timing diagram table 23 electrical characteristics (continued) ac operation (vdd1 = 1.7 to 3.6 v; vdd2 = 1.75 to 4.5 v; vss1,2 = 0v; vlcd = 4.5 to 15 v; tamb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit internal oscillator f osc internal oscillator frequency v dd = 2.8v; tamb = -20 to +70 c 63 72 81 khz f ext external oscillator frequency 20 100 khz f frame frame frequency fosc or fext = 72 khz; note 1 75 hz t w(res) res low pulse width 5 s reset pulse rejection 1 s t logic (res) internal logic reset time 5 s t vdd vdd1 vs. vdd2 delay 0 s vdd1 res inputs i/o (host) lr020 9 vdd2 i/o (driver) osc out fr_out (driver) oscin fr_in (host) interface output hi-z reset table loaded tw(res) hi-z tlogic(res)
ste2004 58/66 figure 72. i 2 c-bus timings ac operation (continued) (vdd1 = 1.7 to 3.6 v; vdd2 = 1.75 to 4.5 v; vss1,2 = 0v; vlcd = 4.5 to 15 v; tamb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit i 2 c bus interface (see note 4, 7) f scl scl clock frequency fast mode dc 400 khz high speed mode; cb=100pf (max);note 6;v dd1 =2 dc 3.4 mhz high speed mode; cb=400pf (max);note 6; v dd1 =2 dc 1.7 mhz fast mode; note 6; v dd1 =1.7v 400 khz t su;sta set-up time (repeated) start condition note 2,3, cb = 100pf 160 ns t hd;sta hold time (repeated) start condition note 2,3, cb = 100pf 160 ns t low low period of sclh clock note 2,3, cb = 100pf 160 ns t high high period of sclh clock note 2,3, cb = 100pf 160 ns t su;dat data set-up time note 2,3, cb = 100pf 60 ns t hd;dat data hold time note 2,3, cb = 100pf 10 ns t r;cl rise time of sclh signal note 2,3, cb = 100pf 10 ns t r;cl1 rise time of sclh signal after a repeated start condition and aftyer an acknowledge bit note 2,3, cb = 100pf 10 ns t f;cl fall time of sclh signal note 2,3, cb = 100pf 10 ns t r;da rise time of sclh signal note 2,3, cb = 100pf 10 ns t f;da fall time of sdah signal note 2,3, cb = 100pf 10 80 ns t r;da rise time of sdah signal note 2,3, cb = 400pf 20 ns t f;da fall time of sdah signal note 2,3, cb = 400pf 20 160 ns t su;sto setup time for stop condition note 2,3, cb = 100pf 160 ns cb capacitive load for sdah and sclh 100 400 pf cb capacitive load for sdah +sda line and sclh +scl line 400 pf sr sclh sdah lr0093 t fda t rda t su;sta t hd;sta t hd;dat t su;dat t low t rcl1 t rcl t high t high t low sr p t rcl1 t fcl (1) (1) = mcs current source pull-up = rp resistor pull-up table 23 electrical characteristics (continued)
59/66 ste2004 figure 73. 68000-series parallel interface timing figure 74. 8080-series parallel interface timing table 23 electrical characteristics (continued) ac operation (continued) (vdd1 = 1.7 to 3.6 v; vdd2 = 1.75 to 4.5v; vss1,2 = 0v; vlcd = 4.5 to 15 v; tamb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit parallel interface t cyc system cycle time v dd1 = 1.7v; read & write 125 ns t clw control low pulse width (wr) 20 ns t chw control high pulse width (wr) 75 ns t clr control low pulse width (rd) 40 ns t chr control high pulse width (rd) 55 ns t ewhw enable high pulse width (write) 60 ns t ewlw enable low pulse width (write) 60 ns t ewhr enable high pulse width (read) 60 ns t ewlr enable low pulse width (read) 60 ns t su(a) address set-up time 10 ns t h(a) address hold time 10 ns t su1 data set-up time 30 ns t h1 data hold time 30 ns t su2 read access time 40 ns t h2 output disable time 0 30 ns d/c r/w cs e d0 to d7 (write) d0 to d7 (read) t su2 t h2 t su1 t cyc t h(a) t su(a) t ewhr , t ewhw t ewlr , t ewlw t h1 d/c cs wr, rd d0 to d7 (write) d0 to d7 (read) t su2 t h2 t su1 t cyc t h (a) t su(a) t clr , t clw t chr , t chw t h1
ste2004 60/66 figure 75. serial interface timing notes: 1. 2. all timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to v il and v ih with an input voltage swing of v ss to v dd 3. cb is the capacitive load for each bus line. 4. for bus line loads cb between 100 and 400pf the timing parameters must be linearly interpolated 5. c vlcd is the filtering capacitor on vlcd 6. trise and tfall (30%-70%) -10ns 7. i 2 c bus ac characteristics are tested by correlation table 23 electrical characteristics (continued) ac operation (continued) (vdd1 = 1.7 to 3.6 v; vdd2 = 1.75 to 4.5 v; vss1,2 = 0v; vlcd = 4.5 to 15 v; tamb =-40 to 85c; unless otherwise specified) symbol parameter test condition min. typ. max. unit serial interface f sclk clock frequency v dd1 = 1.7v; 8 mhz t cyc clock cycle sclk 125 ns t pwh1 sclk pulse width high 60 ns t pwl1 sclk pulse width low 60 ns t s2 cs setup time v dd1 = 1.7v 40 ns t h2 cs hold time 50 ns t pwh2 cs minimum high time 50 ns t s3 sd/c setup time 30 ns t h3 sd/c hold time 30 ns t s4 sdin setup time 30 ns t h4 sdin hold time 40 ns t s5 sdout access time 30 ns t h5 sdout disable time vs. sclk 0 20 ns t h6 sdout disable time vs. cs 0 20 ns d/c cs t s2 t s3 t s4 t h2 t pwh2 sdin sclk t h3 t h4 t pwl1 t wh1 t s2 t cyc sout t s5 t h5 t h6 lr0096 f frame f osc 960 --------- - =
61/66 ste2004 table 28. pad coordinates name pad x ( m) y( m) r5 1 -2925.0 -596.5 r4 2 -2875.0 -596.5 r3 3 -2825.0 -596.5 r2 4 -2775.0 -596.5 r1 5 -2725.0 -596.5 r0 6 -2675.0 -596.5 c0 7 -2625.0 -596.5 c1 8 -2575.0 -596.5 c2 9 -2525.0 -596.5 c3 10 -2475.0 -596.5 c4 11 -2425.0 -596.5 c5 12 -2375.0 -596.5 c6 13 -2325.0 -596.5 c7 14 -2275.0 -596.5 c8 15 -2225.0 -596.5 c9 16 -2175.0 -596.5 c10 17 -2125.0 -596.5 c11 18 -2075.0 -596.5 c12 19 -2025.0 -596.5 c13 20 -1975.0 -596.5 c14 21 -1925.0 -596.5 c15 22 -1875.0 -596.5 c16 23 -1825.0 -596.5 c17 24 -1775.0 -596.5 c18 25 -1725.0 -596.5 c19 26 -1675.0 -596.5 c20 27 -1625.0 -596.5 c21 28 -1575.0 -596.5 c22 29 -1525.0 -596.5 c23 30 -1475.0 -596.5 c24 31 -1425.0 -596.5 name pad x ( m) y( m) c25 32 -1375.0 -596.5 c26 33 -1325.0 -596.5 c27 34 -1275.0 -596.5 c28 35 -1225.0 -596.5 c29 36 -1175.0 -596.5 c30 37 -1125.0 -596.5 c31 38 -1075.0 -596.5 c32 39 -1025.0 -596.5 c33 40 -975.0 -596.5 c34 41 -925.0 -596.5 c35 42 -875.0 -596.5 c36 43 -825.0 -596.5 c37 44 -775.0 -596.5 c38 45 -725.0 -596.5 c39 46 -675.0 -596.5 c40 47 -625.0 -596.5 c41 48 -575.0 -596.5 c42 49 -525.0 -596.5 c43 50 -475.0 -596.5 c44 51 -425.0 -596.5 c45 52 -375.0 -596.5 c46 53 -325.0 -596.5 c47 54 -275.0 -596.5 c48 55 -225.0 -596.5 c49 56 -175.0 -596.5 c50 57 -125.0 -596.5 c51 58 125.0 -596.5 c52 59 175.0 -596.5 c53 60 225.0 -596.5 c54 61 275.0 -596.5 c55 62 325.0 -596.5 table 28. pad coordinates (continued)
ste2004 62/66 name pad x ( m) y( m) c56 63 375.0 -596.5 c57 64 425.0 -596.5 c58 65 475.0 -596.5 c59 66 525.0 -596.5 c60 67 575.0 -596.5 c61 68 625.0 -596.5 c62 69 675.0 -596.5 c63 70 725.0 -596.5 c64 71 775.0 -596.5 c65 72 825.0 -596.5 c66 73 875.0 -596.5 c67 74 925.0 -596.5 c68 75 975.0 -596.5 c69 76 1025.0 -596.5 c70 77 1075.0 -596.5 c71 78 1125.0 -596.5 c72 79 1175.0 -596.5 c73 80 1225.0 -596.5 c74 81 1275.0 -596.5 c75 82 1325.0 -596.5 c76 83 1375.0 -596.5 c77 84 1425.0 -596.5 c78 85 1475.0 -596.5 c79 86 1525.0 -596.5 c80 87 1575.0 -596.5 c81 88 1625.0 -596.5 c82 89 1675.0 -596.5 c83 90 1725.0 -596.5 c84 91 1775.0 -596.5 c85 92 1825.0 -596.5 c86 93 1875.0 -596.5 table 28. pad coordinates (continued) name pad x ( m) y( m) c87 94 1925.0 -596.5 c88 95 1975.0 -596.5 c89 96 2025.0 -596.5 c90 97 2075.0 -596.5 c91 98 2125.0 -596.5 c92 99 2175.0 -596.5 c93 100 2225.0 -596.5 c94 101 2275.0 -596.5 c95 102 2325.0 -596.5 c96 103 2375.0 -596.5 c97 104 2425.0 -596.5 c98 105 2475.0 -596.5 c99 106 2525.0 -596.5 c100 107 2575.0 -596.5 c101 108 2625.0 -596.5 r32 109 2675.0 -596.5 r33 110 2725.0 -596.5 r34 111 2775.0 -596.5 r35 112 2825.0 -596.5 r36 113 2875.0 -596.5 r37 114 2925.0 -596.5 r38 115 3086.5 -525.0 r39 116 3086.5 -475.0 r40 117 3086.5 -425.0 r41 118 3086.5 -375.0 r42 119 3086.5 -325.0 r43 120 3086.5 -275.0 r44 121 3086.5 -225.0 r45 122 3086.5 -175.0 r46 123 3086.5 -125.0 r47 124 3086.5 -75.0 table 28. pad coordinates (continued)
63/66 ste2004 name pad x ( m) y( m) r48 125 3086.5 -25.0 r49 126 3086.5 25.0 r50 127 3086.5 75.0 r51 128 3086.5 125.0 r52 129 3086.5 175.0 r53 130 3086.5 225.0 r54 131 3086.5 275.0 r55 132 3086.5 325.0 r56 133 3086.5 375.0 r57 134 3086.5 425.0 r58 135 3086.5 475.0 r59 136 3086.5 525.0 r60 137 2925.0 596.5 r61 138 2875.0 596.5 r62 139 2825.0 596.5 r63 140 2775.0 596.5 r64-icon 141 2725.0 596.5 vdd1_aux 142 2475.0 596.5 fr_in 143 2425.0 596.5 osc_in 144 2375.0 596.5 vsense_slave 145 2325.0 596.5 test_vref 146 1975.0 596.5 vssaux 147 1925.0 596.5 sa1 148 1875.0 596.5 sa0 149 1825.0 596.5 m/s 150 1775.0 596.5 ext_set 151 1725.0 596.5 sel3 152 1675.0 596.5 sel2 153 1625.0 596.5 sel1 154 1575.0 596.5 icon 155 1525.0 596.5 table 28. pad coordinates (continued) name pad x ( m) y( m) vdd1 156 1475.0 596.5 vdd1 157 1425.0 596.5 vdd1 158 1375.0 596.5 vdd1 159 1325.0 596.5 vdd1 160 1275.0 596.5 vdd1 161 1225.0 596.5 vdd1 162 1175.0 596.5 vdd1 163 1125.0 596.5 vdd2 164 1075.0 596.5 vdd2 165 1025.0 596.5 vdd2 166 975.0 596.5 vdd2 167 925.0 596.5 vdd2 168 875.0 596.5 vdd2 169 825.0 596.5 vdd2 170 775.0 596.5 vdd2 171 725.0 596.5 res 172 375.0 596.5 cs 173 275.0 596.5 d/c 174 175.0 596.5 r/w - rd 175 75.0 596.5 e - wr 176 -25.0 596.5 vssaux 177 -75.0 596.5 sdaout 178 -175.0 596.5 sdin-sdain 179 -225.0 596.5 sdout 180 -275.0 596.5 sclk-scl 181 -375.0 596.5 d7 182 -425.0 596.5 d6 183 -475.0 596.5 d5 184 -525.0 596.5 d4 185 -575.0 596.5 d3 186 -625.0 596.5 table 28. pad coordinates (continued)
ste2004 64/66 table 29. alignment marks coordinates name pad x ( m) y( m) d2 187 -675.0 596.5 d1 188 -725.0 596.5 d0 189 -775.0 596.5 vssaux 190 -825.0 596.5 test_mode 191 -1225.0 596.5 vss 192 -1275.0 596.5 vss 193 -1325.0 596.5 vss 194 -1375.0 596.5 vss 195 -1425.0 596.5 vss 196 -1475.0 596.5 vss 197 -1525.0 596.5 vss 198 -1575.0 596.5 vss 199 -1625.0 596.5 vss 200 -1675.0 596.5 vss 201 -1725.0 596.5 vss 202 -1775.0 596.5 vss 203 -1825.0 596.5 vlcdsense 204 -2075.0 596.5 vlcd 205 -2125.0 596.5 vlcd 206 -2175.0 596.5 vlcd 207 -2225.0 596.5 vlcd 208 -2275.0 596.5 vlcd 209 -2325.0 596.5 osc_out 210 -2475.0 596.5 fr_out 211 -2525.0 596.5 r31 212 -2775.0 596.5 r30 213 -2825.0 596.5 r29 214 -2875.0 596.5 r28 215 -2925.0 596.5 r27 216 -3086.5 525.0 table 28. pad coordinates (continued) r26 217 -3086.5 475.0 name pad x ( m) y( m) r25 218 -3086.5 425.0 r24 219 -3086.5 375.0 r23 220 -3086.5 325.0 r22 221 -3086.5 275.0 r21 222 -3086.5 225.0 r20 223 -3086.5 175.0 r19 224 -3086.5 125.0 r18 225 -3086.5 75.0 r17 226 -3086.5 25.0 r16 227 -3086.5 -25.0 r15 228 -3086.5 -75.0 r14 229 -3086.5 -125.0 r13 230 -3086.5 -175.0 r12 231 -3086.5 -225.0 r11 232 -3086.5 -275.0 r10 233 -3086.5 -325.0 r9 234 -3086.5 -375.0 r8 235 -3086.5 -425.0 r7 236 -3086.5 -475.0 r6 237 -3086.5 -525.0 marks x y mark1 -3089.5 -599.5 mark2 3089.5 -599.5 mark3 -2400.0 599.5 mark4 538.1 599.5 table 28. pad coordinates (continued)
65/66 ste2004 figure 76. alignment marks dimensions table 30. bumps table 31. die mechanical dimensions 94 m 39 m bump number dimensions bumps size 30 m x 98 m x 17.5 pad size 43 m x 107 m pad pitch 50 m spacing between bumps 20 m die size (x x y) 6.42mm x 1.46m m wafers thickness 500 m table 32. revision history date revision description of changes may 2004 3 moved the value of fsclk parameter from min. to max. on the page 60/ 66. july 2004 4 inserted table 24 -n-line inversion in the page 44/66
information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 66/66 ste2004

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