? semiconductor components industries, llc, 2012 february, 2012 ? rev. 5 1 publication order number: mjd128/d mjd128t4g, NJVMJD128T4G (pnp) complementary darlington power transistor dpak for surface mount applications designed for general purpose amplifier and low speed switching applications. features ? monolithic construction with built ? in base ? emitter shunt resistors ? high dc current gain: h fe = 2500 (typ) @ i c = 4.0 adc ? epoxy meets ul 94 v ? 0 @ 0.125 in. ? esd ratings: ? human body model, 3b > 8000 v ? machine model, c > 400 v ? njv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable ? these are pb ? free devices* ??????????????????? ??????????????????? maximum ratings rating symbol value unit collector ? emitter voltage v ceo 120 vdc collector ? base voltage v cb 120 vdc emitter ? base voltage v eb 5 vdc collector current continuous peak i c 8 16 adc base current i b 120 madc total power dissipation @ t c = 25 ? c derate above 25 ? c p d 20 0.16 w w/ ? c total power dissipation* @ t a = 25 ? c derate above 25 ? c p d 1.75 0.014 w w/ ? c operating and storage junction temperature range t j , t stg ? 65 to + 150 ? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ??????????????????? ??????????????????? thermal characteristics characteristic symbol max unit thermal resistance, junction ? to ? case r jc 6.25 ? c/w thermal resistance, junction ? to ? ambient (note 1) r ja 71.4 ? c/w 1. these ratings are applicable when surface mounted on the minimum pad sizes recommended. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram a = assembly location y = year ww = work week j128 = device code g = pb ? free package device package shipping ? ordering information dpak case 369c style 1 mjd128t4g dpak (pb ? free) 2,500/tape & reel http://onsemi.com ayww j128g base collector emitter silicon power transistor 8 amperes 120 volts, 20 watts 4 1 2 3 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. NJVMJD128T4G dpak (pb ? free) 2,500/tape & reel
mjd128t4g, NJVMJD128T4G (pnp) http://onsemi.com 2 ????????????????????????????????? ????????????????????????????????? ????????????????????????????????? (t c = 25 ? c unless otherwise noted) characteristic symbol min max unit off characteristics collector ? emitter sustaining voltage (i c = 30 madc, i b = 0) v ceo(sus) 120 ? vdc collector cutoff current (v ce = 120 vdc, i b = 0) i ceo ? 5 ma collector cutoff current (v cb = 100 vdc, i e = 0) i cbo ? 10 adc emitter cutoff current (v be = 5 vdc, i c = 0) i ebo ? 2 madc on characteristics dc current gain (i c = 4 adc, v ce = 4 vdc) (i c = 8 adc, v ce = 4 vdc) h fe 1000 100 12,000 ? ? collector ? emitter saturation voltage (i c = 4 adc, i b = 16 madc) (i c = 8 adc, i b = 80 madc) v ce(sat) ? ? 2 4 vdc base ? emitter saturation voltage (1) (i c = 8 adc, i b = 80 madc) v be(sat) ? 4.5 vdc base ? emitter on voltage (i c = 4 adc, v ce = 4 vdc) v be(on) ? 2.8 vdc dynamic characteristics current ? gain ? bandwidth product (i c = 3 adc, v ce = 4 vdc, f = 1 mhz) |h fe | 4 ? mhz output capacitance (v cb = 10 vdc, i e = 0, f = 0.1 mhz) c ob ? 300 pf small ? signal current gain (i c = 3 adc, v ce = 4 vdc, f = 1 khz) h fe 300 ? ? 2. pulse test: pulse width 300 s, duty cycle 2%. figure 1. power derating 25 25 t, temperature ( ? c) 0 50 75 100 125 150 20 15 10 5 p d , power dissipation (watts) 2.5 0 2 1.5 1 0.5 t a t c t a surface mount t c
mjd128t4g, NJVMJD128T4G (pnp) http://onsemi.com 3 v ce , collector ? emitter voltage (volts) i c , collector current (amp) 500 0.2 5000 2000 10,000 h fe , dc current gain v ce = 4 v t j = 150 ? c 7000 0.1 0.7 25 ? c -55 ? c 3000 0.5 1 20,000 700 1000 23 5 3 i b , base current (ma) 2.6 2.2 1.8 1.4 0.3 0.5 1 7 35 4 a i c = 2 a 2 t j = 25 ? c 1 i c , collector current (amp) 2 1.5 v, voltage (volts) 3 2.5 1 0.5 t j = 25 ? c v be(sat) @ i c /i b = 250 v be @ v ce = 4 v v ce(sat) @ i c /i b = 250 0.2 3 0.1 0.7 0.3 1 5 10 20 30 figure 2. dc current gain figure 3. collector saturation region figure 4. ?on? voltages 200 300 0.3 7 10 0.7 0.5 7 2 10 6 a typical electrical characteristics v , temperature coefficients (mv/ c) ? ? i c , collector current (amp) 0.2 *i c /i b ? h fe/3 0.1 -55 ? c to 25 ? c 123 10 +5 -5 vb for v be 25 ? c to 150 ? c vc for v ce(sat) figure 5. temperature coefficients -4 -3 -2 -1 0 +4 +3 +2 +1 0.5 0.3 7 5 -55 ? c to 25 ? c 25 ? c to 150 ? c 10 4 v be , base ? emitter voltage (volts) 10 -1 0 +0.4 , collector current ( a) ? i c 10 3 10 2 10 1 10 0 -0.2 -0.4 -0.6 t j = 150 ? c 100 ? c reverse forward 25 ? c v ce = 30 v 10 5 +0.6 +0.2 -0.8 -1 -1.2 -1.4 figure 6. collector cut ? off region figure 7. small ? signal current gain 1 f, frequency (khz) 100 210 500 5000 t c = 25 ? c v ce = 4 vdc i c = 3 adc 3000 550 20 100 10,000 200 300 200 500 1000 2000 1000 10 50 20 30 pnp npn h fe , small ? signal current gain
mjd128t4g, NJVMJD128T4G (pnp) http://onsemi.com 4 v r , reverse voltage (volts) c ib 30 1 5 20 100 t j = 25 ? c 300 50 70 100 0.1 2 10 50 0.5 0.2 200 figure 8. capacitance c, capacitance (pf) c ob t, time or pulse width (ms) 1 0.01 100 0 0.3 0.2 0.07 r(t), effective transient r jc(t) = r(t) r jc r jc = 6.25 ? c/w d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) jc(t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 0.01 thermal resistance (normalized) 0.7 0.5 0.1 0.05 0.03 0.02 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 0.2 single pulse d = 0.5 0.05 0.1 0.5 3 0.3 0.2 0.7 1 5 i c , collector current (amp) v cc = 30 v i c /i b = 250 i b1 = i b2 t j = 25 ? c t, time (s) ? 3 2 0.7 0.5 0.3 0.2 t s t f t r t d @ v be(off) = 0 v figure 9. switching times test circuit figure 10. switching times 0.1 1 10 7 5 2 figure 11. thermal response v 2 a pprox +8 v 0 ? 8 k scope v cc -30 v r c 51 for t d and t r , d 1 is disconnected and v 2 = 0 for npn test circuit reverse all polarities. 25 s t r , t f ? 10 ns duty cycle = 1% + 4 v r b & r c varied to obtain desired current levels d 1 , must be fast recovery type, e.g.: 1n5825 used above i b ? 100 ma msd6100 used below i b ? 100 ma v 1 a pprox -12 v tut r b d 1 ? 120 0.07 0.05 0.1 0.01
mjd128t4g, NJVMJD128T4G (pnp) http://onsemi.com 5 i c , collector current (amp) 5 v ce , collector-emitter voltage (volts) 0.3 5 2 0.5 0.2 bonding wire limit thermal limit t c = 25 ? c (single pulse) second breakdown limit 10 50 7 t j = 150 ? c 100 s 1ms dc 0.1 1 3 15 20 30 20 100 curves apply below rated v ceo 5ms figure 12. maximum forward bias safe operating rea 3 2 1 10 0.05 0.02 0.03 500 s 120 200 there are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. safe operating area curves indicate i c ? v ce limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. the data of figure 12 is based on t j(pk) = 150 ? c; t c is variable depending on conditions. second breakdown pulse limits are valid for duty cycles to 10% provided t j(pk) < 150 ? c. t j(pk) may be calculated from the data in figure 11. at high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. figure 13. darlington schematic base emitter collector ? 8 k ? 120
mjd128t4g, NJVMJD128T4G (pnp) http://onsemi.com 6 package dimensions dpak case 369c ? 01 issue d style 1: pin 1. base 2. collector 3. emitter 4. collector 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mjd128/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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