1 ps2002b 12/10/96 2
1
register
control
i 0 ,i 1
clk
octal
register a1
octal
register a2
octal
register b1
octal
register b2
mux
mux
8
8
d 0 ? 7
y 0 ? 7
oe
s 0 ,s 1
2
logic block diagram 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 pi29fct520t/2520t pi29fct521t fast cmos multilevel pipeline registers product description: pericom semiconductors pi29fct series of logic circuits are pro-duced in the companys advanced 0.8 micron cmos technology, achieving industry leading speed grades. the pi29fct520t/2520t and pi29fct521t are multilevel pipeline registers containing four 8-bit positive triggered registers which can be configured as a dual 2-level or a single 4-level pipeline. these products are designed for use as temporary storage or for storage delays in pipelined systems. the pi29fct521t differs from the pi29fct520t/2520t only in the way data is loaded into and between registers in the dual 2-level operation. when data is entered into the first level (i = 2 or i = 1) of the pi29fct520t/2520t, the existing data in the first level is moved to the second level. in the pi29fct521t, these instructions simply overwrite the data in the first level. transfer of data to the second level is achieved using the 4-level shift instruction (i = 0) causing the first level to change. in either part, i = 3 shift instruction puts the registers on hold. device models available upon request. product features: ? pi29fct520t and pi29fct521t are pinout and function compatible with idt29fct520/521, qs29fct520/521 and amd's am29520/521 ? four 8-bit high-speed registers ? hold, transfer, and load instructions ? dual two-level or single four-level pipeline operation ? ttl input and output levels, reducing problematic "ground bounce" ? high output drive i ol = 48 ma ? extremely low static power (1 mw, typ.) ? industrial operating temperature range: C40c to +85c ? fct (2xxxt) has a 25 w series resistor. ? packages available: C 24-pin 300 mil wide plastic dip (p24) C 24-pin 150 mil wide plastic qsop (q24) C 24-pin 150 mil wide plastic tqsop (r24) C 24-pin 300 mil wide plastic soic (s24) fct520.pm6 12/18/96, 4:44 pm 1
pi29fct520/521t/2520t multilevel pipeline registers 2 ps2002b 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 product pin description pin name description oe output enable input (active low) for 3-state output port clk clock input. enter data into registers on low-to-high transistions i 0 ,i 1 instruction inputs s 0 ,s 1 multiplexer select. inputs either register a1, a2, b1, or b2 data to be avaialbe at the output ports dx register inputs yx register outputs gnd ground v cc power product pin configuration i 0 i 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clk gnd 1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24-pin p24 q24 r24 s24 s1 s0 register 00 b2 01 b1 10 a2 11 a1 register selection pi29fct520/t2520t data loading a1 a2 b1 b2 a1 a2 b1 b2 a1 a2 b1 b2 dual 2-level single 4-level i = 0 i = 1 i = 2 note: i = 3 for hold pi29fct521t data loading a1 a2 b1 b2 a1 a2 b1 b2 a1 a2 b1 b2 dual 2-level single 4-level i = 0 i = 1 i = 2 note: i = 3 for hold v cc s 0 s 1 y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 oe fct520.pm6 12/18/96, 4:44 pm 2
pi29fct520/521t/2520t multilevel pipeline registers 3 ps2002b 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ................................................................. C55c to +125c ambient temperature with power applied ................................. -40c to +85c supply voltage to ground potential (inputs & vcc only) .......... C0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ....... C0.5v to +7.0v dc input voltage ......................................................................... C0.5v to +7.0v dc output current ................................................................................... 120 ma power dissipation ......................................................................................... 0.5w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ max. units c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf notes: 1. for conditions show as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested. dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 5v 5%) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = m in ., v in = v ih or v il i oh = C15.0 ma 2.4 3.0 v v ol output low voltage v cc = m in ., v in = v ih or v il i ol = 48 ma 0.3 0.50 v i ol = 12 ma (25 w series) 0.3 0.50 v v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v cc = m ax .v in = v cc 1a i il input low current v cc = m ax .v in = gnd C1 a i ozh high impedance v cc = m ax .v out = 2.7v 1 a i ozl output current v out = 0.5v C1 a v ik clamp diode voltage v cc = m in ., i in = C18 ma C0.7 C1.2 v i os short circuit current v cc = m ax . (3) , v out = gnd C60 C120 ma i off power down disable v cc = gnd, v out = 4.5v 100 a v h input hysteresis 200 mv fct520.pm6 12/18/96, 4:44 pm 3
pi29fct520/521t/2520t multilevel pipeline registers 4 ps2002b 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.1 10 a supply current d i cc supply current per v cc = max. v in = 3.4v (3) 0.5 2.0 ma input @ ttl high i ccd supply current per v cc = max., v in = gnd 0.15 0.25 ma/ input per mhz (4) outputs open v in = v cc mhz oe = gnd one input toggling 50% duty cycle i c total power supply v cc = max., v in = gnd 1.5 3.5 (5) ma current (5) outputs open v in = v cc f cp = 10 mh z 50% duty cycle oe = gnd v in = 3.4v 2.0 5.5 (5) one bit toggling v in = gnd f i = 5 mh 50% duty cycle v cc = max., v in = gnd 3.8 7.3 (5) outputs open v in = v cc f cp = 10 mh z 50% duty cycle oe = gnd v in = 3.4v 6.0 16.3 (5) eight bits toggling v in = gnd f i = 5 mhz 50% duty cycle notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v, control inputs only); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply characteristics. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. fct520.pm6 12/18/96, 4:44 pm 4
pi29fct520/521t/2520t multilevel pipeline registers 5 ps2002b 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 pi29fct520t/2520t switching characteristics over operating range fct520at/2520at fct520bt/2520bt com. com. parameters description conditions (1) min max min max unit t plh propagation delay c l = 50 pf 2.0 14.0 2.0 7.5 ns t phl clk to y x r l = 500 w t plh propagation delay 2.0 13.0 2.0 7.5 ns t phl s 0 or s 1 to y x t su setup time high 5.0 2.5 ns or low d x to clk t h hold time high 2.0 2.0 ns or low d x to clk t su setup time high 5.0 4.0 ns or low i 0 or i 1 to clk t h hold time high 2.0 2.0 ns or low i 0 or i 1 to clk t pzh output enable time 1.5 12.0 1.5 7.0 ns t pzl oe to y x t phz output disable time (3) 1.5 15.0 1.5 7.5 ns t plz oe to yx t w clock pulse width (3) 7.0 5.5 ns high or low notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. pi29fct521t switching characteristics over operating range fct521at fct521bt com. com. parameters description conditions (1) min max min max unit t plh propagation delay c l = 50 pf 2.0 14.0 2.0 7.5 ns t phl clk to y x r l = 500 w t plh propagation delay 2.0 13.0 2.0 7.5 ns t phl s 0 or s 1 to y x t su setup time high 5.0 2.5 ns or low d x to clk t h hold time high 2.0 2.0 ns or low d x to clk t su setup time high 5.0 4.0 ns or low i 0 or i 1 to clk t h hold time high 2.0 2.0 ns or low i 0 or i 1 to clk t pzh output enable time 1.5 12.0 1.5 7.0 ns t pzl oe to yx t phz output disable time (3) 1.5 15.0 1.5 7.5 ns t plz oe to yx t w clock pulse width (3) 7.0 5.5 ns high or low pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com fct520.pm6 12/18/96, 4:44 pm 5
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