AN208 vishay siliconix document number: 70606 10-aug-99 www.vishay.com faxback 408-970-5600 6-1 a high-performance, low-cost analog switch family introduction vishay siliconix' popular dg201 quad analog switch has been an industry workhorse for over two decades. to meet the demands of new applications for more precision and faster switching speeds, an improved version of the dg201, along with five other general purpose analog switches, is being introduced by vishay siliconix. the new abo series provides lower switch on-resistance, leakage current, turn-on time, charge injection, and power consumption at prices comparable to industry-standard devices. behind these improved levels of performance is vishay siliconix' new high-voltage silicon gate process, hvsg-ii. hvsg-ii substantially increases the switch's overall performance, allowing analog signals to be switched efficiently from 20 v to +3 v. even though these devices were designed on a high-voltage process, they still exhibit very good low-voltage performance and provide a single-supply solution. these general-purpose parts are ideal for a host of applications, including automatic test equipment, instru- mentation, and voice or data communications. this note details performance improvements, and provides a competitive comparison and overview of general applications. improved single-supply operation the abo family can be used with split supplies or a single supply. the dg201b/202b have an internal +5-v regulator. the dg211b and dg212b are ideal for low-voltage single supply operation (+3 v to +5 v). figure 1. abo series diagrams in sd ttl or cmos in sd cmos in sd dg201b normally closed, internal regulator dg211b normally closed dg308b normally closed in sd in sd cmos in sd dg202b normally open, internal regulator dg212b normally open dg309b normally open ttl or cmos ttl or cmos ttl or cmos
AN208 vishay siliconix www.vishay.com faxback 408-970-5600 6-2 document number: 70606 10-aug-99 dg211b/212b typical low-voltage performance v+ & v l (v) logic threshold (v) t on (ns) t off (ns) +5 +2.2 200 50 +4.5 +2 200 50 +4 +1.9 300 50 +3.3 +1.6 400 100 +3 +1.5 500 100 +2.5 +1.2 900 200 +2 +1 1600 400 note: v s = +2 v, r l =1 k , v = 0 v simply connect v l to v+ (figure 2). the voltage at v l sets the logic threshold (table 1). even though the dg211b and dg212b operate as low as +2 v, their turn-on time increases proportionally to the decrease in v+. at +3.3 v these devices are quite suitable for general applications, even though their on-resistance can approach 1 k . later it will be shown how this resistance can also be substantially reduced. the dg201b/202b parts also were tested to +3 v with similar performance (except t on which was slightly slower). speed combined with power normally the speed of an analog switch can only be increased at the expense of the power driving the chip. but the abo series devices overcome this problem with reduced channel lengths and parasitic capacitances. these improvements allow the dg211b's turn-on (t on ) time to be reduced to 120 ns typical, and power dissipation (p d ) to be as low as 0.7 nw during the quiescent condition. note that both t on and p d are a function of the power supplies used to power the chip. table 1 shows the correlation between low voltage effects of the supply voltage used. the switching speed is typically 120 ns with split 15-v supplies. it slows to 1600 ns with a mere +2-v single supply. turn-on time (t on ) is measured from 50% of the input logic control to 90% of the analog output signal. this interval includes the delay through the logic translator, fet driver stages, and the fets themselves. an rc time constant comprised of the channel on-resistance and the output load capacitance (c l ) increases t on with an increase in c l . this effect is minimal as long as a shunt resistive load is also present. the increase in t on is approximately equal to: t on = r ds(on) c l where c l is the value above 35 pf (and 35 pf is the standard c l used to measure t on ). low on-resistance on-resistance can make a critical addition to the error budget in precision applications. for the abo devices, typical r ds(on) is 45 and is in series with a load resistance r l (figure 2). the error is equal to r ds(on) /(r ds(on) + r l ) or 45/(45 + 1 k) = 4.3% figure 2. dg211b single-supply operation in sd dg211b gnd v r l 1 k v+ v l +2 v to +5 v figure 3. low voltage r ds(on) curves v+ = +2 v 01 5 1500 100 900 700 500 300 v d drain voltage (v) r ds(on) () +5 v +4 v +3.3 v +3 v +2.5 v 23 4 1300 1100
AN208 vishay siliconix document number: 70606 10-aug-99 www.vishay.com faxback 408-970-5600 6-3 increasing r l will proportionally reduce this error. however, a large load resistance reduces the off-isolation. if the analog signal is dc, off-isolation is not a problem since it will not be coupled through the off-channel parasitic capacitor. but if the analog signal is ac, then the off-isolation decreases as the frequency increases or if r l increases. one solution to this problem is to run the switch into the virtual ground of an inverting amplifier, as described below. on-resistance flatness on-resistance flatness is a measure of the change in r ds(on) when the source or drain voltage varies. this delta can distort the input signal as follows: harmonic distortion 20 log r on r l limiting analog signal dynamic range to the flattest part of the r ds(on) curve can reduce this error. a avirtual groundo at the summing junction of an op amp can provide the high impedance required to reduce distortion. if the non-inverting input of an op amp is referenced to ground, a virtual ground appears at the inverting input because the input offset voltage (v os ) of most op amps is in the microvolt or millivolt range. thus the inverting input is only the value of this input voltage above or below ground. this virtual ground node is also a very high impedance point because r in v os i b where i b is the input bias current of the op amp. for instance, a typical op amp with v os = 1 mv and i b = 1 na would have an input impedance of 1 m . bandwidth improvements the bandwidth of a general-purpose analog switch is generally not specified on most data sheets. bandwidth can be calculated by this expression: f 3db 1 2 rc where r = r ds(on) and c = c d(on) , also r l assumed to be infinite. substituting 45 and 16 pf, respectively, results in a theoretical calculated bandwidth of 220 mhz. in reality, the switch has no real off-isolation at this frequency so the usable bandwidth is really a function of off-isolation. since off-isolation is 60 db at 3 mhz, then 3 mhz becomes the maximum usable frequency (assuming that 60 db is the minimum acceptable limit). this relationship can be seen on the data sheet off isolation vs. frequency curve. at a bandwidth of 1 mhz, the off-isolation is 90 db. bandwidth is also associated with insertion loss. this specification is expressed in db and equals 20 log r l r on r on the insertion loss of the abo series devices is generally 6 db over the usable frequency range from 0 to 3 mhz with r l = 50 . charge injection charge injection consists of the charge (measured in pc) transferred from the digital driver to the analog channel at the time of switching the device to the aoffo state. this unwanted charge is normally induced through parasitic gate-to-source or gate-to-drain capacitances. in a sample-and-hold circuit, charge injection will cause an offset error called ahold-step.o abo series switches have glitch suppression circuitry on-chip and fewer parasitics at the gate. these improvements have reduced the typical charge to 1 pc, compared with the industry-standard specification of 20 pc. tips for reducing charge injection effects using the drain instead of the source for the output results in less glitch, but the astepo is slightly greater. this approach, however, isn't without its problems. the logic signal (in) can be injected into the analog output path by the package interlead capacitance (pin-to-pin) which is generally about 0.75 pf. another 1-3 pf is usually associated with the pc board stray capacitance, if the input and drain, which are adjacent to each other at the package, are laid out without a ground plane separation. the board used for this test measured about 3 pf of stray capacitance. because of this interlead and board capacitance (ac stray o), it is also recommended that the logic amplitude be clamped to about +3 v . the charge current is expressed here: i c dv dt where dv is the instantaneous logic voltage change and c is c stray .
AN208 vishay siliconix www.vishay.com faxback 408-970-5600 6-4 document number: 70606 10-aug-99 in sd dg211b gnd v+ 15 v to +15 v figure 4. charge injection test circuit v +15 15 0.01 f 10 f 10 f 0.01 f 0.1 f c stray c l 1 nf polysty- rene fet probe glitch charge current (i) can be reduced if dv is reduced, where dv is the logic control signal amplitude. note, for example, the reduction of current injected into the hold capacitor (c l ) shown in figure 4. a proper ground plane separation or guard, as well as logic clamping, can substantially reduce the charge injection caused by c stray . a single point ground (with digital and analog grounds separated), or a ground plane, should be used to reduce ground loops and switching noise. figure 6a depicts the abo series actual hold-step of 9 mv with +2 v at the source. maxim's best currently available equivalent device, for example, offers a 14-mv hold-step (figure 6b) measured at turn-off. to achieve a q of 1 pc (which is actually 1 mv) using a abo series device, the voltage at the source should be at ground and the logic amplitude clamped to about +3 v. or reduce cstray. the voltage change can be calculated by: v q c l a 10- damping resistor in series with the hold capacitor (figure 5), actually increases the effects of charge injection. the load becomes more resistive. c l could be increased to about 10 nf, which would help suppress the glitch and hold-step (while decreasing the droop rate in s/h circuits). figure 5. reducing charge injection effects dc input 0.1 mf 1000 pf polystyrene fet probe scope 10 not recommended dc input 0.1 f 1 nf to 10 nf polystyrene fet probe scope recommended
AN208 vishay siliconix document number: 70606 10-aug-99 www.vishay.com faxback 408-970-5600 6-5 faster turn-on times in the new abo series, t on has been reduced from 480 ns to 120 ns. maxim's best currently available equivalent device, by comparison, has both a slower t on and a glitch with a very slow recovery time (figure 6b). parts like this need a 1.0- s de-glitcher to make them usable. of course, this asolutiono also adds to the cost of implementation. the abo series parts r equire only 300 ns to settle out (figure 6a). improved on-resistance and leakage current while c l can be increased to reduce glitch, this approach can be a problem in sample-and-hold circuits. there is a trade-off between acquisition time and droop-rate. an increase in c l slows the droop-rate but increases the acquisition time. the droop-rate can be understood as the voltage change caused by the sum of the drain-off leakage current (i d(off) ), the capacitor leakage (i c ), which is caused by the dielectric absorption of the capacitor, and the bias current (i b ) if a buffer amplifier is used after the hold capacitor c l . or, dv dt i d(off) i b i c c l for the abo series, typical leakage current at room temperature has been improved from 20 pa to only 10 pa. on-resistance and leakage are critical in determining circuit accuracy. drain-on leakage for abo series devices has been reduced to 20 pa from the industry-standard 150 pa. this current directly increases the error or voltage drop across the channel. this error increases the circuit offset voltage. the error is calculated by: v error = r ds(on) i d(on) for the abo series parts, on-resistance is substantially reduced from 115 to 45 , which also reduces the above error. power consumption the power dissipated by the dg211/212b devices has been reduced to 1 nw typical. competing devices range from 400 nw to 18 mw. the combination of high speed and low power consumption is a unique feature of the new abo series. power consumption is equal to (v+)(i+) + (v)(i) + (v l )(i l ) which is a quiescent condition calculation. this can be added to the channel power when the switch is in a dynamic state. the power consumed by the analog channel is determined by i 2 r where (i) is the current through the channel and (r) is r ds(on) . figure 6. 9 mv 14 mv a) dg201b glitch and hold step due to charge injection b) competitor m's dg201a glitch and hold step v s = 0 v+ = + 15 v v = 15 v c l = 1000 pf 1 = logic input control (logic a1o = off) 2 = v s 3 = v d
AN208 vishay siliconix www.vishay.com faxback 408-970-5600 6-6 document number: 70606 10-aug-99 general applications the abo series general-purpose switches are recommended for ate, instrumentation, communications, and other applications requiring analog signal processing. analog switches can be used just like passive components. for instance, general uses include switches in parallel, switches in series, switches in ainverted l,o and switches in ato configurations. two or more switches can be used in parallel by simply connecting source-to-source, drain-to-drain, and input-to-input (figure 7a). this configuration proportionally increases maximum channel current and reduces on-resistance. for instance, two switches in parallel double the maximum channel current and cut r ds(on) in half. switches in series are sometimes used to increase off-isolation (figure 7b). this approach has a price, however, since on-resistance doubles. a better way to increase off-isolation is the ainverted lo circuit (figure 7c). when the series switch turns off, the shunt switch turns on and clamps the analog signal to ground. this substantially reduces the chance of any signal passing through to the switch output. the ultimate isolation is provided by a ato switch (figure 7d). this configuration is useful when the application calls for a high degree of isolation without grounding the switch input or output. the abo series does not include no and nc switches in the same package, but an spdt circuit can still be easily configured using three spst switches (figure 8). one switch is used as a logic inverter that converts a no switch to a nc switch. then, with no and nc switches, the sources can be connected to form a pole with a double-throw output at the drains. note that the 10-k pull-down resistor will slow the turn-off time to about 800 ns. many of today's applications call for precision single-supply analog switches. the circuit in figure 9 shows a typical inverting op amp circuit with a v = 1. the summing junction (or avirtual ground,o if the amplifier is referenced to ground) is a high z point. as noted above, the ratio r ds(on) /r l can reduce harmonic distortion. if the drain of s1 sees this high z when the switch is closed, distortion is substantially reduced. since the voltage at the summing junction is constant, r ds(on) modulation is eliminated. since this summing point is also at a virtual +2 v (or virtual ground when referenced to ground), it increases the off-isolation. figure 7. general applications in s d in s d in s d in in s d s3 s2 s1 ttl inverter a) parallel switches b) series switches c) inverted alo switches d) ato switches
AN208 vishay siliconix document number: 70606 10-aug-99 www.vishay.com faxback 408-970-5600 6-7 figure 8. design spdt switch with 3 spst +5 v 10 k 1 k analog input 1 k dg201b s2 is used for temperature compensation and tracks the r ds(on) of s1 to minimize gain error. note that s2 is always closed, to avoid disturbing the op amp when s1 opens. the op amp remains closed loop. the reference is set at +2 v to establish a +3-v output offset . the input signal swings 2 vp-p and is offset by +1 v. it was necessary to raise the virtual ground and ensure the amplifier doesn't distort or clip the signal. it is critical that s1 be placed right at the summing point. for instance, if s1 is placed on the other side of the input resistor, that resistor value would set r l instead of the high z of the summing point. also, r on would change, causing distortion. conclusion the vishay siliconix abo series of analog switches offers a high-performance, low-cost solution to many of today's analog signal processing applications. the new abo family has substantially improved the key parameterser ds(on) , i d(on) , t on , p d , and qewithout increasing the price. these new switches are also ideal for many high-speed, high precision, single-supply analog circuit functions. many existing designs can improve circuit performance by simply upgrading to the equivalent abo family device. the improved parameters provide the six key benefits that designers look for: less signal loss higher accuracy higher sample rates faster settling times fewer transients power savings. figure 9. dg201b single supply and summing point (a low distortion single supply summing amplifier) +2 v dg201b s s s1 r r r r l +5 v r v v+ s2 v out +4 v +2 v v out v in 0 v
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