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low cost, 4 - channel, 16 - bit 1 msps pulsar adc ad7655 - ep rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infr ingements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and regis tered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2011 analog devices, inc. all rights reserved. features 4 - channel, 16 - bit resolution adc 2 track - and - hold amplifiers throughput 1 msps ( normal mode) 888 ksps ( i mpulse mode) analog input voltage range: 0 v to 5 v no pipeline delay parallel and serial 5 v/3 v interface spi?/qspi?/microwire?/dsp compati ble single 5 v supply operation power dissipation 120 mw typical 2.6 mw @ 10 ksps 48- lead frame chip scale package (lfcsp) pin - to - pin compatible with the ad7654 low cost supports defense and aerospace applications (aqec standard) military temp eratur e rang e ( ?55c to +125c) controlled manufacturing baseline enhanced product change notification qualification data available on request applications ac motor control 3 - phase power control 4 - channel data acquisition uninterrupted power supplies communications ge neral description the ad7655 - ep is a low cost, simultaneous sampling, dual - cha nnel, 16 - bit, charge redistribution sar, analog - to - digital converter that operates from a single 5 v power supply. it contains two low noise, wide bandwidth, track - and - hold ampli fiers that allow simulta neous sampling, a high speed 16- bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. each track - and - hold has a multiplexer in front to provide a 4 - channel in put adc. the a0 multiplexer control input allows the choice of simulta neously sampling input pairs ina1/inb1 (a0 = low ) or ina2/ inb2 (a0 = high ). the part features a very high sampling rate mode ( n ormal) and, for low functional block dia gram contro l logic and calibr a tion circuit r y a/b 16 d[15:0] bus y cs ser/ p ar ognd ovdd dgnd dvdd seria l port bytes w ap rd a vdd agnd refx refgnd pd reset cnvst inan switched ca p dac ad7655-e p ina1 impulse mux eoc ina2 a0 inb1 inbn inb2 track/hold 2 p aralle l inter f ace clock mux mux 09230-001 figure 1. table 1 . pulsar ? selection type/ksps 100 to 250 500 to 570 800 to 1000 >1000 pseudo differential ad7660 / ad7661 ad7650 / ad7652 ad7664 / ad7666 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differen tial ad7675 ad7676 ad7677 ad7621 ad7623 18 bit ad7678 ad7679 ad7674 ad7641 multichannel/ simultan eous ad7654 ad7655 power applications , a reduced power mode ( i mpulse) where the power is scaled with the throughput. operation is specified from ? 55 c to + 12 5c . full details about this enhanced product are available in the ad7655 data sheet, which should be consulted in conjunction with this data sheet. product highlights 1. multichannel adc. the ad7655 - ep features 4 - ch annel inputs with two samp le - and - hold circuits that allow simultaneous sampling. 2. fast t hroughput. the ad7655 - ep is a 1 msps, charge redistribution, 16 - bit sar adc with internal error correction circuitry. 3. single - supply operation. t he ad7655 - ep operates fr om a single 5 v supply. in im pulse mode, its power dissipation decreases with throughput. 4. serial or parallel interface. versatile parallel or 2 - wire serial interface arrangement s are compat i ble with both 3 v and 5 v logic.
ad7655- ep rev. a | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ...................................................................5 absolute maximum ratings ............................................................7 esd caution ...................................................................................7 pin configuration and function descriptions ..............................8 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 2 / 11 rev. 0 to rev. a removed lqfp from features section ......................................... 1 removed internal power dissipation (700 mw) from table 5 .. 7 7 / 1 0 revision 0: initial version
ad7655- ep rev. a | page 3 of 12 specifications avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v ; v ref = 2.5 v; all specifications t min to t max , unless otherwise noted. table 2 . parameter conditions min typ max unit resolution 16 bits a nalog input voltage range v inx C v inxn 0 2 v ref v common - mode input voltage v inxn ?0.1 +0.5 v analog input cmrr f in = 100 khz 55 db input current 1 msps throughput 45 a input impedance throughput speed complete cycle (2 channels) n ormal mode 2 s throughput rate n ormal mode 0 1 msps complete cycle (2 channels) i mpulse mode 2.25 s throughput rate i mpulse mode 0 888 ksps dc accuracy integral linearity error 1 ?6 +6 lsb 2 no missing codes 15 bits transition noise 0.8 lsb full - scale erro r t min to t max 0.25 0. 5 % of fsr full - scale error drift 2 ppm/c unipolar zero error t min to t max 0.25 % of fsr unipolar zero error drift 0.8 ppm/c power supply sensitivity avdd = 5 v 5% 0.8 lsb ac accuracy signal -to - noise f in = 100 khz 86 db 3 spurious - free dynamic range f in = 100 khz 98 db total harmonic distortion f in = 100 khz ?96 db signal -to - noise and distortion f in = 100 khz 86 db f in = 100 khz, ?60 db i nput 30 db channel - to - channel isolation f in = 100 khz ?92 db ?3 db input bandwidth 10 mhz sampling dynamics aperture delay 2 ns a perture delay matching 30 ps aperture jitter 5 ps rms transient response full - scale step 250 ns reference external reference voltage range 2.3 2.5 avdd/2 v external reference current drain 1 m sps throughput 180 a di gital inputs logic levels v il ?0.3 +0.8 v v ih +2.0 d vdd + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format 4 pipeline delay 5 v ol i sink = 1.6 ma 0.4 v v oh i source = ?500 a ovdd ? 0.2 v
ad7655- ep rev. a | page 4 of 12 parameter conditions min typ max unit power supplies specified performan ce avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 6 v operating current 7 1 msps throughput avdd 15.5 ma dvdd 8.5 ma ovdd 100 a power dissipation 1 msps throughput 7 120 135 mw 20 ksps throughput 8 2.6 mw 888 ksps throughput 8 114 125 mw temperature range 9 specified performance t min to t max ? 55 +12 5 c 1 linearity is tested using endpoints, not best fit. 2 lsb means least significant bit. with the 0 v to 5 v input range, 1 lsb is 76.294 v. 3 all specifications in db are refer red to as full - scale in put, fs . t ested with an input signal at 0.5 db below full scale unless otherwise specified. 4 parallel or serial 16 bit. 5 conversion results are available immediately after completed conversion. 6 the maximum should be the minimum of 5.25 v and dvdd + 0.3 v. 7 in n ormal m ode; tested in parallel reading mode. 8 in impulse mode; tested in parallel reading mode. 9 con sult sales for extended temperature range.
ad7655- ep rev. a | page 5 of 12 timing specification s avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v ; v ref = 2.5 v; all specifications t min to t max , unless otherwise noted. table 3 . parameter symbol min typ max unit conversion and reset co nvert pulse width t 1 5 ns time b etween conversions (normal mode/impulse mode) t 2 2/2.25 s cnvst low to busy high delay t 3 32 ns busy high all modes except in master serial read a fter convert mode (n ormal mode/impulse mode) t 4 1.75/2 s aperture delay t 5 2 ns end of conversions to busy low delay t 6 10 ns conversion time (normal mode/impulse mode) t 7 1.75/2 s acquisition time t 8 250 ns reset pulse width t 9 1 0 ns cnvst low to eoc high delay t 10 30 ns eoc high for channel a conversion (normal mode/impulse mode) t 11 1/1.25 s eoc low after channe l a conversion t 12 45 ns eoc high for channel b conversion t 13 0.75 s channel selection setup time t 14 250 ns channel selection hold time t 15 30 ns parallel interface modes cnvs t low to data valid delay t 16 1.75/2 s data valid to busy low delay t 17 14 ns bus access request to data valid t 18 40 ns bus relinquish time t 19 5 15 ns a/ b low to data valid delay t 20 40 ns master seria l interface modes cs low to sync valid delay t 21 10 ns cs low to internal sclk valid delay 1 t 22 10 ns cs low to sdout delay t 23 10 ns cnvst low to sync delay , read d uring convert (normal mode/impulse mode) t 24 250/500 ns sync asserted to sclk first edge delay t 25 3 ns internal sck period 2 t 26 23 40 ns internal sclk high 2 t 27 12 ns internal sclk low 2 t 28 7 ns sdout valid setup time 2 t 29 4 ns sdout valid hold time 2 t 30 2 ns sclk last edge to sync delay 2 t 31 1 ns cs high to sync h igh -z t 32 10 ns cs high to internal sclk high -z t 33 10 ns cs high to sdout high -z t 34 10 ns busy high in master serial r ead after convert 2 t 35 see table 4 cnvst low to sync asserted delay (normal mode/impulse mode) t 36 0.75/1 s sync deasserted to busy low delay t 37 25 ns
ad7655- ep rev. a | page 6 of 12 parameter symbol min typ max unit slave serial interface modes external sclk setup time t 38 5 ns external sclk active edge to sdout delay t 39 3 18 ns sdin setup time t 40 5 ns sdin hold time t 41 5 ns external sclk period t 42 25 ns externa l sclk high t 43 10 ns external sclk low t 44 10 ns 1 in serial interface modes, the sync, scl k, and sdout timings are defined with a maximum load c l of 10 pf; otherwise c l is 60 pf maximum. 2 in serial master read during convert mode. see table 4 for serial master read after convert mode. table 4 . serial clock timings in master read a fter convert divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 25 3 17 17 17 ns internal sclk period minimum t 26 25 50 100 200 ns internal sclk period typical t 26 40 70 140 280 ns internal sclk high minimum t 27 12 22 50 100 ns internal sclk low minimum t 28 7 21 49 99 ns sdout valid setup time minimum t 29 4 18 18 18 ns sdout valid hold time minimum t 30 2 4 30 80 ns sclk last edge to sync delay minimum t 31 1 3 30 80 ns busy high width maximum (normal) t 35 3.25 4.25 6.25 10.75 s busy high width maximum (impulse) t 35 3.5 4.5 6.5 11 s
ad7655- ep rev. a | page 7 of 12 absolute maximum rat ings table 5 . parameter values analog input inax, inbx, refx, inxn, refgnd avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages av dd, dvdd, ovdd C 0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd ? 0.3 v to +7 v digital inputs ? 0.3 v to dvdd + 0.3 v internal power dissipation 1 2.5 w junction temperature 150 c storage temperature range ?65 c to +150 c lead temperature r ange (soldering 10 sec) 300 c 1 specification is for device in free air : 48 - lead lfcsp, ja = 26 c/w. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated i n the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t o output pin c l 60pf* 500 m a i oh 1.6m a i o l 1.4v *in seria l inter f ace modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; othe r wise, the load is 60pf maximum. 09230-002 figure 2 . load circu it for digital interface timing 0.8v 2v 2v 0.8v t del a y 2v 0.8v t del a y 09230-003 figure 3 . voltage reference levels for timing esd caution
ad7655- ep rev. a | page 8 of 12 pin configuration an d function descripti ons 48 agnd 47 agnd 46 ina1 45 inan 44 ina2 43 re f a 42 refb 41 inb2 40 inbn 39 inb1 38 refgnd 37 ref 35 cnvst 34 pd 33 reset 30 eoc 31 rd 32 cs 36 dvdd 29 bus y 28 d15 27 d14 25 d12 26 d13 2 a vdd 3 a0 4 bytes w ap 7 impulse 6 dgnd 5 a/b 1 agnd 8 ser/ p ar 9 d0 10 d1 12 d3/divsclk[1] 1 1 d2/divsclk[0] 13 d4/ext/int 14 d5/invsync 15 d6/invsclk 16 d7/rdc/sdin 17 ognd 18 ovdd 19 dvdd 20 dgnd 21 d8/sdout 22 d9/sclk 23 d10/sync 24 d1 1/rderror pin 1 ad7655-e p t op view (not to scale) 09230-004 notes 1. paddle connected to gnd. this connection is not required to meet the electrical performances. figure 4. 48 - lead lfcsp (cp - 48 - 1) table 6 . pin function descriptions pin no. mnemonic type 1 description 1, 47, 48 agnd p analog power ground pin. 2 avdd p input analog power pin. nominally 5 v. 3 a0 di multiplexer select. when low, the analog inputs ina1 and inb1 are sampled simultaneously, then converted. when hig h, the analog inputs ina2 and inb2 are sampled simultaneously, then converted. 4 byteswap di parallel mode selection (8 b it, 16 b it). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and t he msb is output on d[7:0]. 5 a/ b di data channel selection. in parallel mode, when low, the data from channel b is read. when high, the data from channel a is read. in serial mode, when high, channel a is output first followed by channel b. when low, channel b is output first followed by channel a. 6, 20 dgnd p digital power ground. 7 impulse di mode selection. when high, this input selects a reduced power mode. in this mode, the power dissipation is approximately prop ortional to the sampling rate. 8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9, 10 d[0:1] do bit 0 and bit 1 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. 11, 12 d[2:3] or di/o when ser/ par is low, these outputs are used as bit 2 and bit 3 of the parallel port data output bus. divsclk[0:1] when ser/ par is high, ext/ int is low, and rdc/sdin is low, which is the serial master read after convert mode . t hese inputs, part of the serial port, are used to slow down the internal serial clock that clocks the data output. in the other serial modes, these inputs are not used. 13 d[4] di/o when ser/ par is low, this output is used as bit 4 of the parallel port data ou tput bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the int ernal or an external data clock called , respectively, master and slave mode. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 d[5] di/ o when ser/ par is low, this output is used as bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sy nc signal in master modes. when low, sync is active high. when high, sync is active low.
ad7655- ep rev. a | page 9 of 12 pin no. mnemonic type 1 description 15 d[6] di/o when ser/ par is low, this output is used as bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both m aster and s lave modes. 16 d[7] di/o when ser/ par is low, this output is used as bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of ext/ int . when ext / int is high, rdc/sdin can be used as a data input to daisy - chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 32 sclk periods after the init iation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the previous data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout onl y when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (5 v or 3 v). 19, 36 dvdd p digital po wer. nominally at 5 v. 21 d[8] do when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used a s a serial data output synchronized to sclk. conversion results are stored in a 32 - bit on - chip register. the ad7655 -ep provides the two conversion results, msb first, from its internal shift register. the order of channel outputs is controlled by a/ b . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on the sclk rising edge and vali d on the next falling edge. if invsclk is high, sdout is updated on the sclk falling edge and valid on the next rising edge. 22 d[9] di/o when ser/ par is low, this output is used as bit 9 of the parallel port data output bu s. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, depend s upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends on the logic state of the invsclk pin. 23 d[10] do when ser/ par is low, this output is used as bit 10 of the parallel port data output bus. or sync when ser/ par is high, this output, p art of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and frames sdout. af ter the first channel is output, sync is pulsed low. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. after the first channel is output, sync is pulsed high. 24 d[11] do when ser/ par is low, this output is used as bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in s lave mode, when a data read is started but not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25 to 28 d[12:15] do bit 12 to bit 15 of the parallel port data ou tput bus. when ser/ par is high, these outputs are in high impedance. 29 busy do busy output. transitions high when a conversion is started and remains high until the two conversions are complete and the data is latched into the on - chip shift register. the falling edge of busy can be used as a data ready clock signal. 30 eoc do end of convert output. goes low at each channel conversion. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface paral lel or serial output bus is enabled. cs is also used to gate the external serial clock. 33 reset di reset input. when set to a logic high, reset the ad7655 -ep . current conversion , if any , is aborted. if not used, this pin could be tied to dgnd. 34 pd di power - down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current conversion is completed.
ad7655- ep rev. a | page 10 of 12 pin no. mnemonic type 1 description 35 cnvst di start conversion. a falling edge on cnvst puts the internal sample - and - hold into the hold state and initiates a conversion. in impulse mode (impulse = high), if cnvst is held low when the acquisition phase (t 8 ) is complete, the internal sample - and - hold is put into the hold state and a conversion is immediately started. 37 ref ai this input pin is used to provide a reference to the converter. 38 refgnd ai reference input analog ground. 39, 41 inb1, inb 2 ai channel b analog inputs. 40, 45 inbn, inan ai analog inputs ground senses. allow to sense each channel ground independently. 42, 43 refb, refa ai these inputs are the references applied to channel a and channel b, respectively. 44, 46 in a2, ina1 ai channel a analog inputs. 1 a l = input; di = digital input; do = d igital o utput ; di/o = b idirectional d igital ; p = p ower .
ad7655- ep rev. a | page 11 of 12 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 080108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 5. 48 - lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp - 48 - 1) dimensions shown in millimeters ordering guide model temperature range package description package option ad7655s cp -ep -rl ?55 c to + 12 5c 48- lead lead frame chip scale package ( lfcsp _vq) cp -48-1
ad7655- ep rev. a | page 12 of 12 notes ? 2010 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09230 - 0- 2/11(a)

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