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peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 1 of 15 product description figure 1. block diagram product specification pe9601 2.2 ghz integer-n pll for rad hard applications features ? 2.2 ghz operation ? 10/11 prescaler ? internal phase detector with charge pump ? serial, parallel or hardwired programmable ? low power ? 25 ma at 3 v ? targeted at q3236 pll replacement ? 100 krad total dose ? 44-lead clcc peregrine?s pe9601 is a high performance integer-n pll capable of frequency synthesis up to 2.2 ghz. the device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space plls. the pe9601 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in figure 1. counter values are programmable through either a serial or parallel interface and can also be directly hard wired. the pe9601 is optimized for commercial space applications. single event latch up (sel) is physically impossible and single event upset (seu) is better than 10 -9 errors per bit/day. fabricated in peregrine?s p atented utsi? (ultra thin silicon) cmos technology, the pe9601 offers excellent rf performance and intrinsic radiation tolerance. f in f in prescaler 10/11 20 main counter 20 secon- dary 20-bit latch 20 primary 20-bit latch pre_en m(6:0) a(3:0) r(3:0) 16 20 r counter f r phase detector 6 6 f c f p 8 d(7:0) 13 sdata pd_u pd_d charge pump cp
pe9601 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0025~02c | utsi ? cmos rfic solutions page 2 of 15 figure 2. pin configuration table 1. pin descriptions pin no. pin name interface mode type description 1 v dd all (note 1) power supply input. input may range from 2.85 v to 3.15 v. bypassing recommended. 2 r 0 direct input r counter bit0 (lsb). 3 r 1 direct input r counter bit1. 4 r 2 direct input r counter bit2. 5 r 3 direct input r counter bit3. 6 gnd all (note 1) ground. d 0 parallel input parallel data bus bit0 (lsb). 7 m 0 direct input m counter bit0 (lsb). 8 d 1 parallel input parallel data bus bit1. m 1 direct input m counter bit1. 9 d 2 parallel input parallel data bus bit2. m 2 direct input m counter bit2. 10 d 3 parallel input parallel data bus bit3. m 3 direct input m counter bit3. 11 v dd all (note 1) same as pin 1. 12 v dd all (note 1) same as pin 1. 11 12 13 14 15 16 17 10 9 8 7 6543214443424140 35 34 33 32 31 30 29 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 d 0 , m 0 d 1 , m 1 d 2 , m 2 d 3 , m 3 v dd v dd s_wr, d 4 , m 4 sdata, d 5 , m 5 sclk, d 6 , m 6 fsels, d 7 , pre_en gnd gnd f p v dd _f p d out v dd c ext v dd cp n/c v dd _f c f c f in f in hop_wr a_wr m1_wr v dd bmode smode, a 3 m2_wr, a 2 e_wr, a 1 fselp, a 0 gnd r 3 r 2 r 1 r 0 v dd enh ld fr gnd gnd
pe9601 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 3 of 15 pin no. pin name interface mode type description s_wr serial input serial load enable input. while s_wr is ?low?, sdata can be serially clocked. primary register data are transferred to the secondary register on s_wr or hop_wr rising edge. d 4 parallel input parallel data bus bit4 13 m 4 direct input m counter bit4 sdata serial input binary serial data input. input data entered msb first. d 5 parallel input parallel data bus bit5. 14 m 5 direct input m counter bit5. sclk serial input serial clock input. sdata is clocked serially into the 20-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e_wr ?high?) on the rising edge of sclk. d 6 parallel input parallel data bus bit6. 15 m 6 direct input m counter bit6. fsels serial input selects contents of primary register (fsel s=1) or secondary register (fsels=0) for programming of internal counters while in serial interface mode. d 7 parallel input parallel data bus bit7 (msb). 16 pre_en direct input prescaler enable, active ?low?. when ?high?, f in bypasses the prescaler. 17 gnd all ground. fselp parallel input selects contents of primary register (fsel p=1) or secondary register (fselp=0) for programming of internal counters while in parallel interface mode. 18 a 0 direct input a counter bit0 (lsb). serial input enhancement register write enable. while e_wr is ?high?, sdata can be serially clocked into the enhancement register on the rising edge of sclk. e_wr parallel input enhancement register write. d[7:0] are latched into the enhancement register on the rising edge of e_wr. 19 a 1 direct input a counter bit1. m2_wr parallel input m2 write. d[3:0] are latched into the primary register (r[5:4], m[8:7]) on the rising edge of m2_wr. 20 a 2 direct input a counter bit2. smode serial, parallel input selects serial bus interface mode ( bmode =0, smode=1) or parallel interface mode ( bmode =0, smode=0). 21 a 3 direct input a counter bit3 (msb). 22 bmode all input selects direct interface mode ( bmode =1). 23 v dd all (note 1) same as pin 1. 24 m1_wr parallel input m1 write. d[7:0] are latched into the primary register ( pre_en , m[6:0]) on the rising edge of m1_wr. 25 a_wr parallel input a write. d[7:0] are latched into the primary register (r[3:0], a[3:0]) on the rising edge of a_wr. 26 hop_wr serial, parallel input hop write. the contents of the primary register are latched into the secondary register on the rising edge of hop_wr. 27 f in all input prescaler input from the vco. input voltage = 223 mv rms for guaranteed operation. 28 f in all input prescaler complementary input. a bypass capacitor should be pl aced as close as possible to this pin and be connected directly to the ground plane. 29 gnd all ground.
pe9601 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0025~02c | utsi ? cmos rfic solutions page 4 of 15 pin no. pin name interface mode type description 30 f p all output monitor pin for main divider output. switching activity can be disabled through enhancement register programming or by floating or grounding v dd pin 31. 31 v dd -f c all (note 2) v dd for f c . 32 dout serial, parallel output data out. the msel signal and the raw prescaler output are available on dout through enhancement register programming. 33 v dd all (note 1) same as pin 1. 34 cext all output logical ?or? of pd_u and pd_d terminated through an on chip, 2 k ? series resistor. connecting cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld. 35 v dd all (note 1) same as pin 1. 36 cp all output charge pump current is sourced for ?up? when f c leads f p and sinked for ?down? when f c lags f p . 37 nc all no connection. 38 v dd -f p all (note 2) v dd for f p 39 f c all output monitor pin for reference divider output. switching activity can be disabled through enhancement register programming or by floating or grounding v dd pin 38. 40 gnd all ground. 41 gnd all ground. 42 f r all input reference frequency input. see figure 3. 43 ld all output, od lock detect and open drain logical inversion of cext. when the loop is in lock, ld is high impedance, otherwise ld is a logic low (?0?). 44 enh serial, parallel input enhancement mode. when asserted low (?0?), enhancement register bits are functional. note 1: v dd pins 1, 11, 12, 23, 33, and 35 are connected by diodes and must be supplied with the same positive voltage level. note 2: v dd pins 31 and 38 are used to enable test modes and should be left floating. figure 3. looking into the device pin 42 - f r 2.8pf 125k pin 42
pe9601 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 5 of 15 table 2. absolute maximum ratings symbol parameter/conditions min max units v dd supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v i i dc into any input -10 +10 ma i o dc into any output -10 +10 ma t stg storage temperature range -65 150 c table 3. operating ratings symbol parameter/conditions min max units v dd supply voltage 2.85 3.15 v t a operating ambient temperature range -40 85 c table 4. esd ratings symbol parameter/conditions level units v esd esd voltage (human body model) ? note 1 1000 v note 1: periodically sampled, not 100% tested. tested per mil- std-883, m3015 c2 electrostatic discharge (esd) precautions when handling this utsi device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 4. latch-up avoidance unlike conventional cmos devices, utsi cmos devices are immune to latch-up.
pe9601 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0025~02c | utsi ? cmos rfic solutions page 6 of 15 table 5. dc characteristics v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified symbol parameter test program name conditions min typ max units i dd operational supply current; prescaler enabled 2 ghz center frequency with 10 mhz reference input. idd_t_oper_at_2 ghz v dd = 2.85 to 3.15 v 25 ma digital inputs: all except f r , r 0 , f in , f in v ih high level input voltage levels_?xxx?_vih(v) where ?xxx? is name of pin being tested v dd = 2.85 to 3.15 v 0.7 x v dd v v il low level input voltage levels_?xxx?_vil(v) where ?xxx? is name of pin being tested v dd = 2.85 to 3.15 v 0.3 x v dd v i ih high level input current iih_?xxx?_(a) where ?xxx? is name of pin being tested v ih = v dd = 3.15 v +1 a i il low level input current iil_?xxx?_(a) where ?xxx? is name of pin being tested v il = 0, v dd = 3.15 v -1 a reference divider input: f r i ihr high level input current iih_fr_(a) v ih = v dd = 3.15 v +100 a i ilr low level input current iil_fr_(a) v il = 0, v dd = 3.15 v -100 a r0 input (pull-up resistor): r 0 i ihr high level input current iih_r0_(a) v ih = v dd = 3.15 v +5 a i ilr low level input current iil_r0_(a) v il = 0, v dd = 3.15 v -5 a counter and phase detector outputs: f c , f p . v old output voltage low levels_?xxx?_vol(v) where ?xxx? is name of pin being tested i out = 6 ma 0.4 v v ohd output voltage high levels_?xxx?_voh(v) where ?xxx? is name of pin being tested i out = -3 ma v dd - 0.4 v lock detect outputs: cext, ld v olc output voltage low, cext levels_cext_vol(v) i out = 0.1 ma 0.4 v v ohc output voltage high, cext levels_cext_voh(v) i out = -0.1 ma v dd - 0.4 v v olld output voltage low, ld levels_cext_vol(v) i out = 1 ma 0.4 v charge pump output: cp i cp - source drive current cp_src_at_0.5 vdd (a) v cp = v dd / 2 -2.6 -2 -1.4 ma i cp ? sink drive current cp_snk_at_0.5 vdd (a) v cp = v dd / 2 1.4 2 2.6 ma i cpl leakage current cp_lkg_pd_dx (a) 1.0 v < v cp < v dd ? 1.0 v -1 1 a i cp ? source vs. i cp sink sink vs. source mismatch cp_srcvsnk_at_0.5 vdd v cp = v dd / 2, t a = 25 c 15 % i cp vs. v cp output current magnitude variation vs. voltage cp_snk_var, cp_src_var v < v cp < v dd ? 1.0 v t a = 25 c 15 %
pe9601 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 7 of 15 table 6. ac characteristics v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified symbol parameter test program name conditions min max units control interface and latches (see figures 4, 5, 6) f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time t_clkh (s) 30 ns t clkl serial clock low time t_clkl (s) 30 ns t dsu sdata set-up time after sclk rising edge, d[7:0] set-up time to m1_wr, m2_wr, a_wr, e_wr rising edge t_dsu_?xxx? (s) where ?xxx? is name of pin being tested 10 ns t dhld sdata hold time after sclk rising edge, d[7:0] hold time to m1_wr, m2_wr, a_wr rising edge t_dhid_?xxx? (s) where ?xxx? is name of pin being tested 10 ns t pw s_wr, m1_wr, m2_wr, a_wr, e_wr pulse width t_pw_?xxx? (s) where ?xxx? is name of pin being tested 30 ns t cwr sclk rising edge to s_wr rising edge. s_wr, m1_wr, m2_wr, a_wr falling edge to hop_wr rising edge t_cwr_?xxx? (s) where ?xxx? is name of pin being tested 30 ns t ce sclk falling edge to e_wr transition t_ce (s) 30 ns t wrc s_wr falling edge to sclk rising edge. hop_wr falling edge to s_wr, m1_wr, m2_wr, a_wr rising edge t_wrc_?xxx? (s) where ?xxx? is name of pin being tested 30 ns t ec e_wr transition to sclk rising edge t_ec (s) 30 ns main divider (including prescaler) f in operating frequency rf_sens 200 2200 mhz p fin input level range rf_sens external ac coupling 0 5 dbm main divider (prescaler bypassed) f in operating frequency 20 220 mhz p fin input level range external ac coupling -5 5 dbm reference divider f r operating frequency fc_sens (note 3) 100 mhz p fr reference input power (note 2) fc_sens single ended input -2 dbm phase detector f c comparison frequency (note 3) 20 mhz note 1: fclk is verified during the functional pattern test. serial pr ogramming sections of the functional pattern are clocked at 10 m hz to verify fclk specification. note 2: cmos logic levels can be used to drive reference input if dc coupled. voltage input needs to be a minimum of 0.5v p-p . note 3: parameter is guaranteed through characterization only and is not tested.
pe9601 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0025~02c | utsi ? cmos rfic solutions page 8 of 15 functional description the pe9601 consists of a prescaler, counters, a phase detector, a charge pump and control logic. the dual modulus prescaler divides the vco frequency by either 10 or 11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. an additional counter (?a?) is used in the modulus select logic. the phase-frequency detector generates up and down frequency control signals, which are implemented as a pulse width modulated current by the charge pump. the control logic includes a selectable chip interface. data can be written via serial bus, parallel bus, or hardwired direct to the pins. there are also various operational and test modes and lock detect. figure 4. functional block diagram control logic modulus select 10/11 prescaler m counter (9-bit) r counter (6-bit) phase detector 2 k ? f c pd_u pd_d ld cext f p r(5:0) m(8:0) a (3:0) d(7:0) sdata control pins f r f in charge pump cp f in
pe9601 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 9 of 15 main counter chain the main counter chain divides the rf input frequency, f in , by an integer derived from the user defined values in the ?m? and ?a? counters. it is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9 bit m counter. setting pre_en ?low? enables the 10/11 prescaler. setting pre_en ?high? allows f in to bypass the prescaler and powers down the prescaler. the output from the main counter chain, f p , is related to the vco frequency, f in , by the following equation: f p = f in / [10 x (m + 1) + a] (1) where a m + 1, m 0 when the loop is locked, f in is related to the reference frequency, f r , by the following equation: f in = [10 x (m + 1) + a] x (f r / (r+1)) (2) where a m + 1, m 0 a consequence of the upper limit on a is that f in must be greater than or equal to 90 x (f r / (r+1)) to obtain contiguous channels. programming the m counter with the minimum value of ?1? will result in a minimum m counter divide ratio of ?2?. in direct interface mode, main counter inputs m 7 and m 8 are internally forced low. reference counter the reference counter chain divides the reference frequency, f r , down to the phase detector comparison frequency, f c . the output frequency of the 6 bit r counter is related to the reference frequency by the following equation: f c = f r / (r + 1) (3) where r > 0 note that programming r equal to ?0? will pass the reference frequency, f r , directly to the phase detector. in direct interface mode, r counter inputs r 4 and r 5 are internally forced low (?0?). register programming parallel interface mode parallel interface mode is selected by setting the bmode input ?low? and the smode input ?low?. parallel input data, d[7:0], are latched in a parallel fashion into one of three, 8-bit primary register sections on the rising edge of m1_wr, m2_wr, or a_wr per the mapping shown in table 7 on page 10. the contents of the primary register are transferred into a secondary register on the rising edge of hop_wr according to the timing diagram shown in figure 4. data are transferred to the counters as shown in table 7 on page 10. the secondary register acts as a buffer to allow rapid changes to the vco frequency. this double buffering for ?ping-pong? counter control is programmed via the fselp input. when fselp is ?high?, the primary register contents set the counter inputs. when fselp is ?low?, the secondary register contents are utilized. parallel input data, d[7:0], are latched into the enhancement register on the rising edge of e_wr according to the timing diagram shown in figure 4. this data provides control bits as shown in table 8 on page 10 with bit functionality enabled by asserting the enh input ?low?. serial interface mode serial interface mode is selected by setting the bmode input ?low? and the smode input ?high?. while the e_wr input is ?low? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 19 , are clocked serially into the primary register on the rising edge of sclk, msb (b 0 ) first. the contents from the primary register are transferred into the secondary register on the rising edge of either s_wr or hop_wr according to the timing diagram shown in figures 4-5. data are transferred to the counters as shown in table 7 on page 10. the double buffering provided by the primary and secondary registers allows for ?ping-pong? counter control using the fsels input. when fsels is ?high?, the primary register contents set the counter inputs. when fsels is ?low?, the secondary register contents are utilized. while the e_wr input is ?high? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 7 , are clocked serially into the enhancement register on the rising edge of sclk, msb (b 0 ) first. the enhancement register is double buffered to prevent
pe9601 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0025~02c | utsi ? cmos rfic solutions page 10 of 15 inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of e_wr according to the timing diagram shown in figure 5. after the falling edge of e_wr, the data provide control bits as shown in table 8 with bit functionality enabled by asserting the enh input ?low?. direct interface mode direct interface mode is selected by setting the bmode input ?high?. counter control bits are set directly at the pins as shown in table 7. in direct interface mode, main counter inputs m 7 and m 8 , and r counter inputs r 4 and r 5 are internally forced low (?0?). table 7. primary register programming interface mode enh bmode smode r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 m2_wr rising edge load m1_wr rising edge load a_wr rising edge load parallel 1 0 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 serial* 1 0 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 direct 1 1 x 0 0 0 0 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 *serial data clocked serially on sclk rising edge while e_wr ?low? and captured in secondary register on s_wr rising edge. msb (first in) (last in) lsb table 8. enhancement register programming interface mode enh bmode smode reserved reserved reserved power down counter load msel output prescaler output f c , f p oe e_wr rising edge load parallel 0 x 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 serial* 0 x 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 *serial data clocked serially on sclk rising edge while e_wr ?high? and captured in the double buffer on e_wr falling edge. msb (first in) (last in) lsb
pe9601 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 11 of 15 figure 5. parallel interface mode timing diagram figure 6. serial interface mode timing diagram t dhld t dsu t pw t cwr t wrc t pw d m1_wr m2_wr a_wr e_wr hop_wr [] 0 : 7 t dhld t dsu t clkh t clkl t cwr t pw t wrc t ec t ce e_wr sdata sclk s_wr
pe9601 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0025~02c | utsi ? cmos rfic solutions page 12 of 15 enhancement register the functions of the enhancement register bits ar e shown below with all bits active ?high?. table 9. enhancement register bit functionality bit function description bit 0 reserved** bit 1 reserved** bit 2 reserved** bit 3 power down power down of all f unctions except programming interface. bit 4 counter load immediate and continuous load of counter programming as directed by the bmode and smode inputs. bit 5 msel output drives the internal dual modulus prescaler modulus select (msel) onto the dout output. bit 6 prescaler output drives the raw internal prescaler output (fmain) onto the dout output. bit 7 f p , f c oe f p , f c outputs disabled. ** program to 0 phase detector the phase detector is triggered by rising edges from the main counter (f p ) and the reference counter (f c ). it has two outputs, namely pd_ u , and pd_ d . if the divided vco leads the divided reference in phase or frequency (f p leads f c ), pd_ d pulses ?high?. if the divided reference leads the divided vco in phase or frequency (f r leads f p ), pd_ u pulses ?high?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . the signals from the phase detector couple directly to a charge pump. pd_ u controls a current source at pin cp with constant amplitude and pulse duration approximately the same as pd_ u . pd_ d similarly drives a current sink at pin cp. the current pulses from pin cp are low pass filtered externally and then connected to the vco tune voltage. pd_ u pulses result in a current source, which increases the vco frequency and pd_ d results in a current sink, which decreases vco frequency. a lock detect output, ld is also provided, via the pin cext. cext is the logical ?or? of pd_ u and pd_ d waveforms, which is driven through a series 2 kohm resistor. connecting cext to an external shunt capacitor provides integration. cext also drives the input of an internal inverting comparator with an open drain output. thus ld is an ?nor? function of pd_ u and pd_ d .
pe9601 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 13 of 15 figure 7. package drawing all dimensions are in mils
pe9601 product specification copyright ? peregrine semiconductor corp. 2001 file no. 70/0025~02c | utsi ? cmos rfic solutions page 14 of 15 table 10. ordering information order code part marking description package shipping method 9601-11 pe9601 flight units 44-pin cqfj 40 units / tray 9601-00 pe9601ek evaluation board 1 / box
pe9601 product specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2001 page 15 of 15 sales offices united states peregrine semiconductor corp. 6175 nancy ridge drive san diego, ca 92121 tel 1-858-455-0660 fax 1-858-455-0770 japan peregrine semiconductor k.k. the imperial tower, 15th floor 1-1-1 uchisaiawaicho, chiyoda-ku tokyo 100-0011 japan tel: 03-3507-5755 fax: 03-3507-5601 europe peregrine semiconductor europe aix-en-provence office parc club du golf, bat 9 13856 aix-en-provence cedex 3 france tel 33-0-4-4239-3360 fax 33-0-4-4239-7227 australia peregrine semiconductor australia 8 herb elliot ave. homebush, nsw 2140 australia tel: 011-61-2-9763-4111 fax: 011-61-2-9746-1501 for a list of representatives in your area, please refer to our web site at: http://www.peregrine-semi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target s pecifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. pe regrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a pcn (product change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. peregrine products are protected under one or more of the following u.s. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. other patents may be pending or applied for. utsi, the peregrine logotype, sel safe, and peregrine se miconductor corp. are registered trademarks of peregrine semiconductor corp. all pe product names and prefixes are trademarks of peregrine semiconductor corp. copyright ? 2001 peregrine semic onductor corp. all rights reserved.

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