k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 1 ver. 1 ..5 preliminary description the kawasaki usb to serial enables your system to have the capability to communicate between the usb (universal serial bus) port and up to four serial port peripherals. this device meets the usb 1.0/1.1 and standard serial port specifications. all the advantages of usb are available to peripherals with serial port interface such as plug and play capabilities. with the usb standard of high-speed data transfers, this device is ideal for connections. kawasaki?s device and software enable the usb interface to be transparent to the peripheral and requires no firmware changes. this makes it possible for peripherals with serial interfaces to easily interface with usb with minimum modifications. this feature is ideal for legacy applications. features advanced 16 bit processor for usb transaction processing and control data processing compliant with the usb 1.0/1.1 (universal serial bus) 1 serial port 115kbps rate plug and play compatible i 2 c interface utilizes low cost external crystal circuitry 1.5k x 16 internal ram buffer for fast communications usb host device drivers available single-chip solution in a 100 pin qfp block diagram pll & clock generator 16 bit address / data bus 16 bit processor serial interface engine ram (3kb) timer 0 usb interface mask rom eeprom serial interface timer 1 data + data - x1 x2 ck dio watchdog timer i 2 c dio ck serial interface dtr rts dcd dsr txd rxd cts ri
k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 2 ver. 1 ..5 preliminary kl5kusb xxxx application block diagram pin diagram 100qfp xd15 vdd1 0vdd1 agnd n/c n/c n/c n/c n/c n/c n/c n/c n/c avdd gnd rts dsr dtr cts ri dcd n/c n/c txd ugnd vp1 vm1 uvdd n/c n/c gndp vco_in cp_out vddp pllen rxd irq1 irq2 n/c n/c n/c n/c xa20 xa19 pu#1 n/c n/c dgnd clk x2 xa10 xa9 xa8 xa7 xa6 xa5 xa4 xa3 xa2 xa1 ntst nreset nxrdmsel nxrd nxrd gnd1 n/c n/c n/c n/c n/c n/c n/c ignd xbhe xa0 xa14 0vdd vdd xa15 xd14 dgnd1 xd13 xd12 ignd1 xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 xa13 xa12 xa11 KL5KUSB105 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 optional external memory serial port usb serial device serial eeprom kl5kusbxxx usb to serial
k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 3 ver. 1 ..5 preliminary pin description pin # qfp i/o pin name description 1 in/out xd15 external data pins 2 vdd1 vdd 3 0vdd1 vdd 4 agnd gnd 5 n/c n/c n/c 6 n/c n/c n/c 7 n/c n/c n/c 8 n/c n/c n/c 9 n/c n/c n/c 10 n/c n/c n/c 11 n/c n/c n/c 12 n/c n/c n/c 13 n/c n/c n/c 14 avdd vdd 15 gnd gnd 16 out rts request to send 17 in dsr data set ready 18 out dtr data transmit ready 19 in cts clear to send 20 in ri ring indicate 21 in dcd data carrier detect 22 n/c n/c n/c 23 n/c n/c n/c 24 out txd transmit data 25 ugnd usb gnd 26 in/out vp1 usb +pin 27 in/out vm1 usb -pin 28 uvdd usb vdd 29 n/c n/c n/c 30 n/c n/c n/c 31 gndp gnd 32 in vco_in pll vco in 33 out cp_out pll vco out 34 vddp vdd 35 in pllen pll enable 36 in rxd receive data 37 in irq1 n/c 38 in irq2 n/c 39 n/c n/c 40 n/c n/c 41 n/c n/c 42 n/c n/c 43 out xa_20 external address pins
k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 4 ver. 1 ..5 preliminary pin # qfp i/o pin name description 44 out xa_19 external address pins 45 pu#1 connected to pullup resistor 46 n/c n/c 47 n/c n/c 48 dgnd gnd 49 in clk 12mhz clock/crystal input 50 out x2 12mhz crystal output 51 out xa15 external address pins 52 vdd vdd 53 0vdd vdd 54 out xa14 external address pins 55 out xa0 external address pins 56 out nxbhe n/c - external byte high enable (active low) 57 ignd gnd 58 n/c n/c 59 n/c n/c 60 n/c n/c 61 n/c n/c 62 n/c n/c 63 n/c n/c 64 n/c n/c 65 gnd1 gnd 66 out nxrd external memory read (active lo) 67 out nxwr external memory write (active lo) 68 out nxromsel external rom cs (active lo) 69 out nreset reset pin 70 out ntst test pin, disconnect for normal operation 71 out xa1 external address pins 72 out xa2 external address pins 73 out xa3 external address pins 74 out xa4 external address pins 75 out xa5 external address pins 76 out xa6 external address pins 77 out xa7 external address pins 78 out xa8 external address pins 79 out xa9 external address pins 80 out xa10 external address pins 81 out xa11 external address pins 82 out xa12 external address pins 83 out xa13 external address pins 84 in/out xd0 external data pins 85 in/out xd1 external data pins 86 in/out xd2 external data pins 87 in/out xd3 external data pins 88 in/out xd4 external data pins 89 in/out xd5 external data pins 90 in/out xd6 external data pins 91 in/out xd7 external data pins 92 in/out xd8 external data pins
k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 5 ver. 1 ..5 preliminary pin # qfp i/o pin name description 93 in/out xd9 external data pins 94 in/out xd10 external data pins 95 in/out xd11 external data pins 96 ignd1 gnd 97 in/out xd12 external data pins 98 in/out xd13 external data pins 99 dgnd1 gnd 100 in/out xd14 external data pins function description 16 bit processor the integrated 16 bit processor serves as a micro controller for usb peripherals. the processor can execute approximately five million instructions per second. with this processing power it allows the design of intelligent peripherals that can process data prior to passing it on to the host pc, thus improving overall performance of the system. the masked rom in the this device or external memory contains a specialized instruction set that has been designed for highly efficient coding of processing algorithms and usb transaction processing. the 16-bit processor is designed for efficient data execution by having direct access to the ram buffer, external memory, i/o interfaces, and all the control and status registers the processor supports prioritized vectored hardware interrupts and has as many as 240 software interrupt vectors. the processor provides six addressing modes, supporting memory-to-memory, memory-to- register, register-to-register, immediate-to-register or immediate-to-memory operations. register, direct, immediate, indirect, and indirect indexed addressing modes are supported. in addition, there is an auto-increment mode in which a register, used as an address pointer is automatically incremented after each use, making repetitive operations more efficient both from a programming and a performance standpoint. the processor features a full set of program control, logical, and integer arithmetic instructions. all instructions are sixteen bits wide, although some instructions require operands, which may occupy another one or two words. several special ? short immediate? instructions are available, so that certain frequently used operations with small constant operand will fit into a 16-bit instruction. ram buffer the usb controller contains internal buffer memory. the memory is used to buffer data and usb packets and accessed by the 16 bit processor and the sie. usb transactions are automatically routed to the memory buffer. the 16-bit processor has the ability to set up pointers and block
k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 6 ver. 1 ..5 preliminary sizes in buffer memory for usb transactions. data is read from the interface and is processed and packetized by the 16-bit i/o processor. pll clock generator the pll circuitry is provided to generate the internal 48mhz clock requirements. this circuitry is designed to allow use of a low cost 12 mhz external crystal which is connected to the usb3 pins x1 and x2. if an external 12 mhz clock is available in the application, it may be used in lieu of the crystal circuit and connected directly to the x1 input pin. usb interface the usb controller meets the universal serial bus (usb) specification ver 1.0 and 1.1. the transceiver is capable of transmitting and receiving serial data at the usb?s full speed, 12 mbits/sec data rate. the driver portion of the transceiver is differential, while the receive section is comprised of a differential receiver and two single ended receivers. internally, the transceiver interfaces to the sie logic. externally, the transceiver connects to the physical layer of the usb. uart serial interface the uart can be configured for a wide selection of baud rates, 300 to 230.4 k baud, and support a set of control signals. each uart provides a means for external serial devices to access the usb. serial eeprom support the usb controller serial interface is used to provide access to external eeprom?s. the interface can support a variety of serial eeprom formats.
k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 7 ver. 1 ..5 preliminary electrical characteristics absolute maximum ratings parameter symbol ratings unit v dd5 -0.6 to 6.0 v supply voltage v dd -0.3 to 4.0 v -0.6 to v dd5 +0.6 v v in (normal) -0.3 to v dd +0.3 v input voltage v in (5v tolerant) -0.3 to 7.3 v dc output current i out 30 ma storage temperature tstg -55 to 125 ** c **plastic package dc characteristics and conditions (v dd5 @ 3v .3v) value symbol parameter condition min typ max unit v dd5 supply voltage - 3.0 3.3 3.6 v v ih input high voltage cmos 2.15 - - v v il input low voltage cmos - - 0.95 v ttl schmitt 1.32 1.75 v v+ input high voltage cmos schmitt 2.17 2.65 v ttl schmitt 0.45 0.86 - v v- input low voltage cmos schmitt 0.50 1.03 - v ttl schmitt 0.25 - - v v h hysteresis voltage cmos schmitt 0.56 - - v i ih input high current v in = v dd5 -10 - 10 m a i il input low current v in = v ss -10 - 10 m a v oh output high voltage i oh = -4ma 2.4 - - v v ol output low voltage i ol = 4ma - - 0.4 v v ol =v dd5 -10 - 10 m a i oz 3-state leakage current v in =v ss -12 -34 -100 m a *idds is design dependent august 1998 copyright 1998 kawasaki lsi printed in u.s.a kawasaki lsi assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice form kawasaki lsi
k usb to serial kawasaki lsi kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 8 ver. 1 ..5 preliminary august 1998 copyright 1998 kawasaki lsi printed in u.s.a kawasaki lsi assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice form kawasaki lsi
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