View SP8503_7870206.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

43 n 3 m s, 5 m s or 10 m s sample/conversion time n standard 10v and 5v input n no missing codes over temperature n ac performance over temperature 71.5db signalCtoCnoise ratio at nyquist 85db spuriousCfree dynamic range at 49khz C81db total harmonic distortion at 49khz n internal sample/hold, reference, clock, and 3-state outputs n low power dissipation: 90mw n 28Cpin narrow pdip and soic description the sp85xx series are complete 12-bit sampling a/d converters using stateCofCtheCart cmos structures. they contain a complete 12Cbit successive approximation a/d converter with internal sample/hold, reference, clock, digital interface for microprocessor control, and threeCstate output drivers. power dissipation is only 90mw. ac and dc performance are completely specified. sampling/conversion rates of 3 m s, 5 m s and 10 m s are offered. ..... ..... ..... ..... ?0v cs r/c hbe i bip in ?v in internal ref control logic clock comparator three state parallel output data bus busy cdac v ref out (1.2043v) sar output latches and three state drivers SP8503, sp8505, sp8510 12-bit sampling a/d converters free datasheet http:///
44 absolute maximum ratings these are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v s to digital common ............................................................... +7v pin 26 (v so ) to pin 27 (v sa ) .................................................... 0.3v analog common to digital common ...................................... 0.3v control inputs to digital common ....................... C0.3 to v s + 0.3 v analog input voltage ........................................................... 16.5v maximum junction temperature ........................................... 160 c internal power dissipation .................................................. 750mw lead temperature (soldering, 10s) ..................................... +300 c thermal resistance. ? ja : plastic dip ....................................................................... 50 c/w soic .............................................................................. 100 c/w specifications (t a = 25 c; sampling frequency, f s , = 333khz for SP8503, 200khz for sp8505, 100khz for sp8510, v s = +5v, unless otherwise specified.) parameter min. typ. max. units conditions analog input voltage ranges 10v/ 5v v impedance 10v range 4.7 6.7 8.7 k w t min t a t max 5v range 2.7 3.9 5.1 k w t min t a t max dc performance full scale error externally adjustable to zero; Ck 0.1 0.50 % t min t a t max integral linearity error note 1 Ck 0.35 0.75 lsb differential linearity error Ck 0.35 0.95 lsb no missing codes guaranteed bipolar zero externally adjustable to zero Ck 1 5 lsb t min t a t max voltage reference voltage output 1.1440 1.2043 1.2645 v output source current 100 m a output resistance 280 w ac performance t min t a t max SP8503 conversion time 2.6 m s complete cycle 3.0 m s throughput rate 333 khz spurious-free dynamic range note 2 @ 49khz 85 db @ 161khz 72 db total harmonic distortion note 2 @ 49khz C81 db @ 161khz C71 db signal to noise ratio (snr) note 2 @ 49khz 71.5 db @ 161khz 71.5 db signal to (noise + distortion) ratio note 2 @ 49khz 71 db @ 161khz 68 db sp8505 conversion time 4.5 m s complete cycle 5.0 m s throughput rate 200 khz spurious-free dynamic range note 2 @ 49khz 85 db @ 97khz 77 db free datasheet http:///
45 specifications (continued) (t a = 25 c; sampling frequency, f s , = 333khz for SP8503, 200khz for sp8505, 100khz for sp8510, v s = +5v, unless otherwise specified.) parameter min. typ. max. units conditions ac performance t min t a t max sp8505 total harmonic distortion note 2 @ 49khz C81 db @ 97khz C76 db signal to noise ratio (snr) note 2 @ 49khz 71.5 db @ 97khz 71.5 db signal to (noise + distortion) ratio note 2 @ 49khz 71 db @ 97khz 70 db sp8510 conversion time 9.5 m s complete cycle 10.0 m s throughput rate 100 khz spurious-free dynamic range 85 db @ 49khz; note 2 total harmonic distortion C81 db @ 49khz; note 2 signal to noise ratio (snr) 71.5 db @ 49khz; note 2 signal to (noise + distortion) ratio 71 db @ 49khz; note 2 sampling dynamics aperture delay 13 ns aperture jitter 150 ps, rms transient response note 3 Ck 150 ns overvoltage recovery 150 ns note 4 digital inputs logic levels v il C0.3 +0.8 v v ih +2.4 +5.3 v i il 0.1 50 m a i ih 5 m a digital outputs resolution 12 bits data format parallel; 12-bit or 8-bit/4-bit data coding offset binary v ol 0.0 +0.4 v i sink = 1.6ma v oh +2.4 v dd vi source = 1.6ma i leakage (high-z state) 0.1 5 m a power supply requirements rated voltage +4.75 +5.0 +5.25 v v s (v sa and v sd ) current 18 21 ma i s power consumption 90 mw environmental and mechanical specification Ck 0 +70 c storage C65 +150 c package Ckn 28Cpin narrow dip Cks 28Cpin soic notes 1. lsb means least significant bit. for sp85xx series , 1lsb = 2.44mv for 5v range, 1 lsb = 4.88mv for 10v range. 2. all specifications in db are referred to a full-scale input, either 10v or 5v. 3. for full-scale step input, 12-bit accuracy attained in specified time. 4. recovers to specified performance in specified time after 2 x f s input overvoltage. free datasheet http:///
46 pinout pin 12 d 5 data bit 5 if hbe is low; low if hbe is high. pin 13 d 4 data bit 4 if hbe is low; low if hbe is high. pin 14 n.c.this pin is not internally connected. pin 15 n.c.this pin is not internally connected. pin 16 dgnd digital ground. connect to pin 5, at the device. pin 17 d 3 data bit 3 if hbe is low; data bit 11 if hbe is high. pin 18 d 2 data bit 2 if hbe is low; data bit 10 if hbe is high. pin 19 d 1 data bit 1 if hbe is low; data bit 9 if hbe is high. pin 20 d 0 data bit 0 if hbe is low. least significant bit (lsb). data bit 8 if hbe is high. pin 21 hbe high byte enable, when held low, data output as 12-bits in parallel. when held high, four msbs presented on pins 17C20, pins 10 C 13 output lows. must be low to initiate conversion. pin 22 r/c read/convert. falling edge initiates conversion when cs is low, hbe is low, and busy is high. pin 23 cs chip select. outputs in hi-z state when high. must be low to initiate conversion or read data. pin 24 busy. output low during conver- sion. data valid on rising edge in convert mode. pin 25 n.c. this pin is not internally connected. pin 26 v sd positive digital power supply, +5v. connect to pin 27, and bypass to dgnd. pin 27 v sa positive analog power supply. +5v. connect to pin 26, and bypass to agnd. pin 28 n.c. this pin is not internally connected. n.c. 1 ?0v in 2 ?v in 3 vref 4 agnd 5 d 11 6 d 10 7 d 9 8 d 8 9 d 7 10 d 6 11 d 5 12 d 4 13 n.c. 14 28 n.c. 27 v sa 26 v sd 25 n.c. 24 busy 23 cs 22 r/c 21 hbe 20 d 0 19 d 1 18 d 2 17 d 3 16 dgnd 15 n.c. SP8503 sp8505 sp8510 pin assignment pin 1 no connection this pin is not internally connected. pin 2 in 1 10v analog input. connected to agnd for 5v range. pin 3 in 2 5v analog input. connected to agnd for 10v range. pin 4 v ref C internal voltage. reference output. pin 5 agnd analog ground. connect to pin 16 at the device. pin 6 d 11 data bit 11. most significant bit (msb). pin 7 d 10 data bit 10. pin 8 d 9 data bit 9. pin 9 d 8 data bit 8. pin 10 d 7 data bit 7 if hbe is low; low if hbe is high. pin 11 d 6 data bit 6 if hbe is low; low if hbe is high. free datasheet http:///
47 edge can be used to read the data from the conver- sion. also, during conversion, the busy signal puts the output data lines in hi-z states and inhibits the input lines. this means that pulses on r/c are ignored, so that new conversions cannot be initi- ated during a conversion, either as a result of spurious signals or to short-cycle the sp85xx series. in the read mode, the input to r/c is kept nor- mally low, and a high pulse is used to read data and initiate a conversion. in this mode, the rising edge of r/c will enable the output data pins, and the data from the previous conversion becomes valid. the falling edge then puts the sp85xx series in a hold mode, and initiates a new conver- sion. the sp85xx series will begin acquiring a new sample just prior to the busy output rising, and will track the input signal until the next conversion is started. for use with an 8-bit bus, the data can be read out in two bytes under the control of hbe. with a low input on hbe, at the end of a conversion, the 8 lsbs of data are loaded into the output drivers on d 7 through d 4 and d 3 through d 0 . taking hbe high then loads the 4 msbs on d 3 through d 0 , with d 7 through d 4 being forced low. analog input ranges the sp85xx series offers two standard bipolar input ranges: 10v and 5v. if a 10v range is required, the analog input signal should be con- nected to pin 2. a signal requiring a 5v range should be connected to pin 3. in either case, the other pin of the two must be grounded or connected to the adjustment circuits described in the section on calibration. controlling the sp85xx series the sp85xx series can be easily interfaced to most microprocessor-based and other digital systems. the microprocessor may take full control of each conver- sion, or the sp85xx series may operate in a stand- alone mode, controlled only by the r/c input. full control consists of initiating the conversion and read- ing the output data at user command, transmitting data either all 12-bits in one parallel word, or in two 8-bit bytes. the three control inputs (cs, r/c and hbe) are features... the sp85xx series are specified at sampling rates of 333khz ( SP8503 ), 200khz ( sp8505 ) or 100khz ( sp8510 ). conversion times are factory set for 2.70 m s, 4.7 m s and 9.7 m s maximum, re- spectively, over temperature, and the high- speed sampling input stage insures a total acqui- sition and conversion time of 3 m s, 5 m s and 10 m s maximum, respectively, over temperature. pre- cision, laser-trimmed scaling resistors provide industryCstandard input ranges of 5v or 10v. the 28-pin sp85xx series are available in narrow body plastic dip, and soic packages and it operates from a single +5v supply. the sp85xx series are available in grades specified over the 0 c to +70 c commercial temperature ranges. operation basic operation figure 1 shows the simple hookup circuit required to operate the sp85xx series in a 10v range in the convert mode. a convert command arriving on r/c puts the sp85xx series in the hold mode, and a conversion is started. this pulse must be low for a minimum of 40ns. because this pulse establishes the sampling instant of the a/d, it must have very low jitter. busy will be held low during the conversion, and rises only after the conversion is completed and the data has been transferred to the output drivers. thus, the rising figure 1. basic 10v operation 2 3 4 5 6 7 8 9 10 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 d0 (lsb) busy convert command 0.1? 6.8? + +5v +5v +5v n.c. busy cs r/c hbe d0 (lsb) d1 d2 d3 dgnd in 1 in 2 v ref agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 d11 (msb) data out input 1 28 n.c. n.c. n.c. n.c. 14 15 free datasheet http:///
48 cs r/c hbe busy operation 1 x x 1 none C outputs in hi-z state. 01 0 0 1 holds signal and initiates conversion. 0101 output three-state buffers enabled once conversion has finished. 0111 enable hi-byte in 8-bit bus mode. 01 0 1 1 inhibit start of conversion. 0011 none C outputs in hi-z state. x x x 0 conversion in progress. outputs hi-z state. new conversion inhibited until present conversion has finished. table 1. control line functions in table 2 . no other combination of states or transi- tions will initiate a conversion. conversion is inhibited if either cs or hbe are high, or if busy is low. cs and hbe should be stable a minimum of 25ns prior to the transition on r/c. timing relationships for start of conversion are illustrated in figure 7 . the busy output indicates the current state of the converter by being low only during conversion. during this time the three-state output buffers remain in a hi-z state, and therefore data cannot be read during conversion. during this period, additional transitions on the three digital inputs (cs, r/c and hbe) will be ignored, so that conversion cannot be prematurely terminated or restarted. internal clock the sp85xx series has an internal clock that is factory trimmed to achieve the typical conversion times given in the specifications, and a maximum conversion time over the full operating tempera- ture range of 2.7 m s, 4.7 m s or 9.7 m s, depending on the model. no external adjustments are required, and with the guaranteed maximum acquisition time of 300ns, throughput performance is assured with convert pulses as close as 3 m s for the SP8503 . reading data after conversion is initiated, the output buffers remain in a hi-z state until the following three logic condi- tions are simultaneously met: r/c is high, busy is high and cs is low. upon satisfying these condi- tions, the data lines are enabled according to the state of hbe. see figure 7 for timing relationships and specifications. calibration... optional external gain and offset trim offset and full-scale errors may be trimmed to zero using external offset and full-scale trim potenti- ometers connected to the sp85xx series as shown in figure 3 . if adjustment of offset and full scale is not required, connections as shown in figure 2 should be used. all ttl/cmos compatible. the functions of the control lines are shown in table 1 . for stand-alone operation, control of the sp85xx series is accomplished by a single control line connected to r/c. in this mode, cs and hbe are connected to gnd. the output data are presented as 12-bit words. the stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. conversion is initiated by a high-to-low transition on r/c. the three-state data output buffers are enabled when r/c is high and busy is high. thus, there are two possible modes of operation: conversion can be initiated with either positive or negative pulses. in either case, the r/c pulse must remain low a minimum of 40ns. figure 5 illustrates timing when conversion is initi- ated by an r/c pulse which goes low and returns high during the conversion. in this case (convert mode), the three-state outputs go into the hi-z state in response to the falling edge of r/c, and are enabled for external access to the data after completion of the conversion. figure 6 illustrates the timing when conversion is initiated by a positive r/c pulse. in this mode (read mode), the output data from the previous conversion is enabled during the high portion of r/c. a new conversion starts on the falling edge of r/c, and the three-state outputs return to the hi-z state until the next occurrence of a high on r/c. conversion start a conversion is initiated on the sp85xx series only by a negative transition occurring on r/c, as shown figure 2. a) 10v range b) 5v range without trims 2 3 ?0v input SP8503/05/10 2 3 ?v input SP8503/05/10 free datasheet http:///
49 input voltage range and lsb values input voltage range defined as: 10v 5v analog input connected to pin 2 3 pin connected to agnd 3 2 one least significant bit (lsb) fsr/2 12 20v/2 12 10v/2 12 4.88mv 2.44mv output transition values ffeh to fffh + full scale +10vC3/2lsb +5vC3/2lsb +9.9927v +4.9963v 7ffh to 800h mid scale 0vC1/2lsb 0vC1/2lsb (bipolar zero) C2.44mv C1.22mv 000h to 001h Cfull scale C10v+1/2lsb C5v+1/2lsb -9.9976v -4.9988v table 2. input voltages, transition voltages and lsb values toggles on and off at code 1111 1111 1110 bin = ffe h = 4094 dec . 10v range offset and gain offset apply 1.2622v to the 10v input at pin 2. adjust the offset potentiometer until the lsb toggles on and off at code 1001 0000 0010 bin = 902 h = 2306 dec . gain apply 9.9927v to the 10v input at pin 2. adjust the gain potentiometer until the lsb toggles on and off at code 1111 1111 1110 bin = ffe h = 4094 dec . layout considerations because of the high resolution and linearity of the sp85xx series , system design problems such as ground path resistance and contact resis- tance become very important. calibration procedure apply a precision input voltage source to your chosen input range ( 10v range at pin 2 or 5v at pin 3). set the a/d to convert continuously. monitor the output code. trim the offset first, then gain. use the appropriate input voltages and output target codes for your chosen input range as follows. the recommended offset cali- bration voltage values eliminate interaction be- tween the offset and gain calibration 5v range offset and gain offset apply 1.5637v to the 5v input at pin 3. adjust the offset potentiometer until the lsb toggles on and off at code 1010 1000 0000 bin = a80 h = 2688 dec . gain apply 4.9963v to the 5v input at pin 3. adjust the gain potentiometer until the lsb figure 3. a) 10v range b) 5v range with external trims a) b) sp85xx 1 2 3 4 5 6 7 r 2 =100 w ?0v input gain adjust 100 w 10k w bipolar zero adjust r 1 =10k w 499 w ?5v +5v sp85xx 1 2 3 4 5 6 7 gain adjust r 2 =100 w ?v input r 1 =10kw +5v ?5v 1k w 30.1k w 301 w free datasheet http:///
50 the input resistance of the sp85xx series is 6.3k w or 4.2k w (for the 10v and 5v ranges respectively). to avoid introducing distortion, the source resistance must be very low, or constant with signal level. the output impedance provided by most op amps is ideal. pins 26 digital supply voltage (v sd ) and 27 analog supply voltage (v sa ) are brought out to separate pins to maximize accuracy on the chip. they should be connected together as close as possible to the unit. pin 27 may be slightly more sensitive than pin 26 to supply variations, but to maintain maximum system accu- racy, both should be wellCisolated from digital supplies with wide load variations. to limit the effects of digital switching elsewhere in a system on the analog performance of the system, it often makes sense to run a separate +5v supply conductor from the supply regulator to any analog components requiring +5v, including the sp85xx series. if the sp85xx series traces cannot be separated back to the power supply terminals, and therefore share the same trace as the logic supply currents, then a 10 ohm isolating resistor should be used between the board supply and pin 24 (v da ) and its bypass capacitors, to keep v da glitchCfree. the v s pins (26 and 27) should be connected together and bypassed with a parallel combination of a 6.8 m f tantalum capacitor and a 0.1 m f ceramic capacitor located close to the con- verter to obtain noise-free operation. (see figure 1 ). noise on the power supply lines can degrade converter performance, especially noise and spikes from a switching power supply. appropriate sup- plies or filters must be used. the gnd pins (5 and 16) are also separated internally, and should be directly connected to a ground plane under the converter. a ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter cir- cuits. where any compromises must be made, the common return of the analog input signal should be referenced to pin 5, agnd, on the sp85xx series, which prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. coupling between analog input and digital lines should be minimized by careful layout. for instance, if the lines must cross, they should do so at right angles. parallel analog and digital lines should be separated from each other by a pattern connected to common. if external full scale and offset potentiometers are used, the potentiometers and related resistors should be located as close to the sp85xx series as possible. hot socket precaution two separate +5v v s pins, 26 and 27, are used to minimize noise caused by digital transients. if one pin is powered and the other is not, the sp85xx figure 4. acquisition and conversion timing r/c busy converter mode acquisition conversion acquisition conversion t ap hold time t c t dbc t b symbol/parameter min. typ. max. units t dbc busy delay from r/c 80 150 ns t b busy low 2.5 2.7 m s SP8503 4.5 4.7 m s sp8505 9.5 9.7 m s sp8510 t ap aperture delay 13 ns d t ap aperture jitter 150 ps, rms t c conversion time 2.47 2.70 m s SP8503 4.47 4.70 m s sp8505 9.47 9.70 m s sp8510 free datasheet http:///
51 r/c busy converter mode data bus acquire convert acquire convert data valid hi-z state hi-z state data valid t w t dbc t b t dbe t a t c t ap t hdr and t hl t db figure 5. convert mode timing r/c pulse low, outputs enabled after conversion series may draw excessive current. in normal operation, this is not a problem because both pins will be soldered together. however, during evalu- ation, incoming inspection, repair, etc., where the potential of a hot socket exists, care should be taken to apply power to the sp85xx series only after it has been socketed. minimizing glitches coupling of external transients into an analog-to- digital converter can cause errors which are difficult to debug. in addition to the discussions earlier on layout considerations for supplies, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance out of a system using the sp85xx series. these potential system problem sources are particularly important to consider when developing a new system, and looking for the causes of errors in breadboards. first, care should be taken to avoid glitches during critical times in the sampling and conversion process. since the sp85xx series has an internal sample/hold function, the signal that puts it into the hold state (r/c going low) is critical, as it would be on any sample/ hold amplifier. the r/c falling edge should have a 5 to 10ns transition time, low jitter, and have minimal ringing, especially during the 20ns after it falls. r/c busy converter mode data bus acquire convert acquire convert data valid hi-z state hi-z state t w t dbc t b t dbe t a t c t ap t hdr and t hl t ap data valid hi-z state t dd figure 6. read mode timing r/c pulse high, outputs enabled only when r/c is high free datasheet http:///
52 ac dynamic timing data naturally, transients on the analog input signal are to be avoided, especially at times within 20ns of r/c going low, when they may be trapped as part of the charge on the capacitor array. this requires careful layout of the circuit in front of the sp85xx series. finally, in multiplexed systems, the timing relative to when the multiplexer is switched may affect the analog performance of the system. in most applica- tions, the multiplexer can be switched as soon as r/c goes low (with appropriate delays), but this may affect the conversion if the switched signal shows glitches or significant ringing at the sp85xx series input. whenever possible, it is safer to wait until the conversion is completed before switching and multi- plexer. the extremely fast acquisition time and con- version time of the sp85xx series make this practi- cal in many applications. although not normally required, it is also good prac- tice to avoid glitches from coupling to the sp85xx series while bit decisions are being made. since the above discussion calls for a fast, clean rise and fall on r/c, it makes sense to keep the rising edge of the convert pulse outside the time when bit decisions are being made. in other words, the convert pulse should either be short (under 100ns so that it transitions before the msb decision), or relatively long (over 2.75 m s to transition after the lsb decision). next, although the data outputs are forced into a hi-z state during conversion, fast bus transients can still be capacitively coupled into the sp85xx series. if the data bus experiences fast transients during conver- sion, these transients can be attenuated by adding a logic buffer to the data outputs. the busy output can be used to enable the buffer. symbol/parameter min . typ. max. units t w r/c pulse width 40 ns t dbc busy delay from r/c 80 150 ns t b busy low 2.47 2.7 m s t ap aperture delay 13 ns d t ap aperture jitter 150 ps, rms t c conversion time 2.5 2.70 m s t dbe busy from end of conversion 100 ns t db busy delay after data valid 25 75 200 ns t a acquisition time 130 300 ns t a + t c throughput time SP8503 3.0 m s sp8505 5.0 m s sp8510 10.0 m s t hdr valid data held after r/c low 20 50 ns t s cs or hbe low before r/c falls 25 5 ns t h cs or hbe low after r/c falls 25 0 ns t dd data valid from cs low, r/c high, and hbe 65 150 ns in desired state (load = 100pf) t hl delay to hi-z state after r/c falls or 50 150 ns cs rises (3k w pullup or pulldown all parameters guaranteed by design. free datasheet http:///
53 figure 7. conversion start timing r/c busy data bus cs or hbe data valid hi-z state t s t h t w t dbc t hdr and t hl ordering information 0 c to +70 c model throughput package SP8503kn .................................................................... 333khz ................................................................................................ 28Cpin 0.3" plastic dip SP8503ks .................................................................... 333khz ........................................................................................................ 28Cpin, 0.3" soic sp8505kn .................................................................... 200khz ................................................................................................ 28Cpin 0.3" plastic dip sp8505ks .................................................................... 200khz ........................................................................................................ 28Cpin, 0.3" soic sp8510kn .................................................................... 100khz ................................................................................................ 28Cpin 0.3" plastic dip sp8510ks .................................................................... 100khz ........................................................................................................ 28Cpin, 0.3" soic free datasheet http:///
54 this page left intentionally blank free datasheet http:///

▲Up To Search▲

Price & Availability of SP8503

	To Download SP8503 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .