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enpirion ? power datasheet en5396qi 9a powersoc synchronous dc- dc buck c onverter with integrated inductor description th e en5396 qi is a power s upply on a chip (pwrsoc) dc- dc converter. it is specifically designed to meet the precise voltage and fast transient requirements of present and future high - performance, low - power processor, dsp, fpga, asic, memory boards , and system level applications in a distributed power architecture. advanced circuit techniques, ultra high switching frequency, and innovative , high - density, integrated circuit and proprietary inductor technology deliver high - quality, ultra compact, non- isolated dc - dc conversion. operating this converter requires as few as five external components that include small value input and output ceramic capacitors and a soft - start capacitor. t he altera enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. in addition, a reduction in the number of vendors required for the complete power s olution helps to enable an overall system cost savings. applications ? point of load regulation for low - power processors, network processors, dsps, fpgas, and asics ? notebook computers, servers, workstations ? broadband, networking, lan/wan, optical ? low voltage, distributed power architectures with 2.5v, 3.3v or 5v rails ? dsl, stb, dvr, dtv, industrial pc ? noise sensitive applications ordering information part number temp rating (c) package en53 96 qi - 40 to +85 58 - pin qfn t&r evb-en5396q i qfn evaluation board features ? i nt egrated inductor technology : i ntegrated i nductor , mosfets, controller in a 10 x 12 x 1.85mm package ? low external part count. ? up to 30w continuous output power. ? low output impedance optimized for 90 nm ? master/slave configuration for paralleling. ? 5mhz operating frequency. ? high efficiency, up to 93%. ? wide input voltage range of 2.375v to 5.5v. ? external resistor divider output voltage select . ? output e nable pin and power ok signal. ? programmable soft - start time. ? adjustable over - current pro tection. ? thermal shutdown, short circuit, over - voltage and under - voltage protection. ? rohs compliant, msl level 3, 260c reflow. typical application circuit v out v in xfb 2 x 47 f 2 x 47 f 15n f vout enable pgnd agnd ss pvin avin pgnd 1 ? xov figure 1 . simple layout. 10mm 12mm w ww.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi pin configuratio n below is a top view diagram of the en539 6 q package. note: nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be so ldered to the pcb. failure to follow this guideline may result in part malfunction or damage. figure 2 . pin diagram, top view. www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi pin descriptions pin n am e function 1-3 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 4-5 nc(sw) no connect ? these pins are internally connected to the common drain output of the internal mosfets. nc(sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. 6- 13 nc no connect ? this pin should not be electrically connect ed to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 14- 20 vout regulated converter output. connect these pins to the load and place output capacitor from these pins the pgnd pins 24 - 26. 21 -22 nc(sw) no connect ? these pins are internally connected to the common drain output of the internal mosfets. nc(sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. 23 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 24 - 29 pgnd output power ground. refer to layout guideline section. 30 - 35 pvin input power supply. connect to input power supply. decouple with input capacitor to pgnd. 36- 37 nc no connect ? this pin should not be electrically connected to any external signal, vo ltage, or ground , but must be soldered to pcb . this pin may be connected internally. 38 rocp optional over current protection adjust pin. place rocp resistor between this pin and agnd (pin 40) to adjust the over current trip point. 39 avin analog voltage input for the controller circuits. connect this pin to the input power supply. 40 agnd analog ground for the controller circuits. 41- 42 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 43 xf b feedback pin for external voltage divider network. 44 xo v over voltage programming feedback pin. 45 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 46 pok power ok is an open drain transistor for power system state indication. pok is a logic high when vout is with - 10% to +20% of vout nominal. 47 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 48 ss soft - start node. the soft - start capacitor is connected between this pin and ag nd. the value of this capacitor determines the startup timing. 49 eain optional error amplifier input. allows for customization of the control loop. 50 eaout optional error amplifier output. allows for customization of the control loop. 51 comp output of the buffer leading to the error amplifier. used for external modifications of the compensation network. 52 enable input enable. applying a logic high, enables the output and initiates a soft - start. applying a logic low disables the output. 53 pwm pwm input/output. used for optional master/slave configuration. when m/s pin is asserted ?low?, pwm will output the gate - drive pwm waveform. when the m/s pin is asserted ?high?, the pwm pin is configured as an input for pwm signal from the ?master? device. pwm pin can drive up to 3 slave devices. 54 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 55 m/s optional master/slave select pin. asserting pin ?low? places device in master mode for current sharing. pwm pin (53) will output pwm drive signal. asserting pin ?high? will place the device in slave mode. pwm pin (53) will be configured to input (receive) pwm drive signal from ?master? device. 56- 58 nc no connect ? this pin should not be electrically connected to any external signal, voltage, or ground , but must be soldered to pcb . this pin may be connected internally. 3 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi block diagram (+) (-) error amp v out p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+ ) (-) pwm comp pvin enable compensation bandgap reference pgnd avin eaout ss reference voltage selector over voltage eain agnd power good logic v out pok rocp voltage selector xfb vsense comp nc(sw) xov over voltage figure 3 . system block diagram. 4 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond recommended operating conditions is not implied. stress beyond absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter symbol min m ax units input supply voltage v in - 0.5 7.0 v voltages on: enable, v sense , xf b , xo v , m/s - 0.5 v in v voltages on: eain, eaout, comp - 0.5 2.5 voltages on: ss, pwm - 0.5 3.0 voltages on: pok - 0.5 v in + 0.3 storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020a 260 c esd rating (based on human body model) 2000 v recommended operating conditions parameter symbol min m ax units input voltage range v in 2.375 5.5 v output voltage range (note: 1) v out 0.75 v in - v dropout v output current (note 2 ) i out 0 9 a operating ambient temperature t a - 40 +85 c operating junction temperature t j - 40 +125 c note 1 : v dropout = i load x dropout resistance note 2 : reference figures 5 and 6 for the output current derating curves. thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) (note 3 ) ja 18 c/w thermal resistance: junction to case (0 lfm) jc 1.5 c/w thermal overload trip point t j - tp +150 c thermal overload trip point hysteresis 20 c note 3 : based on four layer board and proper thermal design in line with jedec eij/jesd 51 standards electrical characteristics note: v in =5.5v over operating temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ m ax units v out initial accuracy ? v out_init t a = 25c , 2.375 v ? v out_ all 2.4v t a + 85c 0a ? v out (i out = 0% to 100% or 100% to 0% or rated load) v in = 5v, 1.2v v out 3.3v c out = 2 x 47 02393 october 11, 2013 rev e
en5396qi parameter symbol test conditions min typ m ax units continuous output current i out 2.375v note: reference figures 5 and 6 for the output current derating curves 9 a current limit threshold i ocp th 11 a shut - down supply current i s enable=0v 50 2.375v v 5.5v ? i out with 2 ? 4 converters in parallel, the difference between any 2 parts. ? v in < 50mv; r trace < 10m ? 02393 october 11, 2013 rev e
en5396qi typical performance characteristics circuit of figure 1, v in = 5 v, v out = 1.2 v and t a = 25c, unless otherwise noted. top to bottom: v out = 2.5 v, 1.8 v, 1.5 v, 1.2 v, 0.8 v top to bottom: v out = 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, 0.8 v ripple voltage, 5. 5v in /1.2v out , i out =9 a, ripple voltage, 3.3v in /1.2v out , i out =9 a, c out = 5x22uf. c out = 5x22uf. transient response : 5v in /1.2v out , 0 - 9a, 7 a/us. transient response : 5v in /3.3v out , 0 - 9a, 7 a/us. c out = 5x 22uf. c out = 5x 22uf efficiency (vin = 5.0v) 50 55 60 65 70 75 80 85 90 95 0 2 4 6 8 10 load (amperes) efficiency (%) efficiency (vin =3.3v) 60 65 70 75 80 85 90 95 0 2 4 6 8 10 load (amperes) efficiency (%) 7 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi start up waveforms v in =5.0v, v out =1.2v, c ss =15nf, start up waveforms v in =5.0v, v out =3.3v, c ss =15nf, ch 1 = v out , ch 3 = enable, ch 4 = pok. ch 1 = v out , ch 3 = enable, ch 4 = pok. 8 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi functional description the en539 6 qi is a synchronous, pin programmable power supply with integrated power mosfet switches and integrated inductor. the nominal input voltage range is 2.375 - 5.5v. the output vo ltage is programmed using an external resistor divider network. the feedback control loop is a type iii voltage - mode and the part uses a low - noise pwm topology. up to 9 a of output current can be drawn from this converter. the 5mhz operating frequency enab les the use of small - size output capacitors. the power supply has the following protection features: ? programmable over - current protection (to protect the ic from excessive load current) ? thermal shutdown with hysteresis. ? over - voltage protection ? under - voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2v additional features include: ? soft - start circuit, limiting the in - rush current when the converter is powered up. ? power good circuit indicat ing whether the output voltage is within 90% - 120% of the programmed voltage. programming output voltage and ovp the en5396 output voltage is programmed using a simple resistor divider network. figure 4 shows the resistor divider configuration. the en5396 output voltage and over voltage thresholds are determined by the voltages presented at the xfb and xov pins respectively. these voltages are set by way of resistor dividers between v out and agnd with the midpoint going to xfb and xov. it is recommended that rb1 and rb2 resistor values be ~2k ? . use the following equation to set the resistor ra1 for the desired output voltage: v rb v vout ra 75.0 1*)75.0( 1 ? = v rb v ovptrip ra 90.0 2*)90.0 ( 2 ? = f 2 x 47 f r a1 r a2 r b1 r b2 figure 4. v out and ovp resistor divider networks. note: if no ovp di vider is present, there will be no over - voltage protection and pok will remain ?high? as long as v out remains above 90% of the nominal v out setting. power - up /down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power down, the avin should not be powered down before the pvin. tying pvin and avin or all three pins (avin, pvin, enable) together during power up or power down meets thes e requirements . pre - bias start - up the en5396qi does not support startup into a pre - biased condition. be sure the output capacitors are not charged or the output of the en5396qi is not pre - biased when the en5396qi is first enabled. 9 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi input capacitor selectio n the en539 6 qi requires approximately 100uf of input capacitance. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these l ose capacitance with frequency, temperature and bias voltage. in some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. recommended input capacitors. description mfg p/n 47uf, 10v, x5r, 1210 murata grm32er61a476ke20l (2 capacitors needed) taiyo yuden lmk325bj476mm -t output capacitor selection the en539 6 qi has been optimized for use with approximately 10 0f of output capacitance. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these loose capacitance with frequency, temperature and bias voltage. recommended output capacitors. description mfg p/n 22uf, 6.3v, 10% x5r, 1206 (5 capacitors needed) murata taiyo yuden grm31cr60j226ke19l jmk316bj226kl - t 47uf, 10v, 10% x5r, 1210 47uf, 6.3v, 10% x5r, 1210 (2 capacitors needed) murata avx grm32er61a476ke20l 12106d476kat2 output ripple voltage is determined by the aggregate output capacitor impedance. output impedance, denoted as z, is comprised of effective series resistance, esr, and effective series inductance, esl: z = esr + esl. placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. n total zzzz 1 ... 111 21 +++= output capacitor configuration typical output ripple (mvp - p) (as measured on en539 6 qi evaluation board) 2 x 47uf 20 5 x 22 uf 12 enable operation the enable pin provides a means to shut down the device, or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter into normal operation. when the enable pin is asserted high, the device will undergo a normal soft start. soft - start operation soft start is a method to reduce in - rush current when the device is enabled. the output voltage is ramped up slowly upon start - up. the output rise time is controlled by choice of a soft - start capacitor, which is placed between the ss pin (pin 48) and the agnd pin (pin 40). rise time: t r = c ss * 80k ? during start - up of the converter, the reference voltage to the error amplifier is gradually increased to its final level by an internal current source of typically 10ua. typical soft - start rise time is 1ms to 3ms. typical ss capacitor values are in the range of 15nf to 30 nf. pok operation the pok signal is an open drain signal from the converter indicating the output voltage is within the specified range. the pok signal will be a logic high when the output voltage is within 90% - 120% of the programmed output voltage. if the output voltage goes outside of this range, the pok signal will be a logic low until the output voltage has returned to within this range. in the 10 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi event of an over - voltage condition the pok signal will go low and will remain in this condition until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state. the internal pok fet is designed to tolerate up to 4ma. the pull - up resistor value should be chosen to limit the current from exceeding this value when pok is logic low. over - current protection when an o ver current condition occurs, v out is pulled low. this condition is maintained for a period of 1.2 ms and then a normal soft start cycle is initiated. if the over current condition still persists, this cycle will repeat. the ocp trip point is nominally s et to 150% of maximum rated load. it is possible to increase the ocp trip point to 200% of the maximum rated load by connecting a 5k ? resistor between the rocp pin (pin 38) and agnd (pin 39). this option is intended for startup into capacitive loads such as certain fpgas and asics. over - voltage protection when the output voltage exceeds 120% of the programmed output voltage, the pwm operation stops, the lower n - mosfet is turned on and the pok signal goes low. when the output voltage drops below 95% of th e programmed output voltage, normal pwm operation resumes and pok returns to its high state. thermal overload protection thermal shutdown will disable operation once the junction temperature exceeds approximately 150oc. once the junction temperature drops by approx 20oc, the converter will re - start with a normal soft - start. input under - voltage lock - out circuitry is provided to ensure that when the input voltage is below the specified voltage range, the converter will not start - up. circuits for hysteresis, input de - glitch and output leading edge blanking are included to ensure high noise immunity and prevent false tripping. compensation the en5396 is internally compensated through the use of a type 3 compensation network and is optimized for use with about 5 0f of output capacitance and will provide excellent loop bandwidth and transient performance for most applications. (see the section on capacitor selection for details on recommended capacitor types.) voltage mode operation provides high noise immunity at light load. in some cases modifications to the compensa tion may be required. the en5396 qi provides access to the internal compensation network to allow for customization. for more information, contact altera power applications support. parallel device operation in order to power a load that is higher than the rated 9 a of the en539 6 , from 2 to 4 devices can be placed in parallel for providing a single load with up to 24a of output current. paralleling more than 1 device is accomplished by s electing a master device and tying that m/s pin to agnd. all slave devices should have their m/s pin tied to avin. the pwm pin from the master device is connected to all slave device pwm pins. the pwm signal is a 5 mhz drive signal and must be routed appropriately. (s ee figure 4.) 1. all master and slave devices should have identical placement and values of input, output and soft - start capacitors. 2. all master and slave devices should have their enable pins tied together and should be operated simultaneously with a fast r ising edge of 10 usec or less, to ensure that devices start up at the same time. startup imbalance could lead to ocp condition on first device to startup. 3. the maximum board trace resistance between any 2 devices vout pins should be less than 10m ? . 4. the max imum difference of pvin between any 2 devices should be less than 50mv. 11 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi figure 4 . paralleling of two devices. figure 5. output current derating curve, v in = 5.0v 12 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi figure 6 . output current derating curve, v in = 3.3v 13 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi layout recommendations thermal considerations are important power supply design facts that cannot be avoided in the real world. whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be acco unted for. the altera enpirion powersoc helps alleviate some of those concerns. the altera enpirion en5396qi dc -d c converter is packaged in a n 10 x12x 1.85 mm 58- pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (pcb) to act as a heat sink. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c may reduce long - term reliability. the device has a thermal overload protec tion circuit designed to turn off the device at an approximate junction temperature value of 1 5 0c. the following example and calculations illustrate the thermal performance of the en5396qi . example: v in = 12 v v out = 3.3v i out = 9a first calculate the output power. p ou t = 3.3v x 9 a = 29.7 w next, determine the input power based on the efficiency () shown in figure 7 . figure 7: effi ciency vs. output current top to bottom: (v out = 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, 0.8 v ) for v in = 12v, v out = 3.3v at 9 a, 86.5 % = p out / p in = 86.5% = 0.865 p in = p out / p in 13.2 w / 0. 865 34.34 w the power dissipation (p d ) is the power loss in the system and can be calculated by subtracting the output power from the input power. p d = p in ? p out 34.34 w ? 29.7 w 4.63 w with the power dissipation known , the temperature rise in the device may be estimated based on the t heta ja value ( ja ). the ja parameter estim ates how much the temperature will rise in the device for every watt of power dissipation. the en5396qi has a ja value of 1 8 oc/w without airflow. determine the change in temperature (t) based on p d and ja . t = p d x ja t 4.63 w x 18c/w = 83.43 c 84 c the junction temperature (t j ) of the device is approximately the ambient temperature (t a ) plus the change in temperature. we assume the initial ambient temperature to be 25c. t j = t a + t t j 25c + 84c 109 c the maximum operating junction temper ature (t j max ) of the device is 125c, so the device can operate at a higher ambient temperature. the maximum ambient temperature (t amax ) allowed can be calculated. t amax = t j max ? p d x ja 125c ? 84c 41 c the maximum ambient temperature the device can reach is 41c given the input and output conditions. note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. efficiency (vin = 5.0v) 50 55 60 65 70 75 80 85 90 95 0 2 4 6 8 10 load (amperes) efficiency (%) 14 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi layout recommendations figure 8. layout of power and ground planes. figure 9 . use of vias connecting local and system ground. recommendation 1: input and output capacitors should be placed as close to the en539 6 qi package as possible to reduce emi from input and output loop currents. this reduces the physical area of the input and output ac current loops. recommendation 2 : place a slit in the input/output capacitor ground plane just beyond the common connection point of the gnd pins of the device as shown in figure 8 . recommendatio n 3 : multiple small (0.25mm) vias should be used to connect ground terminal of the input capacitor and the output capacitor to the system ground plane as shown in f igure 9 . recommendation 4 : the large thermal pad underneath the component must be connect ed to the system ground plane through as many vias as possible. the diameter of the vias should be less than 0.3mm. this provides the quiet, or analog ground for the converter and also provides the path for heat dissipation from the converter. a later se ction of this note makes a recommendation on the pcb footprint. recommendation 5: the system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and the input and output capacitors that carry large ac currents. recommendation 6 : as with any switch - mode dc/dc converter, do not run sensitive signal or control lines underneath the converter package. 15 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi design considerations for lead -frame based modules exposed metal on bottom o f package lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, , and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead - frame cantilevers be exposed at the point where wire- bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package. only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the pc board. the pcb top layer under the en539 6 qi should be clear of any metal except for the large thermal pad. t he ?grayed - out? area in figure 10 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the pcb . figure 10 demonstrates the recommended pcb footprint for the en539 6 qi. figure 11 shows the shape and location of the exposed metal pads as well as the mechanical dimension of the large thermal pad and the pins. figure 10 . lead - frame exposed metal. grey area highlights exposed metal that is not to be mechanically or electrically connected to the pcb. 16 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi figure 1 1 : en5396 qi pcb footprin t ( top view) the solder stencil aperture for the thermal pad is shown in blue and is based on enpirion power product manufacturing specifications. 17 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi package dimensions figure 12 . package dimensions. 18 www.altera.com/enpirion 02393 october 11, 2013 rev e
en5396qi contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 19 www.altera.com/enpirion 02393 october 11, 2013 rev e

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