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esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 1/20 fast ultra high-psrr, low-noise, low-dropout, 600ma micropower cmos linear regulator general description the EMP8966 low-dropout (ldo) cmos linear regulators, feature ultra-high power supply rejection ratio (75db at 1khz), low output voltage noise (30v), low dropout voltage (270mv), low quiescent current (110a), and fast transient response. it guarantees delivery of 600ma output current, and supports adjustable (1.2v to 5.0v) output voltage versions. the EMP8966 is ideal for battery-powered applications by virtue of its low quiescent current consumption and its 1na shutdown mode of logical operation. the regulator provides fast turn-on and star t-up time by using dedicated circuitry to pre-charge an optional external bypass capacitor. this bypass capacitor is used to reduce the output voltage noise without adversely affecting the load transient response. the high power supply rejection ratio of the EMP8966 holds well for low input voltages typically encountered in battery- operated systems. the regulator is stable with small ceramic capacitive loads (2.2f typical). additional features include regulation fault detection, bandgap voltage reference, constant current limiting and thermal overload protection. available in miniature 5-pin sot-89-5 package options, sot-23-5,sot-23-6 package options are also offered to provide additional flexibility for different applications. emp products is rohs compliant. features ? miniature sot-23-5, sot-23-6and sot-89-5 packages ? 600ma guaranteed output current ? 75db typical psrr at 1khz ? 30v rms output voltage noise (10hz to 100khz) ? 270mv typical dropout at 600ma ? 110a typical quiescent current ? 1na typical shutdown mode ? fast line and load transient response ? 80s typical fast turn-on time ? 2.5v to 5.5v input range ? stable with small ceramic output capacitors ? over temperature and over current protection ? 2% output voltage tolerance applications ? wireless handsets ? pcmcia cards ? dsp core power ? hand-held instruments ? battery-powered systems ? portable information appliances
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 2/20 connection diagrams sot-23-5(top view ) sot-23-6(top view) sot-89-5(top view) order information EMP8966-xxvf05grr/nrr xx operation code vf05 sot-23-5 package grr rohs (pb free) rating: -40 to 85c package in tape & reel nrr rohs & halogen free (by request) rating: -40 to 85c package in tape & reel EMP8966-xxvc06grr/nrr xx operation code vc06 sot-23-6 package grr rohs (pb free) rating: -40 to 85c package in tape & reel nrr rohs & halogen free (by request) rating: -40 to 85c package in tape & reel EMP8966-xxvg05grr/nrr xx operation code vg05 sot-89-5 package grr rohs (pb free) rating: -40 to 85c package in tape & reel nrr rohs & halogen free (by request) rating: -40 to 85c package in tape & reel
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 3/20 order, mark & packing information no. of pin adj en cc package marking vout code (xx) vout product id 5 y y n sot-23-5 00 adj EMP8966-00vf05grr 5 y y n sot-89-5 00 adj EMP8966-00vg05grr 6 y y y sot-23-6 00 adj EMP8966-00vc06grr old marking: please see the notice(page 18) package & packing sot-23-5 3k units tape & reel sot-23-6 3k units tape & reel sot-89-5 1k units tape & reel
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 4/20 typical application fig. 1. EMP8966. adjustable output version. please refer to application information section for r1/r2 calculation.
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 5/20 pin functions name sot-23-5 sot-89-5 sot-23-6 function vout 5 5 6 output voltage feedback . vin 1 4 1 supply voltage input . require a minimum input capacitor of close to 1f to ensure stability and sufficient decoupling from the ground pin. gnd 2 2 2 ground pin . adj 4 1 5 adjustable negative feedback control . use external fixed resistors instead of trim pots to achieve the desired output voltage control. cc 4 compensation capacitor . connect an optimum 33nf noise bypass capacitor between the cc and the ground pins to reduce noise in vout. shdn 3 3 3 shutdown input. set the regulator into the disable mode by pulling the shdn pin low. to keep the regulator on during normal operation, connect the shdn pin to vin. the shdn pi n must not exceed vin under all operating conditions.
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 6/20 absolute maximum ratings (notes 1, 2) vin, vout, v shdn , vset, vcc, v fault -0.3v to 6.0v power dissipation (note 3) storage temperature range -65c to160c junction temperature (t j ) 150c lead temperature (10 sec.) 260c esd rating human body model (note 5) 2kv mm 200v thermal resistance ( ja ) (note 3) sot-23-5 250c/w sot-23-6 250c/w sot-89-5 100c/w operating ratings (note 1), (note 2) temperature range -40c to 85c supply voltage 2.5v to 5.5v electrical characteristics unless otherwise specified, all limits guaranteed for v in = v out +1v (note 6), v shdn = v in , c in = c out = 2.2f, c cc = 33nf, t j = 25c. boldface limits apply for the operating temperature extremes: -40c and 85c. symbol parameter conditions min typ (note 7) max units v in input voltage 2.5 5.5 v -2 +2 v otl output voltage tolerance 100a i out 300ma v out (nom) +0.5v vin 5.5v (note 6) adj = vout for the adjust versions -3 +3 % of v out (nom) v out output adjust range 1.20 5.0 v i out maximum output current average dc current rating 600 ma output current limit (sot-23-5, sot-23-6) 600 950 ma i limit output current limit (sot-89-5) 630 950 ma i out = 0ma 110 supply current i out = 600ma 255 i q shutdown supply current v out = 0v, shdn = gnd 0.001 1 a i out = 50ma 22 i out = 300ma 130 v do dropout voltage (note 4), (note 6) i out = 600ma 270 mv line regulation i out = 1ma, (v out + 0.5v) v in 5.5v (note 7) -0.1 0.02 0.1 %/v v out load regulation 100a i out 600ma 0.001 %/ma e n output voltage noise i out = 10ma, 10hz f 100khz 30 v rms v ih , (v out + 0.5v) v in 5.5v (note 6) 1.2 v shdn shdn input threshold v il , (v out + 0.5v) v in 5.5v (note 6) 0.4 v i shdn shdn input bias current shdn = gnd or vin 0.1 100 na i adj adj input leakage adj=1.3v, 0.1 3 na
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 7/20 thermal shutdown temperature 165 t sd thermal shutdown hysteresis 30 t on start-up time c out = 10f, v out at 90% of final value 80 s note 1: absolute maximum ratings indicate limits beyond which damage may occur. electrical specifications do not apply when operating the device outside of its rated operating conditions. note 2: all voltages are with respect to the potential at the ground pin. note 3: maximum power dissipation for the device is ca lculated using the following equations: ja a t - j(max) t d p = where tj(max) is the maximum junction temperature, ta is the ambient temperature, and ja is the junction-to-ambient thermal resistance. e.g. for the msop-8 package ja = 223c/w, t j (max) = 150c and using ta = 25c, the maximum power dissipation is found to be 561mw. the derating factor (-1/ ja ) = -4.5mw/c, thus below 25c the power dissipation figure can be increased by 4.5m w per degree, and similarity decreased by this factor for temperatures above 25c. note 4: typical values represent the most likely parametric norm. note 5: human body model: 1.5k in series with 100pf. note 6: condition does not apply to input voltages below 2.5v since this is the minimum input operating voltage. note 7: dropout voltage is measured by reducing v in until v out drops 100mv from its nominal value at v in -v out = 0.5v. dropout voltage does not apply to the regulator versions with v out less than 2.5v.
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 8/20 functional block diagram fig.2. the EMP8966 functional block diagram
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 9/20 typical performance characteristics unless otherwise specified, vin = v out (nom) + 1v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. psrr vs. frequency psrr vs. frequency psrr vs. frequency psrr vs. frequency psrr vs. frequency dropout voltage vs. load current psrr (db) psrr (db) psrr (db) psrr (db) psrr (db) dropout voltage (mv) frequency (hz) frequency (hz) frequency (hz) frequency (hz) frequency (hz) load current (ma) vin=4.3v, v out =3.3v vin=5v, v out =3.3v vin=4v, v out =2.5v vin=3.3v, v out =1.8v vin=4v, v out =1.8v v out =3.3v
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 10/20 typical performance characteristics unless otherwise specified, vin = v out (nom) + 1v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. (continued) supply current vs. input voltage (sot-89-5) supply current vs. load current input voltage (v) load transient 400 s/div load current (ma) load transient 400 s/div v out i out 50mv/div 100ma/div 1ma~300ma 50mv/div 200ma/div 1ma~600ma v out i out supply current (a) supply current (a)
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 11/20 typical performance characteristics unless otherwise specified, vin = v out (nom) + 1v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. (continued) line transient current limit line transient 200 s/div enable and disable 400 s/div v out =3.3v, i out =10ma v out (10mv/div) 4.3v 5.3v vin v out =3.3v, i out =600ma v out (10mv/div) 4.3v 5.3v v out (1v/div) v shdn (2v/div) 100ms/div 200 s/div i out (200ma/div) vin
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 12/20 application information general description referring to figure 2 as shown in the functional block diagram section, the EMP8966 adopts the classical regulator topology in which negative feedback control is used to perform the desired voltage regulating function. the negative feedback is formed by using feedback resistors (r1, r2) to sample the output voltage for the non-inverting input of the erro r amplifier, whose inverting input is set to the bandgap reference voltage. by virtue of its high open-loop gain, the error amplifier operates to ensure that the sampled output feedback voltage at its non-inverting input is virtually equal to the preset bandgap reference voltage. these feedback resistors can be either internal or external to the EMP8966, depending on whether a preset or an adjustable output voltage version is being used. the error amplifier compares the voltage difference at its inputs and produces an appropriate driving voltage to the p-channel mos pass transistor to control the amount of current reaching the output. if there are changes in the output voltage due to load changes, the feedback resistors register such changes to the non-inverting input of the error amplifier. the error amplifier then adjusts its driving voltage to maintain virtual short between its two input nodes under all loading conditions. in a nutshell, the regulation of the output voltage is achieved as a direct result of the error amplifier keeping its input voltages equal. this negative feedback control topology is further augmented by the shutdown, the fault detection, and the temperature and current protection circuitry. output voltage control the EMP8966 allows direct user control of the output voltage in accordance with the amount of negative feedback present. to see the explicit relationship between the output voltage and the negative feedback, it is convenient to conceptualize the EMP8966 as an ideal non-inverting operational amplifier with a fixed dc reference voltage vref at its non-inverting input. such a conceptual representation of the EMP8966 in closed-loop configuration is shown in figure 3. this ideal op amp features an ultra-high input resistance such that its inverting input voltage is virtually fixed at vref. the output voltage is therefore given by: ? ? ? ? ? ? + = 1 2 r 1 r ref v out v this equation can be rewritten in the following form to facilitate the determination of the resistor values for a chosen output voltage: ? ? ? ? ? ? ? = 1 1.19v out v 2 r 1 r set r2 equal to 100k to optimize for overall accuracy, power supply rejection, noise, and power consumption. v in v out r 1 r 2 v ref + - output capacitor the EMP8966 is specially designed for use with ceramic output capacitors of as low as 2.2f to take advantage of the savings in cost and space as well as the superior filtering of high frequency noise . capacitors of higher value or other types may be used, but it is important to make sure its equivalent series resistance (esr) be restricted to less than 0.5 . the use of larger capacitors with smaller esr values is desirable for applications involving large and fast input or output transients, as well as for situations where the application systems are not physically located immediately adjacent to the figure 3. simplified regulator topology v ref v in v out r 1 r 2
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 13/20 application information (continued) battery power source. typical ceramic capacitors suitable for use with the EMP8966 are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10%, respectively, as the temperature increases. involving large and fast input or output transients, as well as for situations where the application systems are not physically located immediately adjacent to the battery power source. typical ceramic capacitors suitable for use with the EMP8966 are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10%, respectively, as the temperature increases. no-load stability the EMP8966 is capable of stable operation during no-load conditions, a mandatory feature for some applications such as cmos ram keep-alive operations. input capacitor a minimum input capacitance of 1f is required for EMP8966. the capacitor value may be increased without limit. improper workbench set-ups may have adverse effects on the normal operation of the regulator. a case in point is the instability that may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. this will establish a pseudo lcr network, and is likely to happen under high current conditions or near dropout. a 10f tantalum input capacitor will dampen the parasitic lcr action thanks to its high esr. however, cautions should be exercised to avoid regulator short-circuit damage when tantalum capacitors are used, for they are prone to fail in short-circuit operating conditions. compensation (noise bypass) capacitor substantial reduction in the output voltage noise of the EMP8966 is accomplished through the connection of the noise bypass capacitor cc (33nf optimum) between pin 4(sot-23-6) and the ground. because pin 4(sot-23-6) connects directly to the high impedance output of the bandgap reference circuit, the level of the dc leakage currents in the cc capacitors used will adversely reduce the regulator output voltage. this sets the dc leakage level as the key selection criterion of the cc capacitor types for use with the EMP8966. npo and cog ceramic capacitors typically offer very low leakage. although the use of the cc capacitors does not affect the transient response, it does affect the turn-on time of the regulator. tradeoff exists between output noise level and turn-on time when selecting the cc capacitor value. power dissipation and thermal shutdown thermal overload results from excessive power dissipation that causes the ic junction temperature to increase beyond a safe operating level. the EMP8966 relies on dedicated thermal shutdown circuitry to limit its total power dissipation. an ic junction temperature tj exceeding 165c will trigger the thermal shutdown logic, turning off the p-channel mos pass transistor. the pass transistor turns on again after the junction cools off by about 30c. when continuous thermal overload conditions persist, this thermal shutdown action then results in a pulsed waveform at the output of the regulator. the concept of thermal resistance ja (c/w) is often used to describe an ic junction?s relative readiness in allowing its thermal energy to dissipate to its ambient air. an ic junction with a low thermal resistance is preferred because it is relatively effective in dissipating its thermal energy to its ambient, thus resulting in a relatively low and desirable junction temperature. the relationship between ja and tj is as follows: t j = ja (pd) + t a t a is the ambient temperature, and p d is the power generated by the ic and can be written as: p d = i out (v in - v out )
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 14/20 as the above equations show, it is desirable to work with ics whose ja values are small such that t j does not increase strongly with p d . to avoid thermally overloading the EMP8966, refrain from exceeding the absolute maximum junction temperature rating of application information (continued) 150c under continuous operating conditions. overstressing the regulator with high loading currents and elevated input-to-output differential voltages can increase the ic die temperature significantly. shutdown the EMP8966 enters the sleep mode when the shdn pin is low. when this occurs, the pass transistor, the error amplifier, and the biasing circuits, including the bandgap reference, are turned off, th us reducing the supply current to typically 1na. such a low supply current makes the EMP8966 best suited for battery-powered applications. the maximum guaranteed voltage at the shdn pin for the sleep mode to take effect is 0.4v. a minimum guaranteed voltage of 1.2v at the shdn pin will activate the EMP8966. direct connection of the shdn pin to the vin to keep the regulator on is allowed for the EMP8966. in this case, the shdn pin must not exceed the supply voltage vin. fast start-up fast start-up time is important for overall system efficiency improvement. the EMP8966 assures fast start-up speed when using the optional noise bypass capacitor (cc). to shorten start-up time, the EMP8966 internally supplies a 500a current to charge up the capacitor until it reaches about 90% of its final value.
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 15/20 physical dimensions sot-23-5 o 2 symbpls min. nom. max. a 1.05 1.20 1.35 a1 0.05 0.10 0.15 a2 1.00 1.10 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 2.90 3.00 e 2.60 2.80 3.00 e1 1.50 1.60 1.70 e 0.95 bsc e1 1.90 bsc l 0.30 0.45 0.55 l1 0.60 ref 0 5 10 2 6 8 10 unit: mm
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 16/20 sot-23-6 o 2 symbpls min. nom. max. a 1.45 a1 0.15 a2 0.90 1.15 1.30 b 0.30 0.50 c 0.08 0.22 d 2.90 bsc. e 2.80 bsc. e1 1.60 bsc. e 0.95 bsc e1 1.90 bsc l 0.30 0.45 0.60 l1 0.60 ref l2 0.25 ref 0 4 8 2 5 10 15 unit: mm
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 17/20 sot-89-5 dimensions millimeters ref. min. max. a 4.4 4.6 b 4.05 4.25 c 1.5 1.7 d 1.3 1.5 e 2.4 2.6 f 0.8 - g 3.00 ref. h 1.50 ref. i 0.4 0.52 j 1.4 1.6 k 0.35 0.41 l 5 typ. unit: mm
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 18/20 notice order, mark & packing information no. of pin adj en cc vout package old marking product id p630 p630 date code 5 y y n adj sot-23-5 8965 tracking code EMP8966-00vf05grr p530 p530 date code 5 y y n adj sot-89-5 8965 tracking code EMP8966-00vg05grr 6 y y y adj sot-23-6 p630 p630 date code EMP8966-00vc06grr package & packing sot-23-5 3k units tape & reel sot-23-6 3k units tape & reel sot-89-5 1k units tape & reel
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 19/20 revision history revision date description 1.0 2008.10.07 original 1.1 2009.05.08 modify order information
esmt/emp EMP8966 elite semiconductor memory technology inc. / elite micropower inc. publication date : may 2009 revision : 1.1 20/20 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to chang e the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of our products. no responsibility is assum ed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. no license, either ex press , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. a ny semiconductor devices may have inh erently a certain rate of failure. to minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer w hen making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devi ces or system, where failure or abnormal operation may directly affect human live s or cause physical injury or property damage. if products descri bed here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

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