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| SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 1 version 0.5 SN8PC13 user?s manual version 0.5 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or desig n. sonix does not assume any liability arising out of the application or use of an y product or circuit described her ein; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to suppor t or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and re asonable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 2 version 0.5 amendment history version date description sep. 2005 1. first issue ver 0.1 nov.2005 1. add brown-out reset circuit. ver 0.2 dec 2005 1. modify topr value. 2. modify SN8PC13_v02 brown-out reset description 3. remove power consumption(pc) 4. modify m2ide 1.07. 5. modify electrical characteristic. ver 0.3 jan 2006 1. remove p5.4. 2. modify ir output description. irout pin is low status when irout=0 or the system is in power down. ver 0.4 may 2006 1. modify working voltage range to lvd~5.5v. ver 0.5 nov. 2006 1. add marking definition. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 3 version 0.5 table of content amendment history ........................................................................................................................ .... 2 1 1 1 product overview............................................................................................................... .......... 6 1.1 features ................................................................................................................... ..................... 6 1.2 system block diagram .......................................................................................................... 7 1.3 pin assignment ..................................................................................................................... ...... 7 1.4 pin descriptions................................................................................................................... ...... 8 1.5 pin circuit diagrams............................................................................................................... 9 2 2 2 central processor unit (cpu) .............................................................................................. 10 2.1 memory map............................................................................................................................ ... 10 2.1.1 program memory (rom) ................................................................................................. 10 2.1.1.1 reset vector (0000h) .................................................................................................. 1 1 2.1.1.2 checksum calculation........................................................................................... 12 2.1.2 code option table ........................................................................................................... 13 2.1.3 data memory (ram)........................................................................................................... 13 2.1.4 system register................................................................................................................ .14 2.1.4.1 system register table ............................................................................................ 14 2.1.4.2 system register description ............................................................................... 14 2.1.4.3 bit definition of system register....................................................................... 15 2.1.4.4 accumulator ............................................................................................................ ... 16 2.1.4.5 program flag ........................................................................................................... .... 17 2.1.4.6 program counter....................................................................................................... 1 8 2.1.4.7 y, z registers......................................................................................................... ........ 20 2.1.4.8 r registers ............................................................................................................ ......... 21 2.2 addressing mode .................................................................................................................... 22 2.2.1 immediate addressing mode....................................................................................... 22 2.2.2 directly addressing mode .......................................................................................... 22 2.2.3 indirectly addressing mode ...................................................................................... 22 2.3 stack operation...................................................................................................................... 23 2.3.1 overview ....................................................................................................................... ....... 23 2.3.2 stack registers ................................................................................................................ .24 2.3.3 stack operation example............................................................................................. 25 3 3 3 reset .......................................................................................................................... ........................... 26 3.1 overview................................................................................................................... .................. 26 3.2 power on reset......................................................................................................................... 2 7 3.3 watchdog reset...................................................................................................................... 27 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 4 version 0.5 3.4 brown out reset ..................................................................................................................... 28 3.4.1 brown out description ................................................................................................. 28 3.4.2 the system operating voltage decsription........................................................ 29 3.4.3 brown out reset improvement.................................................................................. 29 3.5 external reset ........................................................................................................................ 31 3.6 external reset circuit ....................................................................................................... 31 3.6.1 simply rc reset circuit ........................................................................................................ ... 31 3.6.2 diode & rc reset circuit ....................................................................................................... .32 3.6.3 zener diode reset circuit ...................................................................................................... .. 32 3.6.4 voltage bias reset circuit..................................................................................................... ... 33 3.6.5 external reset ic.............................................................................................................. ........ 34 4 4 4 system clock ................................................................................................................... ............... 35 4.1 overview................................................................................................................... .................. 35 4.2 clock block diagram .......................................................................................................... 35 4.3 oscm register ....................................................................................................................... .... 36 4.4 system high clock ................................................................................................................. 36 5 5 5 system operation mode .......................................................................................................... .37 5.1 overview................................................................................................................... .................. 37 5.2 system mode switching....................................................................................................... 37 5.3 wakeup ..................................................................................................................... .................... 38 5.3.1 overview ....................................................................................................................... ....... 38 5.3.2 wakeup time.................................................................................................................... .... 38 6 6 6 i/o port ....................................................................................................................... ......................... 39 6.1 i/o port mode ........................................................................................................................... .. 39 6.2 i/o port data register .......................................................................................................... 40 7 7 7 timers ......................................................................................................................... ......................... 41 7.1 watchdog timer...................................................................................................................... 41 7.2 timer 0 (t0) ........................................................................................................................... ........ 43 7.2.1 overview ....................................................................................................................... ....... 43 7.2.2 t0m mode register........................................................................................................... 43 7.2.3 t0c counting register................................................................................................... 44 7.2.4 t0 timer operation sequence ..................................................................................... 45 8 8 8 ir output ...................................................................................................................... ...................... 46 8.1 overview................................................................................................................... .................. 46 8.2 ir control register............................................................................................................... 47 8.2.1 tc0m mode register ........................................................................................................ 47 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 5 version 0.5 8.2.2 tc0c counting register ................................................................................................ 47 8.2.3 tc0r auto-load register .............................................................................................. 48 8.2.4 tc0d ir duty control register .................................................................................. 49 8.2.5 ir output operation sequence.................................................................................. 50 8.3 ir remote controller application circuit.............................................................. 51 9 9 9 instruction table .............................................................................................................. ......... 52 1 1 1 0 0 0 electrical characteristic .............................................................................................. 53 10.1 absolute maximum rating ................................................................................................ 53 10.2 electrical characteristic............................................................................................... 53 1 1 1 1 1 1 development tool ............................................................................................................... ... 54 1 1 1 2 2 2 otp programming pin............................................................................................................ .55 12.1 t he pin assignment of e asy w riter transition board socket : .............................................. 55 12.2 p rogramming p in m apping : .......................................................................................................... 56 1 1 1 3 3 3 package information ........................................................................................................... 5 7 13.1 p-dip 20 pin ............................................................................................................................ ........ 57 13.2 sop 20 pin............................................................................................................................ ........... 58 13.3 ssop 20 pin............................................................................................................................ ......... 59 1 1 1 4 4 4 marking definition............................................................................................................. .... 60 14.1 in troduction ............................................................................................................................... .. 60 14.2 m arking indetification system ................................................................................................... 60 14.3 m arking e xample .......................................................................................................................... 61 14.4 d atecode system ........................................................................................................................... 61 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 6 version 0.5 1 1 1 product overview 1.1 features ? memory configuration ? two 8-bit timer/counter otp rom size: 2k * 16 bits. t0: basic timer ram size: 48 * 8 bits. tc0: for ir output ? four levels stack buffer ? one channel ir output. ? i/o pin configuration ? on chip watchdog timer and clock source is internal bi-directional: p1, p0.6, p0.7 low clock rc type (16khz @3v, 32khz @5v). input only: p0.0~p0.4 ir output: irout ? single system clocks wakeup: p0, p1 level change trigger. external high clock: 4 mhz crystal/resonator pull-up resisters: p0, p1 ? operating modes ? powerful instructions normal mode: both high and low clock active four clocks per instruction cycle (4t) sleep mode: both high and low clock stop most of instructions are one cycle only. all rom area jmp instruction. ? package (chip form support) all rom area call address instruction. pdip 20 pins all rom area lookup table function (movc) sop 20 pins ssop 20 pins ) features selection table chip rom ram stack t0 osc. i/o ir output wakeup pin no. package sn8pc01 0.5k*16 32 4 - 455khz 16 fix 38khz 9 dip20/sop20 SN8PC13 2k*16 48 4 v 4mhz 16 duty, cycle programmable 15 dip20/sop20/ssop20 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 7 version 0.5 1.2 system block diagram external high osc. acc internal low rc timing generator ram system registers lvd watchdog timer timer & counter p0 p5 p1 ir alu pc flags ir otp rom ir output 1.3 pin assignment SN8PC13p (p-dip 20 pins) SN8PC13s (sop 20 pins) SN8PC13x (ssop 20 pins) p1.6 1 u 20 p1.5 p1.7 2 19 p1.4 p0.7 3 18 p1.3 p0.6 4 17 p1.2 irout 5 16 p1.1 vdd 6 15 p1.0 xout 7 14 p0.3 xin 8 13 p0.2 vss 9 12 p0.1 p0.4/rst/vpp 10 11 p0.0 SN8PC13p SN8PC13s SN8PC13x SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 8 version 0.5 1.4 pin descriptions pin name type description vdd, vss p power supply input pins for digital circuit. xin i xin: oscillator input pin. xout o xout: oscillator output pin. p1.0 i/o p1.0: port 1.0 bi-direction pin. schmitt trigger structure. built-in pull-up resistors as input mode. build-in wake-up function by edge trigger. p1.1 i/o p1.1: port 1.1 bi-direction pin. schmitt trigger structure. built-in pull-up resistors as input mode. build-in wake-up function by edge trigger. p1 [7:2] i/o p1: port 1 bi-direction pin. schmitt trigger structure. built-in pull-up resistors as input mode. build-in wake-up function by edge trigger. p0 [3:0] i p0.0~p0.3: port 0 input-only pin. schmitt trigger structure. built-in pull-up resistors. build-in wake-up function by edge trigger. p0.4/rst/vpp i, p rst is system external reset input pin under ext_rst mode. schmitt trigger structure, active ?low?, normal stay to ?high?. p0.4 is input only pin without pull-up resistor under p0.4 mode. add the 100 ohm external resistor on p1.4,when it is set to be input pin. build-in wake-up function by edge trigger. otp 12.3v power input pin in programming mode. p0 [7:6] i/o p0[7:6]: port 0 bi-direction pin. schmitt trigger structure. built-in pull-up resistors as input mode. build-in wake-up function by edge trigger. irout o irout: ir output pin. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 9 version 0.5 1.5 pin circuit diagrams port 1, p0.6, p0.7 structure: pull-up pin output latch input bus pnm output bus port 0.0~0.3 structure: pin int. bus pull-up port 0.4 structure: pin ext. reset code option int. bus int. rst irout structure: pin ir output signal irout output low SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 10 version 0.5 2 2 2 central processor unit (cpu) 2.1 memory map 2.1.1 program memory (rom) ) 2k words rom rom 0000h reset vector user reset vector jump to user start address 0001h . . 0007h general purpose area 0008h user program . . 000fh 0010h 0011h . . . . . 07fch general purpose area end of user program 07fdh 07feh 07ffh reserved SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 11 version 0.5 2.1.1.1 reset vector (0000h) a one-word vector address area is used to execute system reset. ) power on reset ) watchdog rese ) external reset after power on reset, external reset or watchdog timer over flow reset, then the chip will restart the program from address 0000h and all system re gisters will be set as default values. the following example shows the way to define the reset vector in the program memory. ? example: defining reset vector org 0 ; 0000h jmp start ; jump to user program address. ? org 10h start: ; 0010h, the head of user program. ? ; user program ? endp ; end of program SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 12 version 0.5 2.1.1.2 checksum calculation the last rom address are reserved area. user should avoi d these addresses (last address) when calculate the checksum value. ? example: the demo program shows how to calculated checksum from 00h to the end of user?s code. mov a,#end_user_code$l mov end_addr1, a ; save low end address to end_addr1 mov a,#end_user_code$m mov end_addr2, a ; save middle end address to end_addr2 mov a, #0 ; set y to 00h mov y, a mov z, a ; set z to 00h @@: movc bclr fc ; clear c flag adc data1, a ; add a to data1 mov a, r adc data2, a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; if z = 00h increase y end_check: mov a, end_addr1 cmprs a, z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a, end_addr2 cmprs a, y ; if yes, check if y = middle end address jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is done. y_add_1: incms y ; increase y nop jmp @b ; jump to checksum calculate checksum_end: ? ? end_user_code: ; label of program end SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 13 version 0.5 2.1.2 code option table code option content function description always_on watchdog timer is always on enable even in power down and green mode. enable enable watchdog timer. watchdog timer stops in power down mode and green mode. watch_dog disable disable watchdog function. reset enable external reset pin. reset_pin p04 enable p0.4 input only without pull-up resister. enable enable rom code security function. security disable disable rom code security function. 2.1.3 data memory (ram) ) 48 x 8-bit ram address ram location 000h ? ? ? ? ? 02fh general purpose area 080h ? 80h~ffh of bank 0 store system registers (128 bytes). ? ? ? ? system register bank 0 0ffh end of bank 0 area SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 14 version 0.5 2.1.4 system register 2.1.4.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag - - - - - - - - - 9 - - - - - - - - - - - - - - - - a - - - - - - - - - - - - - - - - b - - - - - - - - p0m - - - - - - - c - p1m - - - - - - intrq - oscm - wdtr tc0r pcl pch d p0 p1 - - - - - - t0m t0c tc0m tc0c - - - stkp e - - - - - - - @yz tc0d - - - - - - - f - - - - - - - - stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.1.4.2 system register description pflag = rom page and special flag register. r = w orking register and rom look-up data buffer. @yz = ram yz indirect addressing index pointer. y, z = working, @yz and rom addressing register. pnm = port n input/output mode register. pn = port n data buffer. intrq = t0 overflow flag register. pnur = port n pull-up resister control register. oscm = oscillator mode register. pch, pcl = program counter. t0m = t0 mode register. t0c = tc0 counting register. tc0m = tc0 mode register. tc0c = tc0 counting register. tc0r = tc0 auto-reload data buffer. wdtr = watchdog timer clear register. tc0d = ir output duty register. stk0~stk3 = stack 0 ~ stack 3 buffer. stkp = stack pointer buffer. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 15 version 0.5 2.1.4.3 bit definition of system register address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h - - - - - c z r/w pflag 0b8h p07m p06m - - - - - - r/w p0m 0c1h p17m p16m p15m p14m p13m p12m p11m p10m r/w p1m i/o direction 0c8h - - - t0irq - - - - r/w intrq 0cah 0 0 0 cpum1 cpum0 0 0 0 r/w oscm 0cch wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 w wdtr 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - - pc10 pc9 pc8 r/w pch 0d0h p07 p06 - p04 p03 p02 p01 p00 r/w p0 data buffer 0d1h p17 p16 p15 p14 p13 p12 p11 p10 r/w p1 data buffer 0d8h t0enb t0rate2 t0rate1 t0rate0 - - - - r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah - - - - - - - ir0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dfh - - - - - - stkpb1 stkpb0 r/w stkp stack pointer 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz index pointer 0e8h tc0d7 tc0d6 tc0d5 tc0d4 tc0d3 tc0d2 tc0d1 tc0d0 w tc0d 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h - - - - - s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2 pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh - - - - - s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - - s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0 pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - - s0pc10 s0pc9 s0pc8 r/w stk0h ? note: 1. to avoid system error, please be sure to put all the ?0? and ?1? as it indicates in the above table . 2. all of register names had been declared in sn8asm assembler. 3. one-bit name had been declared in sn8asm assembler with ?f? prefix code. 4. ?bset?, ?bclr? instructions are only available to the ?r/w? registers. 5. for detail description, please refer to th e ?system register quick reference table? . SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 16 version 0.5 2.1.4.4 accumulator the acc is an 8-bit data register responsible for trans ferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c) occurrence, then these flags will be set to pflag register. ? example: read and write acc value. ; read acc data and store in buf data memory mov buf, a ; write a immediate data into acc mov a, #0fh ; write acc data from buf data memory mov a, buf SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 17 version 0.5 2.1.4.5 program flag the pflag register contains the arithmet ic status of alu operation. c, z bits indicate the result status of alu operation. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag - - - - - c - z read/write - - - - - r/w - r/w after reset - - - - - 0 - 0 bit 2 c: carry flag 1 = addition with carry, subtraction without borrowing, ro tation with shifting out logic ?1?, comparison result 0. 0 = addition without carry, s ubtraction with borrowing signal, rotation wi th shifting out logic ?0?, comparison result < 0. bit 0 z: zero flag 1 = the result of an arithmetic/logic/branch operation is zero. 0 = the result of an arithmetic/logic/branch operation is not zero. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 18 version 0.5 2.1.4.6 program counter the program counter (pc) is a 11-bit binary counter sepa rated into the high-byte 3 and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by execut ing call or jmp instruction. when jmp or call instruction is executed, the desti nation address will be inserted to bit 0 ~ bit 10. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - - pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - - - - 0 0 0 0 0 0 0 0 0 0 0 pch pcl ) one address skipping there are nine instructions (cmprs, iincms, decms, bts0 , bts1) with one address skipping function. if the result of these instructions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. ? ? c0step: nop mov a, buf0 ; move buf0 value to acc. bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. ? ? c1step: nop if the acc is equal to the immediat e data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step. ? ? c0step: nop SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 19 version 0.5 if the destination increased by 1, wh ich results overflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop if the destination decreased by 1, which results underflo w of 0x00 to 0xff, the pc will add 2 steps to skip next instruction. decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop ) multi-address jumping users can jump around the mult i-address by either jmp inst ruction or add m, a instruction (m = pcl) to activate multi-address jumping function. program counter supports ?adc m,a? instructions for carry to pch when pcl overflow automatically. for jump table or others applications, users can calculat e pc value by the three instructions and don?t care pcl overflow problem. ? note: pch only support pc up counting result and doesn?t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl?acc, pch keeps value and not change. ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h mov a, #28h mov pcl, a ; jump to address 0328h ? ; pc = 0328h mov a, #00h mov pcl, a ; jump to address 0300h ? ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h adc pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point ? ? SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 20 version 0.5 2.1.4.7 y, z registers the y and z registers are the 8-bit buffers. there ar e three major functions of these registers. z can be used as general working registers z can be used as ram data pointers with @yz register z can be used as rom data pointer with the movc instruction for look-up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - ? example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. mov a, #00h ; to set ram bank 0 for y register mov y, a mov a, #25h ; to set location 25h for z register mov z, a mov a, @yz ; to read a data into acc ? example: uses the y, z register as data pointer to clear the ram data. mov a, #0 ; y = 0, bank 0 mov y, a mov a, #07fh ; z = 7fh, the last address of the data memory area mov z, a clr_yz_buf: mov a, #0 ; clear @yz to be zero mov @yz, a decms z ; z ? 1, if z= 0, finish the routine jmp clr_yz_buf ; not zero mov a, #0 ; clear @yz to be zero mov @yz, a end_clr: ; end of clear general purpose data memory area of bank 0 ? SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 21 version 0.5 2.1.4.8 r registers r register is an 8-bit buffer. there ar e two major functions of the register. z can be used as working register z for store high-byte data of look-up table (movc instruction executed, the high- byte data of specified rom address will be stored in r register and the low-byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - ? note: please refer to the ?look-up table description? about r regi ster look-up table application. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 22 version 0.5 2.2 addressing mode 2.2.1 immediate addressing mode the immediate addressing mode uses an immediate data to set up the location in acc or specific ram. ? example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into acc. 2.2.2 directly addressing mode the directly addressing mode moves the cont ent of ram location in or out of acc. ? example: move 0x12 ram location data into acc. mov a, 12h ; to get a content of ram location 0x12 of bank 0 and save in acc. ? example: move acc data into 0x12 ram location. mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. 2.2.3 indirectly addressing mode the indirectly addressing mode is to access the memory by the data pointer registers (y/z). ? example: indirectly addressing mode with @yz register. mov a, #0 ; to clear y register to access ram bank 0. mov y, a mov a, #12h ; to set an immediate data 12h into z register. mov z, a mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 23 version 0.5 2.3 stack operation 2.3.1 overview the stack buffer has 4-level. these buffers are designed to push and pop up program counter?s (pc) data when ?call? instruction are executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack buffer. the stknh and stknl are the stack buffers to store program counter (pc) data. ret call stkp = 3 stkp = 2 stkp = 1 stkp = 0 stack level stk3h stk2h stk1h stk0h stack buffer high byte pch stkp stk3l stk2l stk1l stk0l stack buffer low byte pcl stkp stkp - 1 stkp + 1 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 24 version 0.5 2.3.2 stack registers the stack pointer (stkp) is a 2-bit register to store t he address used to access the st ack buffer, 11-bit data memory (stknh and stknl) set aside for temp orary storage of stack addresses. the two stack operations are writing to the top of the stac k (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always point to the top address of stack buffer and wr ite the last program counter val ue (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction ex ecuted. stack operation is a lifo type (last in and first out). the stack pointer (st kp) and stack buffer (stknh and stknl) are located in the system register area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp - - - - - - stkpb1 stkpb0 read/write - - - - - - r/w r/w after reset - - - - - - 1 1 bit[2:0] stkpbn: stack pointer (n = 0 ~ 1) ? example: stack pointer (stkp) reset, we strongl y recommended to clear the stack pointers in the beginning of the program. mov a, #00000011b mov stkp, a 0f0h~0f8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - - - snpc10 snpc9 snpc8 read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0f0h~0f8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 3 ~ 0) SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 25 version 0.5 2.3.3 stack operation example the two kinds of stack-save operations re fer to the stack pointer (stkp) and writ e the content of program counter (pc) to the stack buffer are call instruction. under each condi tion, the stkp decreases and points to the next available stack location. the stack buffer stores the program counter about the op-code address. the stack-save operation is as the following table. stkp register stack buffer stack level stkpb1 stkpb0 high byte low byte description 0 1 1 free free - 1 1 0 stk0h stk0l - 2 0 1 stk1h stk1l - 3 0 0 stk2h stk2l - 4 1 1 stk3h stk3l - > 4 1 0 - - stack over, error there are stack-restor e operations correspond to each push operation to restore the program counter (pc). the ret instruction is for call instruction. when a pop operation oc curs, the stkp is incremented and points to the next free stack location. the stack buffer restores the last progra m counter (pc) to the progr am counter registers. the stack-restore operation is as the following table. stkp register stack buffer stack level stkpb1 stkpb0 high byte low byte description 4 1 1 stk3h stk3l - 3 0 0 stk2h stk2l - 2 0 1 stk1h stk1l - 1 1 0 stk0h stk0l - 0 1 1 free free - SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 26 version 0.5 3 3 3 reset 3.1 overview the system would be reset in three conditions as following. z power on reset z watchdog reset z brown out reset z external reset (only supports external reset pin enable situation) when any reset condition occurs, all syst em registers keep initial status, progra m stops and program counter is cleared. after reset status released, the system boots up and program starts to execute from org 0. finishing any reset sequence needs some time. the system provides complete procedures to make the power on reset successful. for different oscillat or types, the reset time is different. that causes the vdd rise rate and start-up time of different oscillator is not fixed. rc ty pe oscillator?s start-up time is very shor t, but the crystal type is longer. under clie nt terminal application, users have to take care the power on reset time for the master terminal requirement. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 27 version 0.5 3.2 power on reset the power on reset depend no lvd operation for most power- up situations. the power supplying to system is a rising curve and needs some time to achieve the normal voltage. power on reset sequence is as following. z power-up: system detects the power voltage up and waits for power stable. z external reset (only external reset pin enable): system checks external reset pin status. if external reset pin is not high level, the system keeps reset stat us and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal condition, system works well and clears watchdog timer by program. under error condition, system is in unknown situation and watchdog can?t be clear by program before watchdog timer overflow. watchdog timer overflow occurs and the system is reset. after watchdog reset, the system restarts and returns normal mode. watchdog reset sequence is as following. z watchdog timer status: system checks watchdog timer overflow stat us. if watchdog timer ov erflow occurs, the system is reset. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? note: please refer to the ?watchdog timer? about watchdog timer detail information. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 28 version 0.5 3.4 brown out reset 3.4.1 brown out description the brown out reset is a power dropping condition. the powe r drops from normal voltage to low voltage by external factors (e.g. eft interference or extern al loading changed). the brown out reset would make the system not work well or executing program error. vdd vss v1 v2 v3 system work well area system work error area brown out reset diagram the power dropping might through the voltage range that ?s the system dead-band. the dead-band means the power range can?t offer the system minimum operation power re quirement. the above diagram is a typical brown out reset diagram. there is a serious noise under the vdd, and vdd voltage drops very deep. there is a dotted line to separate the system working area. the above area is the system work well area. the below area is the system work error area called dead-band. v1 doesn?t touch the below area and not effe ct the system operation. but the v2 and v3 is under the below area and may induce the system error occurrence. let system under dead-band includes some conditions. dc application: the power source of dc application is usually using battery . when low battery condition and mcu drive any loading, the power drops and keeps in dead-band. under the situat ion, the power won?t drop dee per and not touch the system reset voltage. that makes the system under dead-band. ac application: in ac power application, the dc power is regulated from ac power source. this kind of power usually couples with ac noise that makes the dc power dirty. or the external loading is very heavy, e. g. driving motor. the loading operating induces noise and overlaps with the dc power. vdd drop s by the noise, and the system works under unstable power situation. the power on duration and power down duration are longer in ac application. the system power on sequence protects the power on successful, but the power do wn situation is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead-band for a while. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 29 version 0.5 3.4.2 the system operating voltage decsription to improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. differe nt system executing rates have differe nt system minimum operating voltage. the electrical characteristic section shows the system voltage to executing rate relationship. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area normally the system operation voltage ar ea is higher than the system reset voltage to vdd, and the reset voltage is decided by lvd detect level. the system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. the dead-band definition is the system minimum operat ing voltage above the system reset voltage. 3.4.3 brown out reset improvement how to improve the brown reset condition? there are some methods to improve brown out reset as following. z lvd reset z watchdog reset z reduce the system executing rate z external reset circuit. (zener diode reset circuit, voltage bias reset circuit, external reset ic) ? note: 1. the ? zener diode reset circuit?, ?voltage bias reset circuit? and ?external reset ic? can completely improve the brown out reset, dc low battery and ac slow power down conditions. 2. for ac power application and enhance eft performance, the s y stem clock is 4mhz/4 ( 1 mips ) and use external reset (? zener diode reset circui t?, ?voltage bias reset circuit?, ?external reset ic?). the structure can improve noise effective and get good eft characteristic. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 30 version 0.5 lvd reset: vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset. the lvd (low voltage detector) is built-in sonix 8-bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be triggered, an d the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of volt age and not easy to cover all dead-band range. using lvd to improve brown out reset is depend on application requiremen t and environment. if the power variation is very deep, violent and trigger the lvd, the lvd ca n be the protection. if the power variation can touch the lvd detect level and make system work error, the lvd can? t be the protection and need to other reset methods. more detail lvd information is in the electrical characteristic section. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog timer in several addresses. the system executes normally and the watchdog won?t reset system. when the system is under dea d-band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously counti ng until overflow occurrence. the overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is still in dead-band, the system reset sequence won?t be successful and the system stays in reset status until the power return to normal range. reduce the system executing rate: if the system rate is fast and the dead-band exists, to redu ce the system executing rate can improve the dead-band. the lower system rate is with lower minimum operating voltage. select the power voltage that?s no dead-band issue and find out the mapping system rate. adjust the system ra te to the value and the syst em exits the dead-band issue. this way needs to modify whole program timing to fit the application requirement. external reset circuit: the external reset methods also can improve brown out rese t and is the complete solution. there are three external reset circuits to improve brown out reset including ?zener di ode reset circuit?, ?voltage bias reset circuit? and ?external reset ic?. these three reset structures use external rese t signal and control to make sure the mcu be reset under power dropping and under dead-band. the external rese t information is described in the next section. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 31 version 0.5 3.5 external reset external reset function is controlled by ?reset_pin? c ode option. set the code option as ?reset? option to enable external reset function. external reset pin is schmitt trigge r structure and low level active. the system is running when reset pin is high level voltage input. the reset pin receives the low voltage and the system is reset. the external reset operation actives in power on and normal running mode. duri ng system power-up, the external reset pin must be high level input, or the system keeps in reset stat us. external reset sequence is as following. z external reset (only external reset pin enable): system checks external reset pin status. if external reset pin is not high level, the system keeps reset stat us and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in ac power application? 3.6 external reset circuit 3.6.1 simply rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow rising signal into reset pin as power up. the reset signal is slower than vdd power up timing, and system occurs a power on signal from the timing difference. ? note: the reset circuit is no any protection against unusual power or brown out reset. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 32 version 0.5 3.6.2 diode & rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm this is the better reset circuit. the r1 and c1 circuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against unusual po wer. the diode offers a power positive path to conduct higher power to vdd. it is can make reset pin voltage le vel to synchronize with v dd voltage. the structure can improve slight brown out reset condition. ? note: the r2 100 ohm resistor of ?simply reset circ uit? and ?diode & rc reset circuit? is necessar y to limit any current flowing into reset pin from external capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or electrical over-stress (eos). 3.6.3 zener diode reset circuit mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b the zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vdd vo ltage level is above ?vz + 0. 7v?, the c terminal of the pnp transistor outputs high voltage and mcu operates normal ly. when vdd is below ?vz + 0.7v?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by zener specification. select the right zene r voltage to conform the application. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 33 version 0.5 3.6.4 voltage bias reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b the voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diode reset ci rcuit. use r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to ?0.7v x (r1 + r2) / r1?, the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below ?0.7v x (r 1 + r2) / r1?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistances. select the right r1, r2 value to conform the application. in the circuit diagram condition, the mcu?s reset pin level varies with vdd voltage variation, and the differential voltage is 0.7v. if the vdd drops and the voltage lower than reset pin det ect level, the system would be reset. if want to make the reset active earlier, set the r2 > r1 and the cap between vd d and c terminal voltage is larger than 0.7v. the external reset circuit is with a stable current through r1 and r2 . for power consumption issue application, e.g. dc power system, the current must be considered to whole system power consumption. ? note: under unstable power condition as brown out re set, ?zener diode rest circuit? and ?volta g e bias reset circuit? can protects system no any error occurrence as power droppin g . when power drops below the reset detect volta g e, the s y stem reset would be tri gg ered, and then s y stem executes reset sequence. that makes sure the system work well under unstable power situation. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 34 version 0.5 3.6.5 external reset ic mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf the external reset circuit also use external reset ic to enhance mcu reset performance. this is a high cost and good effect solution. by different application and system require ment to select suitable reset ic. the reset circuit can improve all power variation. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 35 version 0.5 4 4 4 system clock 4.1 overview the micro-controller is a single clock system. the high-speed cl ock is generated fr om the external oscillator circuit. the high-speed clock can be system clock (f osc). the system clock is divided by 4 to be the instruction cycle (fcpu). ) normal mode (high clock): fcpu = fhosc/4. 4.2 clock block diagram fhosc. fcpu = fhosc/4 xin xout cpum0 hosc fcpu fosc z hosc: high_clk code option. z fhosc: external high-speed clock. z fosc: system clock source. z fcpu: instruction cycle. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 36 version 0.5 4.3 oscm register the oscm register is an oscillator control regi ster. it controls oscillator status, system mode. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm 0 0 0 0 cpum0 0 0 0 read/write - - - - r/w - - - after reset - - - - 0 - - - bit 3 cpum0: power down mode (sleep mode) control bit. 0 = normal. 1 = power down mode (sleep mode). ? example: when entering the power down mode (sl eep mode), high-speed oscillator will be stopped. bset fcpum0 ; to stop external hi gh-speed oscillator called power down ; mode (sleep mode). 4.4 system high clock crystal/ceramic devices are driven by xin, xout pins. only support 4mhz oscillator frequency. mcu vcc gnd c 20pf xin x o u t vdd vss c 20pf crystal ? note: connect the crystal/ceramic and c as near as po ssible to the xin/xout/vss pins of micro-controller. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 37 version 0.5 5 5 5 system operation mode 5.1 overview the chip is featured with low power consumption by switching around two different modes as following. z normal mode (high-speed mode) z power-down mode (sleep mode) power down mode (sleep mode) normal mode p0, p1 wake-up function active. external reset circuit active. cpum0 = 1 system mode switching diagram operating mode description mode normal power down (sleep) remark ehosc running stop cpu instruction executing stop t0 timer *active inactive * active if t0enb=1 watchdog timer by watch_dog code option by watch_dog code option refer to code option description wakeup source - p0, p1, reset ehosc : external high clock 5.2 system mode switching ? example: switch normal/slow mode to power down (sleep) mode. bset fcpum0 ; set cpum0 = 1. ? note: during the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 38 version 0.5 5.3 wakeup 5.3.1 overview under power down mode (sleep mode), program doesn?t execute. the wakeup trigger can wake the system up to normal mode. the wakeup trigger sources are external trigger (p0, p1 level change). z power down mode is waked up to normal mode. the wakeup trigger is only external trigger (p0, p1 level change) 5.3.2 wakeup time when the system is in power down mo de (sleep mode), the high clock oscilla tor stops. when wake d up from power down mode, mcu waits for 4096 exte rnal high-speed oscillator clocks as the wake up time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 4096 (sec) + high clock start-up time ? note: the high clock start-up time is depended on the vdd and o scillator type of high clock. ? example: in power down mode (sleep mode), the sy stem is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/fosc * 4096 = 1.024 ms (fosc = 4mhz) the total wakeup time = 1.024ms + oscillator start-up time SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 39 version 0.5 6 6 6 i/o port there are 16 i/o pins and three ports in the mcu. all pi ns include pull-up registers and with power down mode wake-up function in input mode. the pull-up resistor and wake-up function are fixed. z p0.0~p0.3 are input only pin. z p0.4 is input only pin and shared with external reset pin controlled by code option. z p0.6, p0.7 are bit-direction i/o controlled by p0m register. z p1 is bit-direction i/o port controlled by p0m register. z irout is ir signal output pin as irout=1. when ir output disable and the system is in power down mode, irout outputs low status. (more detail information in ?ir output? section.) 6.1 i/o port mode the port direction is programmed by pnm register. a ll i/o ports can select input or output direction. 0b8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0m p07m p06m - - - - - - read/write r/w r/w - - - - - - after reset 0 0 - - - - - - 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m p17m p16m p15m p14m p13m p12m p12m p10m read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~1). 0 = pn is input mode. 1 = pn is output mode. ? note: users can program them by bit control instructions (bset, bclr). ? example: i/o mode selecting mov a, #0h ; set all ports to be input mode. mov p0m, a mov p1m, a mov a, #0ffh ; set all ports to be output mode. mov p0m, a mov p1m, a bclr p1m.2 ; set p1.2 to be input mode. bset p1m.2 ; set p1.2 to be output mode. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 40 version 0.5 6.2 i/o port data register 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 p07 p06 - p04 p03 p02 p01 p00 read/write r/w r/w - r r r r r after reset 0 0 - 0 0 0 0 0 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 p17 p16 p15 p14 p13 p12 p11 p10 read/write r r/w r r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 ? note: the p04 keeps ?1? when external reset enable by code option. ? note: when set p1.4 to input mode, please add the series external 100 ohm on it. ? example: read data from input port. mov a, p0 ; read data from port 0 mov a, p1 ; read data from port 1 ? example: write data to output port. mov a, #0ffh ; write data ffh to all port. mov p0, a mov p1, a ? example: write one bit data to output port. bset p1.3 ; set p1.3 and p5.5 to be ?1?. bclr p1.3 ; set p1.3 and p5.5 to be ?0?. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 41 version 0.5 7 7 7 timers 7.1 watchdog timer the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program goes into the unknown status by noise interferen ce, wdt overflow signal raises and resets mcu. watchdog clock controlled by code option and the clock source is internal low-speed oscillator (16khz @3v, 32khz @5v). watchdog overflow time = 8192 / inte rnal low-speed oscillator (sec). vdd internal low rc freq. watchdog overflow time 3v 16khz 512ms 5v 32khz 256ms ? note: if watchdog is ?always_on? mode, it keeps running event under power down mode or green mode. watchdog clear is controlled by wdtr register. moving 0x5a data into wdtr is to reset watchdog timer. 0cch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdtr wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 ? example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: mov a, #5ah ; clear the watchdog timer. mov wdtr, a ? ? call sub1 call sub2 ? ? jmp main ? example: clear watchdog timer by @rst_wdt macro. main: @rst_wdt ; clear the watchdog timer. ? ? call sub1 call sub2 ? ? jmp main SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 42 version 0.5 watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: ? ; check i/o. ? ; check ram err: jmp $ ; i/o or ram error. program jump here and don?t ; clear watchdog. wait watchdog timer overflow to reset ic. correct: ; i/o and ram are correct. clear watchdog timer and ; execute program. @rst_wdt ; only one clearing watchdog timer of whole program. ? call sub1 call sub2 ? ? ? jmp main SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 43 version 0.5 7.2 timer 0 (t0) 7.2.1 overview the t0 is an 8-bit binary up timer with out interrupt function. if t0 timer occurs an overflow (from ffh to 00h), it will continue counting and issue a time-out signal to trigger t0 interrupt request flag and set t0irq (t0irq=1). tracking t0irq status is to get right timer period by polling program. the main purposes of the t0 timer is as following. ) 8-bit programmable up counting timer: generates timer overflow request at specific time intervals based on the selected clock frequency. fcpu t0 rate (fcpu/2~fcpu/256) t0enb cpum0,1 t0c 8-bit binary up counting counter t0 time out load internal data bus 7.2.2 t0m mode register 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 - - - - read/write r/w r/w r/w r/w - - - - after reset 0 0 0 0 - - - - bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 44 version 0.5 7.2.3 t0c counting register t0c is an 8-bit counter register for t0 interval time control. 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) ? example: to set 10ms interval time for t0 interr upt. high clock is external 4mhz. fcpu=fosc/4. select t0rate=010 (fcpu/64). t0c initial value = 256 - (t0 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of t0. high speed mode (fcpu = 4mhz / 4) low speed mode (fcpu = 32768hz / 4) t0rate t0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 45 version 0.5 7.2.4 t0 timer operation sequence t0 timer operation sequence of setup t0 timer is as following. ) stop t0 timer counting, clear t0 interrupt request flag. bclr ft0enb ; t0 timer. bclr ft0irq ; t0 time out request flag is cleared. ) set t0 timer rate. mov a, #0xxx0000b ;the t0 rate control bi ts exist in bit4~bit6 of t0m. the ; value is from x000xxxxb~x111xxxxb. mov t0m,a ; t0 timer is disabled. ) set t0 interrupt interval time. mov a,#7fh mov t0c,a ; set t0c value. ) enable t0 timer. bset ft0enb ; enable t0 timer. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 46 version 0.5 8 8 8 ir output 8.1 overview ir signal is generated by tc0 timer. the ir output pin is irout pin. when irout bit of tc0m is logic ?1?, irout pin outputs ir signal. if irout = 0 or system is in power down mode, irput pin is tied to low status. the tc0 is an 8-bit binary up counting timer for ir signal generator. the ir signal is duty/cycle changeable ty pe controlled by tc0r and tc0d. tc0r decides ir cycle and tc0d decides ir duty. tc 0 clock source is only from fhosc (external high clock source), eg. 4mhz crystal. if external oscillator is 4mhz, the tc0 clock rate is 4mhz. tc0 only generate ir output and no interrupt function. when enable ir output function (irout=1 ), ir output status is high level. tc0c initial value is tc0r and starts to count. when tc0c=tc0d, ir output st atus change to low level and finishes high duty operation. when tc0c overflow occurs (tc0c changes from 0xff to 0x00), ir output low duty oper ation stops. system loads tc0r into tc0c automatically and next cycle starts. fhosc irout cpum0 tc0c 8-bit binary up counting counter tc0r reload data buffer up counting reload value compare r s output low irout pin ir signal irout load tc0d data buffer tc0c overflow SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 47 version 0.5 8.2 ir control register 8.2.1 tc0m mode register 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m - - - - - - - irout read/write - - - - - - - r/w after reset - - - - - - - 0 bit 0 irout: ir output control bit. 0 = disable ir output. irout pin is low status.. 1 = enable ir output. ir signal output to irout pin. ? note: when irout=0 or the system is in power down mode, irout pin keeps low status. 8.2.2 tc0c counting register tc0c is an 8-bit counter register for tc0 interval time control. 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 ? note: set tc0c=tc0r before ir output enable to make sure the first cycle correct. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 48 version 0.5 8.2.3 tc0r auto-load register tc0r decides ir signal frequency. tc0 timer is with auto-load function. when tc0c overflow occurs, tc0r value will load to tc0c. it is easy to generate an accurate time for ir signal cycle, and users don?t reset tc0c during interrupt service routine. tc0 is double buffer design. if new tc0r value is set by program, the new value is stored in 1 st buffer. until tc0 overflow occurs, the new value moves to real tc0r buffer. 0cdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc0rinitial value is as following. tc0r initial value = 256 - (tc0 interrupt interval time * input clock) ? note: the input clock is 4mhz of external 4mhz oscillator. ? example: set ir cycle frequency is 38khz. input clock is 4mhz. tc0r initial value = 256 - (tc0 interrupt interval time * input clock) tc0 interval time = 1/38khz = 26.3us input clock = external oscillator 4mhz. tc0r = 256 - (26.3us * 4mhz) = 150.8 151 = 97h SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 49 version 0.5 8.2.4 tc0d ir duty control register the ir signal is duty changeable by tc0d. tc0d decides th e ir output signal high pulse width length. when tc0c=tc0d, the ir signal changes from high pulse to low pulse. the low pulse stops when tc0c overflow. the high pulse width is tc0d-tc0r, and the low pulse width is 256- tc0d. it is easy to modulate ir duty/cycle by tc0r and tc0d registers. 0e8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0d tc0d7 tc0d6 tc0d5 tc0d4 tc0d3 tc0d2 tc0d1 tc0d0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc0dinitial value is as following. tc0d initial value = tc0r + (256-tc0r) / (1/ir duty) ? example: set tc0d for 38khz ir and duty is 1/3. input clock is 4mhz. tc0d initial value = tc0r + (256-tc0r) / (1/ir duty) tc0r of 38khz = 151 tc0d = 151 + (256-151)/(1/ (1/3)) = 186 = bah common ir signal table. system clock is 4mhz. tc0d tc0c tc0d 1/2 duty 1/3 duty 1/4duty ir freq. (khz) dec hex dec hex dec hex dec hex freq. error rate 32 131 83 193.50 c1 172.67 ac 162.25 a2 0.00% 36 145 91 200.50 c8 182.00 b6 172.75 ac 0.10% 38 151 97 203.50 cb 186.00 ba 177.25 b1 0.25% 39.2 154 9a 205.00 cd 188.00 bc 179.50 b3 0.04% 40 156 9c 206.00 ce 189.33 bd 181.00 b5 0.00% 56 185 b9 220.50 dc 208.67 d0 202.75 ca 0.60% SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 50 version 0.5 8.2.5 ir output o peration sequence ) set tc0c and tc0r for ir cycle. mov a, #ircycval ;tc0c, tc0r value for ir cycle. mov tc0c, a mov tc0r, a ) set tc0d for ir duty. mov a, #irdutyval ;tc0d value for ir duty. mov tc0d, a ) enable ir output. bset firout ; enable ir output from irout pin. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 51 version 0.5 8.3 ir remote controller application circuit d1 ir ki5 ... ko2 s51 ko1 ko4 ... s1 r2 330 ki6 c8 20pf s2 s56 ... ko8 s55 u u1 value = SN8PC13 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p1.6 p1.7 p0.7 p0.6 p5.4/irout vdd xout xin vss p0.4/rst/vpp p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.3 p0.2 p0.1 p0.0 ir output ki3 s7 ko3 c8 20pf ko7 ki4 dc power s50 bt1 3v oscillator y1 4mhz 7x8 (56) keys matrix q1 npn ko6 ki2 ... c2 0.1uf ki7 c1 47uf s6 ko5 ki1 r1 1k the application circuit is a typical ir remote controller circuit. z reset pin set as p0.4 input only pin for key matrix input pin. if the project needs external reset pin, the maximum key number is only 49 keys. z the keys are low active type and pulled by p0 internal 100k ohm pull-up resistors. z the system clock source is 4mhz crystal or ceramic. z ir transmitter is driven by a transis tor and there must be connected a resistor between irout pin and transistor?s b terminal. the resistor value must be greater than 330 ohm better, or the current through irout pin is over standard 15ma. z the ir power is supplied from battery power terminal and after c1 47uf capacitor to make sure power stable while ir transmitting. z the ir circuit is drive type. the irout pin initial value is low status. when stop ir transmitting or the system is in power down mode, the irout pin keeps low st atus and won?t be turn on to consume power. the ir only supports drive type. z the c2 is muc?s power bypass capacitor. the value is 0.1uf and it must be beside ic as closer as possible. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 52 version 0.5 9 9 9 instruction table field mnemonic description c z cycle move mov a,m a m - 1 mov m,a m a - - 1 mov a,i a i - - 1 movc r, a rom [y,z] - - 2 arithmetic adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 logic and a,m a a and m - 1 or a,m a a or m - 1 xor a,m a a xor m - 1 rrc m a rrc m -1 bclr m.b m.b 0 - - 1 bset m.b m.b 1 - - 1 branch cmprs a,i zf,c a - i, if a = i, then skip next instruction 1+s incms m m m + 1, if m = 0, then skip next instruction - - 1+s decms m m m - 1, if m = 0, then skip next instruction - - 1+s bts0 m.b if m.b = 0, then skip next instruction - - 1+s bts1 m.b if m.b = 1, then skip next instruction - - 1+s jmp d pc15/14 rompages1/0, pc13~pc0 d - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - 2 mis ret pc stack - - 2 nop no operation - - 1 note: 1. ?m? is system register or ram. 2. if branch condition is true then ?s = 1?, otherwise ?s = 0?. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 53 version 0.5 1 1 1 0 0 0 electrical characteristic 10.1 absolute maximum rating supply voltage (vdd)????????????????????????????????????????????.?????? - 0.3v ~ 6.0v input in voltage (vin)????????????????????????????????????????????.? vss ? 0.2v ~ vdd + 0.2v operating ambient temperature (topr), SN8PC13p, SN8PC13s, SN8PC13x ??????????????????..?????. 0 c ~ + 70 c storage ambient temperature (tstor) ?????????????????????????.???????????????? ?40 c ~ + 125 c 10.2 electrical characteristic (all of voltages refer to vss, vdd = 5.0v, fosc = 4mhz,fcpu=1mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit operating voltage vdd normal mode, vpp = vdd. lvd - 5.5 v ram data retention voltage vdr - 1.5* - v vdd rise rate vpor vdd rise rate to ensure internal power-on reset 0.05 - - v/ms vil1 all input ports vss - 0.3vdd v input low voltage vil2 reset pin vss - 0.2vdd v vih1 all input ports 0.7vdd - vdd v input high voltage vih2 reset pin 0.9vdd - vdd v reset pin leakage current ilekg vin = vdd - - 2 ua vin = vss , vdd = 3v 100 200 300 i/o port pull-up resistor rup vin = vss , vdd = 5v 50 100 150 k ? i/o port input leakage current ilekg pull-up resistor disable, vin = vdd - - 2 ua i/o output source current ioh vop = vdd ? 0.5v - 12* - sink current iol vop = vss + 0.5v - 15* - ma vdd= 5v, fcpu=4mhz/4 - 2.5 5 ma idd1 normal mode (no loading) vdd= 3v, fcpu=4mhz/4 - 1 2 ma vdd= 5v - 0.8 1.6 ua supply current idd2 sleep mode vdd= 3v - 0.7 1.4 ua lvd voltage vdet0 low voltage reset level. 0 o c~70 o c. 1.6 2.0 2.1 v *these parameters are for design reference, not tested. SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 54 version 0.5 1 1 1 1 1 1 development tool SN8PC13 development tools are as following. z ice version: sn8ice2k. z ide version: m2ide_v107 later. z writer: ez-writer, mp-writer. use ?SN8PC13 mpxxxx? transition board. z SN8PC13 ev-kit. SN8PC13 ide files haven?t included into m2ide. pleas e set these files into ide paths as following. z move ? SN8PC13.bit ? into ? c:\sonix\m2ide_vxxx\bit_file ?. z move ? SN8PC13.bol ? into ? c:\sonix\m2ide_vxxx\symbol ?. z move ? SN8PC13.inc ? into ? c:\sonix\m2ide_vxxx\use_inc2 ?. z move ? SN8PC13.prg ? into ? c:\sonix\m2ide_vxxx\use_prg ?. include these file into ide path, the m2ide can simulate and program SN8PC13. for ir remote controller development, sonix provides a ?SN8PC13 ev-kit? and supports m2ide_v107 and later ide. the ev-kit includes 56keys and ir output circuit. the ev-kit circuit is as following. p1.7 vss p1.5 p0.0 p1.0 p1.6 c4 20pf p1.5 p1.0 p0.1 s37 p0.1 s46 p1.0 p1.3 p1.2 p1.4 p1.7 p1.3 c1 47uf s30 p5.4 p0.3 p0.4 p0.1 p1.2 p1.7 p1.7 vcc p0.7 vss p1.6 p0.1 p0.7 p0.4 p1.4 p0.4 p1.6 vdd p0.7 r2 330 s42 p1.3 p1.6 p0.2 s41 p1.6 p1.2 p1.4 p0.0 p1.4 p1.2 p0.0 s38 p1.3 s26 s28 s36 vss s9 s27 vcc p1.5 p0.2 p1.7 p0.1 p1.0 vdd p0.3 p0.6 p1.2 p0.1 p1.1 p1.4 jp1 2 header 12 s39 p1.0 p0.6 vdd s10 p0.7 s55 p1.6 s14 p0.4 p0.3 p0.6 s53 p1.0 p1.3 p1.7 p1.2 p0.4 s54 p1.3 p1.1 p0.4 p1.7 s56 p1.5 p1.4 p1.0 p1.2 p0.0 p0.0 p1.2 p1.2 s22 p0.6 s15 p0.3 p1.1 p1.1 p1.1 p1.1 d1 ir s52 p1.1 s24 p1.3 y1 4mhz p1.0 p1.4 p1.3 s25 s13 s51 s34 p0.2 p0.7 s3 p1.5 p1.4 p0.0 s21 s43 s32 p1.5 p1.0 s2 vss2 p1.4 p1.7 p0.1 p1.0 u u1 value = SN8PC13 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p1.6 p1.7 p0.7 p0.6 irout vdd xout xin vss p0.4/rst/vpp p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.3 p0.2 p0.1 p0.0 p5.4 p0.2 c3 0.1uf p1.7 p1.5 c6 0.1uf p0.7 p0.2 p0.1 jp5 header 10x2 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 p0.3 p0.6 p0.7 p1.1 p1.1 p0.4 p0.4 p1.2 p1.5 p0.7 s19 jp2 header 16x2 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p0.0 p1.3 s23 s6 p1.5 p1.4 p0.0 vdd1 vss p0.1 s29 s18 p1.6 p0.0 p0.3 p0.2 s4 s17 p0.3 p1.1 s16 p1.6 p0.6 s33 p0.2 p1.0 s35 s40 p0.6 p0.7 p0.6 p0.2 p1.6 vdd2 p0.3 s48 vss s50 p1.1 p1.1 s5 p1.2 vdd p0.7 p0.7 s49 p0.7 p1.7 p0.3 vdd s57 reset s31 p1.3 q1 npn p1.6 p0.4 vss1 jp4 vss 1 2 3 p0.2 p0.1 p0.4 p0.3 p1.7 s12 s20 p0.6 irout jp3 vdd 1 2 3 p0.2 p0.0 p0.4 s1 s47 p0.3 p0.4 p0.1 p0.0 p1.6 vdd p0.6 s44 p0.2 p1.5 p0.6 s8 con1 header 30x2 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p1.3 p1.5 p0.6 p0.3 p1.4 c2 0.1uf p0.4 vcc vss p0.0 s45 r1 1k r3 47k p0.1 p5.4 c5 20pf p0.2 p0.0 s7 p0.1 p1.0 s11 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 55 version 0.5 1 1 1 2 2 2 otp programming pin 12.1 the pin assignment of easy writer transition board socket: easy writer jp1/jp2 easy writer jp3 (mapping to 48-pin text tool) vss 2 1 vdd dip1 1 48 dip48 ce 4 3 clk/pgclk dip2 2 47 dip47 oe/shiftdat 6 5 pgm/otpclk dip3 3 46 dip46 d0 8 7 d1 dip4 4 45 dip45 d2 10 9 d3 dip5 5 44 dip44 d4 12 11 d5 dip6 6 43 dip43 d6 14 13 d7 dip7 7 42 dip42 vpp 16 15 vdd dip8 8 41 dip41 rst 18 17 hls dip9 9 40 dip40 alsb/pdb 20 19 - dip10 10 39 dip39 dip11 11 38 dip38 jp1 for mp transition board dip12 12 37 dip38 dip13 13 36 dip36 dip14 14 35 dip35 dip15 15 34 dip34 dip16 16 33 dip33 dip17 17 32 dip32 dip18 18 31 dip31 dip19 19 30 dip30 dip20 20 29 dip29 dip21 21 28 dip28 dip22 22 27 dip27 dip23 23 26 dip26 dip24 24 25 dip25 jp3 for mp transition board SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 56 version 0.5 12.2 programming pin mapping: programming information of SN8PC13 chip name SN8PC13p/s/x ez writer / mp writer connector otp ic / jp3 pin assigment number name number pin 1 vdd 6 vdd 2 gnd 9 vss 3 clk 11 p0.0 4 ce - - 5 pgm 15 p1.0 6 oe 12 p0.1 7 d1 - - 8 d0 - - 9 d3 - - 10 d2 - - 11 d5 - - 12 d4 - - 13 d7 - - 14 d6 - - 15 vdd - - 16 vpp 10 rst 17 hls - - 18 rst - - 19 - - - 20 alsb/pdb 16 p1.1 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 57 version 0.5 1 1 1 3 3 3 package information 13.1 p-dip 20 pin min nor max min nor max symbols (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - - 0.381 - - a2 0.125 0.130 0.135 3.175 3.302 3.429 d 0.980 1.030 1.060 24.892 26.162 26.924 e 0.300 7.620 e1 0.245 0.250 0.255 6.223 6.350 6.477 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.335 0.355 0.375 8.509 9.017 9.525 0 7 15 0 7 15 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 58 version 0.5 13.2 sop 20 pin min nor max min nor max symbols (inch) (mm) a 0.093 0.099 0.104 2.362 2.502 2.642 a1 0.004 0.008 0.012 0.102 0.203 0.305 d 0.496 0.502 0.508 12.598 12.751 12.903 e 0.291 0.295 0.299 7.391 7.493 7.595 h 0.394 0.407 0.419 10.008 10.325 10.643 l 0.016 0.033 0.050 0.406 0.838 1.270 0 4 8 0 4 8 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 59 version 0.5 13.3 ssop 20 pin min nor max min nor max symbols (inch) (mm) a 0.053 0.063 0.069 1.350 1.600 1.750 a1 0.004 0.006 0.010 0.100 0.150 0.250 a2 - - 0.059 - - 1.500 b 0.008 0.010 0.012 0.200 0.254 0.300 c 0.007 0.008 0.010 0.180 0.203 0.250 d 0.337 0.341 0.344 8.560 8.660 8.740 e 0.228 0.236 0.244 5.800 6.000 6.200 e1 0.150 0.154 0.157 3.800 3.900 4.000 [e] 0.025 0.635 h 0.010 0.017 0.020 0.250 0.420 0.500 l 0.016 0.025 0.050 0.400 0.635 1.270 l1 0.039 0.041 0.043 1.000 1.050 1.100 zd 0.059 1.500 y - - 0.004 - - 0.100 0 - 8 0 - 8 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 60 version 0.5 1 1 1 4 4 4 marking definition 14.1 introduction there are many different types in sonix 8-bit mcu production line. this note listed the produ ction definition of all 8-bit mcu for order or obtain information. this definition is only for blank otp mcu. 14.2 marking indetification system sn8 x part no. x x x title sonix 8-bit mcu production rom type p=otp material b = pb-free package g = green package temperature range - = 0 ~ 70 shipping package w = wafer h = dice p = p-dip s = sop x = ssop device c13 SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 61 version 0.5 14.3 marking example name rom type device package temperature material SN8PC13pg otp c13 p-dip 0 ~70 green package SN8PC13sb otp c13 sop 0 ~70 pb-free package 14.4 datecode system there are total 8~9 letters of sonix datecode system. the final four or five char. are for sonix inside use only, and the first 4 indicate the package date including year/month/date. the detail information is following: x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . . SN8PC13 remote controller 8-bit micro-controller sonix technology co., ltd page 62 version 0.5 sonix reserves the right to make change without further notic e to any products herein to im prove reliability, function or design. sonix does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey any license under its patent rights no r the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cos t, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 9f, no. 8, hsien cheng 5th s t, chupei city, hsinchu, taiwan r.o.c. tel: 886-3-551 0520 fax: 886-3-551 0523 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 gr anville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw |
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