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1 integrated digital light sensor isl29034 the isl29034 is an integrated ambient and infrared light-to-digital converter with i 2 c (smbus compatible) interface. its advanced self-calibrated photodiode array emulates human eye response with excellent ir rejection. the on-chip adc is capable of rejecting 50hz and 60hz flicker caused by artificial light sources. the lux range select feature allows users to program the lux range for optimized counts/lux. for ambient light sensing, an internal 16-bit adc has been designed based upon the charge-balancing technique. the adc conversion time is nominally 105ms and is user selectable from 11s to 105ms, depending on oscillator frequency and adc resolution. in normal operation, typical current consumption is 57a. in order to further minimize power consumption, two power-down modes have been provided. if polling is chosen over continuous measurement of light, the auto-power-down function shuts down the whole chip after each adc conversion for the measurement. the other power-down mode is controlled by software via the i 2 c interface. the power consumption can be reduced to less than 0.3a when powered down. the isl29034 supports a soft ware brownout condition detection. the device powers up with the brownout bit asserted until the host clears it through the i 2 c interface. designed to operate on supplies from 2.25v to 3.63v with an i 2 c supply from 1.7v to 3.63v, the isl29034 is specified for operation over the -40c to +85c ambient temperature range. features ? resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-bits adc ? wide dynamic range1: . . . . . . . . . . . . . . . . . . . . . . . . . 4,200,000 ? integrated noise reduction . . . . . . . . . . . . . . . . . . . . . 50/60hz ? close to human eye response with excellent ir/uv rejection ? shutdown modes. . . . . . . . . . . . . . . . . . . software and automatic ? supply current (typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57a ? shutdown current (max) . . . . . . . . . . . . . . . . . . . . . . . . 0.51a ?i 2 c (smb compatible) power supply . . . . . . . . . 1.7v to 3.63v ? sensor power supply . . . . . . . . . . . . . . . . . . . . . 2.25v to 3.63v ? operating temperature range. . . . . . . . . . . . . -40c to +85c ? small form factor package . . . . . . . 4 ld 1.5x1.3x0.75 odfn applications ? mobile devices: smart phone, pda, gps ? computing devices: notebook pc, macbook, tablets ? consumer devices: lcd-tv, digital picture frame, digital camera ? industrial and medical light sensing related literature ? an1591 , ?evaluation hardware/software manual for als and proximity sensor? figure 1. isl29034 typical application diagram figure 2. normalized spectr al response for ambient light sensing isl29034 mcu 1f scl sda 1 2 3 vdd scl sda v dd 4 gnd vdd_pullup 4.7k 4.7k 100 0 0.2 0.4 0.6 0.8 1.0 1.2 300 400 500 600 700 800 900 1000 1100 normalized response wavelength (nm) human eye (photopic) ambient light sensor april 9, 2014 fn8370.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013, 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl29034 2 fn8370.1 april 9, 2014 submit document feedback block diagram pin configuration isl29034 (4 ld odfn) top view scl sda 4 3 r 500k integrating adc cmd register data register iref f osc command register light data process 2 gnd 1 v dd i 2 c/smb photodiode array isl29034 1 2 4 3 vdd gnd sda scl pin descriptions pin number pin name description 1 vdd positive supply 2gndground pin 3scli 2 c serial clock. 4sdai 2 c serial data. ordering information part number (notes 2, 3) temp range (c) package tape & reel (rohs compliant) pkg. dwg. # ISL29034IROZ-T7 (note 1) -40 to +85 4 ld odfn l4.1.5x1.3 isl29034iroz-evalz evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free sold ering operations. intersil pb-fr ee products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl29034 . for more information on msl please see tech brief tb477 .
isl29034 3 fn8370.1 april 9, 2014 submit document feedback absolute maximum rating s thermal information vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0v i 2 c bus (scl, sda) pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 4.0v i 2 c bus (scl, sda) pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10ma input voltage slew rate (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1v/s esd ratings human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kv thermal resistance (typical) ja (c/w) 4 ld odfn package (note 4) 287 maximum junction temperature (tj max ). . . . . . . . . . . . . . . . . . . . . . . +90c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. electrical specifications v dd = 3.0v, t a = +25c, 16-bit adc operation, unless otherwise specified. parameter description test conditions min (note 7) typ max (note 7) units v dd power supply range 2.25 3.63 v i dd supply current 57 85 a i dd1 supply current when powered down software disabled or auto power-down 0.24 0.51 a v i 2 c supply voltage range for i 2 c interface 1.7 3.63 v t int adc integration/conversion time 16-bit adc data 105 ms f i 2 c i 2 c clock rate range 400 khz data_0 count output when dark e = 0 lux, range 0 (1k lux) 1 5 counts data_f full scale adc code 65535 counts %/value part-to-part variation (3 population) e = 300 lux, cold white led range 0 (1k lux) 5 % adc r0 light count output with lsb of 0.015 lux/c ount e = 300 lux, fluorescent light (note 5), als range 0 (1k lux) 15000 20473 25000 counts adc r1 light count output with lsb of 0.06 lux/cou nt e = 300 lux, fluorescent light (note 5), als range 1 (4k lux) 5100 counts adc r2 light count output with lsb of 0.24 lux/co unt e = 300 lux, fluorescent light (note 5), als range 2 (16k lux) 1400 counts adc r3 light count output with lsb of 0.96 lux/cou nt e = 300 lux, fluorescent light (note 5), als range 3 (64k lux) 366 counts adc_ir r0 infrared count output range 0 (1k lux) 1402 1997 2598 adc_ir r1 infrared count output range 1 (4k lux) 481 adc_ir r2 infrared count output range 2 (16k lux) 148 adc_ir r3 infrared count output range 3 (64k lux) 42 i sda sda current sinking capability 4 5 ma notes: 5. 550nm green led is used in production test . the 550nm led irradiance is calibrated to produce the same data count against an illuminance level of 300 lux fluorescent light. 6. 850nm ir led is used in production test. 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
isl29034 4 fn8370.1 april 9, 2014 submit document feedback f i 2 c interface specifications v dd = 3.0v, t a = +25c, 16-bit adc operation, unless otherwise specified. symbol parameter test conditions min (note 7) typ max (note 7) units v il sda and scl input buffer low voltage 0.55 v v ih sda and scl input buffer high voltage 1.25 v v hys (note 8) sda and scl input buffer hysteresis 0.05 x v dd v v ol (note 8) sda output buffer low voltage (open-drain), sinking 4ma 00.4v c pin (note 8) sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid 900 ns t buf time the bus must be free before the start of a new transmission 1300 ns t low clock low time 1300 ns t high clock high time 600 ns t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:dat input data setup time 100 ns t hd:dat input data hold time 30 ns t su:sto stop condition setup time 600 ns t hd:sto stop condition hold time 600 ns t dh output data hold time 0ns t r (note 8) sda and scl rise time 20 + 0.1 x cb ns t f (note 8) sda and scl fall time 20 + 0.1 x cb ns c b (note 10) capacitive loading of sda or scl total on-chip and off-chip 400 pf r pu (note 8) sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2k ? ~ 2.5k ? for cb = 40pf, max is about 15k ? ~ 20k ? 1k ? notes: 8. limits should be considered typical and are not production tested. 9. these are i 2 c specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specificatio n. 10. c b is the capacitance of the bus in pf.
isl29034 5 fn8370.1 april 9, 2014 submit document feedback sda vs scl timing figure 3. i 2 c bus timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:sto figure 4. i 2 c write cycle timing scl sda 8 th bit of last byte stop condition start condition t wc ack
isl29034 6 fn8370.1 april 9, 2014 submit document feedback typical performance curves figure 5. normalized spectral response for ambient light sensing and ir sensing figure 6. normalized radiation pattern figure 7. temperature test in dark condition figure 8. als transfer func tion under f2 light source 0 0.2 0.4 0.6 0.8 1.0 1.2 300 400 500 600 700 800 900 1000 1100 wavelength (nm) human eye ambient light sensor normalized response 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -90 -75 -60 -45 -30 -15 0 15 30 45 60 75 90 normalized sensitivity angular offset () 0 2 4 6 8 10 12 14 -60-50-40-30-20-10 0 102030405060708090100 als reading (counts) temperature (c) 1000 lux range 0 200 400 600 800 1000 0 200 400 600 800 1000 als measured lux (lux) t-10 lux meter (lux) 1000 lux range
isl29034 7 fn8370.1 april 9, 2014 submit document feedback principles of operation photodiodes and adc the isl29034 contains two photodio de arrays, which convert light into current. a typical spectral re sponse for ambient light sensing is shown in figure 5 on page 6. after light is converted to current during the light signal process, th e current output is converted to digital by a built-in 16-bit analog-to-digital converter (adc). an i 2 c command reads the ambient light intensity in counts. the converter is a charge-balancing integrating type 16-bit adc. the chosen method for conversion is best for converting small current signals in the presence of an ac periodic noise. a 105ms integration time, for instance, highly reject s 50hz and 60hz power line noise simultaneously. the integration time of the built-in adc is determined by the internal oscillator, and the n-bit (n = 4, 8, 12, 16) counter inside the adc. a good balancing act of integration ti me and resolution (depending on the application) is required for optimal results. the adc has i 2 c programmable range select to dynamically accommodate various lighting conditions. for very dim conditions, the adc can be configured at its lowest range (range 0) in the ambient light sensing. low-power operation the isl29034 initial operation is at the power-down mode after a supply voltage is provided. the data registers contain the default value at 0. when the isl29034 receives an i 2 c command to do a one-time measurement from an i 2 c master, it will start the adc conversion with light sensing. it will go to the power-down mode automatically after one conversion is finished and keep the conversion data available for the master to fetch anytime afterwards. the isl29034 will co ntinuously do adc conversion with light sensing if it receives an i 2 c command of continuous measurement. it will continuously update the data registers with the latest conversion data. it will go to the power-down mode after it receives the i 2 c command of power-down. ambient light and ir sensing there are four operational modes in isl29034: programmable als once with auto power-down, programmable ir sensing once with auto power-down, programm able continuous als sensing and programmable continuous ir sensing. these four modes can be programmed in series to fulfill the application needs. the detailed program configuration is listed in ?command-i register (address: 0x00)? on page 10. when the part is programmed for ambient light sensing, the ambient light with wavelength within the ?ambient light sensing? spectral response curve in figure 14 is converted into current. with adc, the current is converted to an unsigned n-bit (up to 16 bits) digital output. when the part is programmed for infrared (ir) sensing, the ir light with wavelength within the ?ir sensing? spectral response curve in figure 14 is converted into current. with adc, the current is converted to an unsigned n-bit (up to 16-bits) digital output. serial interface the isl29034 supports the inter-integrated circuit (i 2 c) bus data transmission protocol. the i 2 c bus is a two-wire serial bidirectional interface consisting of scl (clock) and sda (data). both the wires are connected to the device suppl y via pull-up resistors. the i 2 c protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the transmitting device pulls down the sda line to transmit a ?0? and releases it to transmit a ?1?. the master always initiates the data transfer, only when the bus is not busy, and provides the clock for both transmit and receive operations. the isl29034 operates as a slave device in all applications. the serial communication over the i 2 c interface is conducted by sending the most significant bit (msb) of each byte of data first. start condition during data transfer, the sda line must remain stable while the scl line is high. all i 2 c interface operations must begin with a start condition, which is a high-to-low transition of sda while scl is high (refer to figure 11). the isl 29034 continuously monitors the sda and scl lines for the start co ndition and does not respond to any command until this condition is met (refer to figure 11). a start condition is ignored during the power-up sequence. stop condition all i 2 c interface operations must be terminated by a stop condition, which is a low-to-high transition of sda while scl is high (refer to figure 11). a stop condition at the end of a read/write operation places the de vice in its standby mode. if a stop is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the serial communication of the isl29034 resets itself without performing the read/write. the contents of the array are not affected. acknowledge an acknowledge (ack) is a software convention used to indicate a successful data transfer. the tr ansmitting device releases the sda bus after transmitting 8-bits . during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (refer to figure 11). the isl29034 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again, after successful receipt of an address byte. the isl29034 also responds with an ack after rece iving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. device addressing following a start condition, the master must output a device address byte. the 7 msbs of the device address byte are known as the device identifier. the device id entifier bits of the isl29034 are internally hard-wired as ?1000100?. the lsb of the device address byte is defined as a read or write (r/w ) bit. when this r/w bit is a ?1?, a read operation is selected and when ?0?, a write operation is selected (refer to figure 9). the master generates a start condition followed by device address byte 1000100x (x as r/w ) and the isl29034 compares it with the internal device identifier. upon a correct comparison, the device outputs an acknowledge
isl29034 8 fn8370.1 april 9, 2014 submit document feedback (low) on the sda line (refer to figure 11). write operation byte write in a byte write operation, the isl29034 requires the device address byte, register address byte, and the data byte. the master starts the communication with a start condition. upon receipt of the device address by te, register address byte, and the data byte, the isl29034 responds with an acknowledge (ack). following the isl29034 da ta acknowledge response, the master terminates the transfer by generating a stop condition. the isl29034 then begins an internal write cycle of the data to the volatile memory. during the in ternal write cycle, the device inputs are disabled and the sda line is in a high impedance state, so the device will not respond to any requests from the master (refer to figure 10). burst write the isl29034 has a burst write operation, which allows the master to write multiple consecutive bytes from a specific address location. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data byte is transferred, the master can write to the whole register array. after the re ceipt of each byte, the isl29034 responds with an acknowledge, and the address is internally incremented by one. the addre ss pointer remains at the last address byte written. when the counter reaches the end of the register address list, it ?rolls over? and goes back to the first register address. figure 9. device address, regi ster address, and data byte device address byte register address byte data byte 1 0 0 0 1 0 0 r/w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 figure 10. byte write sequence figure 11. start, data stable, acknowledge, and stop condition 10001000 a c k a c k a c k s t o p s t a r t device address byte address byte data byte signal from master device signal at sda signals from slave device sda from receiver sda from transmitter scl from master start data change data stable data stable ack stop 8 th clk 9 th clk high impedance
isl29034 9 fn8370.1 april 9, 2014 submit document feedback read operation the isl29034 has two basic read operations: byte read and burst read. byte read byte read operations allow the master to access any register location in the isl29034. the byte read operation is a two step process. the master issues the start condition, and the device address byte with the r/w bit set to ?0?, receives an acknowledge, then issues the register address byte. after acknowledging receipt of the register address byte, the master immediately issues another start condition and the device address byte with the r/w bit set to ?1?. this is followed by an acknowledge from the device and then by the 8-bit data word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition (refer to figure 12). burst read burst read operation is identical to the byte read operation. after the first data byte is transmitted, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read op eration by not responding with an acknowledge but issuing a stop condition (refer to figure 13). for more information about the i 2 c standard, please consult the phillips ? i 2 c specification documents. power-on reset the power-on reset (por) circuitr y protects the internal logic against powering up in the in correct state. the isl29034 will power-up into standby mode after v dd exceeds the por trigger level and will power-down into reset mode when v dd drops below the por trigger level. this bidirectional por feature protects the device against ?brown-out? failure following a temporary loss of power. the por is an important feature because it prevents the isl29034 from starting to operate with insufficient voltage, prior to stabilization of the internal bandgap. the isl29034 prevents communication to its registers an d greatly reduces the likelihood of data corruption on power-up. 10001000 a c k a c k s t a r t device address write address byte signal from master device signal at sda signals from slave device a c k s t o p device address read data byte s t a r t 10001001 figure 12. byte address read sequence figure 13. burst read sequence 10001000 a c k a c k s t a r t device address write address byte signal from master device signal at sda signals from slave device a c k s t o p device address read data byte 1 s t a r t 10001001 a c k data byte 2 a c k data byte n (?n? is any integer greater than 1)
isl29034 10 fn8370.1 april 9, 2014 submit document feedback register description following are detailed descriptions of the control registers related to the operation of the isl29034 ambi ent light sensor device. these registers are accessed by the i 2 c serial interface. for details on the i 2 c interface, refer to ?serial interface? on page 7. all the features of the device are controlled by the registers. the adc data can also be read. the followin g sections explain the details of each register bit. all reserved bits are intersil used bits only. the value of the reserved bit can change without notice. decimal to hexadecimal conversion to convert decimal value to hexadecimal value, divide the decimal number by 16, and write the remainder on the side as the least significant digit. this process is co ntinued by dividing the quotient by 16 and writing the remainder un til the quotient is 0. when performing the division, the remainders, which will represent the hexadecimal equivalent of the decimal number, are written beginning with the least significant digit (right) and each new digit is written to the next most significan t digit (the left) of the previous digit. consider the number 175 decimal. command-i register (address: 0x00) the command-i register consists three operation mode bits. the default register value is 0x00 at power-on. command-i register (address: 0x0 operation mode bits[7:5]) the isl29034 has different oper ating modes. th ese modes are selected by setting b7 to b5 bits on register address 0x00. the device powers up on a disable mode. table 4 lists the possible operating modes. command-ii register (address: 0x01 ) the command-ii register consists of adc control bits. in this register, there are two range bits and two adac resolution bits. the default register valu e is 0x00 at power-on. full scale lux range [b1:b0] the full scale lux range has four different selectable ranges. the range determines the full scale lux range (1k, 4k, 16k, and 64k). each range has a maximum allowable lux value. table 6 lists the possible values of fsr. table 1. register map name register address register bits default access dec hex b7 b6 b5 b4 b3 b2 b1 b0 command-i 0 0x00 op2 op1 op0 reserved 0x00 rw command-ii 1 0x01 reserved res1 res0 range1 range0 0x00 rw data lsb 20x02 d7 d6 d5 d4 d3 d2 d1 d0 0x00 ro data msb 3 0x03 d15 d14 d13 d12 d11 d10 d9 d8 0x00 ro id 15 0x0f bout reserved 1 0 1 reserved 1x101xxx rw table 2. decimal to hexadecimal division quotient reminder hex number 175/16 10 = a 15 = f 0xaf table 3. command-i register address name addr (hex) register bits dflt (hex) b7 b6 b5 b4 b3 b2 b1 b0 command-i 0x00 op2 op1 op0 reserved 0x00 table 4. operating modes bits b7 b6 b5 operation 0 0 0 power-down the device (default) 0 0 1 the device measures als only once every integration cycle. this is the lowest operating mode. (note 11) 010ir once 0 1 1 reserved (do not use) 1 0 0 reserved (do not use) 1 0 1 measures als continuously 1 1 0 measures ir continuous 1 1 1 reserved (do not use) note: 11. intersil does not recommend using this mode table 5. command-ii register bits name reg. addr (hex) register bits dflt (hex) b7 b6 b5 b4 b3 b2 b1 b0 command-ii 0x01 reserved res1 res0 range1 range0 0x00 table 6. range register bits range selection b1 b0 full scale lux range (lux) 0 0 0 1,000 1 0 1 4,000 2 1 0 16,000 3 1 1 64,000
isl29034 11 fn8370.1 april 9, 2014 submit document feedback integration time adc resolution [b3:b2] b2 and b3 determine the adc?s resolution and the number of clock cycles per conversion. changing the number of clock cycles does more than just change the resolution of the device; it also changes the integration time, which is the period the device?s analog-to-digital (a/d) converter samples the photodiode current signal for a measurement. table 7 lists the possible adc resolution. only 16bit adc resolu tion can reject better 50/60hz noise flickering light source. . integration time data registers (addresses: 0x02 & 0x03) the isl29034 has two 8-bit read-onl y registers to hold the upper and lower byte of the adc value. the upper byte is accessed at address 0x03 and the lower byte is accessed at address 0x02. for 16-bit resolution, the data is from d0 to d15; for 12-bit resolution, the data is from d0 to d11; for 8-bit resolution, the data is from d0 to d7 and for 4-bit resolution, the data is from d0 to d3. the registers are refreshed after every conversion cycle. the default register value is 0x00 at power-on. id register (address: 0x0f) the id register has three different types of information. reserved bits [b2:b0] and [b6] all reserved bits on the isl29034 are intersil used bits only. bit0 to bit2 and bit6 are reserved bits where their value might change without any notification to the user. it is advised when using the identification bits to identify the device in a system the software should mask the bit0 to bi t2 and bit6 to bit7 to properly identify the device. device id bits [b5:b3] the isl29034 provides 3-bits to id entify the device in a system. these bits are located on register address 0x0f, bit3 to bit5. the identification bit value for the isl29034 is xx101xxx. the device identification bits are read only bi ts. it is important to notice that bit7 is a status bit for brownout condition (bout). brownout status bit to bout [b7] bit7 on register address 0x0f is a status bit for brownout condition (bout). the default value of this bit is ?bout = 1? during the initial power-up, which indicates the device may possibly have gone through a brownout condition. therefore, the status bit should be reset to ?bout = 0? by an i 2 c write command during the initial configuration of the device. the default register value is 0xa8 at power-on. applications information figure 14 is a normalized spectral response of various type of light sources for reference. table 7. adc resolution data width b3 b2 number of clock cycles n-bit adc 002 16 = 65,536 16 012 12 = 4,096 12 102 8 = 256 8 112 4 = 16 4 table 8. integration time of n-bit adc n # adc bits integration time (ms) 4 0.022 8 0.352 12 5.6 16 105 table 9. adc register bits name reg. addr (hex) register bits dflt (hex) b7 b6 b5 b4 b3 b2 b1 b0 data lsb 0x02 d7 d6 d5 d4 d3 d2 d1 d0 0x00 data msb 0x03 d15 d14 d13 d12 d11 d10 d9 d8 0x00 table 10. adc data registers address (hex) contents 0x02 d0 is lsb for 4-, 8-, 12- or 16-bit resolution; d3 is msb for 4-bit resolution; d7 is msb for 8-bit resolution 0x03 d15 is msb for 16-bit resolution; d11 is msb for 12-bit resolution table 11. id register bits name addr (hex) register bits dflt b7 b6 b5 b4 b3 b2 b1 b0 id 0x0f bout reserved 1 0 1 reserved 1x101xxx figure 14. normalized spectral response of light sources 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 350 550 750 950 wavelength (nm) normalized intensity fluorescent sun incand. halogen
isl29034 12 fn8370.1 april 9, 2014 submit document feedback calculating lux the isl29034?s adc output codes, data, are directly proportional to lux in the ambient light sensing. where, e cal is the calculated lux reading. the constant is determined by the full scale range and the adc?s maximum output counts. the constant is independent of the light sources (fluorescent, incandescent an d sunlight) because the light sources ir component is removed du ring the light signal process. the constant can also be viewed as the sensitivity (the smallest lux measurement the device can measure). where, range is defined in table 6 on page 10. count max is the maximum output counts from the adc. the transfer function used for n-bits adc becomes: where, n = 4, 8, 12 or 16. this is the number of adc bits programmed in the command register. 2 n represents the maximum number of counts possible from the adc output. data is the adc output stored in the da ta registers (02 hex and 03 hex). enhancing ev accuracy the device has on chip passive op tical filter designed to block (reject) most of the incident infra red. however, ev measurement may be vary under differing ir-content light sources. in order to optimi ze the measurement variation between differing ir-content light sources, isl29034 provides ir channel which is programmed at command-1 (reg0x0) to measure ir level of differing ir-content light sources. the isl29034?s adc output codes, data, are directly proportional to the ir intensity received in the ir sensing. then ev accuracy can be found in equation 5: here, data ev is the received ambient light intensity adc output codes. k is a resolution of visible portion. its unit is lux/count. the typical values of k is 0.82. data ir is the received ir intensity. the constant changes with the spectrum of background ir, such as a, f2 and d65 (notes 8, 9 and 10). the also changes with the adc?s range and resolution selections. a typical for range1 and range2 is -11292.86 and range3 and range4 is 2137.14 without ir tinted glass. noise rejection electrical ac power worldwide is distributed at either 50hz or 60hz. artificial light sources vary in intensity at the ac power frequencies. the undesired interference frequencies are infused on the electrical signals. this variation is one of the main sources of noise for the light sensors. integrating type adc?s have excellent noise-rejection characteristics for periodic noise sources whose frequency is an integer multiple of the conversion rate. by setting the sensor?s integration time to an integer multiple of periodic noise signal, the performance of an ambient light sensor can be improved greatl y in the presence of noise. in order to reject the ac noise, the integration time of the sensor must to adjusted to match the ac noise cycle. for instance, a 60hz ac unwanted signal?s sum from 0ms to k*16.66ms (k = 1,2...k i ) is zero. similarly, setting the device?s integration time to be an integer multiple of the periodic noise signal greatly improves the light sensor output signal in the presence of noise. suggested pcb footprint it is important that users check the ?surface mount assembly guidelines for optical dual flat pack no lead (odfn) package? before starting odfn product board mounting: tb477 board mounting considerations for applications requiring the light measurement, the board mounting location should be reviewed. the device uses an optical dual flat pack no lead (odfn) package, which subjects the die to mild stresses when th e printed circuit (pc) board is heated and cooled, which slightly changes the shape. because of these die stresses, placing the devi ce in areas subject to slight twisting can cause degradation of reference voltage accuracy. it is normally best to place the devi ce near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. layout considerations the isl29034 is relatively insens itive to layout. like other i 2 c devices, it is intended to provide excellent performance even in significantly noisy environments. there are only a few considerations that will ensure best performance. route the supply and i 2 c traces as far as possible from all sources of noise. use two power- supply decoupling capacitors, 1f and 0.1f, placed close to the device. soldering considerations convection heating is recommended for reflow soldering; direct-infrared heating is not recommended. the plastic odfn package does not require a custom reflow soldering profile, and is qualified to +260c. a standard reflow soldering profile with a +260c maximum is recommended. e cal data = (eq. 1) range count max ---------------------------- = (eq. 2) (eq. 3) e cal range 2 n ------------------- data = data ir e ir = (eq. 4) ev accuracy kxdata ev data ir + = (eq. 5)
isl29034 13 fn8370.1 april 9, 2014 submit document feedback temperature coefficient the limits stated for temperature coefficient (tc) are governed by the method of measurement. the ?box? method is usually used for specifying the temperature coefficient. the overwhelming standard for specifying the temperature drift of a reference is to evaluate the maximum voltage change over the specified temperature range. this yields ppm/c, and is calculated using and is calculated using equation 4: where: v high is the maximum reference voltage over the temperature range. v low is the minimum reference voltage over the temperature range. v nominal is the nominal reference voltage at +25c. t high - t low is the specified temperature range (c) digital inputs and termination the isl29034 digital inputs are guaranteed to cmos levels. the internal register is updated on the rising edge of the clock. to minimize reflections, proper termination should be implemented. if the lines driving the clock and the digital inputs are 50 ? lines, then 50 ? termination resistor s should be placed as close to the sensor inputs as possible, connected to the digital ground plane (if separate grounds are used). typical circuit a typical application for the isl29034 is shown in figure 15. the isl29034?s i 2 c address is internally hard-wired as 1000100. the device can be tied onto a system?s i 2 c bus together with other i 2 c compliant devices. (eq. 6) tc v high v low ? v nominal t high t low ? () ---------------------------------------------------------------------------------- 10 6 = figure 15. isl29034 typical circuit figure 16. 4 ld odfn sensor location outline isl29034 mcu 1f scl sda 1 2 3 vdd scl sda vdd 4 gnd vdd_pullup 4.7k 4.7k 100
isl29034 14 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8370.1 april 9, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change april 9, 2014 fn8370.1 initial release
isl29034 15 fn8370.1 april 9, 2014 submit document feedback package outline drawing l4.1.5x1.3 4 ld 1.5x1.3 optical dual flat no-lead (odfn) rev 5, 4/12 bottom view detail "x" side view typical recommended land pattern top view 4 3 1 2 1 3 4 2 (4x) 0.10 index area pin 1 a b pin #1 3x 0 . 40 0 . 10 b 0.10 m a c c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 5 6 6 1.30 1.50 0.50 0.25 0.07 (0.55) (0.50) (1.30) (4 x 0.25) (3x0.60) 0.70 0.05 (0.55) index area 4 (0.75) located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.18mm and 0.32mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: this package not defined by jedec, but mo-229 can be used as 7. a general reference.

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