View Z86C7116PSC_8243153.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds97lvo0500 p r e l i m i n a r y 1-1 1 p reliminary p roduct s pecification z86l70/71/75/c71 1 ir/l ow -v oltage m icrocontroller features n two standby modes (typical) stop - 2 m a halt - 0.8 ma n special architecture to automate both generation and reception of complex pulses or signals: one programmable 8-bit counter/timer with two capture registers one programmable 16-bit counter/timer with one capture register programmable input glitch filter for pulse reception n five priority interrupts n low voltage detection and protection n programmable watch-dog/power-on reset circuits n two independent comparators with programmable interrupt polarity n on-chip oscillator that accepts a crystal, ceramic resonator, lc, rc (mask option), or external clock drive n mask selectable 200 kohm pull-ups on ports 0, 2, 3 general description the z86l7x family of ir (infrared)/low-voltage microcon- trollers are rom/romless-based members of the z8 mcu single-chip family with 237/125 bytes of internal ram. the differentiating factor between these devices is the availability of ram, rom and package options. offer- ing the 3v versions (z86lxx) with the z86c71 gives opti- mum performance in both the low and high voltage ranges. zilog's cmos low-voltage microcontrollers offer fast exe- cution, efficient use of memory, sophisticated interrupts, in- put/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up resis- tors. the z86l7x product line offers easy hardware/soft- ware system expansion with cost-effective and low power consumption. the z86l7x architecture is based on zilog's 8-bit micro- controller core with an expanded register file to allow ac- cess to register mapped peripherals, i/o circuits, and pow- erful counter/timer circuitry. the z8 mcu offers a flexible i/o scheme, an efficient register and address space struc- ture, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery operated hand-held applications. there are three basic address spaces available to support a wide range of configurations: program memory, register file, and expanded register file. the register file is com- posed of 256/144 bytes of ram. it includes four i/o port registers, 15 control and status registers and the rest are general-purpose registers. the expanded register file consists of two additional register groups (f and d). exter- nal memory is not available on 18 and 20-pin versions. part rom (kb) ram* (bytes) i/o voltage ranges z86l70 2 125 14 2.0v to 3.9v z86l71 8 237 16 2.0v to 3.9v z86l75 4 237 14 2.0v to 3.9v z86c71 8 237 16 4.5v to 5.5v note: *general-purpose
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-2 p r e l i m i n a r y ds97lvo0500 general description (continued) to unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the z86l7x family offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (figure 1). also includ- ed are a large number of user-selectable modes, and two on-board comparators to process analog signals (figure 2). figure 1. counter/timer block diagram hi16 lo16 16-bit t16 tc16h tc16l hi8 lo8 and/or logic clock divider glitch filter edge detect circuit 8-bit t8 tc8h tc8l 8 8 16 8 input sclk 1 2 48 timer 16 timer 8/16 timer 8 8 8 8 8 8
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-3 1 note: all signals with a preceding front slash, "/", are ac- tive low, for example, b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: figure 2. functional block diagram port 0 p00 p07 p31 p32 p33 port 3 register file 144/256 x 8-bit rom 2k/4k/8k x 8 z8 core register bus internal address bus internal data bus expanded register file expanded register bus counter/timer 8 8-bit counter/timer 16 16-bit power vdd vss p34 p35 p36 2 p20 p21 p22 p23 p24 p25 p26 p27 port 2 i/o bit programmable machine timing & instruction control xtal2 xtal1 two analog comparators interrupt control connection circuit device power v cc v dd ground gnd v ss
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-4 p r e l i m i n a r y ds97lvo0500 pin description figure 3. 18-pin dip/soic pin assignments p24 p25 p26 p27 vdd xtal2 xtal1 p31 p32 p23 p22 p21 p20 vss p36 p35 p34 p33 18 z86l70/75 dip/soic 1 910 figure 4. 20-pin dip/soic pin assignments p24 p25 p26 p27 vdd xtal2 xtal1 p31 p32 p00 p23 p22 p21 p20 vss p36 p35 p34 p33 p07 20 z86l71/c71 dip/soic 1 10 11 table 1. pin identi?ation 20-pin dip & soic 18-pin dip & soic symbol direction description 10 11 p00 p07 input/output input/output port 0 pins are individually con?urable as input or output. 17 18 19 20 1 2 3 4 15 16 17 18 1 2 3 4 p20 p21 p22 p23 p24 p25 p26 p27 input/output input/output input/output input/output input/output input/output input/output input/output port 2 pins are individually con?urable as input or output. 8 9 12 13 14 15 8 9 10 11 12 13 p31 p32 p33 p34 p35 p36 input input input output output output irq2/modulator input irq0 irq1 t8 output t16 output t8/t16 output 7 6 5 16 7 6 5 14 xtal1 xtal2 v dd v ss input output crystal, oscillator clock crystal, oscillator clock power supply ground
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-5 1 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. exposure to ab- solute maximum rating conditions for an extended period may affect device reliability. standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 5). capacitance t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. symbol description min max units v cc supply voltage (*) -0.3 +7.0 v t stg storage temp. -65 +150 c t a oper. ambient temp. ?c notes: * voltage on all pins with respect to gnd. ? see ordering information figure 5. test load diagram from output under test 150 pf i parameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-6 p r e l i m i n a r y ds97lvo0500 dc characteristics (z86l70/71/75 low voltage specifications) preliminary t a = 0 c to +70 c typ @ sym parameter v cc min max 25 c units conditions notes max input voltage 2.0v 3.9v 7 7 v v i in <250 m a i in <250 m a v ch clock input high voltage 2.0v 3.9v 0.8 v cc 0.8 v cc v cc + 0.3 v cc + 0.3 v v driven by external clock generator driven by external clock generator v cl clock input low voltage 2.0v 3.9v v ss ?0.3 v ss ?0.3 0.2 v cc 0.2 v cc v v driven by external clock generator driven by external clock generator v ih input high voltage 2.0v 3.9v 0.7 v cc 0.7 v cc v cc + 0.3 v cc + 0.3 0.5v cc 0.5v cc v v v il input low voltage 2.0v 3.9v v ss ?0.3 v ss ?0.3 0.2 v cc 0.2 v cc 0.5v cc 0.5v cc v v v oh1 output high voltage 2.0v 3.9v v cc ?0.4 v cc ?0.4 1.7 3.7 v v i oh = ?.5 ma i oh = ?.5 ma v oh2 output high voltage (p36, p37,p00, p01) 2.0v 3.9v v cc - 0.8 v cc - 0.8 v v i oh = ? ma i oh = ? ma v ol1 output low voltage 2.0v 3.9v 0.4 0.4 0.1 0.2 v v i ol = 1.0 ma i ol = 4.0 ma v ol2* output low voltage 2.0v 3.9v 0.8 0.8 0.5 0.3 v v i ol = 5.0 ma i ol = 7.0 ma v ol2 output low voltage(p36, p37,p00,p01) 2.0v 3.9v 0.8 0.8 0.3 0.2 v v i ol = 10 ma i ol = 10 ma v rh reset input high voltage 2.0v 3.9v 0.8 v cc 0.8 v cc v cc v cc 1.5 2.0 v v v rl reset input low voltage 2.0v 3.9v v ss ?0.3 v ss ?0.3 0.2 v cc 0.2 v cc 0.5 0.9 v v v offset comparator input offset voltage 2.0v 3.9v 25 25 10 10 mv mv i il input leakage 2.0v 3.9v -1 -1 1 1 < 1 < 1 m a m a v in = o v , v cc v in = o v , v cc i ol output leakage 2.0v 3.9v ? ? 1 1 < 1 < 1 m a m a v in = o v , v cc v in = o v , v cc i ir reset input pull- up current 2.0v 3.9v ?30 ?00 -50 ?0 m a m a v in = o v v in = o v i cc supply current 2.0v 3.9v 2.0v 3.9v 10 15 250 850 4 10 100 500 ma ma m a m a @ 8.0 mhz @ 8.0 mhz @ 32 khz @ 32 khz 1,2 1,2 1,2,8
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-7 1 t a = 0 c to +70 c typ @ sym parameter v cc min max 25 c units conditions notes i cc1 standby current (wdt off) 2.0v 3.9v 3 5 1 4 ma ma halt mode v in = o v , v cc @ 8.0 mhz halt mode v in = o v , v cc @ 8.0 mhz 1,2 1,2 2.0v 3.9v 2 4 0.8 2.5 ma ma clock divide-by- 16 @ 8.0 mhz clock divide-by- 16 @ 8.0 mhz 1,2 1,2 i cc2 standby current 2.0v 3.9v 2.0v 3.9v 8 10 500 800 2 3 310 600 m a m a m a m a stop mode v in = o v , v cc wdt is not running stop mode v in = o v , v cc wdt is not running stop mode v in = o v , v cc wdt is running 3,5 3,5 3,5 v icr input common mode voltage range 2.0v 3.9v 0 0 v cc - 1.0v v cc - 1.0v v v 8 t por power-on reset 2.0v 3.9v 12 5 75 20 18 7 ms ms v ram static ram data retention voltage vram 0.8 0.5 v 6 v lv v cc low voltage protection 2.15 1.7 v 8 mhz max ext. clk freq. 4 notes: i cc1 crystal/resonator external clock drive typ 3.0 ma 0.3 ma max 5 5 unit ma ma frequency 8.0 mhz 8.0 mhz 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf 3. same as note [4] except inputs at v cc . 4. the v lv increases as the temperature decreases. 5. oscillator stopped 6. oscillator stops when v cc falls below v lv limit. 7. 32 khz clock driver input. 8. for analog comparator, inputs when analog comparators are enabled. * all outputs excluding p00, p01, p36, and p37.
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-8 p r e l i m i n a r y ds97lvo0500 dc characteristics (z86c71 specifications) preliminary t a = 0 c to +70 c typ @ sym parameter v cc min max 25 c units conditions notes max input voltage 4.5v 5.5v 7 7 v v i in 250 m a i in 250 m a v ch clock input high voltage 4.5v 5.5v 0.9 v cc 0.9 v cc v cc + 0.3 v cc + 0.3 v driven by external clock generator v cl clock input low voltage 4.5v 5.5v v ss ?0.3 v ss ?.3 0.2 v cc 0.2 v cc v driven by external clock generator v ih input high voltage 4.5v 5.5v 0.7 v cc 0.7 v cc v cc + 0.3 v cc + 0.3 0.5v cc 0.5v cc v driven by external clock generator v il input low voltage 4.5v 5.5v v ss ?0.3 v ss ?0.3 0.5v cc 0.5v cc v v oh1 output high voltage 4.5v 5.5v v cc ?0.4 v cc ?0.4 4.4 5.4 vi oh = ?.5 ma i oh = ?.5 ma v oh2 output high voltage (p36, p37) 4.5v 5.5v v cc ?0.8 v cc ?0.8 v v i oh = ? ma i oh = ? ma v ol1 output low voltage 4.5v 5.5v 0.4 0.4 0.1 0.2 v v i ol = 1.0 ma i ol = 4.0 ma v ol2* output low voltage 4.5v 3.9 v 0.8 0.8 0.3 0.4 v v i ol = 5.0 ma i ol = 7.0 ma v ol2 output low voltage (p00, p01, p36,p37) 4.5v 5.5v 0.8 0.8 0.3 0.2 vi ol = 10 ma v rh reset input high voltage 4.5v 5.5v 0.8 v cc 0.8 v cc v cc v cc 2.5 3.0 v v v rl reset input low voltage 4.5v 5.5v v ss ?0.3 v ss ?0.3 0.2 v cc 0.2 v cc 0.5 0.9 v offset comparator input offset voltage 4.5v 5.5v 25 25 10 10 mv mv i il input leakage 4.5v 5.5v -1 -1 1 1 <1 <1 m a m a v in = o v , v cc v in = o v , v cc i ol output leakage 4.5v 5.5v -1 -1 1 1 <1 <1 m a m a v in = o v , v cc v in = o v , v cc i ir reset input current 4.5v 5.5v -500 -800 m a m a i cc supply current 4.5v 5.5v 20 30 ma ma @8.0 mhz @8.0 mhz 1,2 1.2 wdt off 4.5v 5.5v 1000 1250 10 10 m a m a @ 32 khz @ 32 khz 1,2,8 1,2,8
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-9 1 t a = 0 c to +70 c typ @ sym parameter v cc min max 25 c units conditions notes i cc1 standby current (wdt off) 4.5v 5.5v 6 8 2 5 ma ma halt mode v in = o v , v cc @ 8.0 mhz halt mode v in = o v , v cc @ 8.0 mhz 1,2 1,2 4.5v 5.5v 5 7 1.0 3.0 ma ma clock divide-by- 16 @ 8.0 mhz clock divide-by- 16 @ 8.0 mhz 1,2 1,2 i cc2 standby current 4.5v 5.5v 8 10 2 3 m a m a stop mode v in = o v , v cc wdt is not running stop mode v in = o v , v cc wdt is not running 3,5 3,5 4.5v 5.5v 500 800 310 600 m a m a stop mode v in = o v , v cc wdt is running 3,5 v icr input common mode voltage range 2.0v 3.9v 0 0 v cc - 1.0v v cc - 1.0v v v 8 t por power-on reset 4.5v 5.5v 5.0 4.0 75 20 8.0 6.0 ms ms v ram static ram data retention voltage v ram 0.8 0.5 v 6 v lv v cc low voltage protection 2.15 1.7 v 8 mhz max ext. clk freq. 4 notes: i cc1 crystal/resonator external clock drive typ 3.5 ma 0.8 ma max 5 5 unit ma ma frequency 8.0 mhz 8.0 mhz 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf 3. same as note [4] except inputs at v cc . 4. the v lv increases as the temperature decreases. 5. oscillator stopped 6. oscillator stops when v cc falls below v lv limit. 7. 32 khz clock driver input 8. for analog comparator, inputs when analog comparators are enabled. * all outputs excluding p00, p01, p36, and p37.
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-10 p r e l i m i n a r y ds97lvo0500 ac characteristics external i/o or memory read and write timing diagram figure 6. external i/o or memory read/write timing r//w 9 12 18 3 16 13 4 5 8 11 6 17 10 15 14 2 1 port 0, /dm port 1 /as /ds (read) port 1 /ds (write) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0 19 20 7
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-11 1 ac characteristics external i/o or memory read and write timing table t a = 0 c to +70 c 8.0 mhz no symbol parameter v cc min max units notes 1 tda(as) address valid to /as rising delay 2.0v 3.9v 55 55 ns ns 2 2 tdas(a) /as rising to address float delay 2.0v 3.9v 70 70 ns ns 2 3 tdas(dr) /as rising to read data required valid 2.0v 3.9v 400 400 ns ns 1,2 4 twas /as low width 2.0v 3.9v 80 80 ns ns 2 5 td address float to /ds falling 2.0v 3.9v 0 0 ns ns 6 twdsr /ds (read) low width 2.0v 3.9v 300 300 ns ns 1,2 7 twdsw /ds (write) low width 2.0v 3.9v 165 165 ns ns 1,2 8 tddsr(dr) /ds falling to read data required valid 2.0v 3.9v 260 260 ns ns 1,2 9 thdr(ds) read data to /ds rising hold time 2.0v 3.9v 0 0 ns ns 2 10 tdds(a) /ds rising to address active delay 2.0v 3.9v 85 85 ns ns 2 11 tdds(as) /ds rising to /as 2.0v 3.9v 60 70 ns ns 2 12 tdr/w(as) r//w valid to /as rising delay 2.0v 3.9v 70 70 ns ns 2 13 tdds(r/w) /ds rising to r//w not valid 2.0v 3.9v 70 70 ns ns 2 14 tddw(dsw) write data valid to /ds falling (write) delay 2.0v 3.9v 80 80 ns ns 2 15 tdds(dw) /ds rising to write data not valid delay 2.0v 3.9v 70 80 ns ns 2 16 tda(dr) address valid to read data required valid 2.0v 3.9v 475 475 ns ns 1,2 17 tdas(ds) /as rising to /ds falling delay 2.0v 3.9v 100 100 ns ns 2 18 tdm(as) /dm valid to /as falling delay 2.0v 3.9v 55 55 ns ns 2 19 tdds(dm) /ds rise to /dm valid delay 2.0v 3.9v 70 70 ns ns 20 thds(a) /ds rise to address valid hold time 2.0v 3.9v 70 70 ns ns notes: 1. when using extended memory timing add 2 tpc. 2. timing numbers given are for minimum tpc. standard test load all timing references use 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0.
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-12 p r e l i m i n a r y ds97lvo0500 ac characteristics additional timing diagram figure 7. additional timing clock 1 3 4 8 2 2 3 t irq in n 6 5 7 7 clock setup 10 9 stop mode recovery source 11
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-13 1 ac characteristics additional timing table t a = 0 c to +70 c 8.0 mhz no symbol parameter v cc min max units notes 1 tpc input clock period 2.0v 3.9v 121 121 dc dc ns ns 1 1 2 trc, tfc clock input rise and fall times 2.0v 3.9v 25 25 ns ns 1 1 3 twc input clock width 2.0v 3.9v 37 37 ns ns 1 1 4 twtinl timer input low width 2.0v 3.9v 100 70 ns ns 1 1 5 twtinh timer input high width 2.0v 3.9v 3tpc 3tpc 1 1 6 tptin timer input period 2.0v 3.9v 8tpc 8tpc 1 1 7 trtin, tftin timer input rise 2.0v 3.9v 100 100 ns ns 1 1 8a twil interrupt request low time 2.0v 3.9v 100 70 ns ns 1,2 1,2 8b twil int. request low time 4.5v 5.5v 5tpc 5tpc 1,3 1,3 9 twih interrupt request input high time 4.5v 5.5v 5tpc 5tpc 1,2 1,2 10 twsm stop-mode recovery width spec 2.0v 3.9v 2.0v 12 12 5tpc 5tpc ns ns 8 8 7 7 11 tost oscillator start-up time 2.0v 3.9v 5tpc 5tpc 4 4 12 twdt watch-dog timer delay time (5 ms) 2.0v 3.9v 12 5 75 20 ms ms d0=0, 5 d1=0, 5 10 ms 2.0v 3.9v 20 10 150 40 ms ms d0=1, 5 d1=0, 5 20 ms 2.0v 3.9v 50 20 300 80 ms ms d0=1, 5 d1=0, 5 80 ms 2.0v 3.9v 225 80 1200 320 ms ms d0=1, 5 d1=0, 5 notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31). 3. interrupt request through port 3 (p30). 4. smr - d5 = 0 5. reg. wdtmr 6. reg. smr - d5 = 0 7. reg. smr - d5 = 1
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-14 p r e l i m i n a r y ds97lvo0500 pin functions xtal1 crystal 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc, or rc network or an external single-phase clock to the on-chip oscillator input. xtal2 crystal 2 (time-based output). this pin connects a parallel-resonant, crystal, ceramic resonant, lc, or rc network to the on-chip oscillator output. port 0 (p07-p00). port 0 is an two-bit, bidirectional, cmos-compatible port. these i/o lines are configured un- der software control as an i/o port. the output drivers are push-pull. an optional 200 kohm pull-up is available as a mask op- tion on both port 0 bits. these pull-ups are disabled when configured (bit by bit) as an output . figure 8. port 0 con?uration oen out in pa d 200 k w mask option
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-15 1 port 2 (p27-p20). port 2 is an 8-bit, bidirectional, cmos- compatible i/o port. these eight i/o lines can be indepen- dently configured under software control as inputs or out- puts. port 2 is always available for i/o operation. a mask option is available to connect eight 200 kohms ( 50%) pull-up resistors on this port. bits programmed as outputs are globally programmed as either push-pull or open- drain. the z8 wakes up with the eight bits of port 2 config- ured as inputs with open-drain outputs. port 2 also has an 8-bit input or and an and gate which can be used to wake up the part from stop mode (figure 33). p20 can be programmed to access the edge selection circuitry (figure 9). figure 9. port 2 con?uration open-drain oen out in pa d port 2 (i/o) z86lxx mcu vcc mask option 200 k w
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-16 p r e l i m i n a r y ds97lvo0500 pin functions (continued) port 3 (p36-p31). port 3 is a 6-bit, cmos-compatible three fixed input and three fixed output port. port 3 consists of three fixed input (p33-p31) and three fixed output (p36- p34), and can be configured under software control for in- put/output, interrupt, and output from the counter/timers. p31, p32, and p33 are standard cmos inputs; outputs are push-pull, except for p34, p35 which have floating drain capability (controlled by p3m, d0). two on-board comparators process analog signals on p31 and p32 with reference to the voltage on p33. the analog function is enabled by programming the port 3 mode reg- ister (bit 1). p31 and p32 are programmable as rising, fall- ing, or both edge triggered interrupts (irq register bits 6 and 7). pref1 and p33 are the comparator reference volt- age inputs. access to the counter timer edge detection circuit is through p31 or p20 (see ctr1 description). port 3 provides the following control functions: three exter- nal interrupt request signals (irq2-irq0). port 3 also provides output for each of the counter/timers and the and/or logic. control is performed by program- ming bits d5-d4 of ctri, bit 0 of ctr0 and bit 0 of ctr2. table 2. pin assignments pin i/o c/t comp. int. ext p31 in in an1 irq2 p32 in an2 irq0 p33 in v ref irq1 p34 out t8 a01 dm p35 out t16 p36 out t8/16 p20 i/o in figure 10. port 3 con?uration p34 out p32 + - p33 0 = p34 standard output 1 = p34 comparator output pcon d0 p31 + - p33 p34 pa d * t8 p34 out 0 normal control 1 8-bit timer output active ctr0 d0 counter/timer reset condition. * comp1 comp2
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-17 1 comparator inputs. in analog mode, port 3 (p31 and p32) have a comparator front end. p33 serves as the ref- erence for both comparators. in this mode, the p33 internal data latch and its corresponding irq1 is diverted to the smr sources (excluding p31, p32, and p33) as shown in figure 38. in digital mode, p33 is used as d3 of the port 3 input register which then generates irq1 as shown in fig- ure 16. notes: comparators are powered down by entering stop mode. for p31-p33 to be used as a stop-mode recovery source, these inputs must be placed into digital mode. comparator outputs . comp1 may be programmed to be outputted on p34 through the pcon register (figure 15). power-on reset. the typical reset output time is 5 ms. the z86l7x does not reset wdtmr, smr, p2m, or p3m registers on a stop-mode recovery operation. figure 11. port 3 con?uration port 3 (i/o or handshake) z86l7x mcu pref1 p31 p32 p33 p34 p35 p36 p37 note: p31, 32, 33 have a 200 k w mask option 200 k w mask option d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref2) from stop-mode recovery source of smr 1 = analog 0 = digital irq2, p31 data latch irq0, p32 data latch irq1, p33 data latch dig. an. - + - + pref comp1 comp2
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-18 p r e l i m i n a r y ds97lvo0500 pin functions (continued) figure 12. port 3 con?uration vdd out 34 t8_out ctr0, d0 pad out 35 t16_out ctr2, d0 out 36 t8/16_out ctr1, d6 mux mux mux p34 vdd pad p35 vdd pad p36
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-19 1 functional description the z8 incorporates special functions to enhance the z8's functionality in consumer and battery operated applica- tions. reset. the device is reset in one of the following condi- tions: 1. power-on reset 2. watch-dog timer 3. stop-mode recovery source 4. low voltage detection program memory . the z86l7x addresses up to 2k, 4k, 8 kb of internal program memory, with the remainder be- ing external memory (figure 13). the first 12 bytes of pro- gram memory are reserved for the interrupt vectors. these locations contain five 16-bit vectors that correspond to the five available interrupts. addresses 12 to 2k, 4k, 8k (de- pendent on version) consist of on-chip mask-programmed rom. figure 13. program memory map 11 10 9 8 7 6 5 4 3 2 1 0 location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) reserved irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 reserved on-chip rom reset start address 12
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-20 p r e l i m i n a r y ds97lvo0500 expanded register file. the register file has been ex- panded to allow for additional system control registers, and for mapping of additional peripheral devices into the register address area. the z8 register address space r0 through r15 has been implemented as 16 banks of 16 reg- isters per bank. these register groups are known as the erf (expanded register file). bits 7-4 of register rp se- lect the working register group. bits 3-0 of register rp se- lect the expanded register file bank. note that expanded register bank is also referred to as expanded register group (figure14). the upper nibble of the register pointer (figure 23) selects which working register group of 16 bytes in the register file, out of the possible 256, will be accessed. the lower nibble selects the expanded register file bank and, in the case of the z86lxx family, banks 0, f, and d are implemented. a 0h in the lower nibble will allow the normal register file (bank 0) to be addressed, but any other value from 1h to fh will exchange the lower 16 registers to an expanded register bank. for example: z86l70: (see figure 16) r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctrl0 r1 = ctrl1 r2 = ctrl2 r3 = reserved the counter/timers are mapped into erf group d. access is easily done using the following example: ld rp, #0dh select erf d for access to bank d ( work- ing register group 0) ld r0,#xx load ctrl0 ld 1, #xx load ctrl1 ld r1, 2 ctrl2 ? ctrl1 ld rp, #7dh select expanded register bank d and working register group 7 of bank 0 for access . ld 71h, 2 ctrl2 ? register 71h ld r1, 2 ctrl2 ? register 71h
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-21 1 figure 14. expanded register file architecture 7 6543210 working register group pointer expanded register file (bank) pointer ff fo 7f 0f 00 z8 register file** register pointer ff fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 spl sph rp flags imr irq ipr p01m p3m p2m u u 0 u 0 0 u 0 0 1 (f) 0f (f) 0e (f) 0d (f) 0c (f) 0b reserved (f) 01 (f) 00 wdtmr smr u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 1 0 1 uu u 0 1 101 001000u0 register** expanded reg. group (f) reset condition register** z8 ? standard control registers reset condition d7 d6 d5 d4 d3 d2 d1 d0 reserved * * * ? reserved smr2 reserved reserved uuuuu uu u uu u uuu u u uu u uu u uu uu u u u uu u 0 0 000000 0u u 00 00 0 reserved pcon u 0 * 0u1 1uu uu uu uuuuuu uu uu uu u u u u u uu u uu register** expanded reg. group (0) reset condition (0) 03 p3 (0) 02 p2 (0) 01 p1 (0) 00 p0 u = unknown * will not be reset with a stop-mode recovery ** all addresses are in hexadecimal @ * ? will not be reset with a stop-mode recovery, except bit 0. reserved reserved reserved reserved reserved u 0 u0 0 0uu expanded reg. group (d) register** (d) 0c (d) 0b (d) 0a (d) 09 (d) 08 (d) 07 (d) 06 (d) 05 (d) 04 (d) 03 (d) 02 reserved hi8 l08 hi16 l016 tc16h tc16l tc8h tc8l reserved ctr2 reset condition u uu u uuuuuuu u u u u u u u 0 uuuuu u u u u u u u uuuuuu u u u u u u u u u u u u uuuu uuuu u u u u uu uuu uuu uuu (d) 01 ctr1 (d) 00 ctr0 u u uuuuu u 0 uuuuuu reserved u u u u u u u reserved reserved reserved reserved reserved reserved reserved reserved @ p36 is set to an unknown state upon smr reset. rest of ports will not be affected.
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-22 p r e l i m i n a r y ds97lvo0500 ram/register file. the register file (group 0) consists of four i/o port registers, 236 general purpose registers, and 16 control and status registers (r0-r3, r4-r239, and r240-r255, respectively), plus two expanded registers group (banks d and f). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working register group. note: registers e0-ef of bank 0 are only accessed through working registers and indirect addressing modes. stack. the z86l7x internal register file is used for the stack. an 8-bit stack pointer (r255) is used for the internal stack that resides in the general-purpose registers (r4- r239). figure 15. register pointer d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank file pointer working register pointer r253 rp default setting after reset = 0000 0000 figure 16. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group r 7 r 6 r 5 r 4 r253 i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register r 3 r 2 r 1 r 0 register group 0 7f register group 1 6f 5f 4f 3f 2f 1f 0f 00 10 20 30 40 50 60 70 r15 to r0 r15 to r4 * r3 to r0 * * rp = 00: selects register group 0, working register 0.
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-23 1 counter/timer register description hi8(d)%0b: holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 1. l08(d)%0a: holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 0. hi16(d)%09: holds the captured data from the output of the 16-bit counter/timer16. this register holds the ms- byte of the data. l016(d)%08: holds the captured data from the output of the 16-bit counter/timer16. this register holds the ls- byte of the data. tc16h(d)%07: counter/timer2 ms-byte hold register. tc16l(d)%06: counter/timer2 ls-byte hold register. tc8h(d)%05: counter/timer8 high hold register. tc8l(d)%04: counter/timer8 low hold register. expanded register group d (d)%0c reserved (d)%0b hi8 (d)%0a lo8 (d)%09 hi16 (d)%08 lo16 (d)%07 tc16h (d)%06 tc16l (d)%05 tc8h (d)%04 tc8l (d)%03 reserved (d)%02 ctr2 (d)%01 ctr1 (d)%00 ctr0 field bit position description t8_capture_hi 76543210 r w captured data no effect field bit position description t16_capture_lo 76543210 r w captured data no effect field bit position description t16_capture_hi 76543210 r w captured data no effect field bit position description t16_capture_lo 76543210 r w captured data no effect field bit position description t16_data_hi 76543210 r w data field bit position description t16_data_lo 76543210 r/w data field bit position description t8_level_hi 76543210 r/w data field bit position description t8_level_lo 76543210 r/w data
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-24 p r e l i m i n a r y ds97lvo0500 ctr0 (d)00: counter/timer8 control register. ctr0: counter/timer8 control register description t8 enable. this field enables t8 when set (written) to 1. single/modulo-n. when set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. when set to 1 (single pass), the counter stops when the terminal count is reached. time-out. this bit is set when t8 times out (terminal count reached). to reset this bit, a 1 should be written to this lo- cation. this is the only way to reset this status condition, therefore, care should be taken to reset this bit prior to us- ing/enabling the counter/timers. note: care must be taken when utilizing the or or and commands to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these instructions use a read-modify-write sequence in which the current status from the ctr0 and ctr1 registers will be ored or anded with the designated value and then written back into the registers. example: when the status of bit 5 is 1, a reset condition will occur. t8 clock. defines the frequency of the input signal to t8. capture_int_mask. set this bit to allow interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in demodulation mode. counter_int_mask. set this bit to allow interrupt when t8 has a time out. p34_out . this bit defines whether p34 is used as a normal output pin or the t8 output. field bit position value description t8_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0 1 modulo-n single pass time_out --5----- r 0 no counter time-out counter time-out occurred no effect reset flag to 0 t8_clock ---43--- r/w 0 0 0 1 1 0 1 1 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disabled data capture int. enable data capture int. counter_int_mask ------1- r/w 0 1 disable data capture int. enable time-out int. p34_out -------0 r/w 0 1 p34 as port output t8 output on p34
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-25 1 ctr1 (d)01: controls the functions in common with the t8 and t16 field bit position value description mode 7------- r/w 0 1 t r ansmit mode demodulation mode p36_out/ demodulator_input -6------ r/w 0 1 0 1 t r ansmit mode port output t8/t16 output demodulation mode p31 p20 t8/t16_logic/ edge _detect --54---- r/w 00 01 10 11 00 01 10 11 t r ansmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved transmit_submode/glitch_ filter ----32-- r/w 00 01 10 11 00 01 10 11 t r ansmit mode normal operation ping-pong mode t16_out=0 t16_out=1 demodulation mode no filter 4 sclk cycle 8 sclk cycle 16 sclk cycle initial_t8_out/ rising_edge ------1- r/w r w 0 1 0 1 0 1 t r ansmit mode t8_out is 1 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0 initial_t16_out/ falling _edge -------0 r/w r w 0 1 0 1 0 1 t r ansmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-26 p r e l i m i n a r y ds97lvo0500 ctr1 register description mode. if it is 0, the counter/timers are in the transmit mode, otherwise they are in the demodulation mode. p36_out/demodulator_input. in transmit mode, this bit defines whether p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whether the input signal to the counter/timers is from p20 or p31. t8/t16_logic/edge _detect. in transmit mode, this field defines how the outputs of t8 and t16 are combined (and, or, nor, nand). in demodulation mode, this field defines which edge should be detected by the edge detector. transmit_submode/glitch filter. in transmit mode, this field defines whether t8 and t16 are in the "ping-pong" mode or in independent normal operation mode. setting this field to "normal operation mode" terminates the "ping- pong mode" operation. when set to 10, t16 is immediately forced to a 0. when set to 11, t16 is immediately forced to a 1. in demodulation mode, this field defines the width of the glitch that should be filtered out. initial_t8_out/rising_edge. in transmit mode, if 0, the output of t8 is set to 0 when it starts to count. if 1, the out- put of t8 is set to 1 when it starts to count. when this bit is set to 1 or 0, t8_out will be set to the opposite state of this bit. this insures that when the clock is enabled a tran- sition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. in order to reset it, a 1 should be written to this location. initial_t16 out/falling _edge . in transmit mode, if it is 0, the output of t16 is set to 0 when it starts to count. if it is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3, d2). when this bit is set, t16_out will be set to the opposite state of this bit. this insures that when the clock is enabled a transition occurs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. in order to reset it, a 1 should be written to this location. note: modifying ctr1, (d1 or d0) while the counters are enabled will cause un-predictable output from t8/16_out.
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-27 1 ctr2 (d)%02: counter/timer16 control register. ctr2 description t16_enable. this field enables t16 when set to 1. single/modulo-n. in transmit mode, when set to 0, the counter reloads the initial value when terminal count is reached. when set to 1, the counter stops when the termi- nal count is reached. in demodulation mode, when set to 0 , t16 captures and reloads on detection of all the edges; when set to 1, t16 captures and detects on the first edge, but ignores the sub- sequent edges. for details, see the description of t16 de- modulation mode. time_out. this bit is set when t16 times out (terminal count reached). in order to reset it, a 1 should be written to this location. t16_clock. defines the frequency of the input signal to counter/timer16. capture_int_mask. set this bit to allow interrupt when data is captured into lo16 and hi16. counter_int_mask. set this bit to allow interrupt when t16 times out. p35_out. this bit defines whether p35 is used as a normal output pin or t16 output. field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r0 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t16 _clock ---43--- r/w 00 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0 1 disable time-out int. enable time-out int. p35_out -------0 r/w 0 1 p35 as port output t16 output on p35 note: * indicates the value upon power-on reset
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-28 p r e l i m i n a r y ds97lvo0500 smr2(f)%0d: stop-mode recovery register 2. field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0* 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000* 001 010 011 100 101 110 111 a. por only b. nand of p23-p20 c. nand or p27-p20 d. nor of p33-p31 e. nand of p33-p31 f. nor of p33-p31, p00,p07 g. nand of p33-p31,p00,p07 h. nand of p33-p31,p22-p20 reserved ------10 00 reserved (must be 0) note: * indicates the value upon power-on reset.
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-29 1 counter/timer functional blocks figure 17. glitch filter circuitry glitch filter edge detector ctr1 d5,d4 ctr1 d3,d2 pos edge neg edge mux ctr1 d6 p31 p20 figure 18. 8-bit counter/timer circuits z8 data bus pos edge neg edge ctr0 d2 irq4 ctr0 d1 t8_out tc8l tc8h clock select sclk ctr0 d4, d3 clock 8-bit counter t8 hi8 lo8 z8 data bus
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-30 p r e l i m i n a r y ds97lvo0500 functional description (continued) input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5-d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal which have a width less than specified (ctr1 d3, d2) are filtered out. t8 transmit mode when t8 is enabled, the output of t8 depends on ctr1, d1. if it is 0, t8_out is 1. if it is 1, t8_out is 0. when t8 is enabled, the output t8_out switches to the initial value (ctr1 d1). if the initial value (ctr1 d1) is 0, tc8l is loaded, otherwise tc8h is loaded into the counter. in single-pass mode (ctr0 d6), t8 counts down to 0 and stops, t8_out toggles, the time-out status bit (ctr0 d5) is set, and a time-out interrupt can be generat- ed if it is enabled (ctr0 d1) (figure 22). in modulo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. then t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, sets the time-out status bit (ctr0 d5) and generates an interrupt if enabled (ctr0 d1) (figure 23). this completes one cycle. t8 then loads from tc8h or tc8l according to the t8_out level, and repeats the cycle. the user can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. care must be taken not to write these registers at the time the values are to be loaded into the counter/timer, to en- sure known operation. an initial count of 1 is not al- lowed (a non-function will occur). an initial count of 0 will cause tc8 to count from 0 to %ff to %fe (note, % is used for hexadecimal values). transition from 0 to %ff is not a time-out condition. note: using the same instructions for stopping the counter/timers and setting the status bits is not rec- ommended. two successive commands, first stopping the counter/timers, then resetting the status bits is neces- sary. this is required because it takes one counter/timer clock interval for the initiated event to actually occur. figure 19. t8_out in single-pass mode tc8h counts counter enable command, t8_out switches to its initial value (ctr1 d1) t8_out toggles, time-out interrupt figure 20. t8_out in modulo-n mode counter enable command, t8_out switches to its initial value (ctr1 d1) t8_out toggles t8_out tc8l tc8h tc8l tc8h tc8l time-out interrupt time-out interrupt
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-31 1 t8 demodulation mode the user should program tc8l and tc8h to %ff. after t8 is enabled, when the first edge (rising, falling, or both depending on ctr1 d5, d4) is detected, it starts to count down. when a subsequent edge (rising, falling, or both de- pending on ctr1 d5, d4) is detected during counting, the current value of t8 is one's complemented and put into one of the capture registers. if it is a positive edge, data is put into lo8, if negative edge, hi8. one of the edge detect status bits (ctr1 d1, d0) is set, and an interrupt can be generated if enabled (ctr0 d2). meanwhile, t8 is loaded with %ff and starts counting again. should t8 reach 0, the time-out status bit (ctr0 d5) is set, an interrupt can be generated if enabled (ctr0 d1), and t8 continues count- ing from %ff (figure 21). figure 21. demodulation mode count capture flowchart t8 (8-bit) count capture t8_enable (set by user) no yes edge present no yes what kind of edge pos t8 ? l08 neg t8 ? hi8 %ff ? t8
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-32 p r e l i m i n a r y ds97lvo0500 functional description (continued) figure 22. transmit mode flowchart t8 (8-bit) transmit mode t8_enable bit set ctr0, d7 no yes ctr1, d1 value 1 load tc8l reset t8_out load tc8h set t8_out enable t8 reset t8_enable bit set time-out status bit (ctr0 d5) and generate timeout_int if enabled no t8_timeout yes single pass? modulo-n t8_out value load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout disable t8 yes set time-out status bit (ctr0 d5) and generate timeout_int if enabled single pass 0 1 0
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-33 1 figure 23. demodulation mode flowchart t8 (8-bit) demodulation mode t8_enable ctr0, d7 no yes edge present no t8_enable bit set yes set edge present status bit and trigger data capture int. if enabled no %ff ? tc8 yes enable tc8 edge present disable t8 yes t8 time out yes set time-out status bit and trigger time out int. if enabled no continue counting
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-34 p r e l i m i n a r y ds97lvo0500 functional description (continued) t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled is dependent on ctr1, d0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. the user can force the out- put of t16 to either a 0 or 1 whether it is enabled or not by programming ctr1 d3, d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1 d0). when t16 counts down to 0, t16_out is toggled (in nor- mal or ping-pong mode), an interrupt is generated if en- abled (ctr2 d1), and a status bit (ctr2 d5) is set. note that global interrupts will override this function as de- scribed in the interrupts section. if t16 is in single-pass mode, it is stopped at this point. if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l and the counting continues. the user can modify the values in tc16h and tc16l at any time. the new values take effect when they are load- ed. care must be taken not to load these registers at the time the values are to be loaded into the counter/timer, to ensure known operation. an initial count of 1 is not al- lowed. an initial count of 0 will cause t16 to count from 0 to %ffff to %fffe. transition from 0 to %ffff is not a time-out condition. figure 24. 16-bit counter/timer circuits z8 data bus pos edge neg edge ctr2 d2 irq3 ctr2 d1 t16_out tc16l tc16h clock select sclk ctr2 d4, d3 clock 16-bit counter t16 hi16 lo16 z8 data bus
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-35 1 t16 demodulation mode the user should program tc16l and tc16h to %ff. after t16 is enabled, when the first edge (rising, falling, or both depending on ctr1 d5, d4) is detected, t16 captures hi16 and lo16 reloads and begins counting. if d6 of ctr2 is 0: when a subsequent edge (rising, fall- ing, or both depending on ctr1 d5, d4) is detected during counting, the current count in t16 is one's complemented and put into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1 d1, d0) is set and an interrupt is generated if enabled (ctr2 d2). t16 is loaded with %ffff and starts again. if d6 of ctr2 is 1: t16 ignores the subsequent edges in the input signal and continues counting down. a time out of t8 will cause t16 to capture its current value and gen- erate an interrupt if enabled (ctr2, d2). in this case, t16 does not reload and continues counting. if d6 bit of ctr2 is toggled (by writing a 0 then a 1 to it), t16 will capture and reload on the next edge (rising, falling, or both depending on ctr1 d5, d4) but continue to ignore subsequent edg- es. should t16 reach 0, it continues counting from %ffff; meanwhile, a status bit (ctr2 d5) is set and an interrupt time-out can be generated if enabled (ctr2 d1). figure 25. t16_out in single-pass mode tc16h*256+tc16l counts counter enable command, t16_out switches to its initial value (ctr1 d0) t16_out toggles, time-out interrupt figure 26. t16_out in modulo-n mode tc16h*256+tc16l counter enable command, t16_out switches to its initial value (ctr1 d0) t16_out toggles, time-out interrupt tc16h*256+tc16l tc16h*256+tc16l t16_out toggles, time-out interrupt t16_out
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-36 p r e l i m i n a r y ds97lvo0500 functional description (continued) ping-pong mode this operation mode is only valid in transmit mode. t8 and t16 need to be programmed in single-pass mode (ctr0 d6, ctr2 d6) and ping-pong mode needs to be programmed in ctr1 d3, d2. the user can begin the op- eration by enabling either t8 or t16 (ctr0 d1 or ctr2 d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1 d1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the terminal count is reached, t8 is disabled and t16 is enabled. t16_out switches to its initial value (ctr1 d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count it stops, t8 is enabled again, and the whole cycle repeats. interrupts can be allowed when t8 or t16 reaches terminal control (ctr0 d1, ctr2 d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. note:enabling ping-pong operation while the counter/timers are running may cause intermittent counter/timer function. disable the counter/timers, then reset the status flags prior to instituting this operation. to initiate ping-pong mode first, make sure both counter/timers are not running. then set t8 into single-pass mode (ctr0 d6), set t16 into sin- gle-pass mode (ctr2 d6), and set ping-pong mode (ctr1 d2, d3). these instructions do not have to be in any particular order. finally, start ping-pong mode by en- abling either t8 (ctr0 d7) or t16 (ctr2 d7). during ping-pong mode the enable bits of t8 and t16 (ctr0 d7, ctr2 d7) will be alternately set and cleared by hardware. the time-out bits (ctr0 d5, ctr2 d5) will be set every time the counter/timers reach the terminal count. figure 27. ping-pong mode enable tc8 time-out enable tc16 time-out ping-pong ctr1 d3,d2
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-37 1 to terminate ping-pong mode change transmit mode to normal mode (ctr1 d2, d3). notice that ping-pong mode is not actually stopped until one of the timer/counter's time-out. before the actual ter- mination of ping-pong mode, the user should not change the value of ctr0 or ctr2, except for resetting the time- out status bit. here is an example for terminating ping- pong mode safely: or ctr0,#%20 ;reset t8 time-out status bit loop_a: tm ctr0,#%20 jr z,loop_a ;wait until t8 times-out id ctr1,#00000000b ;change to normal mode or ctr2,#%20 ;reset t16 time-out status bit loop_b: tm ctr2,#%20 jr z,loop_b ;wait until t16 times-out ;now ping-pong mode is actually id ctr0,#00100000b ;terminated and user can re-program t8 id ctr2,#00100000b ;and t16 figure 28. t8_out and t16_out in ping-pong mode tc8h enable t8, t8_out switches to its initial value tc16h*256+tc16l t16_out toggles t8_out tc8h tc16h*256+tc16l t16_out t16_out t16_out switches to its initial value when tc16 is enabled t8_out toggles t8_out toggles
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-38 p r e l i m i n a r y ds97lvo0500 functional description (continued) figure 29. output circuit and/or/nor/nand logic t8_out ctr1 d5,d4 p34_internal ctr0 d0 p36_internal ctr1 d6 p35_internal ctr2 d0 p35_ext p36_ext p34_ext mux mux mux t16_out mux ctr1, d2 ctr1 d3
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-39 1 interrupts. the z86l7x has five different interrupts. the interrupts are maskable and prioritized (figure 30). the five sources are divided as follows: three sources are claimed by port 3 lines p33-p31, the remaining two by the counter/timers (table 3). the interrupt mask register glo- bally or individually enables or disables the five interrupt requests. figure 30. interrupt block diagram interrupt edge select irq register (d6, d7) irq 1, 3, 4 irq imr ipr priority logic 5 vector select irq0 irq2 global interrupt enable interrupt request
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-40 p r e l i m i n a r y ds97lvo0500 functional description (continued) when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder controlled by the interrupt priority register. an interrupt machine cycle is activated when an interrupt request is granted. this dis- ables all subsequent interrupts, saves the program counter and status flags, and then branches to the pro- gram memory vector location reserved for that interrupt. all z86l7x interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. an interrupt resulting from an1 (p31) is mapped into irq2, and an interrupt from an2 (p32) is mapped into irq0. in- terrupts irq2 and irq0 may be rising, falling, or both edge triggered, and are programmable by the user. the soft- ware can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6 . the configu- ration is shown in table 4. clock . the z86l7x on-chip oscillator has a high-gain, par- allel-resonant amplifier for connection to a crystal, lc, ce- ramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ohms. the z86l7x on-chip oscillator may be driven with a cost-effective rc network or other suitable external clock source. the crystal should be connected across xtal1 and xtal2 using the recommended capacitors (capacitance greater than or equal to 22 pf) from each pin to ground. the rc oscillator configuration is an external resistor con- nected from xtal1 to xtal2, with a frequency-setting ca- pacitor from xtal1 to ground (figure 8). table 3. interrupt types, sources, and vectors name source vector location comments irq0 /dav0, irq0 0, 1 external (p32), rising falling edge triggered irq1, irq1 2, 3 external (p33), falling edge triggered irq2 /dav2, irq2, t in 4, 5 external (p31), rising falling edge triggered irq3 t16 6, 7 internal irq4 t8 8, 9 internal table 4. irq register irq interrupt edge d7 d6 irq2 (p31) irq0 (p32) 00 f f 01 f r 10 r f 1 1 r/f r/f notes: f = falling edge r = rising edge in analog mode, the stop-mode recovery sources selected by the smr register are connected to the irq1 input. any of the stop-mode recovery sources for smr (except p31, p32, and p33) can be used to generate irq1 (falling edge triggered)
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-41 1 power-on reset (por). a timer circuit clocked by a ded- icated on-board rc oscillator is used for the power-on re- set (por) timer function. the por time allows v cc and the oscillator circuit to stabilize before instruction execu- tion begins. the por timer circuit is a one-shot timer triggered by one of three conditions: 1. power fail to power ok status. 2. stop-mode recovery (if d5 of smr = 1). 3. wdt time-out. the por time is a nominal 5 ms. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock, rc, lc oscillators). figure 31. oscillator con?uration xtal1 xtal2 c1 c2 c1 c2 c1 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 47 pf typ * f = 8 mhz lc c1, c2 = 22 pf l = 130 m h * f = 3 mhz * rc @ 3v vcc (typ) c1 = 33 pf * r = 1k * external clock l r * preliminary value including pin parasitics
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-42 p r e l i m i n a r y ds97lvo0500 functional description (continued) halt. halt turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external inter- rupts irq0, irq1, irq2, irq3, and irq4 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be exe- cuted (enabled) to exit halt mode. after the interrupt ser- vice routine, the program continues from the instruction af- ter the halt. stop. this instruction turns off the internal clock and ex- ternal crystal oscillation and reduces the standby current to 10 m a or less. stop mode is terminated only by a reset, such as wdt time-out, por, smr, or external reset. this causes the processor to restart the application program at address 000ch. in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. to do this, the user must execute a nop (opcode = ffh) immediately be- fore the appropriate sleep instruction, i.e., ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode port configuration register (pcon). the pcon regis- ter configures the comparator output on port 3. it is locat- ed in the expanded register file at bank f, location 00 (fig- ure 32). figure 32. port con?uration register (pcon) (write only) reserved (must be 1) d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h comparator output port 3 0 p34,standard output* 1 p34,comparator output * default setting after reset
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-43 1 comparator output port 3 (d0). bit 0 controls the com- parator used in port 3. a 1 in this location brings the com- parator outputs to p34 and p37, and a 0 releases the port to its standard i/o configuration. stop-mode recovery register (smr). this register se- lects the clock divide value and determines the mode of stop-mode recovery (figure 33). all bits are write only ex- cept bit 7, which is read only. bit 7 is a flag bit that is hard- ware set on the condition of stop recovery and reset by a power-on cycle. bits d2, d3, and d4, of the smr regis- ter, specify the source of the stop-mode recovery signal. bit d0 determines if sclk/tclk are divided by 16 or not. the smr is located in bank f of the expanded register group at address 0bh. figure 33. stop-mode recovery register d7 d6 d5 d4 d3 d2 d1 d0 smr (0f) 0b sclk/tclk divide-by-16 0 off 1 on reserved (must be 0) stop-mode recovery source 000 001 010 011 100 101 11 0 111 stop delay 0 off 1 on reserved 0 low reserved must be 0 stop flag 0 por 1 stop recovery * * * default setting after reset ** default setting after reset and stop-mode recovery ** * * * * por only reserved p31 p32 p33 p27 p2 nor 0-3 p2 nor 0-7
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-44 p r e l i m i n a r y ds97lvo0500 functional description (continued) figure 34. stop-mode recovery source p00 p32 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr d4 0 d3 0 d2 0 smr d4 0 d3 1 d2 0 smr d4 0 d3 1 d2 1 smr d4 1 d3 0 d2 0 smr d4 1 d3 0 d2 1 smr d4 1 d3 1 d2 0 smr d4 1 d3 1 d2 1 smr2 d4 0 d3 0 d2 0 smr2 d4 0 d3 1 d2 0 smr2 d4 0 d3 1 d2 1 smr2 d4 1 d3 0 d2 0 smr2 d4 1 d3 0 d2 1 smr2 d4 1 d3 1 d2 0 smr2 d4 1 d3 1 d2 1 smr2 d4 0 d3 0 d2 1 vcc p20 p32 p23 p20 p27 p31 p33 p31 p33 p32 p31 p33 p00 p07 p32 p31 p33 p07 p20 p32 p31 p33 p21 p22 smr2 d6 smr d6 to reset and wdt circuitry (active low) s1 s2 s3 s4 to irq1 (= 0)
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-45 1 sclk/tclk divide-by-16 select (d0). d0 of the smr controls a divide-by-16 prescaler of sclk/tclk. the pur- pose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop-mode recovery, this bit is set to a 0. stop-mode recovery source (d2, d3, and d4). these three bits of the smr specify the wake up source of the stop recovery (figure 36 and table 5). p33-p31 cannot wake up from stop mode if the input lines are configured as analog input. note: port pins defined as an output will drive the corre- sponding input to the default state to allow the remaining inputs to control the and/or function. refer to smr2 reg- ister for other recover sources. stop-mode recovery delay select (d5). this bit, if low, disables the 5 ms /reset delay after stop-mode recov- ery. the default configuration of this bit is one. if the "fast" wake up is selected, the stop-mode recovery source needs to be kept active for at least 5tpc. stop-mode recovery edge select (d6). a 1 in this bit po- sition indicates that a high level on any one of the recovery sources wakes the z86l7x from stop mode. a 0 indi- cates low level recovery. the default is 0 on por (figure 36). cold or warm start (d7). this bit is set by the device upon entering stop mode. it is a read only flag bit. a 1 in d7 (warm) indicates that the device will awaken from a smr source or a wdt while in stop mode. a 0 in this bit (cold) indicates that the device will be reset by a por, wdt while not in stop, or the device awakened a low voltage standby mode. stop-mode recovery register 2 (smr). this register determines the mode of the stop-mode recovery for smr2. if smr2 is used in conjunction with smr, either of the specified events will cause a stop-mode recovery. figure 35. sclk circuit table 5. stop-mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 0 0 1 reserved 0 1 0 p31 transition 0 1 1 p32 transition 1 0 0 p33 transition 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 smr, d0 ? 2 ? 16 osc sclk tclk
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-46 p r e l i m i n a r y ds97lvo0500 functional description (continued) figure 36. stop-mode recovery register 2 ((0f) 0dh: d2-d4: d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) 0dh reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only* 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p23, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level 0 low* 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events will cause a stop-mode recovery. *default setting after reset
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-47 1 watch-dog timer mode register (wdtmr). the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt must initially be en- abled by executing the wdt instruction and refreshed on subsequent executions of the wdt instruction. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source is selected with bit 4 of the wdt register. bit 0 and 1 control a tap circuit that determines the time-out period. bit 2 determines whether the wdt is ac- tive during halt and bit 3 determines wdt activity during stop. bits 5 through 7 are reserved (figure 37). this reg- ister is accessible only during the first 64 processor cycles (128 xtal clocks) from the execution of the first instruc- tion after power-on-reset, watch-dog reset, or a stop- mode recovery (figure 40). after this point, the register cannot be modified by any means, intentional or other- wise. the wdtmr cannot be read and is located in bank f of the expanded register group at address location 0fh. it is organized as follows: figure 37. watch-dog timer mode register (write only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (0f) 0f wdt tap int rc osc external clock 00 5 ms 256 tpc 01 10 ms 512 tpc 10 20 ms 1024 tpc 11 80 ms 4096 tpc wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-chip rc 1 xtal reserved (must be 0) * default setting after reset * * * *
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-48 p r e l i m i n a r y ds97lvo0500 functional description (continued) wdt time select (d0, d1). selects the wdt time period. it is configured as shown in table 6. wdtmr during halt (d2). this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt. the default is 1. wdtmr during stop (d3). this bit determines whether or not the wdt is active during stop mode. since the xtal clock is stopped during stop mode, the on-board rc has to be selected as the clock source to the wdt/por counter. a 1 indicates active during stop. the default is 1. clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscil- lator is bypassed and the por and wdt clock source is driven from the external pin, xtal1. the default configu- ration of this bit is 0, which selects the rc oscillator. table 6. wdt time select d1 d0 time-out of internal rc osc time-out of xtal clock 0 0 5 ms min 256 tpc 0 1 10 ms min 512 tpc 1 0 20 ms min 1024 tpc 1 1 80 ms min 4096 tpc notes: 1. tpc = xtal clock cycle. 2. the default on reset is 10 ms.
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-49 1 figure 38. resets and wdt clk 18 clock reset generator reset * /clr 2 wdt tap select internal rc osc. clk */clr1 por wdt1 234 low operating voltage det. internal reset active high ck source select (wdtmr) xtal vdd vbo/vlv 2v ref. from stop mode recovery source wdt stop delay select (smr) 12 ns glitch filter + - 5 clock filter wdt/por counter chain m u x /reset * /clr1 and /clr2 enable the wdt/por and 18 clock reset timers upon a low to high input transition. vcc
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-50 p r e l i m i n a r y ds97lvo0500 functional description (continued) low voltage detection/protection. an on-chip voltage comparator checks that the v cc is at the required level for correct operation of the device. reset is globally driven when v cc falls below v lv (vrf1). mask selectable options. there are six mask selectable options to choose from based on rom code require- ments. note: internal port 0/pull-up resistors remain connected when port pins are configured as outputs. the low voltage trip voltage (v lv ) is less than 2.1v under the following conditions: maximum (v lv ) conditions: t a = 0 c, +55 c internal clock frequency equal to or less than 4.0 mhz note: the internal clock frequency is one-half the external clock frequency. the device is guaranteed to function normally until the low voltage protection trip point v lv is reached, below which reset is globally driven. the device is guaranteed to func- tion normally at supply voltages above the v lv trip point for the temperatures and operating frequencies in maximum v lv conditions. the actual v lv trip point is a function of temperature and process parameters (figure 39). permanent watch-dog timer on/wdt command invoked ram protect on/off rom protect on/off 32 khz xtal on/off port 00-07 pull-ups on/off port 31-33 pull-ups on/off port 20-27 pull-ups on/off figure 39. typical z86l7x low voltage vs temperature at 8 mhz 0 15 25 35 45 55 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 vlv vlv temperature
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-51 1 expanded register file control registers (0d) figure 40. tc8 control register ((0d) 0h: read/write except where noted) d7 d6 d5 d4 d3 d2 d1 d0 ctr0 (0d) 0h 0 p34 as port output 1 timer8 output 0 disable t8 time out interrupt 1 enable t8 time out interrupt 0 disable t8 data capture interrupt 1 enable t8 data capture interrupt 00 sclk on t8 01 sclk/2 on t8 10 sclk/4 on t8 11 sclk/8 on t8 r 0 no t8 counter time out r 1 t8 counter time out occured w 0 no effect w 1 reset flag to 0 * default setting after reset 0 modulo-n 1 single pass r 0 t8 disabled * r 1 t8 enabled w 0 stop t8 w 1 enable t8
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-52 p r e l i m i n a r y ds97lvo0500 figure 41. t8 and t16 common control functions ((0d) 1h: read/write) d7 d6 d5 d4 d3 d2 d1 d0 ctr1 (0d) 1h 0 t16_out is 0 initially 1 t16_out is 1 initially r/w r r w w 0 no falling edge detection 1 falling edge detection 0 no effect 1 reset flag to 0 0 t8_out is 0 initially 1 t8_out is 1 initially 0 no rising edge detection 1 rising edge detection 0 0 normal operation 0 1 ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 transmit mode/t8/t16 logic 0 0 falling edge detection 0 1 rising edge detection 1 0 both edge detection 1 1 reserved 0 p36 as port output * 1 p36 as t8/t16_out 0 transmit mode * 1 demodulation mode 0 0 no filter 0 1 4 sclk cycle filter 1 0 8 sclk cycle filter 1 1 16 sclk cycle filter demodulation mode transmit mode transmit mode r/w demodulation mode r r w w transmit mode demodulation mode 0 0 and 0 1 or 1 0 nor 1 1 nand demodulation mode transmit mode 0 p31 as demodulator input 1 p20 as demodulator input demodulation mode transmit/demodulation modes 0 no effect 1 reset flag to 0 note: care must be taken in differentiating transmit mode from demodulation mode. depending on which of these two modes is operating, the ctr1 bit will have different functions. *note: changing from one mode to another cannot be done without disabling the counter/timers.
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-53 1 figure 42. t16 control register ((0d) 2h: read/write except where noted) d7 d6 d5 d4 d3 d2 d1 d0 ctr2 (0d) 02h 0 p35 is port output 1 p35 is tc16 output 0 disable t16 time-out interrupt 1 enable t16 time-out interrupt 0 0 sclk on t16 0 1 sclk/2 on t16 1 0 sclk/4 on t16 1 1 sclk/8 on t16 * default setting after reset 0 disable t16 data capture interrupt 1 enable t16 data capture interrupt r 0 no t16 time out r 1 t16 time out occurs w 0 no effect w 1 reset flag to 0 0 modulo-n for t16 1 single pass for t16 r 0 t16 disabled * r 1 t16 enabled w 0 stop t16 w 1 enable t16 transmit mode 0 t16 recognizes edge 1 t16 does not recognize edge demodulator mode
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-54 p r e l i m i n a r y ds97lvo0500 expanded register file control registers (0d) (continued) figure 43. stop-mode recovery register ((f) 0bh: d6-d0 = write only, d7 = read only) d7 d6 d5 d4 d3 d2 d1 d0 smr (f) 0b sclk/tclk divide-by-16 0 off 1 on reserved (must be 0) stop-mode recovery source 000 001 010 011 100 101 11 0 111 stop delay 0 off 1 on reserved (must be 0) stop flag 0 por 1 stop recovery** * default setting after reset ** default setting after reset and stop-mode recovery ** * * por only reserved p31 p32 p33 p27 p2 nor 0-3 p2 nor 0-7
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-55 1 figure 44. stop-mode recovery register 2 ((0f) 0dh: d2-d4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) 0dh reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only* 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p23, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level 0 low* 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events will cause a stop-mode recovery. *default setting after reset
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-56 p r e l i m i n a r y ds97lvo0500 expanded register file control registers (0d) (continued) figure 45. watch-dog timer mode register ((f) ofh: write only) figure 46. port con?uration register (pcon) ((0f) oh: write only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (0f) 0f wdt tap int rc osc external clock 00 5 ms 256 tpc 01 10 ms 512 tpc 10 20 ms 1024 tpc 11 80 ms 4096 tpc wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-chip rc 1 xtal reserved (must be 0) * default setting after reset * * * * reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 pcon (0f) 00h comparator output port 3 0 p34,standard output* 1 p34,comparator output * default setting after reset
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-57 1 z8 standard control register diagrams figure 47. port 3 mode register (f7h: write only) figure 48. port 0 and 1 mode register (f8h: write only) d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 open drain* 1 port 2 push-pull 0 p32 = input p35 = output ** 1 p32 = /dav0/rdy0 p35 = rdy0//dav0 0 p31 = input (tin) p36 = output (tout) 1 p31 = /dav2/rdy2 p36 = rdy2//dav2 0 = p31, p32 digital mode 1 = p31, p32 analog mode 00 p33 = input p34 = output ** 01 p33 = input 10 p34 = /dm p33 = /dav1/rdy1 p34 = rdy1//dav1 11 * default setting after result note: d0 affects p34, p35 as well as port 2. reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p00-p03 mode 00 output 01 input* 1x a11-a8 stack selection 0 external 1 internal* reserved (must be 0) p07-p04 mode 00 output 01 input* 1x a15-a12 external memory timing 0 normal* 1 extended * default setting after reset. note: only p00 and p07 are available on z86l71. figure 49. port 2 mode register (f8h: write only) figure 50. interrupt priority register ((0) f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p27-p20 i/o definition 0 defines bit as output 1 defines bit as input* r246 p2m *default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c>a>b 010 a>b>c 011 a>c>b 100 b>c>a 101 c>b>a 110 b>a>c 111 reserved irq1,irq4,priority (group c) 0 irq1>irq4 1 irq4>irq1 irq0,irq2 priority (group b) 0 irq2>irq0 1 irq0>irq2 irq3,irq5priority (group a) 0 irq5>irq3 1 irq3>irq5 reserved (must be 0)
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-58 p r e l i m i n a r y ds97lvo0500 figure 51. interrupt request register ((0) fah: read/write) figure 52. interrupt mask register ((0) fbh: read/write) figure 53. flag register ((0) fch: read/write) d7 d6 d5 d4 d3 d2 d1 d0 r250 irq inter edge p31 p32 = 00 p31 p32 - = 01 p31 - p32 = 10 p31 - p32 - = 11 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16_out irq4 = t8_out reserved (must be 0) default setting after reset = 0000 0000 d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) 1 enables irq4-irq0 (d0 = irq0) 0 master interrupt disable* 1 master interrupt enable r251 imr * default setting after reset reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow tag sign flag zero flag carry flag r252 flags figure 54. register pointer ((0) fdh: read/write) figure 55. stack pointer high ((0) feh: read/write) figure 56. stack pointer low ((0) ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 expanded register pointer working register pointer r253 rp default setting after reset = 0000 0000 d7 d6 d5 d4 d3 d2 d1 d0 stack pointer upper byte (sp15-sp8) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp7-sp0) r255 spl
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-59 1 package information figure 57. 18-pin dip pin assignments figure 58. 20-pin dip pin assignments
z86l70/71/75/c71 ir/low-voltage microcontroller zilog 1-60 p r e l i m i n a r y ds97lvo0500 figure 59. 18-pin soic pin assignments figure 60. 20-pin soic pin assignments
z86l70/71/75/c71 zilog ir/low-voltage microcontroller ds97lvo0500 p r e l i m i n a r y 1-61 1 ordering information z86l70/71/75/c71 8.0 mhz 18-pin dip 20-pin dip z86l7008psc z86l7108psc z86l7508psc 18-pin soic 20-pin soic z86l7008ssc z86l7108ssc z86l7508ssc 16.0 mhz 20-pin dip Z86C7116PSC codes package p = plastic dip s = soic (small outline chip carrier) temperature standard = 0 c to +70 c environmental c = plastic standard ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com example: z 86l71 08 p s c environmental flow temperature package speed product number zilog prefix is a z86l71, 8 mhz, dip, 0 c to +70 c, plastic standard flow

▲Up To Search▲

Price & Availability of Z86C7116PSC

	To Download Z86C7116PSC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .