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? semiconductor components industries, llc, 2010 july, 2010 ? rev. 3 1 publication order number: NCP4302/d NCP4302 secondary side synchronous flyback controller the NCP4302 is a full featured controller and driver that provide all the control and protection functions necessary for implementing a synchronous rectifier operation in a flyback converter. with the use of the NCP4302, the space conscious flyback applications such as adaptors, chargers, set top boxes can achieve significant efficiency improvements at minimal extra cost. in addition to the synchronous rectifier control, the ic incorporates an accurate tl431 type shunt regulator, current monitoring circuit and optocoupler driver to provide a single ic secondary solution. the NCP4302 works with any type of flyback topology (continuous mode, quasi ? resonant mode or discontinuous mode) ? providing a high level of versatility. features ? self ? contained control of synchronous rectifier in ccm, dcm, and qr flyback applications ? interface to external signal for ccm mode ? true secondary zero current detection ? high gate drive currents (2.5 a source/sink) ? high voltage operation ? current sense flexibility (mosfet r ds(on) or cs resistor) ? accurate low voltage reference ? NCP4302a 2.55 v, 1% ? NCP4302b 1.275 v, 1% ? programmable independent secondary side t on and t off delays ? maximum frequency of operation up to 250 khz ? these are pb ? free devices typical applications ? notebook adapters ? lcd tv adapters ? consumer appliances such as dvd, vcr ? power over ethernet applications (ip phones, wireless access points) ? battery chargers pin configuration 1 sync/cs 8 v cc 2 trig 3 cath 4 v ref 7 drv 6 gnd 5 d lyadj (top view) so ? 8 d suffix case 751 1 8 http://onsemi.com device package shipping ? ordering information NCP4302adr2g so ? 8 (pb ? free) 2500/tape & reel marking diagram x = reference voltage (a or b) a = assembly location l = wafer lot y = year w = work week = pb ? free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 4302x alyw 1 8 NCP4302bdr2g so ? 8 (pb ? free) 2500/tape & reel
NCP4302 http://onsemi.com 2 pin description pin number symbol description 1 sync/cs connected to the flyback winding. the current on this pin is sensed and used to turn on the synchronous rectification mosfet (srfet). this pin is also used to sense the zero crossing of the mosfet current either using the r ds(on) of the srfet or using an external current sense resistor connected between drain of the srfet and the flyback winding. 2 trig input pin for direct turn ? off of the mosfet. typically connected to a signal from primary controller (for ccm mode) or a signal derived from the transformer (for qr mode). has very short propagation delay to output (<50 ns). 3 cath feedback compensation pin for the tl431 shunt regulator. has the capability to sinking 10 ma of opto current. 4 v ref output voltage feedback through resistive divider connected to this pin. regulated at 1.28 v (option b) or 2.55 v (option a). 5 d lyadj a resistive divider between the power supply output and ground with the center point tied to the d lyadj input pin allows for independent adjustment of the minimum t on and t off delay time. the maximum extern- al capacitance from this pin to ground is 25 pf. 6 gnd return pin for the controller ? connected to the output return. 7 drv drive output for external mosfet ? 2.5 a peak drive capability, internally clamped to 13.5 v (maximum) 8 v cc bias voltage for the controller. maximum voltage is 28 v. maximum ratings rating symbol value unit power supply input current v cc i cc ? 0.3 to 28 100 v ma drive voltage current v drv ? 0.3 to 18 100 v ma drive current source sink i drv 2.5 ? 2.5 apk analog and logic inputs trig, v ref , d lyadj ? 0.3 to 10 100 v ma maximum voltage current sync/cs ? 10 to 95 100 v ma operating junction temperature range t j ? 40 to 125 c maximum junction temperature t jmax 150 c storage temperature range t smax ? 65 to 150 c lead temperature (soldering, 10 s) t lmax 300 c reference input current, continuous i ref ? 0.05 to 10 ma total power dissipation p d 225 mw thermal resistance junction ? to ? ambient ja 178 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pin 1 ? 8: human body model 2000 v per mil ? std ? 883, method 3015. machine model method 200 v 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78
NCP4302 http://onsemi.com 3 figure 1. block diagram uv v cc cath v ref v cc drv drv gnd sync/cs d lyadj trig 10 v 10 v t on and t off ramp i discharge i charge cs in cs out cs v cc mngt. uvlo on 10.4 v uvlo off 9.2 v 95 v dlyton dlyoff t on and t off comparators discharge enable charge enable 10 pf cdelay uv 30 v reset dominant 30 v 10 v uv tl431 s r q q s r q q
NCP4302 http://onsemi.com 4 figure 2. typical application ncp1230 8 5 6 4 2 1 3 hv drv vcc gnd fb pfc_vcc cs cath trig +vdc vout sync/cs gnd drv j2 vcc + + d lyadj vout v ref
NCP4302 http://onsemi.com 5 electrical characteristics (v cc = 19 v, sync frequency = 100 khz, v ref = v ka (i ka = 1 ma), r s = 75 ohms, v trig = gnd, c drv = 1 nf, r dlyadj = 30.1 k, v dlyadj = 2.0 v, for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, unless otherwise noted) rating test conditions symbol min typ max unit v cc start ? up threshold v cc , sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v v cc(on) 9.6 10.4 11.2 v stop threshold v cc , sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v v cc(off) 8.5 9.2 ? v v cc shutdown hysteresis v cc(on) ? v cc(off) v cc(hys) 0.9 1.2 1.4 v supply current after turn ? on no ? load on drv pin, sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v i cc1 ? 2.7 5.6 ma supply current after turn ? on sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v i cc2 ? 3.6 7.5 ma drive output output voltage rise ? time 10 ? 90% of the output signal sync/ cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v t r ? ? 40 ns output voltage fall ? time 10 ? 90% of the output signal sync/ cs = 0 to ? 0.5 v, 100 khz, 5 s pulse, trig = 0 v t f ? ? 40 ns output source current (note 3) i drv(source) ? 2.5 ? apk driver high level output voltage i source = 200 ma, sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v, v cc = 12 v v drv(h) 6.5 9.5 ? v output sink current (note 3) i drv(sink) ? 2.5 ? apk driver output low level output voltage i sink = 200 ma, sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v, v cc = 12 v v drv(l) ? 160 500 mv drive voltage internal clamp v cc = 28 v, sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v, drvpin = 10 k v drv(clmp) ? ? 17 v minimum drive output voltage v cc = v cc(off) + 200 mv, drv pin = 10 k + 1 nf, sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v v drv(min) 5.5 6.5 ? v sync/cs the total propagation delay from sync/cs to the drv output sync/cs = +0.5 v to ? 0.5 v 100 khz, 5 s pulse, (trig = 0 v)(refer to the drive output specifications for tr 50% of the output signal t p1 ? 70 135 ns zero current detection v sync/cs < ? 30 mv is(zcd) 50 230 450 a current sense pin offset voltage at zero current level (note 3) vs(zcd) ? 30 ? ? mv sync/cs leakage current v sync/cs = 95 v scs leakage ? ? 10 a trigger section minimum trigger pulse duration sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig trig ? pw 75 ? ? ns 3. guaranteed by design
NCP4302 http://onsemi.com 6 electrical characteristics (v cc = 19 v, sync frequency = 100 khz, v ref = v ka (i ka = 1 ma), r s = 75 ohms, v trig = gnd, c drv = 1 nf, r dlyadj = 30.1 k, v dlyadj = 2.0 v, for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, unless otherwise noted) rating unit max typ min symbol test conditions trigger section trigger pulse voltage for gate turn ? off sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig vtrig 2.0 ? 4.0 v propagation delay from trig to drv turn ? off c drv = no ? load, sync/cs= ? 0.5 v 100 khz, 5 s pulse, trig = 0 ? 5 v t p2 ? 25 85 ns tl431 characteristics reference input voltage i ka = 5 ma, v ka = v ref NCP4302a t j = +25 c t j = ? 40 c to +125 c v ref 2.525 2.499 2.55 ? 2.575 2.60 v reference input voltage (i k = 5 ma, v ka = v ref ) NCP4302b t j = +25 c t j = ? 40 c to +125 c v ref 1.262 1.249 1.275 ? 1.288 1.301 v reference input current i ka = 10 ma i ref ? 0.0018 4.0 a minimum cath current for regulation i source 0 to 1 ma i ka ? 0.5 1.0 ma reference voltage line regulation v ka = v ccon ? 16 v, i ka = 1 ma v ka ? 2.0 5.0 mv/v v ref v ka off ? state cath current v ka = 18 v, v ref = 0 v (test circuit 2, v ref pin grounded) i off ? 11 20 a dynamic impedance v ka = v ref , i ka = 1 ma to 10 ma z ka ? 0.62 1.5 the maximum sink current capability (i source 0 to 10 ma) isinkmax 10 ? ? ma adjustable time delay the t on time delay sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v cd lyadj internal = 10 pf (vs = 2.0 v, rth = 30.1 k ) t on(delay) 1.0 1.4 1.8 s the min and max t on(delay) range (note 3) * r2 = 190 k , r3 = 57 k * r2 = 499 k , r3 = 39 k (*see figure 27) t on(range) 0.45 ? ? ? ? 2.0 s the maximum and minimum input voltage operating range. (note 3) the maximum capacitance from pin 5 to ground is 25 pf. vin dlyadj 1.5 ? 4.5 v the maximum and minimum input operating current into the d lyadj pin (note 3) iin dlyadj 9 ? 200 a the t off time delay sync/cs = 0 to ? 0.5 v 100 khz, 5 s pulse, trig = 0 v cd lyadj internal = 10 pf (vs = 2.0 v, rth = 30.1 k) t off(delay) 2.8 3.8 4.8 s the min and max t off(delay) range (note 3) r2 = 66 k, r3 = 23.6 k * r2 = 408 k, r3 = 32.4 k (*see the schematic below) t off(range) 0.8 ? ? ? ? 4.6 s 3. guaranteed by design
NCP4302 http://onsemi.com 7 typical characteristics figure 1. v cc(on) threshold vs. junction temperature figure 2. v cc(off) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) figure 3. v cc(hys) vs. junction temperature figure 4. internal current consumption at no load vs. junction temperature t j , junction temperature ( c) figure 5. supply current consumption with 1 nf load vs. junction temperature figure 6. drive output rise time vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) v cc(on) , voltage threshold (v) v cc(off) , voltage threshold (v) i cc1 , supply current (ma) i cc2 , supply current (ma) t rise , output voltage rise time (ns) t j , junction temperature ( c) v cc(hys) , shutdown hysteresis (v) 10.2 10.3 10.4 10.5 10.6 ? 50 ? 25 0 25 50 75 100 125 150 v trig = 0 v 9.0 9.1 9.2 9.3 9.4 ? 50 ? 25 0 25 50 75 100 125 150 v trig = 0 v 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 ? 50 ? 25 0 25 50 75 100 125 150 v trig = 0 v 1.50 1.90 2.30 2.70 3.10 ? 50 ? 25 0 25 50 75 100 125 150 v cc = 19 v c drv = no load 2.40 2.80 3.20 3.60 4.00 4.40 ? 50 ? 25 0 25 50 75 100 125 150 v cc = 19 v c drv = 1 nf 0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 ? 50 ? 25 0 25 50 75 100 125 150 c drv = 1 nf
NCP4302 http://onsemi.com 8 typical characteristics figure 7. drive output fall ? time vs. junction temperature figure 8. driver v out high vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) figure 9. driver v out low vs. junction temperature figure 10. v gate clamp vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) figure 11. v out(min) vs. junction temperature figure 12. t p1 propagation delay, sync/cs to drive vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) t fall , output voltage fall time (ns) v drv(h) , driver output high voltage (v) v drv(l) , driver output low voltage (v) v drv(clmp) , drive voltage internal clamp (v) v drv(min) , minimum drive output voltage (v) t p1 , propagation delay from sync to drive output (ns) 0 5.0 10.0 15.0 20.0 25.0 ? 50 ? 25 0 25 50 75 100 125 150 c drv = 1 nf 8.0 8.5 9.0 9.5 10.0 10.5 ? 50 0 50 100 150 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 ? 50 ? 25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 ? 50 ? 25 0 25 50 75 100 125 150 v cc = 28 v 4.0 5.0 6.0 7.0 8.0 9.0 10 ? 50 ? 25 0 25 50 75 100 125 150 v cc = v cc(off) + 200 mv load = 10 k + 1 nf 50 55 60 65 70 75 80 85 90 ? 50 ? 25 0 25 50 75 100 125 150 c load = 1 nf
NCP4302 http://onsemi.com 9 typical characteristics figure 13. zero current detect i source vs. junction temperature t j , junction temperature ( c) figure 14. trigger pulse voltage for gate turn ? off vs. junction temperature figure 15. t p2 propagation delay trig in to drive off, no load vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) figure 16. 2.55 v reference (option a) voltage vs. junction temperature figure 17. 2.55 v reference input current vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) i s(zcd) , zero current detection current ( a) v trig , trigger pulse voltage for gate turn ? off (v) t p2 , propagation delay from trig to drv turn ? off(ns) v ref , reference voltage (v) i ref , reference input current (na) figure 18. 2.55 v reference minimum cathode current for regulation vs. junction temperature t j , junction temperature ( c) i ka , minimum cath current for regulation ( a) 50 100 150 200 250 300 ? 50 ? 25 0 25 50 75 100 125 150 2.8 2.9 3.0 3.1 3.2 ? 50 ? 25 0 25 50 75 100 125 150 20 30 40 50 60 70 80 90 ? 50 ? 25 0 25 50 75 100 125 150 2.40 2.45 2.50 2.55 2.60 ? 50 ? 25 0 25 50 75 100 125 150 i source = 5 ma 0 5.0 10 15 20 25 30 35 40 ? 50 ? 25 0 25 50 75 100 125 150 120 130 140 150 160 170 ? 50 ? 25 0 25 50 75 100 125 150
NCP4302 http://onsemi.com 10 typical characteristics figure 19. 2.55 v reference line regulation vs. junction temperature t j , junction temperature ( c) figure 20. 2.55 v reference off ? state cathode current vs. junction temperature figure 21. 2.55 v reference dynamic impedance vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) figure 22. 1.275 v reference voltage (option b) vs. junction temperature figure 23. t on delay vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) v ka , reference voltage line regulation (mv/v) i off , off ? state cath current ( a) z ka , dynamic impedance (m ) v ref , reference voltage (v) t on(delay) , on time delay ( s) figure 24. t off delay vs. junction temperature t j , junction temperature ( c) t off , off time delay ( s) 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 ? 50 ? 25 0 25 50 75 100 125 150 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 ? 50 ? 25 0 25 50 75 100 125 150 300 400 500 600 700 800 900 1000 ? 50 ? 25 0 25 50 75 100 125 150 1.22 1.23 1.24 1.25 1.26 1.27 1.28 ? 50 ? 25 0 25 50 75 100 125 150 i source = 5 ma 1.25 1.30 1.35 1.40 1.45 1.50 1.55 ? 50 ? 25 0 25 50 75 100 125 150 3 3.5 4 4.5 5 5.5 ? 50 ? 25 0 25 50 75 100 125 150
NCP4302 http://onsemi.com 11 detailed operating description the NCP4302 is designed to operate either as a standalone ic or as a companion ic to a primary side controller to help achieve efficient synchronous rectification for flyback converter systems. it has high current gate driver along with fast logic circuitry to provide appropriately timed drive signals to a synchronous mosfet used for output rectification in a flyback converter. with its novel architecture, the NCP4302 has enough versatility to increase the synchronous rectification efficiency under any operating mode without requiring too much complexity. supply section the NCP4302 works from an available bias supply that can range from 10.4 v to 28 v (typical). this allows direct connection to the output voltage of many adapters such as notebook and lcd tv adapters. as a result, the NCP4302 simplifies circuit operation compared to other devices which require specific bias power supplies (e.g. 5 v). the high voltage capability of the v cc is also a unique feature designed to allow operation across a broader range of applications. to prevent gate signal from operating under inadequate bias conditions, the NCP4302 features a uvlo circuit that turns on at 10.4 v (v cc rising) typical and turns off at 9.2 v typical (v cc falling). gate drive section the NCP4302 features high current gate drivers delivering up to (>2.5 a peak) to achieve fast turn ? on and turn ? off requirements in a synchronous rectifier. having a high gate drive current enables fast turn ? on when sync/cs signal is received (to minimize body diode conduction at the peak of the current waveform) and fast turn ? off when zero current or a trig signals are received (to prevent current reversal or cross conduction). the higher sink current also allows the mosfet to be kept of f during the instances when there is high dv/dt on the drain. the gate voltage is clamped at 13.5 v typical to prevent larger excursion of gate voltage than needed when v cc is operating from a 28 vdc output. the propagation delays through the logic circuits and the gate drivers are kept at a minimum as shown in the specification table. sync/cs input in a synchronous rectification application after the primary side mosfet is turned ? off, the current in the secondary of the flyback transformer initially flows through the synchronous rectification mosfet?s internal body diode. when this occurs, the drain of the mosfet will be ? 0.5 to ? 1.0 v negative with respect to ground (the vf of the internal body diode) and the NCP4302 current sense differential amplifier will output a 230 a current (typical). this current detection method is used by the NCP4302 to determine when current is flowing in the secondary of the transformer and the synchronous rectification mosfet needs to be turned ? on. the zero current detec tion senses the current with a slight negative offset so that the switch turn ? off occurs without reversal of the current. figure 25. input current sense vout cout 75 mirror current sense amplifier to reset dominant flip ? flop adjustable t on delay the sync/cs input to the NCP4302 is used as a reset (through logic) input to the drive enable flip flop; refer to the internal block diagram of the NCP4302. when current flows in the secondary of the flyback transformer any parasitic inductance due to printed wiring board traces, or component lead can cause the voltage at the sync/cs input to ring above ground (refer to figure 26). this ringing may cause the c ontroller dive output to turn ? off. to eliminate this problem the NCP4302 has a programmable t on time which blanks the secondary voltage ringing by adding a minimum controller drive on time. figure 26. discontinuous conduction mode drain waveform time v(u1:4) 0 v 12.5 v 25.0 v 37.5 v 45.0 v 120 s 110 s 100 s 90 s 80 s 70 s 60 s synchronous mosfet drain voltage (v)
NCP4302 http://onsemi.com 12 the minimum on time is set with a voltage divider with resistors r2 and r3 (refer to figure 27). i in v out r3 r3 r2 0.7 1 rth where rth is the thevenin equivalent resistance and is calculated by: rth 1 1 r3 1 r2 this input current is then used to charge an internal 10 pf capacitor setting the minimum t on time. t on(delay) 10 pf 4v i in trig rs sync/cs drv r3 cath gnd r2 figure 27. typical application + c out r lower r upper v out v cc i in d lyadj v ref adjustable t off delay the sync/cs input to the NCP4302 is used as the set input to the drive enable flip flop; refer to the internal block diagram of the NCP4302. refering to the spice simulations (figure 28), you can see that when the system is operating under light load conditions the transformer secondary voltage rings below ground when the current reaches zero. when this occurs, the cs amplifier output may be falsely triggered providing a set input to the drive flip flop, turning on the output drive. to prevent the controller from prematurely turning on the synchronous rectification mosfet, the output of the current sense amplifier is connected to a logic block with a programmable off time delay. the t off(delay) can be independently programmed through the d lyadj pin. i in v out r3 r3 r2 0.7 1 100k t off(delay) 10 pf 3.35 v i in figure 28. discontinuous conduction mode drain waveform time v(u1:4) ? 50 v 0 v 50 v 100 v 160 s 150 s 140 s 130 s 120 s 110 s 100 s synchronous mosfet drain voltage (v) trigger input the trig input is used to turn ? off the synchronous mosfet prior to its current reaching zero. this input is required in a ccm operating mode. while there are several ways to determine the trig input, the simplest way is to generate a pulse in the primary side that precedes the turn ? on of the primary mosfet and transformer couple that pulse to the secondary into the trig input. in converters where the operating mode is always designed to be dcm or qrm, the trig input is not used. it is recommended to ground the trig pin in these cases. voltage amplifier and reference the NCP4302 incorporates an accurate tl431 type shunt regulator with two reference voltage options. the NCP4302a has a 2.5 v reference and the NCP4302b has a 1.25 v reference.
NCP4302 http://onsemi.com 13 figure 29. typical secondary side regulator tx1 r bias c out r lower r upper r comp c comp tl431 when the tl431 is being used to regulate the output of a power supply it is typically configured as shown in figure 29. where the output from the power supply is sensed and divided down with a resistive divider made up of r upper and r lower . the center point of the divider is connected to the reference pin of the NCP4302. the divider ratio scales down the output voltage to match the reference voltage, 2.5 v or 1.25 v. v ref v out r lower r lower r upper the r bias resistor in figure 29 sets the current through the tl431, which must be greater than 0.5 ma to guarantee its performance under all operating conditions. figure 30. synchronous rectifier v in v out c out ss ssd sp using synchronous rectification for a flyback converter to operate correctly with synchronous rectification there must be a delay between the time when the primary side mosfet (sp figure 30) and the secondary side synchronous rectification mosfets (ss figure 29) are conducting current. the NCP4302 can operate in ccm, crm, or qr modes. the next sections cover the losses associated for each of the three operating modes. discontinuous conduction mode the basic switching waveforms for the flyback converter operating in dcm are shown in figure 31. when the primary side mosfet (sp in figure 30) is turned ? on current flows is the transformer primary and ramps up from zero to i peak . when the primary side mosfet (sp) turns ? off, the polarity of the transformer reverses and the energy stored in the transformer is transferred to the secondary. when the energy transfer from the transformer primary to the transformer secondary begins, (prior to the secondary side synchronous mosfet turning ? on) the secondary current flows through the internal body diode synchronous rectifiers mosfets (ss) and (ssd). to minimize the losses in the ssd, the propagation delay (t p1 ) must be low . otherwise, there will be high losses associated with the secondary peak current and the ssd forward voltage drop (NCP4302 has a typical propagation delay of 50 ns). p tsecondary p on p sw p diode (eq. 1) i out i sec,pk 2 (1 d on ) (eq. 2) i sec,rms i sec,pk 1 d on 3 (eq. 3) combining equations 2 and 3, i sec,rms 2 4 i out 2 3 (1 d on ) (eq. 4) p on 4 i out 2 3 (1 d on ) r ds(on) (eq. 5) p sw 1 2 c oss v s 2 f (eq. 6) p diode v f i out t delay (eq. 7) where: i out is the dc output current v f is d is the duty cycle r ds(on) is the on resistance of the mosfet v s v in n v out n is the transformer turns ratio t delay is the delay from the sync to the drive output
NCP4302 http://onsemi.com 14 discontinuous condition mode figure 31. discontinuous conduction mode waveforms sp drv i prm i sec,pk sync drv t p1 i pk ? diode conduction time t p1 is the propagation delay from the sync/cs input to the drive output. continuous conduction mode when operating in continuous conduction mode (ccm) the current in the secondary doesn?t fall to zero prior to turning on the primary side mosfet. to eliminate cross conduction losses (have the primary side mosfet and secondary side mosfet on at the same time) the trigger input to the NCP4302 must be utilized. a signal which leads the primary side (sp) mosfet turning on must be coupled to the trig input of the NCP4302 which will turn ? off the ss mosfet referring to figure 32. when the energy transfer begins in the transformer secondary, prior to the secondary side synchronous mosfet turning ? on, the secondary current flows through the synchronous rectifiers mosfet?s (ss) internal body diode (ssd). to minimize the power loss in the internal body the controller propagation delay has been minimized in the NCP4302. trig sync drv i sec i peak t delay1 sp drv figure 32. continuous conduction mode waveforms body ? diode conduction time i vally i peak,sec t delay2 p sync p on p qrr p d p pp off (eq. 8) i sec,rms i sec,peak i l sec 2 1 d (eq. 9) (eq. 10) i sec,rms 2 i sec,peak i l sec 2 2 1 d combining equations 9 and 10, il sec v out v f lm n 2 (1 d)t (eq. 11) p on i sec,rms 2 r ds(on) (eq. 12) p qrr q rr v out v in n f (eq. 13) p body_diode v f i out f (t delay1 td delay2 ) (eq. 14) p off 1 2 c oss v out v in n 2 f (eq. 15) q rr is the recovery charge of the internal body diode coss is the mosfet drain to source capacitance l m is the transformer primary inductance
NCP4302 http://onsemi.com 15 figure 33. i sec,pk i out i l i lsec
NCP4302 http://onsemi.com 16 package dimensions soic ? 8 nb suffix case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NCP4302/d the product described herein (NCP4302), may be covered by the following u.s. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,22 1. there may be other patents pending. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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