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| Datasheet File OCR Text: |
| this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. june 2014 docid026289 rev 1 1/137 stm32f411xc stm32f411xe arm ? cortex ? -m4 32b mcu+fpu, 125 dmips, 512kb flash, 128kb ram, usb otg fs, 11 tims, 1 adc, 13 comm. interfaces datasheet - preliminary data features ? dynamic efficiency line ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 100 mhz, memory protection unit, 125 dmips/1.25 dmips/mhz (dhrystone 2.1), and dsp instructions ? memories ? up to 512 kbytes of flash memory ? 128 kbytes of sram ? clock, reset and supply management ? 1.7 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? power consumption ? run: 100 a/mhz (peripheral off) ? stop (flash in stop mode, fast wakeup time): 42 a typ @ 25c; 65 a max @25 c ? stop (flash in deep power down mode, fast wakeup time): down to 10 a @ 25 c; 30 a max @25 c ? standby: 2.4 a @25 c / 1.7 v without rtc; 12 a @85 c @1.7 v ?v bat supply for rtc: 1 a @25 c ? 112-bit, 2.4 msps a/d converter: up to 16 channels ? general-purpose dma: 16-stream dma controllers with fifos and burst support ? up to 11 timers: up to six 16-bit, two 32-bit timers up to 100 mhz, each with up to four ic/oc/pwm or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window) and a systick timer ? debug mode ? serial wire debug (swd) & jtag interfaces ? cortex ? -m4 embedded trace macrocell? ? up to 81 i/o ports with interrupt capability ? up to 78 fast i/os up to 100 mhz ? up to 77 5 v-tolerant i/os ? all i/o ports are 5 v-tolerant ? up to 13 communication interfaces ? up to 3 x i 2 c interfaces (smbus/pmbus) ? up to 3 usarts (2 x 12.5 mbit/s, 1 x 6.25 mbit/s), iso 7816 interface, lin, irda, modem control) ? up to 5 spi/i2ss (up to 50 mbit/s, spi or i2s audio protocol), spi2 and spi3 with muxed full-duplex i 2 s to achieve audio class accuracy via internal audio pll or external clock ? sdio interface (sd/mmc/emmc) ? advanced connectivity: usb 2.0 full-speed device/host/otg controller with on-chip phy ? crc calculation unit ? 96-bit unique id ? rtc: subsecond accuracy, hardware calendar ? all packages (wlcsp49, lqfp64/100, ufqfpn48, ufbga100) are ecopack ? 2 table 1. device summary reference part number stm32f411xc stm32f411cc, stm32f411rc, stm32f411vc stm32f411xe stm32f411ce, stm32f411re, stm32f411ve wlcsp49 (3.034 x 3.220 mm) lqfp100 (14 14 mm) lqfp64 (10 10 mm) ufqfpn48 (7 7 mm) ufbga100 (7 7 mm) fbga www.st.com
contents stm32f411xc stm32f411xe 2/137 docid026289 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 compatibility with stm32f4 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 arm ? cortex ? -m4 with fpu core with embedded flash and sram . . . 15 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . . 15 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 16 3.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.3 regulator on/off and internal power supply supervisor availability . . 25 3.16 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25 3.17 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.1 advanced-control timers (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 docid026289 rev 1 3/137 stm32f411xc stm32f411xe contents 4 3.19.3 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.19.4 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.19.5 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.20 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.21 universal synchronous/asynchronous receiver transmitters (usart) . . 29 3.22 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.23 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.24 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.25 secure digital input/output interface (sdio) . . . . . . . . . . . . . . . . . . . . . . . 31 3.26 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 31 3.27 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.28 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.29 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.30 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.31 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2 vcap1/vcap2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.3 operating conditions at power-up/power-down (regulator on) . . . . . . . 64 6.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 65 6.3.5 embedded reset and power control block characteristics . . . . . . . . . . . 65 contents stm32f411xc stm32f411xe 4/137 docid026289 rev 1 6.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.7 wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.9 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.11 pll spread spectrum clock generation (sscg) characteristics . . . . . . 88 6.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 93 6.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.22 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.23 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.24 sd/sdio mmc/emmc card host interface (sdio) characteristics . . . 116 6.3.25 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1.1 wlcsp49, 3.034 x 3.22 mm, 0.4 mm pitch wafer level chip size package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1.2 ufqfpn48, 7 x 7 mm, 0.5 mm pitch package . . . . . . . . . . . . . . . . . . 122 7.1.3 lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package . . . . . . . . 125 7.1.4 lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package . . . . . . 128 7.1.5 ufbga100, 7 x 7 mm, 0.5 mm pitch package . . . . . . . . . . . . . . . . . . 131 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 docid026289 rev 1 5/137 stm32f411xc stm32f411xe list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f411xc/xe features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. regulator on/off and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 25 table 4. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 7. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8. stm32f411xc/xe pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 9. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 10. stm32f411xcxe register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 11. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 12. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 13. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 14. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 15. features depending on the operating power supply range. . . . . . . . . . . . . . . . . . . . . . . . . 63 table 16. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 17. operating conditions at power-up / power-down (regulator on) . . . . . . . . . . . . . . . . . . . . 64 table 18. operating conditions at power-up / power-down (regulator off). . . . . . . . . . . . . . . . . . . . 65 table 19. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 20. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - v dd = 1.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 21. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - v dd = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 22. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory- v dd = 1.7 v . . . 69 table 23. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory - v dd = 3.3 v . . 70 table 24. typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory - v dd = 3.6 v . . . . . . . . . . . . . . . 71 table 25. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled with prefetch) running from flash memory - v dd = 3.6 v . . . . . 72 table 26. typical and maximum current consumption in sleep mode - v dd = 3.6 v . . . . . . . . . . . . . 73 table 27. typical and maximum current consumptions in stop mode - v dd = 1.7 v . . . . . . . . . . . . . 73 table 28. typical and maximum current consumption in stop mode - v dd =3.6 v . . . . . . . . . . . . . . . 74 table 29. typical and maximum current consumption in standby mode - v dd = 1.7 v . . . . . . . . . . . 74 table 30. typical and maximum current consumption in standby mode - v dd = 3.6 v . . . . . . . . . . . 74 table 31. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 75 table 32. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 33. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 34. low-power mode wakeup timings (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 35. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 36. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 37. hse 4-26 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 38. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 39. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 40. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 41. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 42. plli2s (audio pll) characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 list of tables stm32f411xc stm32f411xe 6/137 docid026289 rev 1 table 43. sscg parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 44. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 45. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 46. flash memory programming with v pp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 47. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 48. ems characteristics for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 49. emi characteristics for lqfp100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 50. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 51. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 52. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 53. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 54. output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 55. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 56. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 57. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 58. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 01 table 59. scl frequency (f pclk1 = 50 mhz, v dd = v dd_i2c = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . 102 table 60. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 61. i 2 s dynamic characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 62. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 63. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 64. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 65. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 66. adc accuracy at f adc = 18 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 67. adc accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 68. adc accuracy at f adc = 36 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 69. adc dynamic accuracy at f adc = 18 mhz - limited test conditions . . . . . . . . . . . . . . . . . 112 table 70. adc dynamic accuracy at f adc = 36 mhz - limited test conditions . . . . . . . . . . . . . . . . . 112 table 71. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 table 72. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 73. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 74. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 75. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 76. dynamic characteristics: sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 77. dynamic characteristics: emmc characteristics v dd = 1.7 v to 1.9 v . . . . . . . . . . . . . . . 118 table 78. rtc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 79. stm32f411xc/xe wlcsp49 wafer level chip size package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 80. ufqfpn48, 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 122 table 81. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 126 table 82. lqpf100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 129 table 83. ufbga100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 84. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 85. device order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 86. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 docid026289 rev 1 7/137 stm32f411xc stm32f411xe list of figures 8 list of figures figure 1. compatible board design for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. compatible board design for lqfp64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. stm32f411xc/xe block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. power supply supervisor interconnection with internal reset off . . . . . . . . . . . . . . . . . . . 21 figure 6. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 7. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. stm32f411xc/xe wlcsp49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10. stm32f411xc/xe ufqfpn48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. stm32f411xc/xe lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. stm32f411xc/xe lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. stm32f411xc/xe ufbga100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 15. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 16. input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 17. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 18. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 19. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 20. typical v bat current consumption (lse and rtc on) . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 21. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 22. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 23. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 figure 24. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 25. acc hsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 26. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 27. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 28. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 29. ft i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 30. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 31. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 32. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 33. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 34. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 35. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 36. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 37. i 2 s master timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 38. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 109 figure 39. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 40. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 41. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 114 figure 42. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 114 figure 43. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 44. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 45. wlcsp49 wafer level chip size package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 46. wlcsp49 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 21 list of figures stm32f411xc stm32f411xe 8/137 docid026289 rev 1 figure 47. ufqfpn48, 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 48. ufqfpn48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 49. ufqfpn48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 figure 50. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 125 figure 51. lqfp64 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 figure 52. lqfp64 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 53. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 128 figure 54. lqfp100 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 55. lqpf100 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 56. ufbga100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 57. recommended pcb design rules for pads (0.5 mm-pitch bga) . . . . . . . . . . . . . . . . . . . 132 figure 58. ufbga100 package top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 32 docid026289 rev 1 9/137 stm32f411xc stm32f411xe introduction 56 1 introduction this datasheet provides the description of the stm32f411xc/xe line of microcontrollers. the stm32f411xc/xe datasheet should be read in conjunction with stm32f411xx reference manual which is available from the stmicroelectronics website www.st.com . it includes all information concerning flash memory programming. for information on the cortex ? -m4 core, please refer to the cortex ? -m4 programming manual (pm0214) available from www.st.com. description stm32f411xc stm32f411xe 10/137 docid026289 rev 1 2 description the stm32f411 x c/ x e family is based on the high-performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 100 mhz. its cortex ? -m4 with fpu core features a floating point unit (fpu) single precision which supports all arm single-precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the stm32f411xc/xe incorporate high-speed embedded memories (up to 512 kbytes of flash memory, 128 kbytes of sram), and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb bus and a 32-bit multi-ahb bus matrix. all devices offer one 12-bit adc, a low-power rtc, six general-purpose 16-bit timers including one pwm timer for motor control, two general-purpose 32-bit timers. they also feature standard and advanced communication interfaces. ? up to three i 2 cs ? five spis ? five i 2 ss out of which two are full duplex. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. ? three usarts ? sdio interface ? usb 2.0 otg full speed interface refer to table 2: stm32f411xc/xe features and peripheral counts for the peripherals available for each part number. the stm32f411xc/xe operate in the ?40 to +105 c temperature range from a 1.7 (pdr off) to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. these features make the stm32f411xc/xe microcontrollers suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances ? mobile phone sensor hub figure 3 shows the general block diagram of the device family. docid026289 rev 1 11/137 stm32f411xc stm32f411xe description 56 table 2. stm32f411xc/xe features and peripheral counts peripherals stm32f411xc stm32f411xe flash memory in kbytes 256 512 sram in kbytes system 128 timers general- purpose 7 advanced- control 1 communication interfaces spi/ i 2 s 5/5 (2 full duplex) i 2 c3 usart 3 sdio 1 usb otg fs 1 gpios 36 50 81 36 50 81 12-bit adc number of channels 1 10 16 10 16 maximum cpu frequency 100 mhz operating voltage 1.7 to 3.6 v operating temperatures ambient temperatures: ?40 to +85 c/?40 to +105 c junction temperature: ?40 to + 125 c package wlcsp49 ufqfpn48 lqfp64 ufbga100 lqfp100 wlcsp49 ufqfpn48 lqfp64 ufbga100 lqfp100 description stm32f411xc stm32f411xe 12/137 docid026289 rev 1 2.1 compatibility with stm32f4 family the stm32f411xc/xe are fully software and feature compatible with the stm32f4 family (stm32f42x, stm32f401, stm32f43x, stm32f41x, stm32f405 and stm32f407) the stm32f411xc/xe can be used as drop-in replacement of the other stm32f4 products but some slight changes have to be done on the pcb board. figure 1. compatible board design for lqfp100 package 0 6 9 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 9 & $ 3 9 6 6 9 ' ' 6 7 0 ) [ 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 9 & $ 3 9 ' ' 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 9 ' ' 9 6 6 9 ' ' 9 6 6 3 % docid026289 rev 1 13/137 stm32f411xc stm32f411xe description 56 figure 2. compatible board design for lqfp64 package 9 l q f u h d v h g w r ? i ( 6 5 ? r u e h o r z & $ 3 0 6 9 9 6 6 9 6 6 6 7 0 ) [ 6 7 0 ) 6 7 0 ) o l q h 9 ' ' 9 ' ' 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 & $ 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 9 ' ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 9 ' ' 9 6 6 3 % 9 ' ' 9 6 6 9 6 6 9 ' ' description stm32f411xc stm32f411xe 14/137 docid026289 rev 1 figure 3. stm32f411xc/xe block diagram 1. the timers connected to apb2 are clocked from timxclk up to 100 mhz, while the timers connected to apb1 are clocked from timxclk up to 50 mhz. 0 6 9 * 3 , 2 3 2 5 7 $ $ + % $ 3 % ( ; 7 , 7 : . 8 3 x s w r $ ) 3 $ > @ 7 , 0 3 : 0 f r p s o f k d q q h o v 7 , 0 b & + > @ 1 f k d q q h o v 7 , 0 b & + > @ ( 7 5 % . , 1 d v $ ) 8 6 $ 5 7 5 ; 7 ; & . & 7 6 5 7 6 d v $ ) 6 3 , , 6 $ 3 % 0 + ] $ 3 % 0 + ] d q d o r j l q s x w v 9 ' ' 5 ( ) b $ ' & 0 2 6 , 6 ' 0 , 6 2 6 ' b h [ w 6 & . & . 1 6 6 : 6 6 3 , 6 $ / $ 5 0 b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 9 ' ' $ 9 6 6 $ 1 5 6 7 v p f d u g l u ' $ e 9 % $ 7 w r 9 ' 0 $ 6 & / 6 ' $ 6 0 % $ d v $ ) , & 6 0 % 8 6 - 7 $ * 6 : $ 5 0 & r u w h [ 0 0 + ] 1 9 , & ( 7 0 0 3 8 7 5 $ & ( & / . 7 5 $ & ( ' > @ ' 0 $ 6 w u h d p v ) , ) 2 $ & & ( / & $ & + ( $ + % 0 + ] 8 6 $ 5 7 0 % s v 7 h p s h u d w x u h v h q v r u $ ' & , ) # 9 ' ' $ 3 2 5 3 ' 5 % 2 5 6 x s s o \ v x s h u y l v l r q # 9 ' ' $ 3 9 ' , q w 3 2 5 u h v h w ; 7 $ / n + ] 0 $ 1 $ * 7 5 7 & 5 & + 6 5 & / 6 3 : 5 l q w h u i d f h : ' * . # 9 % $ 7 # 9 ' ' $ # 9 ' ' $ : 8 5 h v h w f o r f n f r q w u r o 3 / / $ 3 % & / . 9 ' ' w r 9 9 6 6 9 & $ 3 9 r o w d j h u h j x o d w r u w r 9 9 ' ' 3 r z h u p d q d j p w # 9 ' ' 6 7 $ 0 3 % d f n x s u h j l v w h u $ + % e x v p d w u l [ 6 0 $ 3 % 0 + ] / 6 7 , 0 f k d q q h o v d v $ ) . % ) o d v k 7 , 0 7 , 0 7 , 0 7 , 0 ' % 8 6 ) 3 8 $ 3 % 0 + ] p d [ $ + % 0 + ] 1 - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 ' 2 6 : ' - 7 ' 2 , % 8 6 6 % 8 6 ' 0 $ 6 w u h d p v ) , ) 2 3 % > @ 3 & > @ 3 + > @ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 + e 7 , 0 e 7 , 0 e v p f d u g l u ' $ 8 6 $ 5 7 f k d q q h o d v $ ) f k d q q h o d v $ ) 5 ; 7 ; & . d v $ ) , & 6 0 % 8 6 , & 6 0 % 8 6 6 & / 6 ' $ 6 0 % $ d v $ ) 6 & / 6 ' $ 6 0 % $ d v $ ) 6 3 , 6 0 2 6 , 6 ' 0 , 6 2 6 ' b h [ w 6 & . & . 1 6 6 : 6 5 ; 7 ; d v $ ) & 7 6 5 7 6 d v $ ) 8 6 $ 5 7 v p f d u g l u ' $ e e e e f k d q q h o v f k d q q h o v ( 7 5 d v $ ) f k d q q h o v ( 7 5 d v $ ) f k d q q h o v ( 7 5 d v $ ) ' 0 $ $ + % $ 3 % / 6 2 6 & b , 1 2 6 & b 2 8 7 + & / . ; 7 $ / 2 6 & 0 + ] . % 6 5 $ 0 : : ' * $ 3 % & / . $ + % 3 & / . $ + % 3 & / . & 5 & 3 ' 5 2 ) ) w r 9 3 ' 5 2 1 6 ' , 2 0 0 & ) , ) 2 ' > @ & 0 ' & . d v $ ) 8 6 % 2 7 * ) 6 ) , ) 2 3 + < ' 3 ' 0 , ' 9 % 8 6 6 2 ) 6 3 , , 6 0 2 6 , 6 ' 0 , 6 2 6 & . & . 1 6 6 : 6 d v $ ) 3 ' > @ * 3 , 2 3 2 5 7 ' 3 ( > @ * 3 , 2 3 2 5 7 ( 0 2 6 , 6 ' 0 , 6 2 6 & . & . 1 6 6 : 6 d v $ ) 6 3 , , 6 0 2 6 , 6 ' 0 , 6 2 6 & . & . 1 6 6 : 6 d v $ ) 0 & . d v $ ) 0 & . d v $ ) docid026289 rev 1 15/137 stm32f411xc stm32f411xe functional overview 56 3 functional overview 3.1 arm ? cortex ? -m4 with fpu core with embedded flash and sram the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu 32-bit risc processor features exceptional code- efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f411xc/xe family is compatible with all arm tools and software. figure 3 shows the general block diagram of the stm32f411xc/xe. note: cortex ? -m4 with fpu is binary compatible with cortex ? -m3. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 with fpu processors. it balances the inherent performance advantage of the arm ? cortex ? -m4 with fpu over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 105 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the -bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accelerator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 100 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. it is usually managed by an rtos (real- time operating system). if a program accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. functional overview stm32f411xc stm32f411xe 16/137 docid026289 rev 1 3.4 embedded flash memory the devices embed up to 512 kbytes of flash memory available for storing programs and data. 3.5 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 embedded sram all devices embed: ? 128 kbytes of system sram which can be accessed (read/write) at cpu clock speed with 0 wait states 3.7 multi-ahb bus matrix the 32-bit multi-ahb bus matrix interconnects all the masters (cpu, dmas) and the slaves (flash memory, ram, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. docid026289 rev 1 17/137 stm32f411xc stm32f411xe functional overview 56 figure 4. multi-ahb matrix 3.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. they feature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? sd/sdio/mmc/emmc host interface ? adc $ 5 0 & r u w h [ 0 * 3 ' 0 $ * 3 ' 0 $ % x v p d w u l [ 6 6 6 6 6 6 6 , & 2 ' ( ' & 2 ' ( $ & & ( / ) o d v k n % 6 5 $ 0 . e \ w h v $ + % s h u l s k 0 0 0 0 , e x v ' e x v 6 e x v ' 0 $ b 3 , ' 0 $ b 0 ( 0 ' 0 $ b 0 ( 0 ' 0 $ b 3 0 6 9 0 $ + % s h u l s k $ 3 % $ 3 % functional overview stm32f411xc stm32f411xe 18/137 docid026289 rev 1 3.9 nested vectored interrupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the cortex ? -m4 with fpu. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 3.10 external interrupt/event controller (exti) the external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 81 gpios can be connected to the 16 external interrupt lines. 3.11 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-trimmed to offer 1% accuracy at 25 c. the application can then select as system clock either the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a failure is detected, the system automatically switches back to the internal rc oscillator and a software interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 100 mhz. similarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly used external oscillator fails). several prescalers allow the configuration of the two ahb buses, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum frequency of the two ahb buses is 100 mhz while the maximum frequency of the high-speed apb domains is 100 mhz. the maximum allowed frequency of the low-speed apb domain is 50 mhz. the devices embed a dedicated pll (plli2s) which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. docid026289 rev 1 19/137 stm32f411xc stm32f411xe functional overview 56 3.12 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1(pa9/10), usart2(pd5/6), usb otg fs in device mode (pa11/12) through dfu (device firmware upgrade), i2c1(pb6/7), i2c2(pb10/3), i2c3(pa8/pb4), spi1(pa4/5/6/7), spi2(pb12/13/14/15) or spi3(pa15, pc10/11/12). for more detailed information on the bootloader, refer to application note: an2606, stm32? microcontroller system memory boot mode . 3.13 power supply schemes ? vdd = 1.7 to 3.6 v: external power supply for i/os with the internal supervisor (por/pdr) disabled, provided externally through vdd pins. requires the use of an external power supply supervisor connected to the vdd and pdr_on pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively, with decoupling technique. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. refer to figure 18: power supply scheme for more details. functional overview stm32f411xc stm32f411xe 20/137 docid026289 rev 1 3.14 power supply supervisor 3.14.1 internal reset on this feature is available for v dd operating voltage range 1.8 v to 3.6 v. the internal power supply supervisor is enabled by holding pdr_on high. the device has an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.14.2 internal reset off this feature is available only on packages featuring the pdr_on pin.the internal power-on reset (por) / power-down reset (pdr) circuitry is disabled by setting the pdr_on pin to low. an external power supply supervisor should monitor v dd and should set the device in reset mode when v dd is below 1.7 v. nrst should be connected to this external power supply supervisor. refer to figure 5: power supply supervisor interconnection with internal reset off . docid026289 rev 1 21/137 stm32f411xc stm32f411xe functional overview 56 1. the prd_on pin is only available in the wlcsp49 and ufbga100 packages. a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry must be disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and vbat pin should be connected to v dd . 3.15 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down ? regulator off 3.15.1 regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all other packages, the regulator is always enabled. figure 5. power supply supervisor interconnection with internal reset off 0 6 y 9 3 ' 5 b 2 1 9 ' ' 1 5 6 7 ( [ w h u q d o 9 ' ' s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 ' ' 9 9 ' ' functional overview stm32f411xc stm32f411xe 22/137 docid026289 rev 1 there are three power modes configured by software when the regulator is on: ? mr is used in the nominal regulation mode (with different voltage scaling in run) in main regulator mode (mr mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. ? lpr is used in the stop modes the lp regulator mode is configured by software when entering stop mode. ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of the registers and sram are lost. depending on the package, one or two external ceramic capacitors should be connected on the v cap_1 and v cap_2 pins. the v cap_2 pin is only available for the lqfp100 and ufbga100 packages. all packages have the regulator on feature. 3.15.2 regulator off the regulator off is available only on the ufbga100, which features the bypass_reg pin. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v12 voltage source through v cap_1 and v cap_2 pins. since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. refer to table 14: general operating conditions . the two 2.2 f v cap ceramic capacitors should be replaced by two 100 nf decoupling capacitors. refer to figure 18: power supply scheme . when the regulator is off, there is no more internal monitoring on v12. an external power supply supervisor should be used to monitor the v12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v12 power domain. in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin since it allows to reset a part of the v12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required. docid026289 rev 1 23/137 stm32f411xc stm32f411xe functional overview 56 figure 6. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.7 v, then pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.7 v (see figure 7 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.7 v, then pa0 could be asserted low externally (see figure 8 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application d l 9 % < 3 $ 6 6 b 5 ( * 9 & $ 3 b 9 & $ 3 b 3 $ 9 9 ' ' 1 5 6 7 9 ' ' $ s s o l f d w l r q u h v h w v l j q d o r s w l r q d o ( [ w h u q d o 9 & $ 3 b s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 & $ 3 b 0 l q 9 9 functional overview stm32f411xc stm32f411xe 24/137 docid026289 rev 1 figure 7. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). figure 8. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). 0 6 y 9 9 ' ' w l p h 0 l q 9 3 ' 5 9 9 & $ 3 b 9 & $ 3 b 9 1 5 6 7 w l p h 9 ' ' w l p h 0 l q 9 9 & $ 3 b 9 & $ 3 b 9 3 $ d v v h u w h g h [ w h u q d o o \ 1 5 6 7 w l p h 0 6 y 9 3 ' 5 9 docid026289 rev 1 25/137 stm32f411xc stm32f411xe functional overview 56 3.15.3 regulator on/off and internal power supply supervisor availability 3.16 real-time clock (rtc) and backup registers the backup domain includes: ? the real-time clock (rtc) ? 20 backup registers the real-time clock (rtc) is an independent bcd timer/counter. dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in bcd (binary- coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc features a reference clock detection, a more precise second source clock (50 or 60 hz) can be used to enhance the calendar precision. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high-speed external clock divided by 128. the internal low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base clock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 3.17: low-power modes ). additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. table 3. regulator on/off and internal power supply supervisor availability package regulator on regulator off power supply supervisor on power supply supervisor off ufqfpn48 yes no yes no wlcsp49 yes no yes pdr_on set to vdd yes pdr_on external control (1) lqfp64 yes no yes no lqfp100 yes no yes no ufbga100 yes bypass_reg set to vss yes bypass_reg set to vdd yes pdr_on set to vdd yes pdr_on external control (1) 1. refer to section 3.14: power supply supervisor functional overview stm32f411xc stm32f411xe 26/137 docid026289 rev 1 the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. 3.17 low-power modes the devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from the stop mode by any of the exti line (the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm/ wakeup/ tamper/ time stamp events). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, the sram and register contents are lost except for registers in the backup domain when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm/ wakeup/ tamper/time stamp event occurs. standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. 3.18 v bat operation the vbat pin allows to power the device v bat domain from an external battery, an external super-capacitor, or from v dd when no external battery and an external super-capacitor are present. v bat operation is activated when v dd is not present. the vbat pin supplies the rtc and the backup registers. note: when the microcontroller is supplied from vbat, external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is not connected to v dd (internal reset off), the v bat functionality is no more available and vbat pin should be connected to v dd . docid026289 rev 1 27/137 stm32f411xc stm32f411xe functional overview 56 3.19 timers and watchdogs the devices embed one advanced-control timer, seven general-purpose timers and two watchdog timers. all timer counters can be frozen in debug mode. table 4 compares the features of the advanced-control and general-purpose timers. 3.19.1 advanced-control timers (tim1) the advanced-control timer (tim1) can be seen as three-phase pwm generators multiplexed on 4 independent channels. it has complementary pwm outputs with programmable inserted dead times. it can also be considered as a complete general- purpose timer. its 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output table 4. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max. interface clock (mhz) max. timer clock (mhz) advanced- control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 100 100 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 50 100 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 50 100 tim9 16-bit up any integer between 1 and 65536 no 2 no 100 100 tim1 0, tim11 16-bit up any integer between 1 and 65536 no 1 no 100 100 functional overview stm32f411xc stm32f411xe 28/137 docid026289 rev 1 if configured as standard 16-bit timers, it has the same features as the general-purpose timx timers. if configured as a 16-bit pwm generator, it has full modulation capability (0- 100%). the advanced-control timer can work together with the timx timers via the timer link feature for synchronization or event chaining. tim1 supports independent dma request generation. 3.19.2 general-purpose timers (timx) there are seven synchronizable general-purpose timers embedded in the stm32f411xc/xe (see table 4 for differences). ? tim2, tim3, tim4, tim5 the stm32f411xc/xe family is 4 full-featured general-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. they all feature four independent channels for input capture/output compare, pwm or one-pulse mode output. this gives up to 15 input capture/output compare/pwms. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have independent dma request generation. they are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10 and tim11 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. 3.19.3 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 3.19.4 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capability and the counter can be frozen in debug mode. docid026289 rev 1 29/137 stm32f411xc stm32f411xe functional overview 56 3.19.5 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. 3.20 inter-integrated circuit interface (i 2 c) up to three i 2 c bus interfaces can operate in multimaster and slave modes. they can support the standard (up to 100 khz) and fast (up to 400 khz) modes. the i2c bus frequency can be increased up to 1 mhz. for more details about the complete solution, please contact your local st sales representative. they also support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. the devices also include programmable analog and digital noise filters (see table 5 ). 3.21 universal synchronous/asynchronous receiver transmitters (usart) the devices embed three universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart6). these three interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and usart6 interfaces are able to communicate at speeds of up to 12.5 mbit/s. the usart2 interface communicates at up to 6.25 bit/s. usart1 and usart2 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interfaces can be served by the dma controller. table 5. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i2c peripheral clocks functional overview stm32f411xc stm32f411xe 30/137 docid026289 rev 1 3.22 serial peripheral interface (spi) the devices feature up to five spis in slave and master modes in full-duplex and simplex communication modes. spi1, spi4 and spi5 can communicate at up to 50 mbit/s, spi2 and spi3 can communicate at up to 25 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operate in ti mode for communications in master mode and slave mode. 3.23 inter-integrated sound (i 2 s) five standard i 2 s interfaces (multiplexed with spi1 to spi5) are available. they can be operated in master or slave mode, in simplex communication modes and full duplex for i2s2 and i2s3, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. all the i2sx audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. all i 2 sx can be served by the dma controller. 3.24 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s application. it allows to achieve error-free i 2 s sampling clock accuracy without compromising on the cpu performance. the plli2s configuration can be modified to manage an i 2 s sample rate change without disabling the main pll (pll) used for the cpu. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. table 6. usart feature comparison usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 6.25 12.5 apb2 (max. 100 mhz) usart2 x x x x x x 3.12 6.25 apb1 (max. 50 mhz) usart6 x n.a x x x x 6.25 12.5 apb2 (max. 100 mhz) docid026289 rev 1 31/137 stm32f411xc stm32f411xe functional overview 56 in addition to the audio pll, a master clock input pin can be used to synchronize the i2s flow with an external pll (or codec output). 3.25 secure digital input/output interface (sdio) an sd/sdio/mmc/emmc host interface is available, that supports multimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 50 mhz, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdio/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc/emmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 3.26 universal serial bus on-the-go full-speed (otg_fs) the devices embed an usb otg full-speed device/host/otg peripheral with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 4 bidirectional endpoints ? 8 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 3.27 general-purpose input/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allowing maximum i/o toggling up to 100 mhz. functional overview stm32f411xc stm32f411xe 32/137 docid026289 rev 1 3.28 analog-to-digital converter (adc) one 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. to synchronize a/d conversion and timers, the adcs could be triggered by any of tim1, tim2, tim3, tim4 or tim5 timer. 3.29 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. refer to the reference manual for additional information. as the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.30 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.31 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f411xc/xe through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using any high-speed channel available. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates with third party debugger software tools. docid026289 rev 1 33/137 stm32f411xc stm32f411xe pinouts and pin description 56 4 pinouts and pin description figure 9. stm32f411xc/xe wlcsp49 pinout 1. the above figure shows the package bump side. 0 6 9 $ % ( ' & ) * 9 ' ' 3 & 2 6 & b , 1 9 % $ 7 3 + 2 6 & b , 1 1 5 6 7 9 ' ' $ 9 5 ( ) 3 $ 9 6 6 3 ' 5 b 2 1 3 & 2 6 & b 2 8 7 9 6 6 $ 9 5 ( ) 3 $ 3 $ % 2 2 7 3 % 3 + 2 6 & b 2 8 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 9 ' ' 3 $ 9 6 6 3 $ 3 % 3 $ 3 % 3 $ 9 & $ 3 3 $ 3 % 9 ' ' 9 6 6 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 & 3 $ 3 $ 3 $ 3 $ 3 % pinouts and pin description stm32f411xc stm32f411xe 34/137 docid026289 rev 1 figure 10. stm32f411xc/xe ufqfpn48 pinout 1. the above figure shows the package top view. 6 3 3 " / / 4 0 " 0 " 0 " 0 " 0 " 0 ! 0 ! 6 $ $ 6 3 3 0 ! 5 & 1 & 0 . 0 ! 6 3 3 ! 6 2 % & 0 ! 6 $ $ ! 6 2 % & 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 " 0 " 6 3 3 - 3 6 0 " 6 # ! 0 0 " 0 " 0 " 0 " 6 " ! 4 0 # 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 0 ( / 3 # ? ) . 0 ( / 3 # ? / 5 4 . 2 3 4 0 " 0 " 6 $ $ docid026289 rev 1 35/137 stm32f411xc stm32f411xe pinouts and pin description 56 figure 11. stm32f411xc/xe lqfp64 pinout 1. the above figure shows the package top view. 6 " ! 4 0 # / 3 # ? ) . 0 ( / 3 # ? ) . . 2 3 4 0 # 0 # 0 # 0 # 6 3 3 ! 6 2 % & 6 $ $ ! 6 2 % & 0 ! 0 ! 0 ! 6 $ $ 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 # 0 # 0 # 0 ! 0 ! 6 $ $ 6 3 3 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 " 0 " 0 " 0 " 0 ! 6 3 3 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 " 6 # ! 0 , 1 & 0 0 # - 3 6 6 $ $ 6 3 3 6 $ $ 6 3 3 0 ( / 3 # ? / 5 4 0 # / 3 # ? / 5 4 pinouts and pin description stm32f411xc stm32f411xe 36/137 docid026289 rev 1 figure 12. stm32f411xc/xe lqfp100 pinout 1. the above figure shows the package top view. 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 6 3 3 6 $ $ 0 ( / 3 # ? ) . . 2 3 4 0 # 0 # 0 # 0 # 6 $ $ 6 3 3 ! 6 2 % & 6 $ $ ! 6 2 % & 0 ! 0 ! 0 ! 6 $ $ 6 3 3 6 # ! 0 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 6 # ! 0 6 3 3 6 $ $ 6 $ $ 6 3 3 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! - 3 6 , 1 & 0 0 # 0 ( / 3 # ? / 5 4 docid026289 rev 1 37/137 stm32f411xc stm32f411xe pinouts and pin description 56 figure 13. stm32f411xc/xe ufbga100 pinout 1. this figure shows the package top view 0 6 9 $ % ( ' & ) * + - . / 0 3 ( 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 & 3 & $ 1 7 , b 7 $ 0 3 3 ( 2 6 & b 2 8 7 3 & 9 6 6 $ 9 5 ( ) 9 5 ( ) 9 ' ' $ 3 ( 3 ( 3 ( 3 ( 9 % $ 7 9 6 6 9 ' ' 1 5 6 7 3 & 3 & 3 $ : . 8 3 3 $ 3 % 3 ( 3 % 9 6 6 % < 3 $ 6 6 b 5 ( * 3 ' 5 b 2 1 3 & 3 $ 3 $ 3 $ % 2 2 7 3 % 9 ' ' 3 $ 3 $ 3 $ 3 ' 3 % 3 % 3 & 3 & 3 % 3 ' 3 ' 3 % 3 % 3 % 3 ' 3 ( 3 ( 3 % 3 ' 3 ' 3 ' 3 ( 3 ( 3 $ 3 ' 3 ' 3 % 3 ( 3 ( 3 $ 3 & 3 & 3 & 3 $ 3 ' 3 ' 3 % 3 % 3 ( 3 $ 3 & 9 & $ 3 3 $ 3 & 3 ' 3 ' 3 % 9 & $ 3 3 ( 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 & 3 & 3 ' 3 ' 3 % 3 % 3 ( 9 6 6 9 ' ' 3 + 3 + 2 6 & b , 1 pinouts and pin description stm32f411xc stm32f411xe 38/137 docid026289 rev 1 table 7. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input/ output pin i/o structure ft 5 v tolerant i/o tc standard 3.3 v i/o b dedicated boot0 pin nrst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers table 8. stm32f411xc/xe pin definitions pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l - - - 1 b2 pe2 i/o ft - traceclk, spi4_sck/i2s4_ck, spi5_sck/i2s5_ck, eventout - - - - 2 a1 pe3 i/o ft - traced0, eventout - - - - 3 b1 pe4 i/o ft - traced1, spi4_nss/i2s4_ws, spi5_nss/i2s5_ws, eventout - - - - 4 c2 pe5 i/o ft - traced2, tim9_ch1, spi4_miso, spi5_miso, eventout - docid026289 rev 1 39/137 stm32f411xc stm32f411xe pinouts and pin description 56 - - - 5 d2 pe6 i/o ft - traced3, tim9_ch2, spi4_mosi/i2s4_sd, spi5_mosi/i2s5_sd, eventout - ----d3vss s-- - - ----c4vdd s-- - - 1 1 b7 6 e2 vbat s - - - - 2 2 d5 7 c1 pc13- anti_tamp i/o ft (2)(3) eventout rtc_amp1, rtc_out, rtc_ts 3 3 c7 8 d1 pc14- osc32_in i/o ft (2)(3) (4) eventout osc32_in 4 4 c6 9 e1 pc15- osc32_out i/o ft - eventout osc32_out - - - 10 f2 vss s - - - - - - - 11 g2 vdd s - - - - 5 5 d7 12 f1 ph0 - osc_in i/o ft - eventout osc_in 6 6 d6 13 g1 ph1 - osc_out i/o ft - eventout osc_out 7 7 e7 14 h2 nrst i/o ft - eventout - - 8 - 15 h1 pc0 i/o ft - eventout adc1_10 - 9 - 16 j2 pc1 i/o ft - eventout adc1_11 - 10 - 17 j3 pc2 i/o ft - spi2_miso, i2s2ext_sd, eventout adc1_12 - 11 - 18 k2 pc3 i/o ft - spi2_mosi/i2s2_sd, eventout adc1_13 - - - 19 - vdd s - - - - 8 12 e6 20 j1 vssa s - - - - ----k1 vref- s - - - - 9 13 f7 21 l1 vref+ s - - - - - - - 22 m1 vdda s - - - - table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l pinouts and pin description stm32f411xc stm32f411xe 40/137 docid026289 rev 1 10 14 f6 23 l2 pa0-wkup i/o tc (5) tim2_ch1/tim2_et, tim5_ch1, usart2_cts, eventout adc1_0, wkup1 11 15 g7 24 m2 pa1 i/o ft - tim2_ch2, tim5_ch2, spi4_mosi/i2s4_sd, usart2_rts, eventout adc1_1 12 16 e5 25 k3 pa2 i/o ft - tim2_ch3, tim5_ch3, tim9_ch1, i2s2_ckin, usart2_tx, eventout adc1_2 13 17 e4 26 l3 pa3 i/o ft - tim2_ch4, tim5_ch4, tim9_ch2, i2s2_mck, usart2_rx, eventout adc1_3 - 18 - 27 - vss s - - - - ----e3byp ass_reg s - - - - - 19 - 28 - vdd i ft - eventout - 14 20 g6 29 m3 pa4 i/o tc - spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, usart2_ck, eventout adc1_4 15 21 f5 30 k4 pa5 i/o tc - tim2_ch1/tim2_et, spi1_sck/i2s1_ck, eventout adc1_5 16 22 f4 31 l4 pa6 i/o ft - tim1_bkin, tim3_ch1, spi1_miso, i2s2_mck, sdio_cmd, eventout adc1_6 17 23 f3 32 m4 pa7 i/o ft - tim1_ch1n, tim3_ch2, spi1_mosi/i2s1_sd, eventout adc1_7 table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l docid026289 rev 1 41/137 stm32f411xc stm32f411xe pinouts and pin description 56 - 24 - 33 k5 pc4 i/o ft - eventout adc1_14 - 25 - 34 l5 pc5 i/o ft - eventout adc1_15 18 26 g5 35 m5 pb0 i/o ft - tim1_ch2n, tim3_ch3, spi5_sck/i2s5_ck, eventout adc1_8 19 27 g4 36 m6 pb1 i/o ft - tim1_ch3n, tim3_ch4, spi5_nss/i2s5_ws, eventout adc1_9 20 28 g3 37 l6 pb2 i/o ft - eventout boot1 - - - 38 m7 pe7 i/o ft - tim1_etr, eventout - - - - 39 l7 pe8 i/o ft - tim1_ch1n, eventout - - - - 40 m8 pe9 i/o ft - tim1_ch1, eventout - - - - 41 l8 pe10 i/o ft - tim1_ch2n, eventout - - - - 42 m9 pe11 i/o ft - tim1_ch2, spi4_nss/i2s4_ws, spi5_nss/i2s5_ws, eventout - - - - 43 l9 pe12 i/o ft - tim1_ch3n, spi4_sck/i2s4_ck, spi5_sck/i2s5_ck, eventout - - - - 44 m10 pe13 i/o ft - tim1_ch3, spi4_miso, spi5_miso, eventout - - - - 45 m11 pe14 i/o ft - tim1_ch4, spi4_mosi/i2s4_sd, spi5_mosi/i2s5_sd, eventout - - - - 46 m12 pe15 i/o ft - tim1_bkin, eventout - table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l pinouts and pin description stm32f411xc stm32f411xe 42/137 docid026289 rev 1 21 29 e3 47 l10 pb10 i/o ft - tim2_ch3, i2c2_scl, spi2_sck/i2s2_ck, i2s3_mck, sdio_d7, eventout - ----k9pb11 i/oft- tim2_ch4, i2c2_sda, i2s2_ckin, eventout - 22 30 g2 48 l11 vcap1 s - - - - 23 31 d3 49 f12 vss s - - - - 24 32 f2 50 g12 vdd s - - - - 25 33 e2 51 l12 pb12 i/o ft - tim1_bkin, i2c2_smba, spi2_nss/i2s2_ws, spi4_nss/i2s4_ws, spi3_sck/i2s3_ck, eventout - 26 34 g1 52 k12 pb13 i/o ft - tim1_ch1n, spi2_sck/i2s2_ck, spi4_sck/i2s4_ck, eventout - 27 35 f1 53 k11 pb14 i/o ft - tim1_ch2n, spi2_miso, i2s2ext_sd, sdio_d6, eventout - 28 36 e1 54 k10 pb15 i/o ft - rtc_50hz, tim1_ch3n, spi2_mosi/i2s2_sd, sdio_ck, eventout rtc_refin - - - 55 - pd8 i/o ft - - - - - - 56 k8 pd9 i/o ft - - - - - - 57 j12 pd10 i/o ft - - - - - - 58 j11 pd11 i/o ft - - - - - - 59 j10 pd12 i/o ft - tim4_ch1, eventout - table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l docid026289 rev 1 43/137 stm32f411xc stm32f411xe pinouts and pin description 56 - - - 60 h12 pd13 i/o ft - tim4_ch2, eventout - - - - 61 h11 pd14 i/o ft - tim4_ch3, eventout - - - - 62 h10 pd15 i/o ft - tim4_ch4, eventout - - 37 - 63 e12 pc6 i/o ft - tim3_ch1, i2s2_mck, usart6_tx, sdio_d6, eventout - - 38 - 64 e11 pc7 i/o ft - tim3_ch2, spi2_sck/i2s2_ck, i2s3_mck, usart6_rx, sdio_d7, eventout - - 39 - 65 e10 pc8 i/o ft - tim3_ch3, usart6_ck, sdio_d0, eventout - - 40 - 66 d12 pc9 i/o ft - mco_2, tim3_ch4, i2c3_sda, i2s2_ckin, sdio_d1, eventout - 29 41 d1 67 d11 pa8 i/o ft - mco_1, tim1_ch1, i2c3_scl, usart1_ck, usb_fs_sof, sdio_d1, eventout - 30 42 d2 68 d10 pa9 i/o ft - tim1_ch2, i2c3_smba, usart1_tx, usb_fs_vbus, sdio_d2, eventout otg_fs_vbus table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l pinouts and pin description stm32f411xc stm32f411xe 44/137 docid026289 rev 1 31 43 c2 69 c12 pa10 i/o ft - tim1_ch3, spi5_mosi/i2s5_sd, usart1_rx, usb_fs_id, eventout - 32 44 c1 70 b12 pa11 i/o ft - tim1_ch4, spi4_miso, usart1_cts, usart6_tx, usb_fs_dm, eventout - 33 45 c3 71 a12 pa12 i/o ft - tim1_etr, spi5_miso, usart1_rts, usart6_rx, usb_fs_dp, eventout - 34 46 b3 72 a11 pa13 i/o ft - jtms-swdio, eventout - - - - 73 c11 vcap2 s - - - - 35 47 b1 74 f11 vss s - - - - 36 48 b2 75 g11 vdd s - - - - 37 49 a1 76 a10 pa14 i/o ft - jtck-swclk, eventout - 38 50 a2 77 a9 pa15 i/o ft - jtdi, tim2_ch1/tim2_etr , spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, usart1_tx, eventout - - 51 - 78 b11 pc10 i/o ft - spi3_sck/i2s3_ck, sdio_d2, eventout - - 52 - 79 c10 pc11 i/o ft - i2s3ext_sd, spi3_miso, sdio_d3, eventout - - 53 - 80 b10 pc12 i/o ft - spi3_mosi/i2s3_sd, sdio_ck, eventout - table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l docid026289 rev 1 45/137 stm32f411xc stm32f411xe pinouts and pin description 56 - - - 81 c9 pd0 i/o ft - eventout - - - - 82 b9 pd1 i/o ft - eventout - - 54 - 83 c8 pd2 i/o ft - tim3_etr, sdio_cmd, eventout - - - - 84 b8 pd3 i/o ft - spi2_sck/i2s2_ck, usart2_cts, eventout - - - - 85 b7 pd4 i/o ft - usart2_rts, eventout - - - - 86 a6 pd5 i/o ft - usart2_tx, eventout - - - - 87 b6 pd6 i/o ft - spi3_mosi/i2s3_sd, usart2_rx, eventout - - - - 88 a5 pd7 i/o ft - usart2_ck, eventout - 39 55 a3 89 a8 pb3 i/o ft - jtdo-swo, tim2_ch2, spi1_sck/i2s1_ck, spi3_sck/i2s3_ck, usart1_rx, i2c2_sda, eventout - 40 56 a4 90 a7 pb4 i/o ft - jtrst, tim3_ch1, spi1_miso, spi3_miso, i2s3ext_sd, i2c3_sda, sdio_d0, eventout - 41 57 b4 91 c5 pb5 i/o tc - tim3_ch2, i2c1_smba, spi1_mosi/i2s1_sd, spi3_mosi/i2s3_sd, sdio_d3, eventout - 42 58 c4 92 b5 pb6 i/o ft - tim4_ch1, i2c1_scl, usart1_tx, eventout - table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l pinouts and pin description stm32f411xc stm32f411xe 46/137 docid026289 rev 1 43 59 d4 93 b4 pb7 i/o ft - tim4_ch2, i2c1_sda, usart1_rx, sdio_d0, eventout - 44 60 a5 94 a4 boot0 i b - - - 45 61 b5 95 a3 pb8 i/o ft - tim4_ch3, tim10_ch1, i2c1_scl, spi5_mosi/i2s5_sd, i2c3_sda, sdio_d4, eventout - 46 62 c5 96 b3 pb9 i/o ft - tim4_ch4, tim11_ch1, i2c1_sda, spi2_nss/i2s2_ws, i2c2_sda, sdio_d5, eventout - - - - 97 c3 pe0 i/o ft - tim4_etr, eventout - - - - 98 a2 pe1 i/o ft - eventout - 47 63 a6 99 - vss s - - - - - - b6 - h3 pdr_on i ft - eventout - 48 64 a7 100 - vdd s - - - - 1. function availability depends on the chosen device. 2. pc13, pc14 and pc15 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a current source (e.g. to drive an led). 3. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main reset). for details on how to manage these i/os, refer to the rtc register description sections in the stm32f411xx reference manual. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). 5. if the device is delivered in an ufbga100 and the bypass_reg pin is set to vdd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low) table 8. stm32f411xc/xe pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions uqfn48 lqfp64 wlcsp49 lqfp100 ufbga100l stm32f411xc stm32f411xe pinouts and pin description docid026289 rev 1 47/137 table 9. alternate function mapping port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/i2s1/ spi2/ i2s2/spi3/ i2s3 spi2/i2s2/ spi3/ i2s3/spi4/ i2s4/spi5/ i2s5 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 sdio port a pa0 - tim2_ch1/ tim2_etr tim5_ch1 --- - usart2_ cts -- ----- event out pa1 - tim2_ch2 tim5_ch2 -- spi4_mosi /i2s4_sd - usart2_ rts -- ----- event out pa2 - tim2_ch3 tim5_ch3 tim9_ch1 - i2s2_ckin - usart2_ tx -- ----- event out pa3 - tim2_ch4 tim5_ch4 tim9_ch2 - i2s2_mck - usart2_ rx -- ----- event out pa4 -- - -- spi1_nss/i 2s1_ws spi3_nss/i2 s3_ws usart2_ ck -- ----- event out pa5 - tim2_ch1/ tim2_etr --- spi1_sck/i 2s1_ck --------- event out pa6 - tim1_bkin tim3_ch1 -- spi1_miso i2s2_mck --- -- sdio_ cmd -- event out pa7 - tim1_ch1n tim3_ch2 -- spi1_mosi /i2s1_sd --------- event out pa8 mco_1 tim1_ch1 -- i2c3_scl -- usart1_ ck -- usb_fs_ sof - sdio_ d1 -- event out pa9 - tim1_ch2 -- i2c3_smb a -- usart1_ tx -- usb_fs_ vbus - sdio_ d2 -- event out pa10 - tim1_ch3 ---- spi5_mosi/i 2s5_sd usart1_ rx -- usb_fs_i d ---- event out pa11 - tim1_ch4 ---- spi4_miso usart1_ cts usart6_ tx - usb_fs_ dm ---- event out pa12 - tim1_etr ---- spi5_miso usart1_ rts usart6_ rx - usb_fs_ dp ---- event out pinouts and pin description stm32f411xc stm32f411xe 48/137 docid026289 rev 1 port a pa13 jtms- swdio ----- - -------- event out pa14 jtck- swclk ----- - -------- event out pa15 jtdi tim2_ch1/ tim2_etr --- spi1_nss/i 2s1_ws spi3_nss/i2 s3_ws usart1_ tx -- ----- event out port b pb0 - tim1_ch2n tim3_ch3 --- spi5_sck/i2 s5_ck -- ----- event out pb1 - tim1_ch3n tim3_ch4 --- spi5_nss/i2 s5_ws -- ----- event out pb2 -- - --- - -------- event out pb3 jtdo- swo tim2_ch2 --- spi1_sck/i 2s1_ck spi3_sck/i2 s3_ck usart1_ rx - i2c2_sda ----- event out pb4 jtrst tim3_ch1 -- spi1_miso spi3_miso i2s3ext_s d - i2c3_sda sdio_ d0 -- event out pb5 -- tim3_ch2 - i2c1_smb a spi1_mosi /i2s1_sd spi3_mosi/i 2s3_sd -- -- sdio_ d3 -- event out pb6 -- tim4_ch1 - i2c1_scl -- usart1_ tx -- -- -- event out pb7 -- tim4_ch2 - i2c1_sda -- usart1_ rx -- -- sdio_ d0 -- event out pb8 -- tim4_ch3 tim10_ch1 i2c1_scl - spi5_mosi/i 2s5_sd -- i2c3_sda -- sdio_ d4 -- event out pb9 -- tim4_ch4 tim11_ch1 i2c1_sda spi2_nss/i 2s2_ws --- i2c2_sda -- sdio_ d5 -- event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/i2s1/ spi2/ i2s2/spi3/ i2s3 spi2/i2s2/ spi3/ i2s3/spi4/ i2s4/spi5/ i2s5 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 sdio stm32f411xc stm32f411xe pinouts and pin description docid026289 rev 1 49/137 port b pb10 - tim2_ch3 -- i2c2_scl spi2_sck/i 2s2_ck i2s3_mck --- -- sdio_ d7 -- event out pb11 - tim2_ch4 -- i2c2_sda i2s2_ckin --------- event out pb12 - tim1_bkin -- i2c2_smb a spi2_nss/i 2s2_ws spi4_nss/i2 s4_ws spi3_sck /i2s3_ck -- ----- event out pb13 - tim1_ch1n --- spi2_sck/i 2s2_ck spi4_sck/i2 s4_ck --- ----- event out pb14 - tim1_ch2n --- spi2_miso i2s2ext_sd --- -- sdio_ d6 -- event out pb15 rtc_50h z tim1_ch3n --- spi2_mosi /i2s2_sd ------ sdio_ ck -- event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/i2s1/ spi2/ i2s2/spi3/ i2s3 spi2/i2s2/ spi3/ i2s3/spi4/ i2s4/spi5/ i2s5 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 sdio pinouts and pin description stm32f411xc stm32f411xe 50/137 docid026289 rev 1 port c pc0 -- - --- - -------- event out pc1 -- - --- - -------- event out pc2 -- - -- spi2_miso i2s2ext_sd --- ----- event out pc3 -- - -- spi2_mosi /i2s2_sd --------- event out pc4 -- - -- - -------- event out pc5 -- - -- - -------- event out pc6 -- tim3_ch1 -- i2s2_mck -- usart6_ tx --- sdio_ d6 -- event out pc7 -- tim3_ch2 -- spi2_sck/i 2s2_ck i2s3_mck - usart6_ rx --- sdio_ d7 -- event out pc8 -- tim3_ch3 --- - - usart6_ ck --- sdio_ d0 -- event out pc9 mco_2 - tim3_ch4 - i2c3_sda i2s2_ckin -- --- sdio_ d1 -- event out port c pc10 -- - --- spi3_sck/i2 s3_ck --- -- sdio_ d2 -- event out pc11 -- - -- i2s3ext_sd spi3_miso --- -- sdio_ d3 -- event out pc12 -- - --- spi3_mosi/i 2s3_sd --- -- sdio_ ck -- event out pc13 -- - --- - -------- event out pc14 -- - --- - -------- event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/i2s1/ spi2/ i2s2/spi3/ i2s3 spi2/i2s2/ spi3/ i2s3/spi4/ i2s4/spi5/ i2s5 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 sdio stm32f411xc stm32f411xe pinouts and pin description docid026289 rev 1 51/137 port d pc15 -- - --- - -------- event out pd0 -- - --- - -------- event out pd1 -- - --- - -------- event out pd2 -- tim3_etr --- - ----- sdio_ cmd event out pd3 -- - -- spi2_sck/i 2s2_ck usart2_ cts -- ----- event out pd4 -- - --- - usart2_ rts -- ----- event out pd5 -- - --- - usart2_ tx -- ----- event out pd6 -- - -- spi3_mosi /i2s3_sd - usart2_ rx -- ----- event out pd7 -- - --- - usart2_ ck -- ----- event out pd8 -- - --- - -------- event out pd9 -- - --- - -------- event out pd10 -- - --- - -------- event out pd11 -- - --- - -------- event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/i2s1/ spi2/ i2s2/spi3/ i2s3 spi2/i2s2/ spi3/ i2s3/spi4/ i2s4/spi5/ i2s5 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 sdio pinouts and pin description stm32f411xc stm32f411xe 52/137 docid026289 rev 1 port d pd12 -- tim4_ch1 --- - -------- event out pd13 -- tim4_ch2 --- - -------- event out pd14 -- tim4_ch3 --- - -------- event out pd15 -- tim4_ch4 --- - -------- event out port e pe0 -- tim4_etr --- - -------- event out pe1 -- --- - -------- event out pe2 tracecl k ---- spi4_sck/i 2s4_ck spi5_sck/i2 s5_ck --- ----- event out pe3 traced0 ----- - -------- event out pe4 traced1 ---- spi4_nss/i 2s4_ws spi5_nss/i2 s5_ws --- ----- event out pe5 traced2 -- tim9_ch1 - spi4_miso spi5_miso --- ----- event out pe6 traced3 -- tim9_ch2 - spi4_mosi /i2s4_sd spi5_mosi/i 2s5_sd --- ----- event out pe7 - tim1_etr ---- - -------- event out pe8 - tim1_ch1n ---- - -------- event out pe9 - tim1_ch1 ---- - -------- event out pe10 - tim1_ch2n ---- - -------- event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/i2s1/ spi2/ i2s2/spi3/ i2s3 spi2/i2s2/ spi3/ i2s3/spi4/ i2s4/spi5/ i2s5 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 sdio stm32f411xc stm32f411xe pinouts and pin description docid026289 rev 1 53/137 port e pe11 - tim1_ch2 --- spi4_nss/i 2s4_ws spi5_nss/i2 s5_ws --- ----- event out pe12 - tim1_ch3n --- spi4_sck/i 2s4_ck spi5_sck/i2 s5_ck --- ----- event out pe13 - tim1_ch3 --- spi4_miso spi5_miso --- ----- event out pe14 - tim1_ch4 --- spi4_mosi /i2s4_sd spi5_mosi/i 2s5_sd --- ----- event out pe15 - tim1_bkin ---- - -------- event out port h ph0 -- - --- - -------- event out ph1 -- - --- - -------- event out table 9. alternate function mapping (continued) port af00 af01 af02 af03 af04 af05 af06 af07 af08 af09 af10 af11 af12 af13 af14 af15 sys_af tim1/tim2 tim3/ tim4/ tim5 tim9/ tim10/ tim11 i2c1/i2c2/ i2c3 spi1/i2s1/ spi2/ i2s2/spi3/ i2s3 spi2/i2s2/ spi3/ i2s3/spi4/ i2s4/spi5/ i2s5 spi3/i2s3/ usart1/ usart2 usart6 i2c2/ i2c3 sdio memory mapping stm32f411xc stm32f411xe 54/137 docid026289 rev 1 5 memory mapping the memory map is shown in figure 14 . figure 14. memory map table 10. stm32f411xcxe register boundary addresses bus boundary address peripheral 0xe010 0000 - 0xffff ffff reserved cortex ? -m4 0xe000 0000 - 0xe00f ffff cortex-m4 internal peripherals 0x5004 0000 - 0xdfff ffff reserved ahb2 0x5000 0000 - 0x5003 ffff usb otg fs 0 6 y 9 0 e \ w h e o r f n & r u w h [ 0 v l q w h u q d o s h u l s k h u d o v 0 e \ w h e o r f n 1 r w x v h g 0 e \ w h e o r f n 3 h u l s k h u d o v 0 e \ w h e o r f n 6 5 $ 0 [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ & [ ' ) ) ) ) ) ) ) [ ( [ ) ) ) ) ) ) ) ) 0 e \ w h e o r f n & r g h [ [ ) ) ) ) ) ) ) [ 5 h v h u y h g [ ) ) [ [ ) ) ) ) [ [ [ ' ) ) ) ) ) ) ) $ + % 5 h v h u y h g [ ) ) ) ) [ 6 5 $ 0 . % d o l d v h g e \ e l w e d q g l q j [ [ $ 3 % $ 3 % [ % ) ) [ & [ ) ) ) ) 5 h v h u y h g [ [ ) ) ) ) ) ) ) [ ) ) $ + % 5 h v h u y h g ) o d v k p h p r u \ [ [ ) ) ( ) ) ) ) [ ) ) ) & [ ) ) ) & [ [ ) ) ) ) [ [ ) ) ) ) ) ) [ [ ) ) ) ) 5 h v h u y h g 5 h v h u y h g $ o l d v h g w r ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q w k h % 2 2 7 s l q v 6 \ v w h p p h p r u \ [ ) ) ) & [ ) ) ) ) ) ) ) [ ) ) ) $ [ ) ) ) % ) ) ) [ ) ) ) [ ) ) ) $ ) 2 s w l r q e \ w h v [ & r u w h [ 0 l q w h u q d o s h u l s k h u d o v [ ( [ ( ) ) ) ) ) 5 h v h u y h g [ ( [ ) ) ) ) ) ) ) ) 5 h v h u y h g [ % ) ) ) ) ) ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g docid026289 rev 1 55/137 stm32f411xc stm32f411xe memory mapping 56 0x4002 6800 - 0x4fff ffff reserved ahb1 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 4fff reserved 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2000 - 0x4002 2fff reserved 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1400 - 0x4002 1bff reserved 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa apb2 0x4001 5400- 0x4001 ffff reserved 0x4001 5000 - 0x4001 53fff spi5/i2s5 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff spi4/i2s4 0x4001 3000 - 0x4001 33ff spi1/i2s1 0x4001 2c00 - 0x4001 2fff sdio 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 0x4000 7400 - 0x4000 ffff reserved table 10. stm32f411xcxe register boundary addresses (continued) bus boundary address peripheral memory mapping stm32f411xc stm32f411xe 56/137 docid026289 rev 1 apb1 0x4000 7000 - 0x4000 73ff pwr 0x4000 6000 - 0x4000 6fff reserved 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 4800 - 0x4000 53ff reserved 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff i2s3ext 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff i2s2ext 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2bff rtc & bkp registers 0x4000 1000 - 0x4000 27ff reserved 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 table 10. stm32f411xcxe register boundary addresses (continued) bus boundary address peripheral docid026289 rev 1 57/137 stm32f411xc stm32f411xe electrical characteristics 118 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.7 v ? ? v dd ? ? 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 15 . figure 15. pin loading conditions - 3 6 # p & - # 5 p i n electrical characteristics stm32f411xc stm32f411xe 58/137 docid026289 rev 1 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 16 . figure 16. input voltage measurement - 3 6 - # 5 p i n 6 ) . docid026289 rev 1 59/137 stm32f411xc stm32f411xe electrical characteristics 118 6.1.6 power supply scheme figure 17. power supply scheme 1. to connect pdr_on pin, refer to section 3.14: power supply supervisor . 2. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. 3. vcap_2 pad is only available on lqfp100 and ufbga100 packages. 4. v dda =v dd and v ssa =v ss . caution: each power supply pair (for example v dd /v ss , v dda /v ssa ) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure good operation of the device. it is not recommended to remove filtering capacitors to reduce pcb size or cost. this might cause incorrect operation of the device. 0 6 9 % d f n x s f l u f x l w u \ 2 6 & . 5 7 & : d n h x s o r j l f % d f n x s u h j l v w h u v . h u q h o o r j l f & 3 8 g l j l w d o 5 $ 0 $ q d o r j 5 & v 3 / / 3 r z h u v z l w f k 9 % $ 7 * 3 , 2 v 2 8 7 , 1 ? q ) ? ? ) 9 % $ 7 w r 9 9 r o w d j h u h j x o d w r u 9 ' ' $ $ ' & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) ) o d v k p h p r u \ 9 & $ 3 b % < 3 $ 6 6 b 5 ( * 3 ' 5 b 2 1 5 h v h w f r q w u r o o h u 9 ' ' 9 6 6 9 ' ' 9 5 ( ) 9 5 ( ) 9 6 6 $ 9 5 ( ) q ) ? ) 9 & $ 3 b ? ? ) ? ? ) r u electrical characteristics stm32f411xc stm32f411xe 60/137 docid026289 rev 1 6.1.7 current consumption measurement figure 18. current consumption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 11: voltage characteristics , table 12: current characteristics , and table 13: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. a i 6 " ! 4 6 $ $ 6 $ $ ! ) $ $ ? 6 " ! 4 ) $ $ table 11. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd and v bat ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on ft pins (2) 2. v in maximum value must always be respected. refer to table 12 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4.0 input voltage on any other pin v ss ?0.3 4.0 input voltage for boot0 v ss 9.0 | ? v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.14: absolute maximum ratings (electrical sensitivity) docid026289 rev 1 61/137 stm32f411xc stm32f411xe electrical characteristics 118 table 12. current characteristics symbol ratings max. unit ? i vdd total current into sum of all v dd_x power lines (source) (1) 160 ma ?? i vss total current out of sum of all v ss_x ground lines (sink) (1) -160 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss_x ground line (sink) (1) -100 i io output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin -25 ? i io total output current sunk by sum of all i/o and control pins (2) 120 total output current sourced by sum of all i/os and control pins (2) -120 i inj(pin) (3) injected current on ft pins (4) ?5/+0 injected current on nrst and b pins (4) ? i inj(pin) total injected current (sum of all i/o and control pins) (5) 25 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. 3. negative injection disturbs the analog performance of the device. see note in section 6.3.20: 12-bit adc characteristics . 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. when several inputs are submitted to a current injection, the maximum e i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 13. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 125 t lead maximum lead temperature during soldering (wlcsp49, lqfp64/100, ufqfpn48, ufbga100) see note (1) 1. compliant with jedec std j-std-020d (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs directive 2011/65/eu, july 2011). electrical characteristics stm32f411xc stm32f411xe 62/137 docid026289 rev 1 6.3 operating conditions 6.3.1 general operating conditions table 14. general operating conditions symbol parameter conditions min typ max unit f hclk internal ahb clock frequency power scale3: regulator on, vos[1:0] bits in pwr_cr register = 0x01 0-64 mhz power scale2: regulator on, vos[1:0] bits in pwr_cr register = 0x10 0 - 84 power scale1: regulator on, vos[1:0] bits in pwr_cr register = 0x11 0 - 100 f pclk1 internal apb1 clock frequency 0 - 50 mhz f pclk2 internal apb2 clock frequency 0 - 100 mhz v dd standard operating voltage 1.7 (1) - 3.6 v v dda (2)(3) analog operating voltage (adc limited to 1.2 m samples) must be the same potential as v dd (4) 1.7 (1) - 2.4 v analog operating voltage (adc limited to 2.4 m samples) 2.4 - 3.6 v bat backup operating voltage 1.65 - 3.6 v v 12 regulator on: 1.2 v internal voltage on vcap1/vcap2 pins vos[1:0] bits in pwr_cr register = 0x01 max frequency 64 mhz 1.08 (5) 1.14 1.20 (5) v vos[1:0] bits in pwr_cr register = 0x10 max frequency 84 mhz 1.20 (5) 1.26 1.32 (5) vos[1:0] bits in pwr_cr register = 0x11 max frequency 100 mhz 1.26 1.32 1.38 v 12 regulator off: 1.2 v external voltage must be supplied on vcap1/vcap2 pins max frequency 64 mhz 1.10 1.14 1.20 v max frequency 84 mhz 1.20 1.26 1.32 max frequency 100 mhz 1.26 1.32 1.38 v in input voltage on rst and ft pins (6) 2 v ?? ? v dd ?? ? 3.6 v?0.3-5.5 v v dd ?? ? 2 v?0.3-5.2 input voltage on boot0 pin - 0 - 9 p d maximum allowed package power dissipation for suffix 7 (7) ufqfpn48 - - 625 mw wlcsp49 - - 392 lqfp64 - - 313 lqfp100 - - 465 ufbga100 - - 323 docid026289 rev 1 63/137 stm32f411xc stm32f411xe electrical characteristics 118 t a ambient temperature for 6 suffix version maximum power dissipation ?40 - 85 c low power dissipation (8) ?40 - 105 ambient temperature for 7 suffix version maximum power dissipation ?40 - 105 low power dissipation (8) ?40 - 125 t j junction temperature range 6 suffix version ?40 - 105 7 suffix version ?40 - 125 1. v dd /v dda minimum value of 1.7 v with the use of an external power supply supervisor (refer to section 3.14.2: internal reset off ). 2. when the adc is used, refer to table 65: adc characteristics . 3. if vref+ pin is present, it must respect the following condition: vdda-vref+ < 1.2 v. 4. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 5. guaranteed by test in production 6. to sustain a voltage higher than vdd+0.3, the internal pull-up and pull-down resistors must be disabled 7. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 8. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 14. general operating conditions (continued) symbol parameter conditions min typ max unit table 15. features depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum flash memory access frequency with wait states (1)(2) i/o operation clock output frequency on i/o pins (3) possible flash memory operations v dd =1.7 to 2.1 v (4) conversion time up to 1.2 msps 16 mhz (5) 100 mhz with 6 wait states ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 18 mhz 100 mhz with 5 wait states ? no i/o compensation up to 30 mhz 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 100 mhz with 4 wait states ? i/o compensation works up to 50 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v (6) conversion time up to 2.4 msps 30 mhz 100 mhz with 3 wait states ? i/o compensation works ? up to 100 mhz when v dd = 3.0 to 3.6 v ? up to 50 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations electrical characteristics stm32f411xc stm32f411xe 64/137 docid026289 rev 1 6.3.2 vcap1/vcap2 external capacitors stabilization for the main regulator is achieved by connecting the external capacitor c ext to the vcap1 and vcap2 pins. for packages supporting only 1 vcap pin, the 2 cext capacitors are replaced by a single capacitor. c ext is specified in table 16 . figure 19. external capacitor c ext 1. legend: esr is the equivalent series resistance. 6.3.3 operating conditions at power-up/power-down (regulator on) subject to general operating conditions for t a . table 17. operating conditions at power-up / power-down (regulator on) 1. applicable only when the code is executed from flash memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. refer to table 55: i/o ac characteristics for frequencies vs. external load. 4. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 3.14.2: internal reset off ). 5. prefetch is not available. refer to an3430 application note for details on how to adjust performance and power. 6. the voltage range for the usb full speed embedded phy can drop down to 2.7 v. however the electrical characteristics of d- and d+ pins will be degraded between 2.7 and 3 v. table 16. vcap1/vcap2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter conditions cext capacitance of external capacitor with a single vcap pin available 4.7 f esr esr of external capacitor with a single vcap pin available < 1 ? 0 6 9 ( 6 5 5 / h d n & symbol parameter min max unit t vdd v dd rise time rate 20 ? s/v v dd fall time rate 20 ? docid026289 rev 1 65/137 stm32f411xc stm32f411xe electrical characteristics 118 6.3.4 operating conditions at power-up / power-down (regulator off) subject to general operating conditions for t a . note: this feature is only available for ufbga100 package. 6.3.5 embedded reset and power control block characteristics the parameters given in table 19 are derived from tests performed under ambient temperature and v dd supply voltage @ 3.3v. table 18. operating conditions at power-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 ? s/v v dd fall time rate power-down 20 ? t vcap v cap_1 and v cap_2 rise time rate power-up 20 ? v cap_1 and v cap_2 fall time rate power-down 20 ? table 19. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 pls[2:0]=001 (rising edge) 2.23 2.30 2.37 pls[2:0]=001 (falling edge) 2.13 2.19 2.25 pls[2:0]=010 (rising edge) 2.39 2.45 2.51 pls[2:0]=010 (falling edge) 2.29 2.35 2.39 pls[2:0]=011 (rising edge) 2.54 2.60 2.65 pls[2:0]=011 (falling edge) 2.44 2.51 2.56 pls[2:0]=100 (rising edge) 2.70 2.76 2.82 pls[2:0]=100 (falling edge) 2.59 2.66 2.71 pls[2:0]=101 (rising edge) 2.86 2.93 2.99 pls[2:0]=101 (falling edge) 2.65 2.84 3.02 pls[2:0]=110 (rising edge) 2.96 3.03 3.10 pls[2:0]=110 (falling edge) 2.85 2.93 2.99 pls[2:0]=111 (rising edge) 3.07 3.14 3.21 pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v pvdhyst (2) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 (1) 1.68 1.76 v rising edge 1.64 1.72 1.80 electrical characteristics stm32f411xc stm32f411xe 66/137 docid026289 rev 1 6.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 18: current consumption measurement scheme . all the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. v pdrhyst (2) pdr hysteresis - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 rising edge 2.53 2.59 2.63 v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 rising edge 2.85 2.92 2.97 v borhyst (2) bor hysteresis - 100 - mv t rsttempo (2)(3) por reset timing 0.5 1.5 3.0 ms i rush (2) in-rush current on voltage regulator power- on (por or wakeup from standby) - 160 200 ma e rush (2) in-rush energy on voltage regulator power- on (por or wakeup from standby) v dd = 1.7 v, t a = 105 c, i rush = 171 ma for 31 s - - 5.4 c 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 2. guaranteed by design, not tested in production. 3. the reset timing is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is fetched by the user application code. table 19. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit docid026289 rev 1 67/137 stm32f411xc stm32f411xe electrical characteristics 118 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at vdd or vss (no load). ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted to both f hclk frequency and vdd ranges (refer to table 15: features depending on the operating power supply range ). ? the voltage scaling is adjusted to f hclk frequency as follows: ? scale 3 for f hclk ? ? ? 64 mhz ? scale 2 for 64 mhz < f hclk ? ? 84 mhz ? scale 1 for 84 mhz < f hclk ? ? 100 mhz ? the system clock is hclk, f pclk1 = f hclk /2, and f pclk2 = f hclk . ? external clock is 4 mhz and pll is on except if it is explicitly mentioned. ? the maximum values are obtained for v dd = 3.6 v and a maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. table 20. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - v dd = 1.7 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 25 c t a =85 c t a =105 c i dd supply current in run mode external clock, pll on (2) , all peripherals enabled (3)(4) 100 22.0 23.6 23.6 24.0 ma 84 18.0 18.9 (5) 19.1 19.2 64 12.2 13.2 13.2 13.7 50 9.6 10.4 10.4 11.0 20 4.3 4.8 5.0 5.6 hsi, pll off, all peripherals enabled (4) 16 2.4 3.1 3.6 4.3 1 0.4 0.6 1.0 1.7 external clock, pll on (2) )all peripherals disabled (3) 100 13.2 14.4 14.4 14.8 84 10.9 11.6 (5) 11.8 12 64 7.4 8.2 8.2 8.7 50 5.8 6.5 6.5 7.1 20 2.6 3.1 3.3 3.9 hsi, pll off, all peripherals disabled (4) 16 1.5 1.9 2.4 3.0 1 0.4 0.5 0.9 1.6 1. guaranteed by characterization, not tested in production unless otherwise specified 2. refer to table 41 and rm0383 for the possible pll vco setting 3. when analog peripheral blocks such as adc, hse, lse, hsi, or lsi are on, an additional power consumption has to be considered. 4. when the adc is on (adon bit set in the adc_cr2 register), add an additional power consumption of 1.6 ma for the analog part. electrical characteristics stm32f411xc stm32f411xe 68/137 docid026289 rev 1 5. tested in production. table 21. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - v dd = 3.6 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a =85 c t a =105 c i dd supply current in run mode external clock, pll on (2) , all peripherals enabled (3)(4) 100 22.3 23.9 23.9 24.3 ma 84 18.3 19.2 (5) 19.4 19.4 64 12.5 13.6 13.5 14.0 50 9.9 10.7 10.7 11.2 20 4.6 5.1 5.3 5.9 hsi, pll off, all peripherals enabled (3) 16 2.4 3.1 3.6 4.3 1 0.4 0.6 1.0 1.7 external clock, pll off (2) , all peripherals disabled (3) 100 13.8 14.6 (5) 14.6 14.9 84 11.2 11.9 (5) 12.1 12.2 64 7.9 8.4 (5) 8.8 8.9 50 6.1 6.8 6.8 8.9 20 2.9 3.3 3.5 4.2 hsi, pll off, all peripherals disabled (3) 16 1.5 1.9 2.4 3.1 1 0.4 0.5 0.9 1.6 1. guaranteed by characterization, not tested in production unless otherwise specified 2. refer to table 41 and rm0383 for the possible pll vco setting 3. when analog peripheral blocks such as adc, hse, lse, hsi, or lsi are on, an additional power consumption has to be considered. 4. when the adc is on (adon bit set in the adc_cr2 register), add an additional power consumption of 1.6 ma for the analog part. 5. tested in production docid026289 rev 1 69/137 stm32f411xc stm32f411xe electrical characteristics 118 table 22. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory- v dd = 1.7 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, pll on (2) , all peripherals enabled (3)(4) 100 20.4 21.8 22.1 22.8 ma 84 16.5 17.6 17.8 18.6 64 11.4 12.3 12.5 13.1 50 9.0 9.7 10.0 10.6 20 4.6 5.0 5.3 6.0 hsi, pll off (2) , all peripherals enabled (3) 16 2.9 3.2 3.6 4.3 1 0.7 0.8 1.3 1.9 external clock, pll on (2) all peripherals disabled (3) 100 11.2 12.2 12.4 13.2 84 9.1 9.9 10.1 10.9 64 6.4 7.0 7.3 7.9 50 5.1 5.6 5.9 6.6 20 2.6 3.0 3.3 4.0 hsi, pll off (2) , all peripherals disabled (3) 16 1.8 2.0 2.4 3.0 1 0.6 0.7 1.2 1.9 1. guaranteed by characterization, not tested in production unless otherwise specified. 2. refer to table 41 and rm0383 for the possible pll vco setting 3. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 4. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. electrical characteristics stm32f411xc stm32f411xe 70/137 docid026289 rev 1 table 23. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory - v dd = 3.3 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, pll on (2) , all peripherals enabled (3)(4) 100 20.7 22.2 22.5 23.2 ma 84 16.8 18.0 18.3 19.0 64 11.8 12.7 12.9 13.6 50 9.3 10.2 10.4 11.1 20 4.8 5.5 5.8 6.5 hsi, pll off (2) , all peripherals enabled (3) 16 3.0 3.3 3.8 4.5 1 0.7 1.0 1.4 2.1 external clock, pll on (2) all peripherals disabled (3) 100 11.6 12.6 12.9 13.6 84 9.7 10.2 (5) 11.1 11.3 64 6.7 7.4 7.7 8.3 50 5.4 6.0 6.3 7.0 20 2.9 3.4 3.7 4.4 hsi, pll off (2) , all peripherals disabled (3) 16 1.9 2.2 2.6 3.3 1 0.7 0.9 1.3 2.1 1. guaranteed by characterization, not tested in production unless otherwise specified. 2. refer to table 41 and rm0383 for the possible pll vco setting 3. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 4. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. 5. tested in production. docid026289 rev 1 71/137 stm32f411xc stm32f411xe electrical characteristics 118 table 24. typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory - v dd = 3.6 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, pll on (2) , all peripherals enabled (3)(4) 100 29.5 31.5 32.3 33.3 ma 84 25.5 27.1 27.9 28.9 64 18.6 19.8 20.4 21.2 50 15.2 16.4 16.9 17.7 20 7.6 8.4 8.8 9.5 hsi, pll off (2) , all peripherals enabled (3) 16 4.8 5.2 5.7 6.5 1 0.9 1.3 1.6 2.4 external clock, pll on (2) all peripherals disabled (3) 100 20.4 21.8 22.7 23.8 84 18.4 19.2 (5) 20.9 21.1 64 13.5 14.5 15.2 15.9 50 11.3 12.2 12.8 13.6 20 5.6 6.4 6.7 7.4 hsi, pll off (2) , all peripherals disabled (3) 16 3.6 4.1 4.5 5.2 1 0.9 1.2 1.6 2.3 1. guaranteed by characterization, not tested in production unless otherwise specified. 2. refer to table 41 and rm0383 for the possible pll vco setting 3. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 4. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. 5. tested in production electrical characteristics stm32f411xc stm32f411xe 72/137 docid026289 rev 1 table 25. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled with prefetch) running from flash memory - v dd = 3.6 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, pll on (2) , all peripherals enabled (3)(4) 100 20.7 22.2 22.5 23.2 ma 84 16.8 18.0 18.3 19.0 64 11.8 18.0 18.3 19.0 50 9.3 10.2 10.4 11.1 20 4.8 5.5 5.8 6.5 hsi, pll off (2) , all peripherals enabled (3) 16 3.0 3.3 3.8 4.5 1 0.7 1.0 1.4 2.1 external clock, pll on (2) all peripherals disabled (3) 100 11.6 12.6 12.9 13.6 84 9.7 10.2 (5) 11.1 11.2 64 6.7 7.4 7.7 8.3 50 5.4 6.0 6.3 7.0 20 2.9 3.4 3.7 4.4 hsi, pll off (2) , all peripherals disabled (3) 16 1.9 2.2 2.6 3.3 1 0.7 0.9 1.3 2.1 1. guaranteed by characterization, not tested in production unless otherwise specified. 2. refer to table 41 and rm0383 for the possible pll vco setting 3. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 4. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. 5. tested in production docid026289 rev 1 73/137 stm32f411xc stm32f411xe electrical characteristics 118 table 26. typical and maximum current consumption in sleep mode - v dd = 3.6 v symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, pll on (2) , all peripherals enabled (3)(4) 100 12.2 13.2 13.4 14.1 ma 84 9.8 10.6 10.9 11.6 64 6.9 7.4 7.7 8.3 50 5.4 5.9 6.2 6.8 20 2.8 3.2 3.5 4.1 hsi, pll off (2) , all peripherals enabled (3) 16 1.3 1.7 2.2 2.8 1 0.4 0.5 0.9 1.6 external clock, pll on (2) all peripherals disabled (3) 100 3.0 3.6 3.9 4.5 84 2.5 3.0 3.2 3.9 64 1.9 2.2 2.5 3.0 50 1.6 1.9 2.1 2.7 20 1.1 1.4 1.7 2.3 hsi, pll off (2) , all peripherals disabled (3) 16 0.4 0.5 0.9 1.6 1 0.3 0.4 0.8 1.5 1. guaranteed by characterization, not tested in production unless otherwise specified. 2. refer to table 41 and rm0383 for the possible pll vco setting 3. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). 4. when the adc is on (adon bit set in the adc_cr2), add an additional power consumption of 1.6ma per adc for the analog part. table 27. typical and maximum current consumptions in stop mode - v dd = 1.7 v symbol conditions parameter typ (1) max (1) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop flash in stop mode, all oscillators off, no independent watchdog main regulator usage 112 142 (2) 400 710 (2) a low power regulator usage 42.6 67 (2) 300 580 flash in deep power down mode, all oscillators off, no independent watchdog main regulator usage 75 99 (2) 310 580 (2) low power regulator usage 13.6 37 (2) 265 550 (2) low power low voltage regulator usage 9 28 (2) 230 500 (2) 1. guaranteed by characterization, not tested in production. 2. tested in production electrical characteristics stm32f411xc stm32f411xe 74/137 docid026289 rev 1 table 28. typical and maximum current consumption in stop mode - v dd =3.6 v symbol conditions parameter typ max (1) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop flash in stop mode, all oscillators off, no independent watchdog main regulator usage 113.7 145 (2) 410 720 (2) a low power regulator usage 43.1 68 (2) 310 600 (2) flash in deep power down mode, all oscillators off, no independent watchdog main regulator usage 76.2 105 (2) 320 600 (2) low power regulator usage 14 38 (2) 275 560 (2) low power low voltage regulator usage 10 30 (2) 235 510 (2) 1. guaranteed by characterization, not tested in production. 2. tested in production. table 29. typical and maximum current consumption in standby mode - v dd = 1.7 v symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stby supply current in standby mode low-speed oscillator (lse) and rtc on 2.6 4 12 24 a rtc and lse off 1.8 3 (3) 11 25 (3) 1. when the pdr is off (internal reset is off), the typical current consumption is reduced by 1.2 a. 2. guaranteed by characterization, not tested in production unless otherwise specified. 3. tested in production. table 30. typical and maximum current consumption in standby mode - v dd = 3.6 v symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stby supply current in standby mode low-speed oscillator (lse) and rtc on 3 5 14 28 a rtc and lse off 2.1 4 (3) 13.5 30 (3) 1. when the pdr is off (internal reset is off), the typical current consumption is reduced by 1.2 a. 2. guaranteed by characterization, not tested in production unless otherwise specified. 3. tested in production. docid026289 rev 1 75/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 20. typical v bat current consumption (lse and rtc on) i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 53: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is table 31. typical and maximum current consumptions in v bat mode symbol parameter conditions (1) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c v bat = 1.7 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vbat backup domain supply current low-speed oscillator (lse) and rtc on 0.86 096 1.11 3 5 a rtc and lse off 0.1 0.1 0.1 2 4 1. crystal used: abracon abs07-120-32.768 khz-t with a c l of 6 pf for typical values. 2. guaranteed by characterization, not tested in production. - 3 6 ? # ? # ? # ? # ? # ) $ $ ? 6 " ! 4 ? ! 4 e m p e r a t u r e 6 6 6 6 6 6 6 6 6 electrical characteristics stm32f411xc stm32f411xe 76/137 docid026289 rev 1 required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 33: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c ? ? = docid026289 rev 1 77/137 stm32f411xc stm32f411xe electrical characteristics 118 table 32. switching output i/o current consumption symbol parameter conditions (1) 1. cs is the pcb board capacitance including the pad pin. cs = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit iddio i/o switching current v dd = 3.3 v c = c int 2 mhz 0.05 ma 8 mhz 0.15 25 mhz 0.45 50 mhz 0.85 60 mhz 1.00 84 mhz 1.40 90 mhz 1.67 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.10 8 mhz 0.35 25 mhz 1.05 50 mhz 2.20 60 mhz 2.40 84 mhz 3.55 90 mhz 4.23 v dd = 3.3 v c ext =10 pf c = c int + c ext + c s 2 mhz 0.20 8 mhz 0.65 25 mhz 1.85 50 mhz 2.45 60 mhz 4.70 84 mhz 8.80 90 mhz 10.47 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.25 8 mhz 1.00 25 mhz 3.45 50 mhz 7.15 60 mhz 11.55 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 0.32 8 mhz 1.27 25 mhz 3.88 50 mhz 12.34 electrical characteristics stm32f411xc stm32f411xe 78/137 docid026289 rev 1 on-chip peripheral current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are in analog input configuration. ? all peripherals are disabled unless otherwise mentioned. ? the art accelerator is on. ? voltage scale 2 mode selected, internal digital voltage v12 = 1.26 v. ? hclk is the system clock at 100 mhz. f pclk1 = f hclk /2, and f pclk2 = f hclk . the given value is calculated by measuring the difference of current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature is 25 c and v dd =3.3 v. table 33. peripheral current consumption peripheral i dd (typ) unit ahb1 (up to 100 mhz) gpioa 1.55 a/mhz gpiob 1.55 gpioc 1.55 gpiod 1.55 gpioe 1.55 gpioh 1.55 crc 0.36 dma1 (1) 20.24 dma1 (2) tbd dma2 (1) 21.07 dma2 (2) tbd apb1 (up to 50 mhz) tim2 11.19 a/mhz tim3 8.57 tim4 8.33 tim5 11.19 pwr 0.71 usart2 3.33 i2c1/2/3 3.10 spi2 (3) 2.62 spi3 (3) 2.86 i2s2 1.90 i2s3 1.67 wwdg 0.71 docid026289 rev 1 79/137 stm32f411xc stm32f411xe electrical characteristics 118 6.3.7 wakeup time from low-power modes the wakeup times given in table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep modes: the wakeup event is wfe. ? wkup (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd =3.3 v. apb2 (up to 100 mhz) otg_fs 23.93 a/mhz tim1 5.71 tim9 2.86 tim10 1.79 tim11 2.02 adc1 (4) 2.98 spi1 1.19 usart1 3.10 usart6 2.86 sdio 5.95 spi4 1.31 syscfg 0.71 1. valid if all the dma streams are activated (please refer to the reference manual rm0383). 2. for one dma stream activated (please refer to the reference manual rm0383). 3. i2smod bit set in spi_i2scfgr register, and then the i2se bit set to enable i2s peripheral. 4. when the adc is on (adon bit set in the adc_cr2 register), add an additional power consumption of 1.6 ma for the analog part. table 33. peripheral current consumption (continued) peripheral i dd (typ) unit table 34. low-power mode wakeup timings (1) symbol parameter min (1) typ (1) max (1) unit t wusleep (2) wakeup from sleep mode - 4 6 cpu clock cycle t wustop (2) wakeup from stop mode, usage of main regulator - 13.5 14.5 s wakeup from stop mode, usage of main regulator, flash memory in deep power down mode - 105 111 wakeup from stop mode, regulator in low power mode - 21 33 wakeup from stop mode, regulator in low power mode, flash memory in deep power down mode - 113 130 t wustdby (2)(3) wakeup from standby mode - 314 407 s 1. guaranteed by characterization, not tested in production. electrical characteristics stm32f411xc stm32f411xe 80/137 docid026289 rev 1 6.3.8 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 53 . however, the recommended clock input waveform is shown in figure 21 . the characteristics given in table 35 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 53 . however, the recommended clock input waveform is shown in figure 22 . the characteristics given in table 36 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . 2. the wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. t wustdby maximum value is given at ?40 c. table 35. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 1 - 50 mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss - 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss ? ? v in ? ? v dd --1 a docid026289 rev 1 81/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 21. high-speed external clock source ac timing diagram table 36. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss - 0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5-pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss ? ?? v in ? ?? v dd --1 a 1. guaranteed by design, not tested in production. a i / 3 # ? ) . % x t e r n a l 3 4 - & c l o c k s o u r c e 6 ( 3 % ( t f ( 3 % t 7 ( 3 % ) , 4 ( 3 % t t r ( 3 % t 7 ( 3 % f ( 3 % ? e x t 6 ( 3 % , electrical characteristics stm32f411xc stm32f411xe 82/137 docid026289 rev 1 figure 22. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on characterization results obtained with typical external components specified in table 37 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 23 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the table 37. hse 4-26 mhz oscillator characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k ? i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf @25 mhz - 450 - a v dd =3.3 v, esr= 30 ? , c l =10 pf @25 mhz - 530 - g m_crit_max maximum critical crystal g m startup - - 1 ma/v t su(hse) (2) 2. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms a i / 3 # ? ) . % x t e r n a l 3 4 - & c l o c k s o u r c e 6 , 3 % ( t f , 3 % t 7 , 3 % ) , 4 , 3 % t t r , 3 % t 7 , 3 % f , 3 % ? e x t 6 , 3 % , docid026289 rev 1 83/137 stm32f411xc stm32f411xe electrical characteristics 118 series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the combined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 23. typical application with an 8 mhz crystal 1. r ext value depends on the crystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on characterization results obtained with typical external components specified in table 38 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). the lse high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption. table 38. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit r f feedback resistor - - 18.4 - m ? i dd lse current consumption low-power mode (default) --1 a high-drive mode - - 3 g m _crit_max maximum critical crystal g m startup, low-power mode - - 0.56 a/v startup, high-drive mode - - 1.50 t su(lse) (2) 2. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is guaranteed by characterization and not tested in production. it is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - s a i / 3 # ? / 5 4 / 3 # ? ) . f ( 3 % # , 2 & 3 4 - & - ( z r e s o n a t o r 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s " i a s c o n t r o l l e d g a i n 2 % 8 4 # , electrical characteristics stm32f411xc stm32f411xe 84/137 docid026289 rev 1 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. for information about the lse high-power mode, refer to the reference manual rm0383. figure 24. typical application with a 32.768 khz crystal 6.3.9 internal clock source characteristics the parameters given in table 39 and table 40 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . high-speed internal (hsi) rc oscillator l a i / 3 # ? / 5 4 / 3 # ? ) . f , 3 % # , 2 & 3 4 - & k ( z r e s o n a t o r 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s " i a s c o n t r o l l e d g a i n # , table 39. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. guaranteed by design, not tested in production --1% factory- calibrated t a = ?40 to 105 c (3) 3. guaranteed by characterization, not tested in production ?8 - 4.5 % t a = ?10 to 85 c (3) ?4 - 4 % t a = 25 c ?1 - 1 % t su(hsi) (2) hsi oscillator startup time - 2.2 4 s i dd(hsi) (2) hsi oscillator power consumption -6080 a docid026289 rev 1 85/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 25. acc hsi versus temperature 1. guaranteed by characterization, not tested in production. low-speed internal (lsi) rc oscillator table 40. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed by characterization, not tested in production. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a - 3 6 - i n - a x 4 y p i c a 4 ! ? # ! # # ( 3 ) electrical characteristics stm32f411xc stm32f411xe 86/137 docid026289 rev 1 figure 26. acc lsi versus temperature 6.3.10 pll characteristics the parameters given in table 41 and table 42 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 14 . - 3 6 . o r m a l i z e d d e v i a t i o n 4 e m p e r a t u r e ? # m a x a v g m i n table 41. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) 0.95 (2) 1 2.10 mhz f pll_out pll multiplier output clock 24 - 100 mhz f pll48_out 48 mhz pll multiplier output clock - 48 75 mhz f vco_out pll vco output 100 - 432 mhz t lock pll lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 100 mhz rms - 25 - ps peak to peak - ? 150 - period jitter rms - 15 - peak to peak - ? 200 - docid026289 rev 1 87/137 stm32f411xc stm32f411xe electrical characteristics 118 i dd(pll) (4) pll power consumption on vdd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division factor m to obtain the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design, not tested in production. 3. the use of two plls in parallel could degraded the jitter up to +30%. 4. guaranteed by characterization, not tested in production. table 41. main pll characteristics (continued) symbol parameter conditions min typ max unit table 42. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) - 0.95 (2) 1 2.10 mhz f plli2s_out plli2s multiplier output clock - - - 216 f vco_out plli2s vco output - 100 - 432 t lock plli2s lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48 khz period, n=432, r=5 rms - 90 - peak to peak - ? 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 - ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples - 400 - i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division factor m to have the specified pll input clock values. 2. guaranteed by design, not tested in production. 3. value given with main pll running. 4. guaranteed by characterization, not tested in production. electrical characteristics stm32f411xc stm32f411xe 88/137 docid026289 rev 1 6.3.11 pll spread spectrum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 49: emi characteristics for lqfp100 ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation depth (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = s 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: table 43. sscg parameter constraints symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep (modulation period) * (increment step) - - 2 15 -1 - 1. guaranteed by design, not tested in production. modeper round f pll_in 4f mod ? ?? ? ?? = modeper round 10 6 410 3 ? ?? ? ?? 250 == incstep round 2 15 1 ? ?? md plln ? ? ?? 100 5 ? modeper ? ?? ? ?? = incstep round 2 15 1 ? ?? 2 240 ? ? ?? 100 5 ? 250 ? ?? ? ?? 126md(quantitazed)% == md quantized % modeper incstep ? 100 ? 5 ? ?? 2 15 1 ? ?? plln ? ?? ? = md quantized % 250 126 ? 100 ? 5 ? ?? 2 15 1 ? ?? 240 ? ?? ? 2.002%(peak) == docid026289 rev 1 89/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 27 and figure 28 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 27. pll output clock waveforms in center spread mode figure 28. pll output clock waveforms in down spread mode 6.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e x t m o d e m d a i m d & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e x t m o d e x m d a i table 44. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.7 v- 5 - ma write / erase 16-bit mode, v dd = 2.1 v- 8 - write / erase 32-bit mode, v dd = 3.3 v - 12 - electrical characteristics stm32f411xc stm32f411xe 90/137 docid026289 rev 1 table 45. flash memory programming symbol parameter conditions min (1) typ max (1) 1. guaranteed by characterization, not tested in production. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 - 16 100 (2) 2. the maximum programming time is measured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 - 1.3 2.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -816 s program/erase parallelism (psize) = x 16 - 5.5 11 program/erase parallelism (psize) = x 32 -48 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.7 - 3.6 v table 46. flash memory programming with v pp voltage symbol parameter conditions min (1) typ max (1) unit t prog double word programming t a ??? 0 to +40 c v dd = 3.3 v v pp = 8.5 v - 16 100 (2) s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 3.50 - s v prog programming voltage 2.7 - 3.6 v docid026289 rev 1 91/137 stm32f411xc stm32f411xe electrical characteristics 118 table 47. flash memory endurance and data retention 6.3.13 emc characteristics susceptibility tests are performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 49 . they are based on the ems levels and classes defined in application note an1709. v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (3) cumulative time during which v pp is applied - - 1 hour 1. guaranteed by design, not tested in production. 2. the maximum programming time is measured after 100k erase operations. 3. v pp should only be connected during programming/erasing. symbol parameter conditions value unit min (1) 1. guaranteed by characterization, not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 46. flash memory programming with v pp voltage (continued) symbol parameter conditions min (1) typ max (1) unit electrical characteristics stm32f411xc stm32f411xe 92/137 docid026289 rev 1 when the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. the pins showing a middle range robustness are: pa0, pa1, pa2, on lqfp100 packages and pdr_on on wlcsp49. as a consequence, it is recommended to add a serial resistor (1 k ?? maximum) located as close as possible to the mcu to the pins exposed to noise (connected to tracks longer than 50 mm on pcb). designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 48. ems characteristics for lqfp100 package symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, lqfp100, wlcsp49, t a = +25 c, f hclk = 100 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, lqfp100, wlcsp49, t a = +25 c, f hclk = 100 mhz, conforms to iec 61000-4-4 4a docid026289 rev 1 93/137 stm32f411xc stm32f411xe electrical characteristics 118 electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. 6.3.14 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latchup two complementary static tests are required on six parts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. table 49. emi characteristics for lqfp100 symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 8/84 mhz s emi peak level v dd = 3.6 v, t a = 25 c, conforming to iec61967-2 0.1 to 30 mhz 19 db v 30 to 130 mhz 17 130 mhz to 1 ghz 12 sae emi level 3.5 - table 50. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c conforming to ansi/esd stm5.3.1 ii 400 1. guaranteed by characterization, not tested in production. electrical characteristics stm32f411xc stm32f411xe 94/137 docid026289 rev 1 6.3.15 i/o current injection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failure (for example reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 52 . note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 51. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a table 52. i/o current injection susceptibility (1) 1. na = not applicable . symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin ?0 na ma injected current on nrst pin ?0 na injected current on pb3, pb4, pb5, pb6, pb7, pb8, pb9, pc13, pc14, pc15, ph1, pdr_on, pc0, pc1,pc2, pc3, pd1, pd5, pd6, pd7, pe0, pe2, pe3, pe4, pe5, pe6 ?0 na injected current on any other ft pin ?5 na injected current on any other pins ?5 +5 docid026289 rev 1 95/137 stm32f411xc stm32f411xe electrical characteristics 118 6.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 53 are derived from tests performed under the conditions summarized in table 14 . all i/os are cmos and ttl compliant. table 53. i/o static characteristics symbol parameter conditions min typ max unit v il ft and nrst i/o input low level voltage 1.7 v ? ? v dd ?? 3.6 v - - 0.3v dd (1) v boot0 i/o input low level voltage 1.75 v ? ? v dd ?? 3.6 v, -40 c ? ? t a ?? 105 c -- 0.1v dd +0.1 (2) 1.7 v ? ? v dd ?? 3.6 v, 0 c ? ? t a ?? 105 c -- v ih ft and nrst i/o input high level voltage (5) 1.7 v ? ? v dd ?? 3.6 v0.7v dd (1) -- v boot0 i/o input high level voltage 1.75 v ? ? v dd ?? 3.6 v, -40 c ? ? t a ?? 105 c 0.17v dd +0.7 (2) -- 1.7 v ? ? v dd ?? 3.6 v, 0 c ? ? t a ?? 105 c v hys ft and nrst i/o input hysteresis 1.7 v ? ? v dd ?? 3.6 v 10% v dd (2)(3) -- v boot0 i/o input hysteresis 1.75 v ? ? v dd ?? 3.6 v, -40 c ? ? t a ?? 105 c 0.1 - - 1.7 v ? ? v dd ?? 3.6 v, 0 c ? ? t a ?? 105 c i lkg i/o input leakage current (4) v ss ? ? v in ?? v dd -- ? 1 a i/o ft input leakage current (5) v in ?? 5 v--3 r pu weak pull-up equivalent resistor (6) all pins except for pa10 (otg_fs_id) v in ?? v ss 30 40 50 k ? pa10 (otg_fs_id) - 7 10 14 r pd weak pull-down equivalent resistor (7) all pins except for pa10 (otg_fs_id) v in ?? v dd 30 40 50 pa10 (otg_fs_id) - 7 10 14 c io (8) i/o pin capacitance - - 5 - pf 1. guaranteed by test in production. 2. guaranteed by design, not tested in production. 3. with a minimum of 200 mv. electrical characteristics stm32f411xc stm32f411xe 96/137 docid026289 rev 1 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft i/os is shown in figure 29 . figure 29. ft i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to ? 8 ma, and sink or source up to ? 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to ? 3ma. when using the pc13 to pc15 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. 4. leakage could be higher than the maximum value, if negative current is injected on adjacent pins, refer to table 52: i/o current injection susceptibility 5. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors must be disabled. leakage could be higher than the maximum value, if negative current is injected on adjacent pins.refer to table 52: i/o current injection susceptibility 6. pull-up resistors are designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is minimum (~10% order). 7. pull-down resistors are designed with a true resistance in series with a switchable nmos. this nmos contribution to the series resistance is minimum (~10% order). 8. hysteresis voltage between schmitt trigger switching levels. guaranteed by characterization, not tested in production. 0 6 9 9 ' ' 9 9 , / 9 , + 9 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , / p d [ 9 ' ' % d v h g r q ' h v l j q v l p x o d w l r q v 9 , / p d [ 9 ' ' 7 7 / u h t x l u h p h q w 9 , + p l q 9 7 7 / u h t x l u h p h q w 9 , / p d [ 9 $ u h d q r w g h w h u p l q h g % d v h g r q ' h v l j q v l p x o d w l r q v 9 , + p l q 9 ' ' docid026289 rev 1 97/137 stm32f411xc stm32f411xe electrical characteristics 118 in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maximum rating specified in section 6.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating ? i vdd (see table 12 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating ? i vss (see table 12 ). output voltage levels unless otherwise specified, the parameters given in table 54 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . all i/os are cmos and ttl compliant. input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 30 and table 55 , respectively. unless otherwise specified, the parameters given in table 55 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . table 54. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always respect the absolute maximum rating specified in table 12 . and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v ?? v dd ? 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. - 0.4 v v oh (3) 3. the i io current sourced by the device must always respect the absolute maximum rating specified in table 12 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+8 ma 2.7 v ? v dd ? 3.6 v - 0.4 v v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1) output low level voltage for an i/o pin i io = +20 ma 2.7 v ? v dd ? 3.6 v - 1.3 (4) 4. guaranteed by characterization results, not tested in production. v v oh (3) output high level voltage for an i/o pin v dd ?1.3 (4) - v ol (1) output low level voltage for an i/o pin i io = +6 ma 1.8 v ? v dd ? 3.6 v - 0.4 (4) v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (4) - v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.7 v ? v dd ? 3.6 v - 0.4 (5) 5. guaranteed by design, not tested in production. v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (5) - electrical characteristics stm32f411xc stm32f411xe 98/137 docid026289 rev 1 table 55. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.70 v - - 4 mhz c l = 50 pf, v dd 1.7 v - - 2 c l = 10 pf, v dd 2.70 v - - 8 c l = 10 pf, v dd 1.7 v - - 4 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.7 v to 3.6 v - - 100 ns 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.70 v - - 25 mhz c l = 50 pf, v dd 1.7 v - - 12.5 c l = 10 pf, v dd 2.70 v - - 50 c l = 10 pf, v dd 1.7 v - - 20 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd 2.7 v - - 10 ns c l = 50 pf, v dd 1.7 v - - 20 c l = 10 pf, v dd 2.70 v - - 6 c l = 10 pf, v dd 1.7 v - - 10 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd 2.70 v - - 50 (4) mhz c l = 40 pf, v dd 1.7 v - - 25 c l = 10 pf, v dd 2.70 v - - 100 (4) c l = 10 pf, v dd 1.7 v - - 50 (4) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd 2.70 v - - 6 ns c l = 40 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 2.70 v - - 4 c l = 10 pf, v dd 1.7 v - - 6 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd 2.70 v - - 100 (4) mhz c l = 30 pf, v dd 1.7 v - - 50 (4) c l = 10 pf, v dd 2.70 v - - 180 (4) c l = 10 pf, v dd 1.7 v - - 100 (4) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd 2.70 v - - 4 ns c l = 30 pf, v dd 1.7 v - - 6 c l = 10 pf, v dd 2.70 v - - 2.5 c l = 10 pf, v dd 1.7 v - - 4 -t extipw pulse width of external signals detected by the exti controller 10 - - ns 1. guaranteed by characterization, not tested in production. docid026289 rev 1 99/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 30. i/o ac characteristics definition 6.3.17 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 53 ). unless otherwise specified, the parameters given in table 56 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . refer to table 53: i/o static characteristics for the values of vih and vil for nrst pin. 2. the i/o speed is configured using the ospeedry[1:0] bits. refer to the stm32f4xx reference manual for a description of the gpiox_speedr gpio port output speed register. 3. the maximum frequency is defined in figure 30 . 4. for maximum frequencies above 50 mhz and v dd > 2.4 v, the compensation cell should be used. d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w table 56. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in ?? v ss 30 40 50 k ? v f(nrst) (2) nrst input filtered pulse - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design, not tested in production. electrical characteristics stm32f411xc stm32f411xe 100/137 docid026289 rev 1 figure 31. recommended nrst pin protection 1. the reset network protects the device against parasitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 56 . otherwise the reset is not taken into account by the device. 6.3.18 tim timer characteristics the parameters given in table 57 are guaranteed by design. refer to section 6.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). a i c 3 4 - & x x x 2 0 5 . 2 3 4 6 $ $ & i l t e r ) n t e r n a l 2 e s e t ? & % x t e r n a l r e s e t c i r c u i t table 57. timx characteristics (1)(2) 1. timx is used as a general term to refer to the tim1 to tim11 timers. 2. guaranteed by design, not tested in production. symbol parameter conditions (3) 3. the maximum timer frequency on apb1 is 50 mhz and on apb2 is up to 100 mhz, by setting the timpre bit in the rcc_dckcfgr register, if apbx prescaler is 1 or 2 or 4, then timxclk = hckl, otherwise timxclk >= 4x pclkx. min max unit t res(tim) timer resolution time ahb/apbx prescaler=1 or 2 or 4, f timxclk = 100 mhz 1- t timxclk 11.9 - ns ahb/apbx prescaler>4, f timxclk = 100 mhz 1- t timxclk 11.9 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 100 mhz 0 f timxclk /2 mhz 0 50 mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected f timxclk = 100 mhz 0.0119 780 s t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 100 mhz - 51.1 s docid026289 rev 1 101/137 stm32f411xc stm32f411xe electrical characteristics 118 6.3.19 communications interfaces i 2 c interface characteristics the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 58 . refer also to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . the i 2 c bus interface supports standard mode (up to 100 khz) and fast mode (up to 400 khz). the i 2 c bus frequency can be increased up to 1 mhz. for more details about the complete solution, please contact your local st sales representative. table 58. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1)(2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 3450 (3) 3. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 0 900 (4) 4. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s t sp pulse width of the spikes that are suppressed by the analog filter for standard fast mode 050 (5) 050 (5) s c b capacitive load for each bus line - 400 - 400 pf electrical characteristics stm32f411xc stm32f411xe 102/137 docid026289 rev 1 figure 32. i 2 c bus ac waveforms and measurement circuit 1. r s = series protection resistor. 2. r p = external pull-up resistor. 3. v dd_i2c is the i2c bus power supply. 5. the minimum width of the spikes filtered by the analog filter is above t sp (max) table 59. scl frequency (f pclk1 = 50 mhz, v dd = v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed 2. for speeds around 200 khz, the tolerance on the achieved speed is of ? 5%. for other speed ranges, the tolerance on the achieved speed is ? 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k ? 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee ]e?? ^ d z d ^ z w /? ? s z /? ^ d d?? &?? ^ ^ > ? (~ ^ ? ?~ ^ ^ > ? z~ ^ d ? ~ ^ > , ? ~ ^ > > ? ?~ ^ ? ?~ ^ > ? (~ ^ > ? z~ ^ ^ d z d z w d ^ d z d ? ?~ ^ d ? ?~ ^ d k ^ d k w ? ~ ^ d kw ^ d s z /? z w z ^ z ^ docid026289 rev 1 103/137 stm32f411xc stm32f411xe electrical characteristics 118 spi interface characteristics unless otherwise specified, the parameters given in table 60 for the spi interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 60. spi dynamic characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master full duplex/receiver mode, 2.7 v < v dd < 3.6 v spi1/4/5 --42 mhz master full duplex/receiver mode, 3.0 v < v dd < 3.6 v spi1/4/5 -- 50 master transmitter mode 1.7 v < v dd < 3.6 v spi1/4/5 -- 50 master mode 1.7 v < v dd < 3.6 v spi1/2/3/4/5 -- 25 slave transmitter/full duplex mode 2.7 v < v dd < 3.6 v spi1/4/5 -- 38 (2) slave receiver mode, 1.8 v < v dd < 3.6 v spi1/4/5 --50 slave mode, 1.8 v < v dd < 3.6 v spi1/2/3/4/5 -- 25 duty(sck) duty cycle of spi clock frequency slave mode 30 50 70 % t w(sckh) t w(sckl) sck high and low time master mode, spi presc = 2 t pclk ? 1.5 t pclk t pclk +1.5 ns t su(nss) nss setup time slave mode, spi presc = 2 3t pclk --ns t h(nss) nss hold time slave mode, spi presc = 2 2t pclk --ns t su(mi) data input setup time master mode 4 - - ns t su(si) slave mode 2.5 - - ns t h(mi) data input hold time master mode 7.5 - - ns t h(si) slave mode 3.5 - - ns electrical characteristics stm32f411xc stm32f411xe 104/137 docid026289 rev 1 figure 33. spi timing diagram - slave mode and cpha = 0 t a(so ) data output access time slave mode 7 - 21 ns t dis(so) data output disable time slave mode 5 - 12 ns t v(so) data output valid time slave mode (after enable edge), 2.7 v < v dd < 3.6 v -1113ns slave mode (after enable edge), 1.7 v < v dd < 3.6 v - 11 18.5 ns t h(so) data output hold time slave mode (after enable edge), 1.7 v < v dd < 3.6 v 8--ns t v(mo) data output valid time master mode (after enable edge) - 4 6 ns t h(mo) data output hold time master mode (after enable edge) 0 - - ns 1. guaranteed by characterization, not tested in production. 2. maximum frequency in slave transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value can be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50% table 60. spi dynamic characteristics (1) (continued) symbol parameter conditions min typ max unit ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) docid026289 rev 1 105/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 34. spi timing diagram - slave mode and cpha = 1 (1) figure 35. spi timing diagram - master mode (1) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input ai14136 sck input cpha= 0 mosi output miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical characteristics stm32f411xc stm32f411xe 106/137 docid026289 rev 1 i 2 s interface characteristics unless otherwise specified, the parameters given in table 61 for the i 2 s interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (ck, sd, ws). note: refer to the i2s section of rm0383 reference manual for more details on the sampling frequency (f s ). f mck , f ck , and d ck values reflect only the digital peripheral behavior. the values of these parameters might be slightly impacted by the source clock precision. d ck depends mainly on the value of odd bit. the digital contribution leads to a minimum value of (i2sdiv/(2*i2sdiv+odd) and a maximum value of (i2sdiv+odd)/(2*i2sdiv+odd). f s maximum value is supported for each mode/condition. table 61. i 2 s dynamic characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256x8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode 0 7 ns t h(ws) ws hold time master mode 1.5 - t su(ws) ws setup time slave mode 1.5 - t h(ws) ws hold time slave mode 3 - t su(sd_mr) data input setup time master receiver 1 - t su(sd_sr) slave receiver 2.5 - t h(sd_mr) data input hold time master receiver 7 - t h(sd_sr) slave receiver 2.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 20 t v(sd_mt) master transmitter (after enable edge) - 6 t h(sd_st) data output hold time slave transmitter (after enable edge) 8 - t h(sd_mt) master transmitter (after enable edge) 2 - 1. guaranteed by characterization, not tested in production. 2. the maximum value of 256xfs is 50 mhz (apb1 maximum frequency). docid026289 rev 1 107/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 36. i 2 s slave timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. figure 37. i 2 s master timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14881b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14884b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2) electrical characteristics stm32f411xc stm32f411xe 108/137 docid026289 rev 1 usb otg full speed (fs) characteristics this interface is present in usb otg fs controller. note: when vbus sensing feature is enabled, pa9 should be left at their default state (floating input), not as alternate function. a typical 200 a current consumption of the embedded sensing block (current to voltage conversion to determine the different sessions) can be observed on pa9 when the feature is enabled. table 62. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb otg fs transceiver startup time 1 s table 63. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the usb otg fs functionality is ensured down to 2.7 v but not the full usb full speed electrical characteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. - 3.6 v v di (3) 3. guaranteed by design, not tested in production. differential input sensitivity i(usb_fs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k ? to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers. - - 0.3 v v oh static output level high r l of 15 k ? to v ss (4) 2.8 - 3.6 r pd pa11, pa12 (usb_fs_dm/dp) v in = v dd 17 21 24 k ? pa9 (otg_fs_vbus) 0.65 1.1 2.0 r pu pa11, pa12 (usb_fs_dm/dp) v in = v ss 1.5 1.8 2.1 pa9 (otg_fs_vbus) v in = v ss 0.25 0.37 0.55 docid026289 rev 1 109/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 38. usb otg fs timings: definition of data signal rise and fall time 6.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in table 65 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in table 14 . table 64. usb otg fs electrical characteristics (1) 1. guaranteed by design, not tested in production. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v ai14137 t f differen tial data l ines v ss v cr s t r crossover points table 65. adc characteristics symbol parameter conditions min typ max unit v dda power supply v dda ? v ref+ < 1.2 v 1.7 (1) - 3.6 v v ref+ positive reference voltage 1.7 (1) -v dda v f adc adc clock frequency v dda = 1.7 (1) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v 0.6 30 36 mhz f trig (2) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz - - 17 1/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 for details - - 50 k ? r adc (2)(4) sampling switch resistance - - 6 k ? c adc (2) internal sample and hold capacitor -47pf electrical characteristics stm32f411xc stm32f411xe 110/137 docid026289 rev 1 equation 1: r ain max formula t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s 3 - 480 1/f adc t stab (2) power-up time - 2 3 s t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.30 - 16.20 s 9 to 492 (t s for sampling +n-bit resolution for successive approximation) 1/f adc f s (2) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode - - 6 msps i vref+ (2) adc v ref dc current consumption in conversion mode - 300 500 a i vdda (2) adc v dda dc current consumption in conversion mode - 1.6 1.8 ma 1. v dda minimum value of 1.7 v is possible with the use of an external power supply supervisor (refer to section 3.14.2: internal reset off ). 2. guaranteed by characterization, not tested in production. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.7 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 65 . table 65. adc characteristics (continued) symbol parameter conditions min typ max unit r ain k 0.5 ? ?? f adc c adc 2 n 2 + ?? ln ? ? -------------------------------------------------------------- r adc ? = docid026289 rev 1 111/137 stm32f411xc stm32f411xe electrical characteristics 118 the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. table 66. adc accuracy at f adc = 18 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. guaranteed by characterization, not tested in production. unit et total unadjusted error f adc =18 mhz v dda = 1.7 to 3.6 v v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 3 4 lsb eo offset error 2 3 eg gain error 1 3 ed differential linearity error 1 2 el integral linearity error 2 3 table 67. adc accuracy at f adc = 30 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. guaranteed by characterization, not tested in production. unit et total unadjusted error f adc = 30 mhz, r ain < 10 k ? , v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v, v dda ? v ref < 1.2 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 4 ed differential linearity error 1 2 el integral linearity error 1.5 3 table 68. adc accuracy at f adc = 36 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. guaranteed by characterization, not tested in production. unit et total unadjusted error f adc =36 mhz, v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 4 7 lsb eo offset error 2 3 eg gain error 3 6 ed differential linearity error 2 3 el integral linearity error 3 6 electrical characteristics stm32f411xc stm32f411xe 112/137 docid026289 rev 1 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.16 does not affect the adc accuracy. table 69. adc dynamic accuracy at f adc = 18 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =18 mhz v dda = v ref+ = 1.7 v input frequency = 20 khz temperature = 25 c 10.3 10.4 - bits sinad signal-to-noise and distortion ratio 64 64.2 - db snr signal-to-noise ratio 64 65 - thd total harmonic distortion - 67 - 72 - 1. guaranteed by characterization, not tested in production. table 70. adc dynamic accuracy at f adc = 36 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc = 36 mhz v dda = v ref+ = 3.3 v input frequency = 20 khz temperature = 25 c 10.6 10.8 - bits sinad signal-to noise and distortion ratio 66 67 - db snr signal-to noise ratio 64 68 - thd total harmonic distortion - 70 - 72 - 1. guaranteed by characterization, not tested in production. docid026289 rev 1 113/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 39. adc accuracy characteristics 1. see also table 67 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves. eo = offset error: deviation between the first actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviation between any actual transition and the end point correlation line. figure 40. typical connection diagram using the adc 1. refer to table 65 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. a i c % / % ' , 3 " ) $ % ! , % 4 % $ % , 6 $ $ ! 6 3 3 ! 6 2 % & o r d e p e n d i n g o n p a c k a g e = 6 $ $ ! ; , 3 " ) $ % ! , a i175 3 4 s tm 3 2f v dd ainx i l 1 a 0.6 v v t r ain (1) c p a r as itic v ain 0.6 v v t r adc (1) c adc (1) 12-bit converter sa mple a nd hold adc converter electrical characteristics stm32f411xc stm32f411xe 114/137 docid026289 rev 1 general pcb design guidelines power supply decoupling should be performed as shown in figure 41 or figure 42 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 41. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref- inputs are both available on ufbga100. v ref+ is also available on lqfp100. when v ref+ and v ref- are not available, they are internally connected to v dda and v ssa . figure 42. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref- inputs are both available on ufbga100. v ref+ is also available on lqfp100. when v ref+ and v ref- are not available, they are internally connected to v dda and v ssa . v ref+ s tm 3 2f v dda v ss a /v ref- 1 f // 10 nf 1 f // 10 nf a i175 3 5 ( s ee note 1) ( s ee note 1) v ref+ /v dda s tm 3 2f 1 f // 10 nf v ref? /v ss a a i175 3 6 ( s ee note 1) ( s ee note 1) docid026289 rev 1 115/137 stm32f411xc stm32f411xe electrical characteristics 118 6.3.21 temperature sensor characteristics 6.3.22 v bat monitoring characteristics 6.3.23 embedded reference voltage the parameters given in table 74 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . table 71. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - ? 1 ? 2c avg_slope (1) average slope - 2.5 - mv/c v 25 (1) voltage at 25 c - 0.76 - v t start (2) startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. guaranteed by characterization, not tested in production. 2. guaranteed by design, not tested in production. table 72. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff 7a2c - 0x1fff 7a2d ts_cal2 ts adc raw data acquired at temperature of 110 c, v dda = 3.3 v 0x1fff 7a2e - 0x1fff 7a2f table 73. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k ? q ratio on v bat measurement - 4 - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- - s 1. guaranteed by design, not tested in production. 2. shortest sampling time can be determined in the application by multiple iterations. table 74. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -10-- s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3v ?? 10mv - 3 5 mv electrical characteristics stm32f411xc stm32f411xe 116/137 docid026289 rev 1 6.3.24 sd/sdio mmc/emmc card host interface (sdio) characteristics unless otherwise specified, the parameters given in table 76 for the sdio/mmc/emmc interface are derived from tests performed under the ambient temperature, f pclk2 frequency and v dd supply voltage conditions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf (for emmc c = 20 pf) ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.16: i/o port characteristics for more details on the input/output characteristics. figure 43. sdio high-speed mode t coeff (2) temperature coefficient - - 30 50 ppm/c t start (2) startup time - - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design, not tested in production table 74. embedded internal reference voltage (continued) symbol parameter conditions min typ max unit table 75. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff 7a2a - 0x1fff 7a2b t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14 88 7 docid026289 rev 1 117/137 stm32f411xc stm32f411xe electrical characteristics 118 figure 44. sd default mode ck d, cmd (output) t ovd t ohd ai14 888 table 76. dynamic characteristics: sd / mmc characteristics (1)(2) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 8/3 - t w(ckl) clock low time fpp = 50 mhz 10.5 11 - ns t w(ckh) clock high time fpp = 50 mhz 8.5 9 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs fpp = 50 mhz 2.5 - - ns t ih input hold time hs fpp = 50 mhz -40c docid026289 rev 1 119/137 stm32f411xc stm32f411xe package characteristics 135 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.1.1 wlcsp49, 3.034 x 3.22 mm, 0.4 mm pitch wafer level chip size package figure 45. wlcsp49 wafer level chip size package outline ! o r i e n t a t i o n r e f e r e n c e 7 a f e r b a c k s i d e % $ $ e t a i l ! r o t a t e d ? 3 e a t i n g p l a n e . o t e ! " u m p b 3 i d e v i e w ! ! $ e t a i l ! ' ! e & ' e e ! b a l l l o c a t i o n e % ! " u m p s i d e e e e : . o t e & r o n t v i e w ! 8 - ? - % ? 6 package characteristics stm32f411xc stm32f411xe 120/137 docid026289 rev 1 table 79. stm32f411xc/xe wlcsp49 wafer level chip size package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating - 0.025 - - 0.0010 - b (3) 3. dimension is measured at the maximum bump diameter parallel to primary datum z. 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 2.964 2.999 3.034 0.1167 0.1181 0.1194 e 3.150 3.185 3.220 0.1240 0.1254 0.1268 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - f - 0.2995 - - 0.0118 - g - 0.3925 - - 0.0155 - aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - docid026289 rev 1 121/137 stm32f411xc stm32f411xe package characteristics 135 marking of engineering samples figure 46. wlcsp49 package top view 1. samples marked "es" are to be considered as "engineering samples": i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials d ^??? s ( q j l q h h u l q j v d p s o h p d u n l q j ( 6 package characteristics stm32f411xc stm32f411xe 122/137 docid026289 rev 1 7.1.2 ufqfpn48, 7 x 7 mm, 0.5 mm pitch package figure 47. ufqfpn48, 7 x 7 mm, 0.5 mm pitch, package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. $ % b 0 ( b 9 ' 3 l q l g h q w l i l h u o d v h u p d u n l q j d u h d ( ( ' < ' ( ( [ s r v h g s d g d u h d = ' h w d l o = 5 w \ s / & [ ? s l q f r u q h u $ 6 h d w l q j s o d q h $ e h g g g ' h w d l o < 7 table 80. ufqfpn48, 7 x 7 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 d 6.900 7.000 7.100 0.2717 0.2756 0.2795 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 d2 5.500 5.600 5.700 0.2165 0.2205 0.2244 e2 5.500 5.600 5.700 0.2165 0.2205 0.2244 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 docid026289 rev 1 123/137 stm32f411xc stm32f411xe package characteristics 135 figure 48. ufqfpn48 recommended footprint 1. dimensions are in millimeters. t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - 1. values in inches are converted from mm and rounded to 4 decimal digits. table 80. ufqfpn48, 7 x 7 mm, 0.5 mm pitch, package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. ! " ? & 0 ? 6 package characteristics stm32f411xc stm32f411xe 124/137 docid026289 rev 1 marking of engineering samples figure 49. ufqfpn48 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials 0 6 9 d ( 6 ( q j l q h h u l q j v d p s o h docid026289 rev 1 125/137 stm32f411xc stm32f411xe package characteristics 135 7.1.3 lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package figure 50. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline 1. drawing is not to scale. ! ! ! 3 % ! 4 ) . ' 0 , ! . % c c c # b # c ! , , + ' ! 5 ' % 0 , ! . % m m ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . $ $ $ e % % % 7 ? - % ? 6 package characteristics stm32f411xc stm32f411xe 126/137 docid026289 rev 1 figure 51. lqfp64 recommended footprint 1. dimensions are in millimeters. table 81. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.60 - - 0.0630 a1 0.05 - 0.15 0.0020 - 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 - 0.0079 d - 12.00 - - 0.4724 - d1 - 10.00 - - 0.3937 - e - 12.00 - - 0.4724 - e1 - 10.00 - - 0.3937 - e - 0.50 - - 0.0197 - k 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 - 1.00 - - 0.0394 - n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits. a i c docid026289 rev 1 127/137 stm32f411xc stm32f411xe package characteristics 135 marking of engineering samples figure 52. lqfp64 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials 0 6 9 ( 6 & o h j o f f s j o h t b n q m f package characteristics stm32f411xc stm32f411xe 128/137 docid026289 rev 1 7.1.4 lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package figure 53. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! docid026289 rev 1 129/137 stm32f411xc stm32f411xe package characteristics 135 table 82. lqpf100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.6 - - 0.063 a1 0.05 - 0.15 0.002 - 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.2 0.0035 - 0.0079 d 15.8 16 16.2 0.622 0.6299 0.6378 d1 13.8 14 14.2 0.5433 0.5512 0.5591 d3 - 12 - - 0.4724 - e 15.8 16 16.2 0.622 0.6299 0.6378 e1 13.8 14 14.2 0.5433 0.5512 0.5591 e3 - 12 - - 0.4724 - e - 0.5 - - 0.0197 - l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 - 1 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f411xc stm32f411xe 130/137 docid026289 rev 1 figure 54. lqfp100 recommended footprint 1. dimensions are in millimeters. marking of engineering samples figure 55. lqpf100 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials a i c 0 6 9 ( 6 ( q j l q h h u l q j v d p s o h docid026289 rev 1 131/137 stm32f411xc stm32f411xe package characteristics 135 7.1.5 ufbga100, 7 x 7 mm, 0.5 mm pitch package figure 56. ufbga100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline $ & b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' 0 ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : $ e d o o l g h q w l i l h u h $ $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ $ $ e d o o l q g h [ d u h d table 83. ufbga100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.0020 0.0031 0.0043 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 a3 0.080 0.130 0.180 0.0031 0.0051 0.0071 a4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 d 6.950 7.000 7.050 0.2736 0.2756 0.2776 d1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e 6.950 7.000 7.050 0.2736 0.2756 0.2776 e1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - f 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.100 - - 0.0039 package characteristics stm32f411xc stm32f411xe 132/137 docid026289 rev 1 figure 57. recommended pcb design rules for pads (0.5 mm-pitch bga) 1. non solder mask defined (nsmd) pads are recommended. 2. 4 to 6 mils solder paste screen printing process. marking of engineering samples figure 58. ufbga100 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 83. ufbga100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. pitch 0.5 mm d pad 0.27 mm dsm 0.35 mm typ (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter dpad dsm ai15495 0 6 9 ( 6 ( q j l q h h u l q j v d p s o h docid026289 rev 1 133/137 stm32f411xc stm32f411xe package characteristics 135 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 14: general operating conditions on page 60 . the maximum chip-junction temperature, t j max., in degrees celsius, may be calculated using the following equation: t j max = t a max + (pd max x ? ja ) where: ? t a max is the maximum ambient temperature in c, ?? ja is the package junction-to-ambient thermal resistance, in ? c/w, ? pd max is the sum of p int max and p i/o max (pd max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. part numbering stm32f411xc stm32f411xe 134/137 docid026289 rev 1 8 part numbering table 84. ordering information scheme example: stm32 f 411 c e y 6 tr device family stm32 = arm ? -based 32-bit microcontroller product type f = general-purpose device subfamily 411 = 411 family pin count c = 48/49 pins r = 64 pins v = 100 pins flash memory size c = 256 kbytes of flash memory e = 512 kbytes of flash memory package h = ufbga t = lqfp u = ufqfpn y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c packing tr = tape and reel no character = tray or tube docid026289 rev 1 135/137 stm32f411xc stm32f411xe part numbering 135 table 85. device order codes reference order codes stm32f411xc stm32f411ccy6, stm32f411rct6, stm32f411vct6, stm32f411ccu6, stm32f411vch6 stm32f411xe stm32f411cey6, stm32f411ret6, stm32f411vet6, stm32f411ceu6, stm32f411veh6 revision history stm32f411xc stm32f411xe 136/137 docid026289 rev 1 9 revision history table 86. document revision history date revision changes 19-jun-2014 1 initial release. docid026289 rev 1 137/137 stm32f411xc stm32f411xe 137 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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